Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16214

1

T7

12

T10

10

T12

16

auto[1]

11132

1

T9

4

T15

55

T16

132

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3001	1			T15	60		T18	4		T53	20
values[1]	3629	1			T15	22		T16	54		T17	10
values[2]	2978	1			T10	10		T15	20		T16	96
values[3]	3321	1			T7	12		T9	4		T12	16
values[4]	3576	1			T16	37		T57	28		T151	6
values[5]	3538	1			T16	20		T45	20		T46	25
values[6]	3805	1			T16	66		T45	25		T46	47
values[7]	3498	1			T16	21		T29	20		T46	64

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3959	1			T16	41		T29	20		T45	25
values[1]	3264	1			T15	21		T16	20		T17	10
values[2]	3231	1			T16	47		T151	6		T52	20
values[3]	3789	1			T7	12		T15	20		T16	37
values[4]	4185	1			T15	20		T16	27		T54	6
values[5]	2829	1			T10	10		T12	16		T15	20
values[6]	2703	1			T15	20		T16	49		T18	4
values[7]	3386	1			T9	4		T15	22		T16	22

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	252	1			T46	9		T26	15		T190	70
auto[0]	values[0]	values[1]	161	1			T46	15		T200	6		T48	12
auto[0]	values[0]	values[2]	379	1			T222	8		T35	10		T139	14
auto[0]	values[0]	values[3]	280	1			T15	13		T53	20		T46	19
auto[0]	values[0]	values[4]	188	1			T15	9		T211	14		T48	25
auto[0]	values[0]	values[5]	167	1			T15	5		T227	10		T230	8
auto[0]	values[0]	values[6]	254	1			T18	4		T46	11		T190	12
auto[0]	values[0]	values[7]	233	1			T87	15		T93	14		T82	16
auto[0]	values[1]	values[0]	237	1			T46	9		T20	16		T87	10
auto[0]	values[1]	values[1]	369	1			T17	10		T134	13		T191	11
auto[0]	values[1]	values[2]	346	1			T98	41		T203	9		T217	54
auto[0]	values[1]	values[3]	132	1			T45	29		T167	10		T56	11
auto[0]	values[1]	values[4]	392	1			T46	19		T198	11		T48	32
auto[0]	values[1]	values[5]	153	1			T16	19		T48	12		T190	9
auto[0]	values[1]	values[6]	198	1			T16	11		T47	9		T56	12
auto[0]	values[1]	values[7]	333	1			T15	9		T93	8		T231	11
auto[0]	values[2]	values[0]	265	1			T56	13		T190	41		T192	11
auto[0]	values[2]	values[1]	210	1			T16	13		T202	17		T194	8
auto[0]	values[2]	values[2]	207	1			T16	13		T26	14		T205	15
auto[0]	values[2]	values[3]	308	1			T20	20		T47	11		T56	9
auto[0]	values[2]	values[4]	208	1			T16	21		T20	15		T219	10
auto[0]	values[2]	values[5]	205	1			T10	10		T16	13		T189	44
auto[0]	values[2]	values[6]	169	1			T15	15		T134	13		T56	11
auto[0]	values[2]	values[7]	62	1			T96	7		T232	3		T161	13
auto[0]	values[3]	values[0]	310	1			T16	8		T26	16		T56	52
auto[0]	values[3]	values[1]	312	1			T15	17		T202	31		T93	10
auto[0]	values[3]	values[2]	125	1			T233	2		T190	13		T234	12
auto[0]	values[3]	values[3]	442	1			T7	12		T46	16		T56	30
auto[0]	values[3]	values[4]	278	1			T54	6		T46	17		T20	11
auto[0]	values[3]	values[5]	104	1			T12	16		T20	12		T198	9
auto[0]	values[3]	values[6]	144	1			T56	2		T82	23		T139	13
auto[0]	values[3]	values[7]	227	1			T47	14		T96	10		T235	4
auto[0]	values[4]	values[0]	293	1			T26	23		T167	134		T48	7
auto[0]	values[4]	values[1]	350	1			T190	43		T96	16		T34	12
auto[0]	values[4]	values[2]	218	1			T151	6		T48	17		T202	11
auto[0]	values[4]	values[3]	394	1			T16	32		T47	9		T190	4
auto[0]	values[4]	values[4]	267	1			T20	9		T47	17		T190	9
auto[0]	values[4]	values[5]	229	1			T222	12		T194	10		T236	12
auto[0]	values[4]	values[6]	197	1			T57	28		T182	6		T237	8
auto[0]	values[4]	values[7]	117	1			T47	10		T82	11		T238	6
auto[0]	values[5]	values[0]	436	1			T24	8		T56	13		T79	20
auto[0]	values[5]	values[1]	240	1			T239	18		T82	31		T194	12
auto[0]	values[5]	values[2]	167	1			T240	15		T210	15		T241	16
auto[0]	values[5]	values[3]	246	1			T26	8		T47	12		T87	11
auto[0]	values[5]	values[4]	408	1			T26	6		T167	10		T242	6
auto[0]	values[5]	values[5]	187	1			T16	11		T47	15		T93	13
auto[0]	values[5]	values[6]	105	1			T26	15		T192	12		T243	6
auto[0]	values[5]	values[7]	235	1			T45	10		T46	10		T137	2
auto[0]	values[6]	values[0]	315	1			T16	11		T45	11		T26	16
auto[0]	values[6]	values[1]	190	1			T244	14		T82	11		T245	15
auto[0]	values[6]	values[2]	239	1			T16	9		T52	12		T47	8
auto[0]	values[6]	values[3]	262	1			T46	19		T205	10		T87	46
auto[0]	values[6]	values[4]	466	1			T196	18		T87	9		T191	22
auto[0]	values[6]	values[5]	223	1			T26	6		T167	13		T219	14
auto[0]	values[6]	values[6]	239	1			T220	17		T246	4		T247	11
auto[0]	values[6]	values[7]	310	1			T16	10		T46	12		T219	11
auto[0]	values[7]	values[0]	258	1			T29	13		T46	9		T20	14
auto[0]	values[7]	values[1]	295	1			T37	20		T229	14		T48	11
auto[0]	values[7]	values[2]	310	1			T20	8		T248	22		T82	15
auto[0]	values[7]	values[3]	242	1			T46	14		T191	14		T33	12
auto[0]	values[7]	values[4]	347	1			T46	8		T87	24		T203	10
auto[0]	values[7]	values[5]	305	1			T26	11		T48	16		T192	27
auto[0]	values[7]	values[6]	200	1			T16	12		T26	18		T87	10
auto[0]	values[7]	values[7]	274	1			T218	24		T190	15		T191	10
auto[1]	values[0]	values[0]	209	1			T152	14		T46	11		T26	5
auto[1]	values[0]	values[1]	68	1			T46	7		T48	10		T59	13
auto[1]	values[0]	values[2]	153	1			T222	12		T35	10		T139	6
auto[1]	values[0]	values[3]	112	1			T15	7		T46	1		T20	3
auto[1]	values[0]	values[4]	104	1			T15	11		T48	8		T191	11
auto[1]	values[0]	values[5]	141	1			T15	15		T96	7		T43	10
auto[1]	values[0]	values[6]	121	1			T46	10		T190	8		T202	5
auto[1]	values[0]	values[7]	179	1			T87	5		T93	6		T82	6
auto[1]	values[1]	values[0]	172	1			T46	11		T20	4		T87	31
auto[1]	values[1]	values[1]	192	1			T134	7		T191	9		T82	7
auto[1]	values[1]	values[2]	177	1			T98	7		T203	11		T217	11
auto[1]	values[1]	values[3]	194	1			T45	4		T167	37		T56	85
auto[1]	values[1]	values[4]	176	1			T46	3		T198	9		T48	10
auto[1]	values[1]	values[5]	80	1			T16	7		T48	9		T190	11
auto[1]	values[1]	values[6]	231	1			T16	17		T47	11		T56	21
auto[1]	values[1]	values[7]	247	1			T15	13		T93	12		T231	49
auto[1]	values[2]	values[0]	172	1			T56	14		T190	9		T192	9
auto[1]	values[2]	values[1]	136	1			T16	7		T202	8		T194	16
auto[1]	values[2]	values[2]	111	1			T16	10		T26	7		T205	5
auto[1]	values[2]	values[3]	261	1			T20	4		T47	9		T56	11
auto[1]	values[2]	values[4]	146	1			T16	6		T20	6		T219	10
auto[1]	values[2]	values[5]	147	1			T16	13		T189	5		T208	10
auto[1]	values[2]	values[6]	244	1			T15	5		T134	8		T56	50
auto[1]	values[2]	values[7]	127	1			T96	13		T232	68		T161	10
auto[1]	values[3]	values[0]	228	1			T16	13		T26	4		T55	26
auto[1]	values[3]	values[1]	199	1			T15	4		T202	10		T93	10
auto[1]	values[3]	values[2]	154	1			T249	22		T190	43		T250	2
auto[1]	values[3]	values[3]	235	1			T46	6		T56	5		T48	35
auto[1]	values[3]	values[4]	142	1			T46	5		T20	18		T56	7
auto[1]	values[3]	values[5]	79	1			T20	33		T198	11		T139	5
auto[1]	values[3]	values[6]	133	1			T56	39		T82	7		T204	10
auto[1]	values[3]	values[7]	209	1			T9	4		T47	6		T96	10
auto[1]	values[4]	values[0]	208	1			T26	21		T167	4		T48	103
auto[1]	values[4]	values[1]	213	1			T190	8		T96	4		T34	8
auto[1]	values[4]	values[2]	212	1			T48	12		T202	9		T182	11
auto[1]	values[4]	values[3]	168	1			T16	5		T47	11		T190	16
auto[1]	values[4]	values[4]	224	1			T20	20		T47	3		T190	14
auto[1]	values[4]	values[5]	148	1			T222	8		T194	15		T245	20
auto[1]	values[4]	values[6]	161	1			T182	14		T231	14		T223	7
auto[1]	values[4]	values[7]	177	1			T47	10		T82	22		T59	8
auto[1]	values[5]	values[0]	229	1			T56	7		T59	8		T98	15
auto[1]	values[5]	values[1]	122	1			T82	7		T194	17		T203	7
auto[1]	values[5]	values[2]	100	1			T240	5		T210	5		T251	26
auto[1]	values[5]	values[3]	218	1			T26	12		T47	8		T87	43
auto[1]	values[5]	values[4]	248	1			T26	14		T167	10		T87	18
auto[1]	values[5]	values[5]	315	1			T16	9		T47	5		T93	7
auto[1]	values[5]	values[6]	118	1			T26	9		T252	18		T192	19
auto[1]	values[5]	values[7]	164	1			T45	10		T46	15		T40	18
auto[1]	values[6]	values[0]	151	1			T16	9		T45	14		T26	5
auto[1]	values[6]	values[1]	101	1			T82	18		T245	5		T62	18
auto[1]	values[6]	values[2]	204	1			T16	15		T52	8		T47	12
auto[1]	values[6]	values[3]	163	1			T46	6		T205	10		T87	10
auto[1]	values[6]	values[4]	354	1			T212	16		T87	72		T191	18
auto[1]	values[6]	values[5]	172	1			T26	14		T167	7		T219	6
auto[1]	values[6]	values[6]	69	1			T220	4		T247	9		T253	5
auto[1]	values[6]	values[7]	347	1			T16	12		T46	10		T219	9
auto[1]	values[7]	values[0]	224	1			T29	7		T46	12		T20	6
auto[1]	values[7]	values[1]	106	1			T48	9		T191	5		T35	7
auto[1]	values[7]	values[2]	129	1			T20	15		T82	7		T33	14
auto[1]	values[7]	values[3]	132	1			T46	9		T191	6		T33	8
auto[1]	values[7]	values[4]	237	1			T46	12		T87	31		T203	10
auto[1]	values[7]	values[5]	174	1			T26	9		T48	10		T192	5
auto[1]	values[7]	values[6]	120	1			T16	9		T26	6		T87	26
auto[1]	values[7]	values[7]	145	1			T190	5		T191	10		T93	11