Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	336	1			T10	6		T15	3		T16	4
auto[ReadAddrCrossIntoMailbox]	240	1			T15	2		T46	3		T26	3
auto[ReadAddrCrossOutOfMailbox]	276	1			T16	3		T46	3		T26	8
auto[ReadAddrCrossAllMailbox]	172	1			T15	1		T16	1		T54	2
auto[ReadAddrOutsideMailbox]	3335	1			T7	12		T12	2		T15	19

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2110

1

T7

6

T10

3

T12

1

auto[1]

2249

1

T7

6

T10

3

T12

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	749	1			T7	6		T15	5		T16	5
read_ops[0x0b]	727	1			T7	2		T15	2		T16	10
read_ops[0x3b]	714	1			T10	2		T15	4		T16	5
read_ops[0x6b]	714	1			T7	4		T10	2		T15	8
read_ops[0xbb]	731	1			T12	2		T15	1		T16	11
read_ops[0xeb]	724	1			T10	2		T15	5		T16	9

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	22	1			T16	1		T47	1		T190	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T15	1		T47	1		T190	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	13	1			T46	1		T203	2		T139	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T15	1		T26	1		T56	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T48	1		T226	1		T87	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T26	2		T20	1		T56	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T46	1		T47	1		T56	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T20	1		T47	1		T254	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	315	1			T7	3		T15	1		T16	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	277	1			T7	3		T15	2		T16	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T54	1		T46	1		T47	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T16	1		T54	1		T26	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T47	1		T56	1		T87	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T20	1		T190	1		T191	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T87	1		T93	1		T222	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T46	1		T20	2		T167	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T54	1		T192	1		T222	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T54	1		T48	1		T87	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	257	1			T7	1		T15	1		T16	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	285	1			T7	1		T15	1		T16	6
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	17	1			T10	1		T17	1		T20	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T10	1		T17	1		T29	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T46	1		T20	1		T47	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T56	1		T198	1		T48	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T47	2		T191	1		T194	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T190	1		T96	2		T222	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	9	1			T15	1		T47	1		T226	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T45	1		T226	1		T190	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	274	1			T15	3		T16	2		T46	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	272	1			T16	3		T45	1		T46	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	16	1			T10	1		T47	2		T229	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	23	1			T10	1		T229	1		T211	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T20	1		T47	1		T190	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T15	1		T47	1		T48	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T16	1		T46	2		T229	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T20	1		T47	1		T229	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T190	1		T82	1		T194	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T16	1		T87	1		T192	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	249	1			T7	2		T15	3		T16	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	302	1			T7	2		T15	4		T16	7
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T16	2		T18	1		T46	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T18	1		T26	1		T47	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T26	2		T87	1		T192	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T46	1		T93	1		T82	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T26	5		T87	2		T254	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	12	1			T48	1		T190	1		T254	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T87	1		T255	1		T220	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T20	1		T202	1		T96	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	298	1			T12	1		T16	4		T53	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	277	1			T12	1		T15	1		T16	5
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T10	1		T17	1		T229	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T10	1		T15	2		T17	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T20	1		T47	1		T229	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T20	1		T47	2		T229	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T16	2		T26	1		T47	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T20	1		T47	1		T48	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	8	1			T229	1		T254	2		T33	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T46	1		T229	1		T254	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	238	1			T15	1		T16	1		T17	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	291	1			T15	2		T16	6		T17	1