Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3623	1			T16	111		T57	28		T46	47
values[1]	3253	1			T15	62		T53	20		T45	33
values[2]	3166	1			T7	12		T10	10		T15	20
values[3]	3078	1			T16	86		T29	20		T46	85
values[4]	3558	1			T15	21		T16	26		T17	10
values[5]	3042	1			T16	48		T45	45		T46	20
values[6]	3823	1			T12	16		T15	20		T26	65
values[7]	3803	1			T9	4		T54	6		T151	6

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3075	1			T16	20		T45	33		T46	21
values[1]	3338	1			T7	12		T9	4		T15	20
values[2]	4089	1			T15	20		T54	6		T46	86
values[3]	3970	1			T16	110		T17	10		T53	20
values[4]	2941	1			T12	16		T15	22		T57	28
values[5]	3326	1			T15	41		T16	64		T152	14
values[6]	3289	1			T10	10		T15	20		T16	95
values[7]	3318	1			T151	6		T46	70		T26	61

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26646

1

T7

12

T9

4

T10

10

auto[1]

700

1

T15

4

T16

4

T45

3

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	454	1			T16	19		T190	20		T214	20
auto[0]	values[0]	values[1]	384	1			T46	22		T20	26		T40	18
auto[0]	values[0]	values[2]	405	1			T56	41		T205	20		T87	20
auto[0]	values[0]	values[3]	476	1			T16	48		T26	23		T191	20
auto[0]	values[0]	values[4]	415	1			T57	28		T20	29		T47	19
auto[0]	values[0]	values[5]	338	1			T16	21		T203	18		T139	38
auto[0]	values[0]	values[6]	513	1			T16	21		T26	19		T190	20
auto[0]	values[0]	values[7]	521	1			T46	25		T26	20		T56	29
auto[0]	values[1]	values[0]	278	1			T45	33		T47	16		T229	14
auto[0]	values[1]	values[1]	309	1			T56	25		T87	34		T192	19
auto[0]	values[1]	values[2]	701	1			T15	20		T46	19		T198	20
auto[0]	values[1]	values[3]	487	1			T53	20		T37	20		T192	25
auto[0]	values[1]	values[4]	427	1			T15	20		T26	20		T47	19
auto[0]	values[1]	values[5]	275	1			T96	19		T203	40		T215	20
auto[0]	values[1]	values[6]	201	1			T15	20		T191	16		T202	41
auto[0]	values[1]	values[7]	508	1			T20	20		T56	35		T33	100
auto[0]	values[2]	values[0]	215	1			T96	19		T256	20		T210	18
auto[0]	values[2]	values[1]	518	1			T7	12		T15	20		T134	20
auto[0]	values[2]	values[2]	334	1			T46	21		T226	8		T194	29
auto[0]	values[2]	values[3]	407	1			T16	23		T167	47		T82	31
auto[0]	values[2]	values[4]	315	1			T52	19		T198	19		T222	22
auto[0]	values[2]	values[5]	377	1			T152	14		T190	20		T202	25
auto[0]	values[2]	values[6]	489	1			T10	10		T16	20		T26	21
auto[0]	values[2]	values[7]	431	1			T56	61		T233	2		T190	75
auto[0]	values[3]	values[0]	382	1			T46	21		T26	19		T33	29
auto[0]	values[3]	values[1]	496	1			T46	44		T249	22		T257	10
auto[0]	values[3]	values[2]	340	1			T82	20		T243	6		T194	22
auto[0]	values[3]	values[3]	391	1			T16	37		T29	20		T193	26
auto[0]	values[3]	values[4]	454	1			T196	18		T202	25		T84	4
auto[0]	values[3]	values[5]	423	1			T16	22		T56	20		T258	16
auto[0]	values[3]	values[6]	431	1			T16	26		T46	20		T259	12
auto[0]	values[3]	values[7]	87	1			T242	6		T93	20		T61	19
auto[0]	values[4]	values[0]	418	1			T167	137		T56	96		T253	39
auto[0]	values[4]	values[1]	508	1			T16	26		T18	4		T20	23
auto[0]	values[4]	values[2]	637	1			T46	21		T47	36		T227	10
auto[0]	values[4]	values[3]	312	1			T17	10		T24	8		T190	50
auto[0]	values[4]	values[4]	346	1			T200	6		T260	14		T191	19
auto[0]	values[4]	values[5]	363	1			T15	20		T26	21		T191	20
auto[0]	values[4]	values[6]	373	1			T190	50		T93	20		T96	20
auto[0]	values[4]	values[7]	519	1			T46	42		T191	20		T248	22
auto[0]	values[5]	values[0]	404	1			T87	34		T219	20		T96	20
auto[0]	values[5]	values[1]	322	1			T48	41		T93	19		T231	59
auto[0]	values[5]	values[2]	375	1			T46	20		T192	30		T261	14
auto[0]	values[5]	values[3]	329	1			T45	42		T20	23		T87	32
auto[0]	values[5]	values[4]	289	1			T211	14		T198	20		T48	56
auto[0]	values[5]	values[5]	554	1			T16	20		T198	20		T202	28
auto[0]	values[5]	values[6]	328	1			T16	28		T134	21		T20	29
auto[0]	values[5]	values[7]	369	1			T48	44		T87	41		T98	20
auto[0]	values[6]	values[0]	425	1			T47	19		T48	29		T96	19
auto[0]	values[6]	values[1]	425	1			T33	20		T237	8		T139	35
auto[0]	values[6]	values[2]	558	1			T56	37		T48	20		T87	35
auto[0]	values[6]	values[3]	900	1			T20	21		T47	20		T48	72
auto[0]	values[6]	values[4]	342	1			T12	16		T47	20		T194	20
auto[0]	values[6]	values[5]	499	1			T15	19		T20	20		T190	20
auto[0]	values[6]	values[6]	344	1			T26	22		T167	18		T56	20
auto[0]	values[6]	values[7]	226	1			T26	38		T55	14		T202	39
auto[0]	values[7]	values[0]	435	1			T190	76		T87	18		T191	14
auto[0]	values[7]	values[1]	304	1			T9	4		T46	20		T20	39
auto[0]	values[7]	values[2]	627	1			T54	6		T26	18		T48	21
auto[0]	values[7]	values[3]	563	1			T46	22		T137	2		T47	20
auto[0]	values[7]	values[4]	270	1			T190	20		T43	19		T215	20
auto[0]	values[7]	values[5]	404	1			T198	20		T59	20		T194	20
auto[0]	values[7]	values[6]	523	1			T93	19		T96	20		T231	59
auto[0]	values[7]	values[7]	573	1			T151	6		T56	58		T252	16
auto[1]	values[0]	values[0]	8	1			T16	1		T93	2		T210	1
auto[1]	values[0]	values[1]	11	1			T20	3		T96	2		T223	3
auto[1]	values[0]	values[2]	14	1			T191	1		T223	2		T262	5
auto[1]	values[0]	values[3]	10	1			T16	1		T26	1		T263	1
auto[1]	values[0]	values[4]	14	1			T47	1		T87	1		T93	1
auto[1]	values[0]	values[5]	20	1			T203	2		T139	2		T264	4
auto[1]	values[0]	values[6]	22	1			T26	1		T192	2		T96	1
auto[1]	values[0]	values[7]	18	1			T56	4		T194	1		T139	1
auto[1]	values[1]	values[0]	5	1			T47	4		T208	1		-	-
auto[1]	values[1]	values[1]	6	1			T56	1		T87	1		T192	1
auto[1]	values[1]	values[2]	9	1			T46	2		T33	1		T265	3
auto[1]	values[1]	values[3]	12	1			T192	1		T98	1		T253	2
auto[1]	values[1]	values[4]	8	1			T15	2		T47	1		T160	1
auto[1]	values[1]	values[5]	14	1			T96	1		T251	3		T266	4
auto[1]	values[1]	values[6]	7	1			T191	4		T223	1		T267	2
auto[1]	values[1]	values[7]	6	1			T33	1		T268	1		T262	1
auto[1]	values[2]	values[0]	4	1			T96	1		T210	2		T265	1
auto[1]	values[2]	values[1]	8	1			T96	1		T231	1		T269	2
auto[1]	values[2]	values[2]	15	1			T46	2		T210	1		T208	2
auto[1]	values[2]	values[3]	12	1			T16	1		T82	2		T270	1
auto[1]	values[2]	values[4]	7	1			T52	1		T198	1		T194	1
auto[1]	values[2]	values[5]	11	1			T202	2		T82	2		T271	1
auto[1]	values[2]	values[6]	14	1			T240	2		T189	1		T272	2
auto[1]	values[2]	values[7]	9	1			T190	2		T191	2		T34	1
auto[1]	values[3]	values[0]	13	1			T26	1		T33	1		T251	5
auto[1]	values[3]	values[1]	15	1			T43	2		T272	1		T62	1
auto[1]	values[3]	values[2]	8	1			T203	1		T35	3		T263	1
auto[1]	values[3]	values[3]	9	1			T43	1		T215	2		T195	3
auto[1]	values[3]	values[4]	11	1			T220	1		T43	5		T62	1
auto[1]	values[3]	values[5]	10	1			T16	1		T61	1		T273	2
auto[1]	values[3]	values[6]	7	1			T82	1		T33	2		T268	1
auto[1]	values[3]	values[7]	1	1			T61	1		-	-		-	-
auto[1]	values[4]	values[0]	3	1			T167	1		T253	1		T63	1
auto[1]	values[4]	values[1]	7	1			T205	1		T59	2		T274	3
auto[1]	values[4]	values[2]	27	1			T46	1		T47	4		T275	4
auto[1]	values[4]	values[3]	8	1			T190	1		T208	2		T276	1
auto[1]	values[4]	values[4]	10	1			T191	1		T60	4		T253	1
auto[1]	values[4]	values[5]	11	1			T15	1		T26	3		T228	2
auto[1]	values[4]	values[6]	8	1			T217	1		T277	2		T278	2
auto[1]	values[4]	values[7]	8	1			T46	3		T82	1		T223	1
auto[1]	values[5]	values[0]	7	1			T240	1		T245	2		T216	2
auto[1]	values[5]	values[1]	9	1			T48	1		T93	1		T231	1
auto[1]	values[5]	values[2]	12	1			T192	2		T33	2		T279	4
auto[1]	values[5]	values[3]	13	1			T45	3		T20	1		T35	2
auto[1]	values[5]	values[4]	9	1			T48	3		T265	1		T280	1
auto[1]	values[5]	values[5]	8	1			T231	1		T272	1		T273	1
auto[1]	values[5]	values[6]	6	1			T98	3		T208	1		T232	1
auto[1]	values[5]	values[7]	8	1			T231	3		T35	1		T265	2
auto[1]	values[6]	values[0]	12	1			T47	1		T96	1		T210	2
auto[1]	values[6]	values[1]	5	1			T240	2		T60	1		T63	1
auto[1]	values[6]	values[2]	14	1			T87	1		T192	3		T82	1
auto[1]	values[6]	values[3]	26	1			T48	1		T190	2		T33	1
auto[1]	values[6]	values[4]	13	1			T210	1		T247	7		T61	1
auto[1]	values[6]	values[5]	10	1			T15	1		T228	1		T139	1
auto[1]	values[6]	values[6]	5	1			T26	2		T167	2		T60	1
auto[1]	values[6]	values[7]	19	1			T26	3		T55	12		T195	1
auto[1]	values[7]	values[0]	12	1			T87	2		T191	6		T61	2
auto[1]	values[7]	values[1]	11	1			T20	6		T82	1		T61	2
auto[1]	values[7]	values[2]	13	1			T26	2		T48	1		T87	2
auto[1]	values[7]	values[3]	15	1			T205	1		T87	3		T217	2
auto[1]	values[7]	values[4]	11	1			T43	1		T195	1		T61	1
auto[1]	values[7]	values[5]	9	1			T203	2		T231	1		T265	2
auto[1]	values[7]	values[6]	18	1			T93	1		T281	4		T35	1
auto[1]	values[7]	values[7]	15	1			T56	2		T252	2		T35	1