Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	773	1			T52	4		T19	14		T20	17
all_values[1]	773	1			T52	4		T19	14		T20	17
all_values[2]	773	1			T52	4		T19	14		T20	17
all_values[3]	773	1			T52	4		T19	14		T20	17
all_values[4]	773	1			T52	4		T19	14		T20	17
all_values[5]	773	1			T52	4		T19	14		T20	17
all_values[6]	773	1			T52	4		T19	14		T20	17
all_values[7]	773	1			T52	4		T19	14		T20	17

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3351

1

T52

20

T19

57

T20

65

auto[1]

2833

1

T52

12

T19

55

T20

71

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2523

1

T52

12

T19

53

T20

60

auto[1]

3661

1

T52

20

T19

59

T20

76

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3526

1

T52

22

T19

66

T20

74

auto[1]

2658

1

T52

10

T19

46

T20

62

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	166	1			T52	1		T19	2		T20	5
all_values[0]	auto[0]	auto[0]	auto[1]	85	1			T52	1		T19	1		T20	2
all_values[0]	auto[0]	auto[1]	auto[0]	151	1			T19	4		T20	3		T21	2
all_values[0]	auto[0]	auto[1]	auto[1]	66	1			T52	1		T20	2		T32	1
all_values[0]	auto[1]	auto[0]	auto[1]	180	1			T52	1		T19	3		T20	1
all_values[0]	auto[1]	auto[1]	auto[1]	125	1			T19	4		T20	4		T21	1
all_values[1]	auto[0]	auto[0]	auto[0]	191	1			T52	2		T19	6		T20	8
all_values[1]	auto[0]	auto[0]	auto[1]	65	1			T21	3		T22	2		T32	3
all_values[1]	auto[0]	auto[1]	auto[0]	132	1			T52	1		T19	2		T20	4
all_values[1]	auto[0]	auto[1]	auto[1]	69	1			T19	1		T20	1		T32	1
all_values[1]	auto[1]	auto[0]	auto[1]	159	1			T19	2		T20	3		T21	4
all_values[1]	auto[1]	auto[1]	auto[1]	157	1			T52	1		T19	3		T20	1
all_values[2]	auto[0]	auto[0]	auto[0]	165	1			T19	1		T20	3		T21	2
all_values[2]	auto[0]	auto[0]	auto[1]	84	1			T19	1		T20	1		T21	2
all_values[2]	auto[0]	auto[1]	auto[0]	120	1			T19	5		T20	2		T21	1
all_values[2]	auto[0]	auto[1]	auto[1]	61	1			T52	2		T19	1		T20	2
all_values[2]	auto[1]	auto[0]	auto[1]	193	1			T52	2		T19	6		T20	4
all_values[2]	auto[1]	auto[1]	auto[1]	150	1			T20	5		T21	1		T22	2
all_values[3]	auto[0]	auto[0]	auto[0]	187	1			T19	2		T20	3		T21	1
all_values[3]	auto[0]	auto[0]	auto[1]	64	1			T19	1		T20	1		T21	1
all_values[3]	auto[0]	auto[1]	auto[0]	147	1			T19	4		T20	2		T21	1
all_values[3]	auto[0]	auto[1]	auto[1]	65	1			T52	2		T19	2		T20	3
all_values[3]	auto[1]	auto[0]	auto[1]	173	1			T52	2		T19	2		T20	1
all_values[3]	auto[1]	auto[1]	auto[1]	137	1			T19	3		T20	7		T21	3
all_values[4]	auto[0]	auto[0]	auto[0]	143	1			T19	5		T20	2		T22	2
all_values[4]	auto[0]	auto[0]	auto[1]	88	1			T52	3		T19	1		T21	1
all_values[4]	auto[0]	auto[1]	auto[0]	104	1			T19	2		T20	4		T22	2
all_values[4]	auto[0]	auto[1]	auto[1]	76	1			T19	1		T21	2		T22	2
all_values[4]	auto[1]	auto[0]	auto[1]	201	1			T52	1		T19	4		T20	6
all_values[4]	auto[1]	auto[1]	auto[1]	161	1			T19	1		T20	5		T21	1
all_values[5]	auto[0]	auto[0]	auto[0]	234	1			T52	1		T19	4		T20	3
all_values[5]	auto[0]	auto[1]	auto[0]	205	1			T52	2		T19	4		T20	4
all_values[5]	auto[1]	auto[0]	auto[1]	184	1			T19	1		T20	5		T21	1
all_values[5]	auto[1]	auto[1]	auto[1]	150	1			T52	1		T19	5		T20	5
all_values[6]	auto[0]	auto[0]	auto[0]	150	1			T52	2		T19	3		T20	7
all_values[6]	auto[0]	auto[0]	auto[1]	64	1			T19	2		T22	3		T32	1
all_values[6]	auto[0]	auto[1]	auto[0]	127	1			T52	1		T19	1		T20	3
all_values[6]	auto[0]	auto[1]	auto[1]	74	1			T19	1		T20	1		T22	1
all_values[6]	auto[1]	auto[0]	auto[1]	187	1			T52	1		T19	4		T20	1
all_values[6]	auto[1]	auto[1]	auto[1]	171	1			T19	3		T20	5		T21	1
all_values[7]	auto[0]	auto[0]	auto[0]	151	1			T52	2		T19	4		T20	2
all_values[7]	auto[0]	auto[0]	auto[1]	69	1			T52	1		T20	1		T32	1
all_values[7]	auto[0]	auto[1]	auto[0]	150	1			T19	4		T20	5		T21	2
all_values[7]	auto[0]	auto[1]	auto[1]	73	1			T19	1		T21	1		T22	4
all_values[7]	auto[1]	auto[0]	auto[1]	168	1			T19	2		T20	6		T21	2
all_values[7]	auto[1]	auto[1]	auto[1]	162	1			T52	1		T19	3		T20	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal