Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1784

1

T2

5

T3

6

T6

4

auto[1]

1760

1

T2

7

T3

9

T6

3

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2035

1

T2

12

T3

11

T15

15

auto[1]

1509

1

T3

4

T6

7

T27

10

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2759

1

T2

7

T3

8

T6

7

auto[1]

785

1

T2

5

T3

7

T15

6

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	735	1			T2	3		T3	4		T6	2
valid[1]	709	1			T3	2		T6	1		T15	3
valid[2]	719	1			T2	4		T3	4		T6	3
valid[3]	683	1			T2	2		T3	3		T15	2
valid[4]	698	1			T2	3		T3	2		T6	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	129	1			T44	1		T46	1		T42	1
auto[0]	auto[0]	valid[0]	auto[1]	153	1			T6	1		T27	1		T29	1
auto[0]	auto[0]	valid[1]	auto[0]	126	1			T3	1		T15	1		T29	1
auto[0]	auto[0]	valid[1]	auto[1]	173	1			T27	1		T92	2		T95	6
auto[0]	auto[0]	valid[2]	auto[0]	139	1			T2	1		T15	2		T52	1
auto[0]	auto[0]	valid[2]	auto[1]	150	1			T6	2		T27	1		T92	2
auto[0]	auto[0]	valid[3]	auto[0]	129	1			T2	1		T3	2		T46	1
auto[0]	auto[0]	valid[3]	auto[1]	130	1			T27	1		T28	1		T30	1
auto[0]	auto[0]	valid[4]	auto[0]	122	1			T2	2		T16	1		T46	2
auto[0]	auto[0]	valid[4]	auto[1]	134	1			T6	1		T27	1		T29	1
auto[0]	auto[1]	valid[0]	auto[0]	128	1			T2	2		T3	1		T15	1
auto[0]	auto[1]	valid[0]	auto[1]	154	1			T6	1		T28	1		T30	2
auto[0]	auto[1]	valid[1]	auto[0]	115	1			T15	2		T16	2		T52	1
auto[0]	auto[1]	valid[1]	auto[1]	152	1			T3	1		T6	1		T27	1
auto[0]	auto[1]	valid[2]	auto[0]	112	1			T2	1		T15	2		T16	1
auto[0]	auto[1]	valid[2]	auto[1]	153	1			T3	1		T6	1		T27	1
auto[0]	auto[1]	valid[3]	auto[0]	123	1			T15	1		T16	1		T42	1
auto[0]	auto[1]	valid[3]	auto[1]	146	1			T3	1		T30	2		T92	3
auto[0]	auto[1]	valid[4]	auto[0]	127	1			T16	1		T29	1		T46	3
auto[0]	auto[1]	valid[4]	auto[1]	164	1			T3	1		T27	3		T28	1
auto[1]	auto[0]	valid[0]	auto[0]	94	1			T3	1		T16	1		T42	2
auto[1]	auto[0]	valid[1]	auto[0]	75	1			T42	1		T294	1		T292	1
auto[1]	auto[0]	valid[2]	auto[0]	81	1			T3	2		T46	1		T42	2
auto[1]	auto[0]	valid[3]	auto[0]	77	1			T16	1		T52	2		T42	1
auto[1]	auto[0]	valid[4]	auto[0]	72	1			T2	1		T15	3		T46	1
auto[1]	auto[1]	valid[0]	auto[0]	77	1			T2	1		T3	2		T44	1
auto[1]	auto[1]	valid[1]	auto[0]	68	1			T42	1		T134	1		T294	2
auto[1]	auto[1]	valid[2]	auto[0]	84	1			T2	2		T3	1		T15	2
auto[1]	auto[1]	valid[3]	auto[0]	78	1			T2	1		T15	1		T16	1
auto[1]	auto[1]	valid[4]	auto[0]	79	1			T3	1		T46	1		T52	3

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal