Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50589

1

T2

300

T3

361

T11

5

auto[1]

15492

1

T3

76

T6

7

T27

10

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47704

1

T2

211

T3

310

T6

7

auto[1]

18377

1

T2

89

T3

127

T11

4

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34132	1			T2	157		T3	232		T6	7
others[1]	5554	1			T2	26		T3	27		T15	24
others[2]	5605	1			T2	25		T3	41		T15	24
others[3]	6227	1			T2	27		T3	40		T13	1
interest[1]	3664	1			T2	15		T3	34		T15	14
interest[4]	22336	1			T2	108		T3	158		T6	7
interest[64]	10899	1			T2	50		T3	63		T11	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16645	1			T2	112		T3	127		T15	79
auto[0]	auto[0]	others[1]	2701	1			T2	18		T3	14		T15	11
auto[0]	auto[0]	others[2]	2704	1			T2	16		T3	21		T15	16
auto[0]	auto[0]	others[3]	3048	1			T2	19		T3	22		T15	15
auto[0]	auto[0]	interest[1]	1762	1			T2	12		T3	17		T15	9
auto[0]	auto[0]	interest[4]	10868	1			T2	77		T3	89		T15	47
auto[0]	auto[0]	interest[64]	5352	1			T2	34		T3	33		T11	1
auto[0]	auto[1]	others[0]	8087	1			T3	46		T6	7		T27	10
auto[0]	auto[1]	others[1]	1291	1			T3	4		T28	5		T92	20
auto[0]	auto[1]	others[2]	1333	1			T3	5		T28	5		T29	4
auto[0]	auto[1]	others[3]	1410	1			T3	5		T28	7		T29	1
auto[0]	auto[1]	interest[1]	870	1			T3	6		T29	2		T92	5
auto[0]	auto[1]	interest[4]	5357	1			T3	31		T6	7		T27	10
auto[0]	auto[1]	interest[64]	2501	1			T3	10		T28	13		T29	1
auto[1]	auto[0]	others[0]	9400	1			T2	45		T3	59		T11	4
auto[1]	auto[0]	others[1]	1562	1			T2	8		T3	9		T15	13
auto[1]	auto[0]	others[2]	1568	1			T2	9		T3	15		T15	8
auto[1]	auto[0]	others[3]	1769	1			T2	8		T3	13		T13	1
auto[1]	auto[0]	interest[1]	1032	1			T2	3		T3	11		T15	5
auto[1]	auto[0]	interest[4]	6111	1			T2	31		T3	38		T11	3
auto[1]	auto[0]	interest[64]	3046	1			T2	16		T3	20		T15	21

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal