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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.39 93.99 98.62 89.36 97.23 95.45 99.26


Total test records in report: 1129
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T175 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1201611661 Jul 14 07:07:34 PM PDT 24 Jul 14 07:07:55 PM PDT 24 2497477993 ps
T123 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2721313144 Jul 14 07:07:20 PM PDT 24 Jul 14 07:07:24 PM PDT 24 20764192 ps
T1026 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1161053879 Jul 14 07:07:24 PM PDT 24 Jul 14 07:07:28 PM PDT 24 65863766 ps
T1027 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3748140233 Jul 14 07:07:22 PM PDT 24 Jul 14 07:07:26 PM PDT 24 27921792 ps
T157 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2121428382 Jul 14 07:07:35 PM PDT 24 Jul 14 07:07:39 PM PDT 24 82919724 ps
T1028 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1372829771 Jul 14 07:07:26 PM PDT 24 Jul 14 07:07:29 PM PDT 24 12931801 ps
T1029 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3080500929 Jul 14 07:07:36 PM PDT 24 Jul 14 07:07:40 PM PDT 24 13405870 ps
T1030 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1316717621 Jul 14 07:07:25 PM PDT 24 Jul 14 07:07:30 PM PDT 24 325762998 ps
T176 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.456237901 Jul 14 07:07:21 PM PDT 24 Jul 14 07:07:31 PM PDT 24 1145678526 ps
T1031 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1183031399 Jul 14 07:07:41 PM PDT 24 Jul 14 07:07:50 PM PDT 24 321040990 ps
T1032 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3168247663 Jul 14 07:07:33 PM PDT 24 Jul 14 07:07:35 PM PDT 24 16993342 ps
T1033 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1567667812 Jul 14 07:07:39 PM PDT 24 Jul 14 07:07:45 PM PDT 24 14186556 ps
T1034 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2066613532 Jul 14 07:07:15 PM PDT 24 Jul 14 07:07:18 PM PDT 24 40080430 ps
T158 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4218062939 Jul 14 07:07:20 PM PDT 24 Jul 14 07:07:47 PM PDT 24 10236811996 ps
T124 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2041588427 Jul 14 07:07:25 PM PDT 24 Jul 14 07:07:30 PM PDT 24 210473065 ps
T1035 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3496151671 Jul 14 07:07:39 PM PDT 24 Jul 14 07:07:46 PM PDT 24 18110806 ps
T111 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.929949532 Jul 14 07:07:38 PM PDT 24 Jul 14 07:07:46 PM PDT 24 201209016 ps
T125 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3040221680 Jul 14 07:07:23 PM PDT 24 Jul 14 07:07:40 PM PDT 24 237326587 ps
T1036 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1923959386 Jul 14 07:07:26 PM PDT 24 Jul 14 07:07:30 PM PDT 24 156187780 ps
T1037 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3660633472 Jul 14 07:07:40 PM PDT 24 Jul 14 07:07:46 PM PDT 24 14141026 ps
T181 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2873059017 Jul 14 07:07:40 PM PDT 24 Jul 14 07:08:00 PM PDT 24 2896112417 ps
T178 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3722130061 Jul 14 07:07:26 PM PDT 24 Jul 14 07:07:43 PM PDT 24 1149852405 ps
T1038 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3474843078 Jul 14 07:07:34 PM PDT 24 Jul 14 07:07:41 PM PDT 24 1322743541 ps
T1039 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1360651573 Jul 14 07:07:37 PM PDT 24 Jul 14 07:07:41 PM PDT 24 51920170 ps
T1040 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.412901433 Jul 14 07:07:26 PM PDT 24 Jul 14 07:07:36 PM PDT 24 648761417 ps
T126 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1176084441 Jul 14 07:07:23 PM PDT 24 Jul 14 07:07:29 PM PDT 24 104448832 ps
T114 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.96471087 Jul 14 07:07:35 PM PDT 24 Jul 14 07:07:40 PM PDT 24 153628259 ps
T177 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.66663540 Jul 14 07:07:36 PM PDT 24 Jul 14 07:07:50 PM PDT 24 391956037 ps
T179 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2894762379 Jul 14 07:07:37 PM PDT 24 Jul 14 07:08:01 PM PDT 24 1818392637 ps
T1041 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.4056363635 Jul 14 07:07:41 PM PDT 24 Jul 14 07:07:50 PM PDT 24 203066778 ps
T1042 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.854887126 Jul 14 07:07:15 PM PDT 24 Jul 14 07:07:20 PM PDT 24 425215222 ps
T1043 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3017759955 Jul 14 07:07:35 PM PDT 24 Jul 14 07:07:37 PM PDT 24 14783080 ps
T180 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2924204918 Jul 14 07:07:22 PM PDT 24 Jul 14 07:07:44 PM PDT 24 882958093 ps
T1044 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3058568435 Jul 14 07:07:37 PM PDT 24 Jul 14 07:07:43 PM PDT 24 12551062 ps
T1045 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2446079923 Jul 14 07:07:41 PM PDT 24 Jul 14 07:07:47 PM PDT 24 212399312 ps
T1046 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1635284902 Jul 14 07:07:13 PM PDT 24 Jul 14 07:07:18 PM PDT 24 263767286 ps
T1047 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3132543610 Jul 14 07:07:36 PM PDT 24 Jul 14 07:07:43 PM PDT 24 768644128 ps
T128 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1047148896 Jul 14 07:07:29 PM PDT 24 Jul 14 07:07:32 PM PDT 24 450867355 ps
T129 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1238762005 Jul 14 07:07:22 PM PDT 24 Jul 14 07:07:26 PM PDT 24 74138152 ps
T1048 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.212352568 Jul 14 07:07:20 PM PDT 24 Jul 14 07:07:22 PM PDT 24 79092640 ps
T130 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2597644497 Jul 14 07:07:25 PM PDT 24 Jul 14 07:07:29 PM PDT 24 30453668 ps
T1049 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1517434285 Jul 14 07:07:20 PM PDT 24 Jul 14 07:07:26 PM PDT 24 62505385 ps
T1050 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2807523098 Jul 14 07:07:35 PM PDT 24 Jul 14 07:07:41 PM PDT 24 215370827 ps
T1051 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1408717557 Jul 14 07:07:39 PM PDT 24 Jul 14 07:07:51 PM PDT 24 335123327 ps
T1052 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1708995961 Jul 14 07:07:37 PM PDT 24 Jul 14 07:07:42 PM PDT 24 203208953 ps
T1053 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2169222546 Jul 14 07:07:30 PM PDT 24 Jul 14 07:07:32 PM PDT 24 46292883 ps
T131 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2190308738 Jul 14 07:07:21 PM PDT 24 Jul 14 07:07:32 PM PDT 24 111456292 ps
T1054 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2367643324 Jul 14 07:07:40 PM PDT 24 Jul 14 07:07:46 PM PDT 24 34731023 ps
T1055 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.656201421 Jul 14 07:07:39 PM PDT 24 Jul 14 07:07:45 PM PDT 24 25043646 ps
T1056 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1482533424 Jul 14 07:07:34 PM PDT 24 Jul 14 07:07:38 PM PDT 24 135888053 ps
T115 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1186421685 Jul 14 07:07:13 PM PDT 24 Jul 14 07:07:21 PM PDT 24 991790621 ps
T1057 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2058761323 Jul 14 07:07:38 PM PDT 24 Jul 14 07:07:44 PM PDT 24 12747584 ps
T1058 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.997254061 Jul 14 07:07:20 PM PDT 24 Jul 14 07:07:45 PM PDT 24 5207963421 ps
T113 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2259989701 Jul 14 07:07:39 PM PDT 24 Jul 14 07:07:46 PM PDT 24 106884839 ps
T1059 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.4220951129 Jul 14 07:07:18 PM PDT 24 Jul 14 07:07:23 PM PDT 24 90452552 ps
T1060 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3293266760 Jul 14 07:07:37 PM PDT 24 Jul 14 07:07:43 PM PDT 24 56989483 ps
T1061 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4149281884 Jul 14 07:07:16 PM PDT 24 Jul 14 07:07:19 PM PDT 24 11196689 ps
T1062 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2629491731 Jul 14 07:07:40 PM PDT 24 Jul 14 07:07:47 PM PDT 24 33285255 ps
T1063 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2480246905 Jul 14 07:07:33 PM PDT 24 Jul 14 07:07:47 PM PDT 24 216236999 ps
T1064 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2590323381 Jul 14 07:07:21 PM PDT 24 Jul 14 07:07:26 PM PDT 24 437813865 ps
T1065 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2564952495 Jul 14 07:07:39 PM PDT 24 Jul 14 07:07:45 PM PDT 24 58741077 ps
T1066 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3950425561 Jul 14 07:07:21 PM PDT 24 Jul 14 07:07:24 PM PDT 24 19296576 ps
T1067 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1032666070 Jul 14 07:07:42 PM PDT 24 Jul 14 07:07:47 PM PDT 24 28189152 ps
T1068 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1286577496 Jul 14 07:07:27 PM PDT 24 Jul 14 07:07:37 PM PDT 24 1250534458 ps
T1069 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3166624166 Jul 14 07:07:34 PM PDT 24 Jul 14 07:07:38 PM PDT 24 101703010 ps
T1070 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1272484624 Jul 14 07:07:38 PM PDT 24 Jul 14 07:07:44 PM PDT 24 28448812 ps
T1071 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2041478734 Jul 14 07:07:19 PM PDT 24 Jul 14 07:07:23 PM PDT 24 140879112 ps
T1072 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3892459450 Jul 14 07:07:33 PM PDT 24 Jul 14 07:07:34 PM PDT 24 21527231 ps
T1073 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1068435716 Jul 14 07:07:32 PM PDT 24 Jul 14 07:07:37 PM PDT 24 4020437438 ps
T1074 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2125156016 Jul 14 07:07:15 PM PDT 24 Jul 14 07:07:18 PM PDT 24 25436581 ps
T173 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1419761969 Jul 14 07:07:21 PM PDT 24 Jul 14 07:07:27 PM PDT 24 135239474 ps
T1075 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2628393668 Jul 14 07:07:21 PM PDT 24 Jul 14 07:07:30 PM PDT 24 921729691 ps
T1076 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2594057506 Jul 14 07:07:38 PM PDT 24 Jul 14 07:07:44 PM PDT 24 16870650 ps
T1077 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3002113276 Jul 14 07:07:31 PM PDT 24 Jul 14 07:07:35 PM PDT 24 1289206450 ps
T1078 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2955982294 Jul 14 07:07:13 PM PDT 24 Jul 14 07:07:23 PM PDT 24 227135809 ps
T90 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.4129076266 Jul 14 07:07:24 PM PDT 24 Jul 14 07:07:28 PM PDT 24 32380982 ps
T1079 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.954161335 Jul 14 07:07:37 PM PDT 24 Jul 14 07:07:41 PM PDT 24 55550196 ps
T174 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.763185729 Jul 14 07:07:33 PM PDT 24 Jul 14 07:07:40 PM PDT 24 70747972 ps
T1080 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3832872002 Jul 14 07:07:15 PM PDT 24 Jul 14 07:07:19 PM PDT 24 62149220 ps
T1081 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.688291793 Jul 14 07:07:35 PM PDT 24 Jul 14 07:07:38 PM PDT 24 11484965 ps
T1082 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3926365467 Jul 14 07:07:24 PM PDT 24 Jul 14 07:07:27 PM PDT 24 18174805 ps
T1083 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1742749234 Jul 14 07:07:27 PM PDT 24 Jul 14 07:07:32 PM PDT 24 53862448 ps
T1084 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1641510811 Jul 14 07:07:15 PM PDT 24 Jul 14 07:07:19 PM PDT 24 59585902 ps
T1085 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1571070654 Jul 14 07:07:16 PM PDT 24 Jul 14 07:07:41 PM PDT 24 362788949 ps
T1086 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2988160304 Jul 14 07:07:21 PM PDT 24 Jul 14 07:07:24 PM PDT 24 63316499 ps
T1087 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.629982114 Jul 14 07:07:21 PM PDT 24 Jul 14 07:07:24 PM PDT 24 39091361 ps
T1088 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.75783147 Jul 14 07:07:14 PM PDT 24 Jul 14 07:07:17 PM PDT 24 16467698 ps
T1089 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2023406867 Jul 14 07:07:18 PM PDT 24 Jul 14 07:07:38 PM PDT 24 299836912 ps
T1090 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1759954594 Jul 14 07:07:33 PM PDT 24 Jul 14 07:07:34 PM PDT 24 31825034 ps
T1091 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2981626902 Jul 14 07:07:35 PM PDT 24 Jul 14 07:07:42 PM PDT 24 720395236 ps
T1092 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2975428558 Jul 14 07:07:34 PM PDT 24 Jul 14 07:07:36 PM PDT 24 35716933 ps
T1093 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2216688737 Jul 14 07:07:41 PM PDT 24 Jul 14 07:07:47 PM PDT 24 77711765 ps
T1094 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1072032714 Jul 14 07:07:38 PM PDT 24 Jul 14 07:07:44 PM PDT 24 27965063 ps
T1095 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.350492466 Jul 14 07:07:35 PM PDT 24 Jul 14 07:07:40 PM PDT 24 227317157 ps
T1096 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.928080939 Jul 14 07:07:22 PM PDT 24 Jul 14 07:07:25 PM PDT 24 15463549 ps
T1097 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1538730922 Jul 14 07:07:21 PM PDT 24 Jul 14 07:07:26 PM PDT 24 148965979 ps
T1098 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2901431151 Jul 14 07:07:19 PM PDT 24 Jul 14 07:07:26 PM PDT 24 423589224 ps
T1099 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1788732666 Jul 14 07:07:42 PM PDT 24 Jul 14 07:07:48 PM PDT 24 32834625 ps
T1100 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3042148989 Jul 14 07:07:24 PM PDT 24 Jul 14 07:07:27 PM PDT 24 69701742 ps
T1101 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1476705769 Jul 14 07:07:23 PM PDT 24 Jul 14 07:07:42 PM PDT 24 620525666 ps
T1102 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.853145461 Jul 14 07:07:26 PM PDT 24 Jul 14 07:07:32 PM PDT 24 102214464 ps
T1103 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.601638850 Jul 14 07:07:34 PM PDT 24 Jul 14 07:07:41 PM PDT 24 919596715 ps
T1104 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2361549188 Jul 14 07:07:19 PM PDT 24 Jul 14 07:07:46 PM PDT 24 7243004046 ps
T1105 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1952787871 Jul 14 07:07:26 PM PDT 24 Jul 14 07:07:31 PM PDT 24 185170794 ps
T1106 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2668061207 Jul 14 07:07:39 PM PDT 24 Jul 14 07:07:46 PM PDT 24 29248637 ps
T1107 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2210747424 Jul 14 07:07:29 PM PDT 24 Jul 14 07:07:30 PM PDT 24 13677805 ps
T1108 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4079986558 Jul 14 07:07:14 PM PDT 24 Jul 14 07:07:17 PM PDT 24 10131769 ps
T1109 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3160596422 Jul 14 07:07:33 PM PDT 24 Jul 14 07:07:35 PM PDT 24 17308313 ps
T1110 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3145840203 Jul 14 07:07:34 PM PDT 24 Jul 14 07:07:39 PM PDT 24 148768575 ps
T1111 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.555092978 Jul 14 07:07:39 PM PDT 24 Jul 14 07:07:45 PM PDT 24 17219844 ps
T1112 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3167171577 Jul 14 07:07:21 PM PDT 24 Jul 14 07:07:27 PM PDT 24 178361735 ps
T1113 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2904574004 Jul 14 07:07:37 PM PDT 24 Jul 14 07:07:42 PM PDT 24 13633222 ps
T1114 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2215050901 Jul 14 07:07:39 PM PDT 24 Jul 14 07:07:46 PM PDT 24 42048351 ps
T1115 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3521253106 Jul 14 07:07:41 PM PDT 24 Jul 14 07:07:49 PM PDT 24 43310361 ps
T1116 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3234045086 Jul 14 07:07:16 PM PDT 24 Jul 14 07:07:25 PM PDT 24 429916834 ps
T1117 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4155033104 Jul 14 07:07:20 PM PDT 24 Jul 14 07:07:24 PM PDT 24 39084700 ps
T91 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1257682881 Jul 14 07:07:24 PM PDT 24 Jul 14 07:07:27 PM PDT 24 23346740 ps
T1118 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1616595191 Jul 14 07:07:39 PM PDT 24 Jul 14 07:07:47 PM PDT 24 116376239 ps
T1119 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.258895844 Jul 14 07:07:35 PM PDT 24 Jul 14 07:07:38 PM PDT 24 107855208 ps
T1120 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3927178555 Jul 14 07:07:16 PM PDT 24 Jul 14 07:07:19 PM PDT 24 100221807 ps
T1121 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.263266497 Jul 14 07:07:15 PM PDT 24 Jul 14 07:07:25 PM PDT 24 629208387 ps
T1122 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3127361594 Jul 14 07:07:13 PM PDT 24 Jul 14 07:07:17 PM PDT 24 57506546 ps
T1123 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3783641416 Jul 14 07:07:26 PM PDT 24 Jul 14 07:07:32 PM PDT 24 121681860 ps
T1124 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1960635005 Jul 14 07:07:25 PM PDT 24 Jul 14 07:07:29 PM PDT 24 39815977 ps
T1125 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4192319364 Jul 14 07:07:26 PM PDT 24 Jul 14 07:07:31 PM PDT 24 315340203 ps
T1126 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2315279638 Jul 14 07:07:21 PM PDT 24 Jul 14 07:07:25 PM PDT 24 10988944 ps
T1127 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2624460254 Jul 14 07:07:34 PM PDT 24 Jul 14 07:07:40 PM PDT 24 168894570 ps
T1128 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1440001747 Jul 14 07:07:22 PM PDT 24 Jul 14 07:07:28 PM PDT 24 87992298 ps
T1129 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2490095226 Jul 14 07:07:40 PM PDT 24 Jul 14 07:07:46 PM PDT 24 38079203 ps

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3022383127
Short name T2
Test name
Test status
Simulation time 92196601626 ps
CPU time 180.48 seconds
Started Jul 14 06:56:50 PM PDT 24
Finished Jul 14 06:59:59 PM PDT 24
Peak memory 265612 kb
Host smart-e18a5aee-b9ec-4ed4-b2c5-c7300f9c38ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022383127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3022383127
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3414188020
Short name T52
Test name
Test status
Simulation time 65118344127 ps
CPU time 329.81 seconds
Started Jul 14 06:55:19 PM PDT 24
Finished Jul 14 07:00:51 PM PDT 24
Peak memory 260728 kb
Host smart-5be561d1-c017-41a4-a878-adc4c8084a0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414188020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3414188020
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2597294851
Short name T16
Test name
Test status
Simulation time 137281403054 ps
CPU time 336.08 seconds
Started Jul 14 06:55:27 PM PDT 24
Finished Jul 14 07:01:06 PM PDT 24
Peak memory 256476 kb
Host smart-28cdc7b4-9b04-4216-b298-821e5caf5820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597294851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2597294851
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.287278968
Short name T20
Test name
Test status
Simulation time 24477025348 ps
CPU time 183.81 seconds
Started Jul 14 06:55:10 PM PDT 24
Finished Jul 14 06:58:20 PM PDT 24
Peak memory 265684 kb
Host smart-806b1d53-a988-4084-a716-3afdb9f8d879
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287278968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.287278968
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3971791790
Short name T116
Test name
Test status
Simulation time 359949121 ps
CPU time 8.3 seconds
Started Jul 14 07:07:31 PM PDT 24
Finished Jul 14 07:07:39 PM PDT 24
Peak memory 216004 kb
Host smart-23b0dde3-c9e9-4329-9b95-2611067a92ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971791790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3971791790
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.79565422
Short name T71
Test name
Test status
Simulation time 34928555 ps
CPU time 0.73 seconds
Started Jul 14 06:54:41 PM PDT 24
Finished Jul 14 06:54:49 PM PDT 24
Peak memory 216108 kb
Host smart-acfa92dc-8807-412a-8d0c-4bbe3cab197c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79565422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.79565422
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3417169742
Short name T44
Test name
Test status
Simulation time 15379538968 ps
CPU time 72.54 seconds
Started Jul 14 06:55:23 PM PDT 24
Finished Jul 14 06:56:38 PM PDT 24
Peak memory 256340 kb
Host smart-a5210a3c-d66c-4d40-90bf-fe1c8d25a78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417169742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3417169742
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3397644015
Short name T46
Test name
Test status
Simulation time 416968837969 ps
CPU time 975.97 seconds
Started Jul 14 06:54:44 PM PDT 24
Finished Jul 14 07:11:04 PM PDT 24
Peak memory 265652 kb
Host smart-00bf203d-4fa8-4c6b-88af-1155d75ee441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397644015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3397644015
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.1971837816
Short name T96
Test name
Test status
Simulation time 3710460099 ps
CPU time 90.63 seconds
Started Jul 14 06:56:18 PM PDT 24
Finished Jul 14 06:57:54 PM PDT 24
Peak memory 257460 kb
Host smart-619ef6bb-75a1-4223-a90e-8381df3f9af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971837816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.1971837816
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1140875860
Short name T104
Test name
Test status
Simulation time 196574843 ps
CPU time 4.46 seconds
Started Jul 14 07:07:35 PM PDT 24
Finished Jul 14 07:07:41 PM PDT 24
Peak memory 216000 kb
Host smart-7d59b75c-2775-4c1b-a4f2-03720dd7e8fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140875860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1140875860
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2675177002
Short name T82
Test name
Test status
Simulation time 43678311714 ps
CPU time 191.56 seconds
Started Jul 14 06:55:43 PM PDT 24
Finished Jul 14 06:58:55 PM PDT 24
Peak memory 263596 kb
Host smart-c701a09f-2e74-4676-b6f9-81296b51a14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675177002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2675177002
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.381569075
Short name T26
Test name
Test status
Simulation time 57237870970 ps
CPU time 586.78 seconds
Started Jul 14 06:55:02 PM PDT 24
Finished Jul 14 07:04:52 PM PDT 24
Peak memory 271732 kb
Host smart-88235d5f-1a8d-444e-bb9c-cb251c73e437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381569075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.381569075
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.94139682
Short name T23
Test name
Test status
Simulation time 101389173 ps
CPU time 0.93 seconds
Started Jul 14 06:54:44 PM PDT 24
Finished Jul 14 06:54:48 PM PDT 24
Peak memory 234916 kb
Host smart-501a8d01-e52e-447c-a17f-b57c49067c56
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94139682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.94139682
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3140056406
Short name T147
Test name
Test status
Simulation time 11500432159 ps
CPU time 35.97 seconds
Started Jul 14 06:55:15 PM PDT 24
Finished Jul 14 06:55:55 PM PDT 24
Peak memory 251092 kb
Host smart-5bfee961-58ec-41d4-a316-bd0d4e4c30c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140056406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3140056406
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2786930251
Short name T231
Test name
Test status
Simulation time 9982793091 ps
CPU time 138.68 seconds
Started Jul 14 06:56:12 PM PDT 24
Finished Jul 14 06:58:33 PM PDT 24
Peak memory 262500 kb
Host smart-e79a1b39-a8aa-4675-b460-79465bbda4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786930251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2786930251
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1093330923
Short name T217
Test name
Test status
Simulation time 37829916987 ps
CPU time 402.17 seconds
Started Jul 14 06:56:47 PM PDT 24
Finished Jul 14 07:03:33 PM PDT 24
Peak memory 283064 kb
Host smart-51524c0f-1df0-4621-9a5b-29a107b61277
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093330923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1093330923
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2305330696
Short name T88
Test name
Test status
Simulation time 33139350 ps
CPU time 1.15 seconds
Started Jul 14 07:07:16 PM PDT 24
Finished Jul 14 07:07:19 PM PDT 24
Peak memory 207476 kb
Host smart-9071176d-0479-47af-b397-dbb4c75266f4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305330696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2305330696
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1256700177
Short name T33
Test name
Test status
Simulation time 6199485909 ps
CPU time 117.73 seconds
Started Jul 14 06:56:07 PM PDT 24
Finished Jul 14 06:58:06 PM PDT 24
Peak memory 265612 kb
Host smart-b682dafe-827b-4211-a9e1-59b6a0de8ceb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256700177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1256700177
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.77900094
Short name T63
Test name
Test status
Simulation time 49884399134 ps
CPU time 297.52 seconds
Started Jul 14 06:56:00 PM PDT 24
Finished Jul 14 07:01:00 PM PDT 24
Peak memory 260168 kb
Host smart-fa17a47c-664f-4f61-8baa-f9597b777916
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77900094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stress
_all.77900094
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2794881403
Short name T190
Test name
Test status
Simulation time 16228449074 ps
CPU time 171.01 seconds
Started Jul 14 06:55:58 PM PDT 24
Finished Jul 14 06:58:52 PM PDT 24
Peak memory 269300 kb
Host smart-fd86e618-e86c-4be4-b338-cae70baf2ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794881403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2794881403
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3937662086
Short name T85
Test name
Test status
Simulation time 5489963976 ps
CPU time 111 seconds
Started Jul 14 06:56:32 PM PDT 24
Finished Jul 14 06:58:26 PM PDT 24
Peak memory 257224 kb
Host smart-082ccfc5-2595-4710-b738-5f9f1cc0e65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937662086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3937662086
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2613449135
Short name T194
Test name
Test status
Simulation time 32118380006 ps
CPU time 352.05 seconds
Started Jul 14 06:55:21 PM PDT 24
Finished Jul 14 07:01:15 PM PDT 24
Peak memory 269340 kb
Host smart-6ceb5b17-47e6-4d12-a351-3310938c2c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613449135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2613449135
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3641769560
Short name T162
Test name
Test status
Simulation time 118368132680 ps
CPU time 273.92 seconds
Started Jul 14 06:55:43 PM PDT 24
Finished Jul 14 07:00:18 PM PDT 24
Peak memory 268776 kb
Host smart-ffc8eecc-92bf-4555-9f0b-63091eabf27d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641769560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3641769560
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1266416553
Short name T223
Test name
Test status
Simulation time 29402619134 ps
CPU time 146.24 seconds
Started Jul 14 06:55:52 PM PDT 24
Finished Jul 14 06:58:19 PM PDT 24
Peak memory 251928 kb
Host smart-13110ca6-7253-4c18-9e76-40e97351683e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266416553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1266416553
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2924204918
Short name T180
Test name
Test status
Simulation time 882958093 ps
CPU time 20.08 seconds
Started Jul 14 07:07:22 PM PDT 24
Finished Jul 14 07:07:44 PM PDT 24
Peak memory 215768 kb
Host smart-e0c2f8ca-ad89-4263-9fae-7906a0403b89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924204918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2924204918
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.1098112973
Short name T203
Test name
Test status
Simulation time 91650568962 ps
CPU time 354.02 seconds
Started Jul 14 06:55:51 PM PDT 24
Finished Jul 14 07:01:46 PM PDT 24
Peak memory 251952 kb
Host smart-86a01539-39e2-4408-8886-973c1d82f6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098112973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.1098112973
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1456471532
Short name T66
Test name
Test status
Simulation time 33213485 ps
CPU time 0.73 seconds
Started Jul 14 06:55:04 PM PDT 24
Finished Jul 14 06:55:10 PM PDT 24
Peak memory 205900 kb
Host smart-bc0491e6-2bae-4f8f-bda1-4074ca3d2a37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456471532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1456471532
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.763185729
Short name T174
Test name
Test status
Simulation time 70747972 ps
CPU time 4.54 seconds
Started Jul 14 07:07:33 PM PDT 24
Finished Jul 14 07:07:40 PM PDT 24
Peak memory 215996 kb
Host smart-6814bbdd-c14a-4328-b427-da378be26d7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763185729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.763185729
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1018243817
Short name T43
Test name
Test status
Simulation time 4154030563 ps
CPU time 77.84 seconds
Started Jul 14 06:56:18 PM PDT 24
Finished Jul 14 06:57:42 PM PDT 24
Peak memory 254924 kb
Host smart-e4ca970b-0423-4d83-8eae-7ed46a5e8cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018243817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1018243817
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.2202719741
Short name T208
Test name
Test status
Simulation time 37922879752 ps
CPU time 318 seconds
Started Jul 14 06:55:41 PM PDT 24
Finished Jul 14 07:01:01 PM PDT 24
Peak memory 251716 kb
Host smart-9da3e5ec-a6b8-4d8c-a402-82dcb9075253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202719741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.2202719741
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3570526535
Short name T268
Test name
Test status
Simulation time 114972381762 ps
CPU time 222.55 seconds
Started Jul 14 06:56:15 PM PDT 24
Finished Jul 14 07:00:01 PM PDT 24
Peak memory 257376 kb
Host smart-194d1f55-4e87-4158-a84a-992c5305d0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570526535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3570526535
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3082624045
Short name T61
Test name
Test status
Simulation time 23150189643 ps
CPU time 158.9 seconds
Started Jul 14 06:56:45 PM PDT 24
Finished Jul 14 06:59:25 PM PDT 24
Peak memory 268100 kb
Host smart-40853e84-5a9a-4e64-a445-8622daca64c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082624045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3082624045
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2863390680
Short name T282
Test name
Test status
Simulation time 439389246 ps
CPU time 10.47 seconds
Started Jul 14 06:55:06 PM PDT 24
Finished Jul 14 06:55:22 PM PDT 24
Peak memory 249612 kb
Host smart-4784357d-cde1-44a7-b430-00973df6e337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863390680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2863390680
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.878622491
Short name T10
Test name
Test status
Simulation time 584028687 ps
CPU time 7.64 seconds
Started Jul 14 06:55:31 PM PDT 24
Finished Jul 14 06:55:42 PM PDT 24
Peak memory 232672 kb
Host smart-bebd5172-8b58-42ed-9717-b39e2ac4cef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878622491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.878622491
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1699514273
Short name T48
Test name
Test status
Simulation time 65449929505 ps
CPU time 296.99 seconds
Started Jul 14 06:55:29 PM PDT 24
Finished Jul 14 07:00:30 PM PDT 24
Peak memory 256600 kb
Host smart-a96f1305-160d-4712-bef8-54f86a68cbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699514273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1699514273
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3723486786
Short name T253
Test name
Test status
Simulation time 41879315123 ps
CPU time 88.38 seconds
Started Jul 14 06:56:28 PM PDT 24
Finished Jul 14 06:58:00 PM PDT 24
Peak memory 255292 kb
Host smart-cd2257ee-35e1-4e5e-9b82-0536818bb636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723486786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3723486786
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.437243493
Short name T19
Test name
Test status
Simulation time 34353096806 ps
CPU time 150.65 seconds
Started Jul 14 06:55:18 PM PDT 24
Finished Jul 14 06:57:51 PM PDT 24
Peak memory 241104 kb
Host smart-95fbeedc-5135-447a-9468-97e7e5021ff8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437243493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.437243493
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3722130061
Short name T178
Test name
Test status
Simulation time 1149852405 ps
CPU time 14.97 seconds
Started Jul 14 07:07:26 PM PDT 24
Finished Jul 14 07:07:43 PM PDT 24
Peak memory 215796 kb
Host smart-c7749256-a36b-4273-8001-098b4ac5a4ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722130061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3722130061
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3832816483
Short name T296
Test name
Test status
Simulation time 4633255555 ps
CPU time 17.13 seconds
Started Jul 14 06:55:02 PM PDT 24
Finished Jul 14 06:55:24 PM PDT 24
Peak memory 217616 kb
Host smart-3d71b172-0dc1-4c34-9e4b-8fd962561f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832816483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3832816483
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3252261450
Short name T274
Test name
Test status
Simulation time 101297799436 ps
CPU time 253.22 seconds
Started Jul 14 06:56:41 PM PDT 24
Finished Jul 14 07:00:55 PM PDT 24
Peak memory 255884 kb
Host smart-249b41cf-4ee9-4544-adaf-b7a007df70ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252261450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3252261450
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3085273353
Short name T698
Test name
Test status
Simulation time 264644838 ps
CPU time 10.51 seconds
Started Jul 14 06:56:47 PM PDT 24
Finished Jul 14 06:57:01 PM PDT 24
Peak memory 224476 kb
Host smart-8dc447df-2b99-4aa5-92a4-b92273631066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085273353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3085273353
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3154076277
Short name T146
Test name
Test status
Simulation time 328209703 ps
CPU time 3.86 seconds
Started Jul 14 06:55:24 PM PDT 24
Finished Jul 14 06:55:30 PM PDT 24
Peak memory 223176 kb
Host smart-b5a230a2-6eae-4315-b462-86d7e476678c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3154076277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3154076277
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.3019316231
Short name T21
Test name
Test status
Simulation time 229507960711 ps
CPU time 211.41 seconds
Started Jul 14 06:55:50 PM PDT 24
Finished Jul 14 06:59:22 PM PDT 24
Peak memory 249308 kb
Host smart-268f559d-4f07-41c0-856d-e2e4648ed931
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019316231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3019316231
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3896323042
Short name T107
Test name
Test status
Simulation time 95610492 ps
CPU time 4.13 seconds
Started Jul 14 07:07:24 PM PDT 24
Finished Jul 14 07:07:30 PM PDT 24
Peak memory 216032 kb
Host smart-a3e0cfb2-9e58-47ef-8368-addfc06f452c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896323042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
896323042
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.101474274
Short name T102
Test name
Test status
Simulation time 1720231793 ps
CPU time 6.48 seconds
Started Jul 14 07:07:27 PM PDT 24
Finished Jul 14 07:07:35 PM PDT 24
Peak memory 215904 kb
Host smart-6939e3b6-2e9b-44aa-aa45-b17b17d35eb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101474274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.101474274
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1706036420
Short name T964
Test name
Test status
Simulation time 41534274296 ps
CPU time 68.8 seconds
Started Jul 14 06:54:41 PM PDT 24
Finished Jul 14 06:55:52 PM PDT 24
Peak memory 224676 kb
Host smart-c65b018c-873f-4e04-bd76-92878ddeee0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706036420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1706036420
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.4032255600
Short name T94
Test name
Test status
Simulation time 36250873 ps
CPU time 0.76 seconds
Started Jul 14 06:55:20 PM PDT 24
Finished Jul 14 06:55:23 PM PDT 24
Peak memory 205996 kb
Host smart-26b2b2cd-d3b9-4846-93e4-1a3f25c37fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032255600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.4032255600
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.666592876
Short name T93
Test name
Test status
Simulation time 33317653665 ps
CPU time 244.15 seconds
Started Jul 14 06:56:17 PM PDT 24
Finished Jul 14 07:00:26 PM PDT 24
Peak memory 252672 kb
Host smart-42327e7b-5ecf-473f-addc-711611aabaee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666592876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds
.666592876
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.630690358
Short name T98
Test name
Test status
Simulation time 53438476473 ps
CPU time 212.69 seconds
Started Jul 14 06:56:50 PM PDT 24
Finished Jul 14 07:00:28 PM PDT 24
Peak memory 249200 kb
Host smart-7b58d6bb-2a3b-46c6-9317-ada9b93c7935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630690358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.630690358
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.263266497
Short name T1121
Test name
Test status
Simulation time 629208387 ps
CPU time 8.26 seconds
Started Jul 14 07:07:15 PM PDT 24
Finished Jul 14 07:07:25 PM PDT 24
Peak memory 215692 kb
Host smart-61a3298a-e927-4c8c-9923-ab9cb589b16b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263266497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.263266497
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1774352079
Short name T127
Test name
Test status
Simulation time 10071408546 ps
CPU time 13.18 seconds
Started Jul 14 07:07:20 PM PDT 24
Finished Jul 14 07:07:36 PM PDT 24
Peak memory 207728 kb
Host smart-f56c9915-c72b-40a1-a999-21f7bf89902a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774352079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1774352079
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3927178555
Short name T1120
Test name
Test status
Simulation time 100221807 ps
CPU time 0.93 seconds
Started Jul 14 07:07:16 PM PDT 24
Finished Jul 14 07:07:19 PM PDT 24
Peak memory 207236 kb
Host smart-261f6cbf-eaed-464b-b7b5-4ebd5d76136a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927178555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3927178555
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.854887126
Short name T1042
Test name
Test status
Simulation time 425215222 ps
CPU time 2.84 seconds
Started Jul 14 07:07:15 PM PDT 24
Finished Jul 14 07:07:20 PM PDT 24
Peak memory 217808 kb
Host smart-b22bc36b-bf1c-466d-bdca-feaa959c5cf0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854887126 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.854887126
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2041478734
Short name T1071
Test name
Test status
Simulation time 140879112 ps
CPU time 2.48 seconds
Started Jul 14 07:07:19 PM PDT 24
Finished Jul 14 07:07:23 PM PDT 24
Peak memory 215668 kb
Host smart-0aef0ce1-db9f-4241-9ba4-d42141505cf5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041478734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
041478734
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2125156016
Short name T1074
Test name
Test status
Simulation time 25436581 ps
CPU time 0.69 seconds
Started Jul 14 07:07:15 PM PDT 24
Finished Jul 14 07:07:18 PM PDT 24
Peak memory 204316 kb
Host smart-08ee1304-db3f-4207-bba1-cddd264234ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125156016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
125156016
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1641510811
Short name T1084
Test name
Test status
Simulation time 59585902 ps
CPU time 1.72 seconds
Started Jul 14 07:07:15 PM PDT 24
Finished Jul 14 07:07:19 PM PDT 24
Peak memory 215784 kb
Host smart-b9f9dac7-eb44-4bef-bb43-ee783d577a50
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641510811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1641510811
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3748140233
Short name T1027
Test name
Test status
Simulation time 27921792 ps
CPU time 0.65 seconds
Started Jul 14 07:07:22 PM PDT 24
Finished Jul 14 07:07:26 PM PDT 24
Peak memory 204096 kb
Host smart-6be45617-7e3f-4c81-b0e6-44fec20ea432
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748140233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3748140233
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1635284902
Short name T1046
Test name
Test status
Simulation time 263767286 ps
CPU time 2.9 seconds
Started Jul 14 07:07:13 PM PDT 24
Finished Jul 14 07:07:18 PM PDT 24
Peak memory 215796 kb
Host smart-002d3e65-0bf7-4c80-86de-89c9a7dc25e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635284902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1635284902
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4155033104
Short name T1117
Test name
Test status
Simulation time 39084700 ps
CPU time 2.69 seconds
Started Jul 14 07:07:20 PM PDT 24
Finished Jul 14 07:07:24 PM PDT 24
Peak memory 216040 kb
Host smart-6b0e2040-9f40-4347-96ac-5ece0fbf0eae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155033104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.4
155033104
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4218062939
Short name T158
Test name
Test status
Simulation time 10236811996 ps
CPU time 24.16 seconds
Started Jul 14 07:07:20 PM PDT 24
Finished Jul 14 07:07:47 PM PDT 24
Peak memory 215852 kb
Host smart-79429fc7-46d0-4603-98d6-4cd346492f25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218062939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.4218062939
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2955982294
Short name T1078
Test name
Test status
Simulation time 227135809 ps
CPU time 7.9 seconds
Started Jul 14 07:07:13 PM PDT 24
Finished Jul 14 07:07:23 PM PDT 24
Peak memory 207524 kb
Host smart-21a6e8da-6f07-4a8d-9511-38957830ef7b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955982294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2955982294
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1571070654
Short name T1085
Test name
Test status
Simulation time 362788949 ps
CPU time 23.05 seconds
Started Jul 14 07:07:16 PM PDT 24
Finished Jul 14 07:07:41 PM PDT 24
Peak memory 207484 kb
Host smart-8f25c8a5-3690-41f5-9582-2df6ee72a1c9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571070654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1571070654
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3832872002
Short name T1080
Test name
Test status
Simulation time 62149220 ps
CPU time 1.75 seconds
Started Jul 14 07:07:15 PM PDT 24
Finished Jul 14 07:07:19 PM PDT 24
Peak memory 215860 kb
Host smart-0df85dc7-c0d6-4653-b839-7d2ccd802a6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832872002 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3832872002
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1745907643
Short name T120
Test name
Test status
Simulation time 87258788 ps
CPU time 2.41 seconds
Started Jul 14 07:07:20 PM PDT 24
Finished Jul 14 07:07:24 PM PDT 24
Peak memory 207552 kb
Host smart-85614057-27f3-4b9e-9a8d-e180712a33e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745907643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
745907643
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2066613532
Short name T1034
Test name
Test status
Simulation time 40080430 ps
CPU time 0.72 seconds
Started Jul 14 07:07:15 PM PDT 24
Finished Jul 14 07:07:18 PM PDT 24
Peak memory 204564 kb
Host smart-81ec59ae-27c2-4375-98bf-a2304c74ac8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066613532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
066613532
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2988160304
Short name T1086
Test name
Test status
Simulation time 63316499 ps
CPU time 1.28 seconds
Started Jul 14 07:07:21 PM PDT 24
Finished Jul 14 07:07:24 PM PDT 24
Peak memory 215800 kb
Host smart-b94cdf94-6e15-4fd1-90f3-f32748187ef1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988160304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2988160304
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4149281884
Short name T1061
Test name
Test status
Simulation time 11196689 ps
CPU time 0.71 seconds
Started Jul 14 07:07:16 PM PDT 24
Finished Jul 14 07:07:19 PM PDT 24
Peak memory 204124 kb
Host smart-baa42e19-94ac-4437-a5ba-4d582f705fc6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149281884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.4149281884
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3880749896
Short name T155
Test name
Test status
Simulation time 207832021 ps
CPU time 4.18 seconds
Started Jul 14 07:07:15 PM PDT 24
Finished Jul 14 07:07:21 PM PDT 24
Peak memory 215700 kb
Host smart-dcc34109-4ec4-4fee-b7f2-a56829162a94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880749896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3880749896
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1186421685
Short name T115
Test name
Test status
Simulation time 991790621 ps
CPU time 5.54 seconds
Started Jul 14 07:07:13 PM PDT 24
Finished Jul 14 07:07:21 PM PDT 24
Peak memory 216920 kb
Host smart-05cc85aa-c9bf-4fb5-be82-ed90755872ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186421685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
186421685
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3234045086
Short name T1116
Test name
Test status
Simulation time 429916834 ps
CPU time 7.06 seconds
Started Jul 14 07:07:16 PM PDT 24
Finished Jul 14 07:07:25 PM PDT 24
Peak memory 215780 kb
Host smart-715fcf05-6778-428b-97e4-bddba76a9f94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234045086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3234045086
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1742749234
Short name T1083
Test name
Test status
Simulation time 53862448 ps
CPU time 3.41 seconds
Started Jul 14 07:07:27 PM PDT 24
Finished Jul 14 07:07:32 PM PDT 24
Peak memory 218460 kb
Host smart-777095a0-e78d-4154-9ab7-f68339e1c222
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742749234 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1742749234
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2041588427
Short name T124
Test name
Test status
Simulation time 210473065 ps
CPU time 2.6 seconds
Started Jul 14 07:07:25 PM PDT 24
Finished Jul 14 07:07:30 PM PDT 24
Peak memory 215652 kb
Host smart-bb99a787-99cd-4755-99d7-031c4895db91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041588427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2041588427
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1372829771
Short name T1028
Test name
Test status
Simulation time 12931801 ps
CPU time 0.73 seconds
Started Jul 14 07:07:26 PM PDT 24
Finished Jul 14 07:07:29 PM PDT 24
Peak memory 204232 kb
Host smart-26171124-e6f9-4e8e-ab50-ff5e1aff33c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372829771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1372829771
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3188701492
Short name T143
Test name
Test status
Simulation time 291628768 ps
CPU time 3.24 seconds
Started Jul 14 07:07:31 PM PDT 24
Finished Jul 14 07:07:35 PM PDT 24
Peak memory 216448 kb
Host smart-71009deb-5daa-4744-a84c-0c48c260e3d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188701492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3188701492
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.853145461
Short name T1102
Test name
Test status
Simulation time 102214464 ps
CPU time 3.21 seconds
Started Jul 14 07:07:26 PM PDT 24
Finished Jul 14 07:07:32 PM PDT 24
Peak memory 215988 kb
Host smart-653b2d50-7af5-4bda-ac05-5fe6e59a8348
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853145461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.853145461
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1923959386
Short name T1036
Test name
Test status
Simulation time 156187780 ps
CPU time 1.97 seconds
Started Jul 14 07:07:26 PM PDT 24
Finished Jul 14 07:07:30 PM PDT 24
Peak memory 216872 kb
Host smart-024a2cc8-5df1-4602-b1f7-e44980a794b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923959386 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1923959386
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4192319364
Short name T1125
Test name
Test status
Simulation time 315340203 ps
CPU time 2.59 seconds
Started Jul 14 07:07:26 PM PDT 24
Finished Jul 14 07:07:31 PM PDT 24
Peak memory 215748 kb
Host smart-f475ce34-f6c9-455e-b129-1aa17e278b18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192319364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
4192319364
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2210747424
Short name T1107
Test name
Test status
Simulation time 13677805 ps
CPU time 0.74 seconds
Started Jul 14 07:07:29 PM PDT 24
Finished Jul 14 07:07:30 PM PDT 24
Peak memory 204256 kb
Host smart-87ad58c9-224e-403a-9e5f-101c5d5dc574
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210747424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2210747424
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1952787871
Short name T1105
Test name
Test status
Simulation time 185170794 ps
CPU time 2.78 seconds
Started Jul 14 07:07:26 PM PDT 24
Finished Jul 14 07:07:31 PM PDT 24
Peak memory 215820 kb
Host smart-542dc12b-1662-47a8-9338-625ab2a8efea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952787871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1952787871
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1316717621
Short name T1030
Test name
Test status
Simulation time 325762998 ps
CPU time 2.32 seconds
Started Jul 14 07:07:25 PM PDT 24
Finished Jul 14 07:07:30 PM PDT 24
Peak memory 215856 kb
Host smart-b4f511e0-065d-4179-8793-0faa00d088b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316717621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1316717621
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2807523098
Short name T1050
Test name
Test status
Simulation time 215370827 ps
CPU time 3.12 seconds
Started Jul 14 07:07:35 PM PDT 24
Finished Jul 14 07:07:41 PM PDT 24
Peak memory 218460 kb
Host smart-e02c42ad-bce3-4a5c-aaaf-44d3d64f9645
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807523098 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2807523098
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3590260088
Short name T119
Test name
Test status
Simulation time 154469644 ps
CPU time 2 seconds
Started Jul 14 07:07:28 PM PDT 24
Finished Jul 14 07:07:31 PM PDT 24
Peak memory 215736 kb
Host smart-645f4938-3a7e-49f9-9899-5f9e3e3c5ec3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590260088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3590260088
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1417740051
Short name T1013
Test name
Test status
Simulation time 15764554 ps
CPU time 0.77 seconds
Started Jul 14 07:07:32 PM PDT 24
Finished Jul 14 07:07:33 PM PDT 24
Peak memory 204600 kb
Host smart-c706e323-c3a3-4c1f-9d11-3f16142423f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417740051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1417740051
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2624460254
Short name T1127
Test name
Test status
Simulation time 168894570 ps
CPU time 4.27 seconds
Started Jul 14 07:07:34 PM PDT 24
Finished Jul 14 07:07:40 PM PDT 24
Peak memory 215776 kb
Host smart-1d700790-94e3-40e5-af6e-2e5711447ff8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624460254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2624460254
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1482533424
Short name T1056
Test name
Test status
Simulation time 135888053 ps
CPU time 1.59 seconds
Started Jul 14 07:07:34 PM PDT 24
Finished Jul 14 07:07:38 PM PDT 24
Peak memory 215940 kb
Host smart-e989c12b-b2d9-49cb-926b-02558f40bc47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482533424 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1482533424
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.258895844
Short name T1119
Test name
Test status
Simulation time 107855208 ps
CPU time 1.43 seconds
Started Jul 14 07:07:35 PM PDT 24
Finished Jul 14 07:07:38 PM PDT 24
Peak memory 215692 kb
Host smart-b8c28737-bc64-4173-b6ba-57bcab6e5058
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258895844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.258895844
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3017759955
Short name T1043
Test name
Test status
Simulation time 14783080 ps
CPU time 0.75 seconds
Started Jul 14 07:07:35 PM PDT 24
Finished Jul 14 07:07:37 PM PDT 24
Peak memory 204436 kb
Host smart-b87bd286-4017-40d3-b764-0bc939a64cfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017759955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3017759955
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3474843078
Short name T1038
Test name
Test status
Simulation time 1322743541 ps
CPU time 4.44 seconds
Started Jul 14 07:07:34 PM PDT 24
Finished Jul 14 07:07:41 PM PDT 24
Peak memory 215804 kb
Host smart-a68d5b44-1dbe-4553-ab9d-fbc70d59c0c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474843078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3474843078
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.96471087
Short name T114
Test name
Test status
Simulation time 153628259 ps
CPU time 2.77 seconds
Started Jul 14 07:07:35 PM PDT 24
Finished Jul 14 07:07:40 PM PDT 24
Peak memory 216016 kb
Host smart-3997c67e-13ca-41ee-ad7b-7c614f03a9e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96471087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.96471087
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2480246905
Short name T1063
Test name
Test status
Simulation time 216236999 ps
CPU time 12 seconds
Started Jul 14 07:07:33 PM PDT 24
Finished Jul 14 07:07:47 PM PDT 24
Peak memory 215732 kb
Host smart-78262d6b-aef1-47bc-97d2-bc5c83c0e11f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480246905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2480246905
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2668061207
Short name T1106
Test name
Test status
Simulation time 29248637 ps
CPU time 1.93 seconds
Started Jul 14 07:07:39 PM PDT 24
Finished Jul 14 07:07:46 PM PDT 24
Peak memory 215876 kb
Host smart-c3cdfe40-6f6e-4285-b702-a46c2b2ce891
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668061207 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2668061207
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.350492466
Short name T1095
Test name
Test status
Simulation time 227317157 ps
CPU time 2.42 seconds
Started Jul 14 07:07:35 PM PDT 24
Finished Jul 14 07:07:40 PM PDT 24
Peak memory 207624 kb
Host smart-3ec5cb27-e94f-4fdb-a5bb-081cbcdeaca5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350492466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.350492466
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2975428558
Short name T1092
Test name
Test status
Simulation time 35716933 ps
CPU time 0.72 seconds
Started Jul 14 07:07:34 PM PDT 24
Finished Jul 14 07:07:36 PM PDT 24
Peak memory 204248 kb
Host smart-8cd52977-033c-4aea-b218-60008e21d385
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975428558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2975428558
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.601638850
Short name T1103
Test name
Test status
Simulation time 919596715 ps
CPU time 4.38 seconds
Started Jul 14 07:07:34 PM PDT 24
Finished Jul 14 07:07:41 PM PDT 24
Peak memory 215808 kb
Host smart-6740109e-ca89-4dfa-96e7-349473d564fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601638850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.601638850
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1686652480
Short name T69
Test name
Test status
Simulation time 35227081 ps
CPU time 1.91 seconds
Started Jul 14 07:07:35 PM PDT 24
Finished Jul 14 07:07:39 PM PDT 24
Peak memory 216128 kb
Host smart-4f0bd539-0103-494a-8095-dc73e6c55945
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686652480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1686652480
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1201611661
Short name T175
Test name
Test status
Simulation time 2497477993 ps
CPU time 19.52 seconds
Started Jul 14 07:07:34 PM PDT 24
Finished Jul 14 07:07:55 PM PDT 24
Peak memory 223972 kb
Host smart-e6cb5e6a-eddb-4ac8-90c6-01583c181e04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201611661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1201611661
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2215050901
Short name T1114
Test name
Test status
Simulation time 42048351 ps
CPU time 1.73 seconds
Started Jul 14 07:07:39 PM PDT 24
Finished Jul 14 07:07:46 PM PDT 24
Peak memory 215876 kb
Host smart-c831b1fa-a272-476f-b3d8-982f9e9923b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215050901 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2215050901
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1101647749
Short name T121
Test name
Test status
Simulation time 102669807 ps
CPU time 1.74 seconds
Started Jul 14 07:07:33 PM PDT 24
Finished Jul 14 07:07:35 PM PDT 24
Peak memory 215620 kb
Host smart-1b0f134c-4c7f-4b8b-a498-178facb4aaec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101647749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1101647749
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1759954594
Short name T1090
Test name
Test status
Simulation time 31825034 ps
CPU time 0.75 seconds
Started Jul 14 07:07:33 PM PDT 24
Finished Jul 14 07:07:34 PM PDT 24
Peak memory 204304 kb
Host smart-1dcd095c-7814-4894-9459-f4669c89ef26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759954594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1759954594
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2349250160
Short name T154
Test name
Test status
Simulation time 271924533 ps
CPU time 2.96 seconds
Started Jul 14 07:07:32 PM PDT 24
Finished Jul 14 07:07:36 PM PDT 24
Peak memory 215800 kb
Host smart-e813118b-defc-4a95-8358-67025984f798
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349250160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2349250160
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1408717557
Short name T1051
Test name
Test status
Simulation time 335123327 ps
CPU time 6.76 seconds
Started Jul 14 07:07:39 PM PDT 24
Finished Jul 14 07:07:51 PM PDT 24
Peak memory 215796 kb
Host smart-765cc2c5-d2c5-4bdc-a3ef-c8a3e6addca9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408717557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1408717557
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3145840203
Short name T1110
Test name
Test status
Simulation time 148768575 ps
CPU time 2.8 seconds
Started Jul 14 07:07:34 PM PDT 24
Finished Jul 14 07:07:39 PM PDT 24
Peak memory 217472 kb
Host smart-ef46cab6-b126-4ead-b65f-bf1e407c2dde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145840203 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3145840203
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1616595191
Short name T1118
Test name
Test status
Simulation time 116376239 ps
CPU time 2.73 seconds
Started Jul 14 07:07:39 PM PDT 24
Finished Jul 14 07:07:47 PM PDT 24
Peak memory 207576 kb
Host smart-7804433d-35a9-437e-b58f-95e4103a2687
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616595191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1616595191
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3160596422
Short name T1109
Test name
Test status
Simulation time 17308313 ps
CPU time 0.74 seconds
Started Jul 14 07:07:33 PM PDT 24
Finished Jul 14 07:07:35 PM PDT 24
Peak memory 204516 kb
Host smart-ff19afbc-1cab-43ba-b6b1-fa27c71514a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160596422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3160596422
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1068435716
Short name T1073
Test name
Test status
Simulation time 4020437438 ps
CPU time 4.14 seconds
Started Jul 14 07:07:32 PM PDT 24
Finished Jul 14 07:07:37 PM PDT 24
Peak memory 215796 kb
Host smart-29d3d637-7e5a-454b-8c48-a4fe531bc8f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068435716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1068435716
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3132543610
Short name T1047
Test name
Test status
Simulation time 768644128 ps
CPU time 4.19 seconds
Started Jul 14 07:07:36 PM PDT 24
Finished Jul 14 07:07:43 PM PDT 24
Peak memory 215940 kb
Host smart-ca847e8e-34f9-46cf-9c42-96c811934b0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132543610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3132543610
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2894762379
Short name T179
Test name
Test status
Simulation time 1818392637 ps
CPU time 20.4 seconds
Started Jul 14 07:07:37 PM PDT 24
Finished Jul 14 07:08:01 PM PDT 24
Peak memory 215864 kb
Host smart-1541628c-0814-4364-8ccc-150396b51d34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894762379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2894762379
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3521253106
Short name T1115
Test name
Test status
Simulation time 43310361 ps
CPU time 3.02 seconds
Started Jul 14 07:07:41 PM PDT 24
Finished Jul 14 07:07:49 PM PDT 24
Peak memory 217184 kb
Host smart-6baf974f-9020-4d82-b697-bec519ac4bb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521253106 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3521253106
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3293266760
Short name T1060
Test name
Test status
Simulation time 56989483 ps
CPU time 1.12 seconds
Started Jul 14 07:07:37 PM PDT 24
Finished Jul 14 07:07:43 PM PDT 24
Peak memory 207460 kb
Host smart-635c5eed-20c5-4243-b162-c72164fe617a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293266760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3293266760
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1708995961
Short name T1052
Test name
Test status
Simulation time 203208953 ps
CPU time 0.73 seconds
Started Jul 14 07:07:37 PM PDT 24
Finished Jul 14 07:07:42 PM PDT 24
Peak memory 204276 kb
Host smart-44727c42-09e3-419d-91e7-e6cc0b7f3465
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708995961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1708995961
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3002113276
Short name T1077
Test name
Test status
Simulation time 1289206450 ps
CPU time 3 seconds
Started Jul 14 07:07:31 PM PDT 24
Finished Jul 14 07:07:35 PM PDT 24
Peak memory 215820 kb
Host smart-bef08af8-e085-42f5-9d6f-12b164a79e49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002113276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3002113276
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.4145855447
Short name T105
Test name
Test status
Simulation time 48395954 ps
CPU time 2.87 seconds
Started Jul 14 07:07:38 PM PDT 24
Finished Jul 14 07:07:45 PM PDT 24
Peak memory 216032 kb
Host smart-2775ed25-16ff-4a66-80fa-d509d8afe09f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145855447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
4145855447
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.66663540
Short name T177
Test name
Test status
Simulation time 391956037 ps
CPU time 12.33 seconds
Started Jul 14 07:07:36 PM PDT 24
Finished Jul 14 07:07:50 PM PDT 24
Peak memory 217288 kb
Host smart-b2c8c829-47a2-4efb-a67f-be8b7d0ef991
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66663540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_
tl_intg_err.66663540
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2873790116
Short name T1022
Test name
Test status
Simulation time 333924901 ps
CPU time 2.62 seconds
Started Jul 14 07:07:45 PM PDT 24
Finished Jul 14 07:07:51 PM PDT 24
Peak memory 218436 kb
Host smart-21488fa0-fd7b-4e58-8483-14b5b0ffe78f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873790116 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2873790116
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3166624166
Short name T1069
Test name
Test status
Simulation time 101703010 ps
CPU time 1.99 seconds
Started Jul 14 07:07:34 PM PDT 24
Finished Jul 14 07:07:38 PM PDT 24
Peak memory 215684 kb
Host smart-b3b3bfac-508e-4665-ae38-3c0d3b7cf80b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166624166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3166624166
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1272484624
Short name T1070
Test name
Test status
Simulation time 28448812 ps
CPU time 0.69 seconds
Started Jul 14 07:07:38 PM PDT 24
Finished Jul 14 07:07:44 PM PDT 24
Peak memory 204632 kb
Host smart-59eb681d-6351-42e8-bd94-a3d5ba264f2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272484624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1272484624
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2981626902
Short name T1091
Test name
Test status
Simulation time 720395236 ps
CPU time 4.13 seconds
Started Jul 14 07:07:35 PM PDT 24
Finished Jul 14 07:07:42 PM PDT 24
Peak memory 207612 kb
Host smart-324b45c5-5862-4ed6-a1ee-8d29e2dd43a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981626902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2981626902
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2259989701
Short name T113
Test name
Test status
Simulation time 106884839 ps
CPU time 1.88 seconds
Started Jul 14 07:07:39 PM PDT 24
Finished Jul 14 07:07:46 PM PDT 24
Peak memory 216060 kb
Host smart-4ddafa4d-1b64-4502-bbfa-a040979bba33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259989701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2259989701
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.4014724016
Short name T100
Test name
Test status
Simulation time 215349067 ps
CPU time 6.68 seconds
Started Jul 14 07:07:39 PM PDT 24
Finished Jul 14 07:07:51 PM PDT 24
Peak memory 215704 kb
Host smart-b2d286ed-8af5-4d42-a209-5c303dc700b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014724016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.4014724016
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.4056363635
Short name T1041
Test name
Test status
Simulation time 203066778 ps
CPU time 3.84 seconds
Started Jul 14 07:07:41 PM PDT 24
Finished Jul 14 07:07:50 PM PDT 24
Peak memory 217904 kb
Host smart-490df02a-0a58-45c7-9cd8-ee67172b1752
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056363635 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.4056363635
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2629491731
Short name T1062
Test name
Test status
Simulation time 33285255 ps
CPU time 1.9 seconds
Started Jul 14 07:07:40 PM PDT 24
Finished Jul 14 07:07:47 PM PDT 24
Peak memory 215884 kb
Host smart-d255bb3a-b22e-4b88-b8a2-94d95cfe3935
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629491731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2629491731
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2216688737
Short name T1093
Test name
Test status
Simulation time 77711765 ps
CPU time 0.68 seconds
Started Jul 14 07:07:41 PM PDT 24
Finished Jul 14 07:07:47 PM PDT 24
Peak memory 204288 kb
Host smart-b1f9a7d9-af20-4130-8f84-421afb1ee366
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216688737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2216688737
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1183031399
Short name T1031
Test name
Test status
Simulation time 321040990 ps
CPU time 3.96 seconds
Started Jul 14 07:07:41 PM PDT 24
Finished Jul 14 07:07:50 PM PDT 24
Peak memory 215704 kb
Host smart-f087dbf3-188a-4264-8c39-17cb23e88c1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183031399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1183031399
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.929949532
Short name T111
Test name
Test status
Simulation time 201209016 ps
CPU time 3.01 seconds
Started Jul 14 07:07:38 PM PDT 24
Finished Jul 14 07:07:46 PM PDT 24
Peak memory 216144 kb
Host smart-5b87fdd8-f6d8-4f3e-ad59-8b414710c2d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929949532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.929949532
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2873059017
Short name T181
Test name
Test status
Simulation time 2896112417 ps
CPU time 15.07 seconds
Started Jul 14 07:07:40 PM PDT 24
Finished Jul 14 07:08:00 PM PDT 24
Peak memory 216208 kb
Host smart-3dfb6d11-6433-485c-adbc-018e6c322a95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873059017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2873059017
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2190308738
Short name T131
Test name
Test status
Simulation time 111456292 ps
CPU time 7.74 seconds
Started Jul 14 07:07:21 PM PDT 24
Finished Jul 14 07:07:32 PM PDT 24
Peak memory 215668 kb
Host smart-0bd60ace-8e06-4b0a-8484-bf4f173b08af
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190308738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2190308738
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.997254061
Short name T1058
Test name
Test status
Simulation time 5207963421 ps
CPU time 23.51 seconds
Started Jul 14 07:07:20 PM PDT 24
Finished Jul 14 07:07:45 PM PDT 24
Peak memory 215868 kb
Host smart-6ec1e1e5-6d17-4946-99d7-b153c6452389
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997254061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.997254061
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1625614790
Short name T89
Test name
Test status
Simulation time 301177586 ps
CPU time 1.44 seconds
Started Jul 14 07:07:22 PM PDT 24
Finished Jul 14 07:07:26 PM PDT 24
Peak memory 207424 kb
Host smart-cd80e380-f0e3-4218-8426-9f491de9f19f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625614790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1625614790
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1642537141
Short name T99
Test name
Test status
Simulation time 878478915 ps
CPU time 3.64 seconds
Started Jul 14 07:07:23 PM PDT 24
Finished Jul 14 07:07:29 PM PDT 24
Peak memory 218704 kb
Host smart-f4778ed9-38b5-4ce5-8fd0-cc650b5726a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642537141 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1642537141
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1176084441
Short name T126
Test name
Test status
Simulation time 104448832 ps
CPU time 2.55 seconds
Started Jul 14 07:07:23 PM PDT 24
Finished Jul 14 07:07:29 PM PDT 24
Peak memory 215664 kb
Host smart-7a2ed31c-be13-4dc0-b39f-15876a66a953
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176084441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
176084441
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.75783147
Short name T1088
Test name
Test status
Simulation time 16467698 ps
CPU time 0.78 seconds
Started Jul 14 07:07:14 PM PDT 24
Finished Jul 14 07:07:17 PM PDT 24
Peak memory 204300 kb
Host smart-dbc9ca43-4ed4-41a5-b209-e73df3e589f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75783147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.75783147
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3631626733
Short name T118
Test name
Test status
Simulation time 165503680 ps
CPU time 1.88 seconds
Started Jul 14 07:07:18 PM PDT 24
Finished Jul 14 07:07:22 PM PDT 24
Peak memory 215792 kb
Host smart-8fef1706-3c70-4cc6-bb8d-967e8bfaac5c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631626733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3631626733
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4079986558
Short name T1108
Test name
Test status
Simulation time 10131769 ps
CPU time 0.67 seconds
Started Jul 14 07:07:14 PM PDT 24
Finished Jul 14 07:07:17 PM PDT 24
Peak memory 204404 kb
Host smart-d8ca78fb-273e-4c60-9fcf-5617d5c4fa86
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079986558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.4079986558
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3783641416
Short name T1123
Test name
Test status
Simulation time 121681860 ps
CPU time 4.03 seconds
Started Jul 14 07:07:26 PM PDT 24
Finished Jul 14 07:07:32 PM PDT 24
Peak memory 215808 kb
Host smart-4f1082af-e97f-4570-91d6-f2753f86cda9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783641416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3783641416
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3127361594
Short name T1122
Test name
Test status
Simulation time 57506546 ps
CPU time 1.73 seconds
Started Jul 14 07:07:13 PM PDT 24
Finished Jul 14 07:07:17 PM PDT 24
Peak memory 215968 kb
Host smart-c4d519ab-c5a0-4ac2-983e-92164afede7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127361594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
127361594
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2023406867
Short name T1089
Test name
Test status
Simulation time 299836912 ps
CPU time 18.59 seconds
Started Jul 14 07:07:18 PM PDT 24
Finished Jul 14 07:07:38 PM PDT 24
Peak memory 215872 kb
Host smart-15296a8d-74a4-4a59-b814-10b9459ee807
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023406867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2023406867
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3660633472
Short name T1037
Test name
Test status
Simulation time 14141026 ps
CPU time 0.71 seconds
Started Jul 14 07:07:40 PM PDT 24
Finished Jul 14 07:07:46 PM PDT 24
Peak memory 204540 kb
Host smart-8bc0eed7-ec6e-4bd9-948a-5cfb9fd83379
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660633472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3660633472
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3058568435
Short name T1044
Test name
Test status
Simulation time 12551062 ps
CPU time 0.69 seconds
Started Jul 14 07:07:37 PM PDT 24
Finished Jul 14 07:07:43 PM PDT 24
Peak memory 204624 kb
Host smart-3c9e7f89-4858-40c0-958d-c8810e374af0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058568435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3058568435
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1032666070
Short name T1067
Test name
Test status
Simulation time 28189152 ps
CPU time 0.72 seconds
Started Jul 14 07:07:42 PM PDT 24
Finished Jul 14 07:07:47 PM PDT 24
Peak memory 204324 kb
Host smart-2b51992d-629a-48f0-bd9d-4fa7df3d1041
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032666070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1032666070
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.149913256
Short name T1019
Test name
Test status
Simulation time 21287394 ps
CPU time 0.72 seconds
Started Jul 14 07:07:37 PM PDT 24
Finished Jul 14 07:07:43 PM PDT 24
Peak memory 204252 kb
Host smart-bbd90b52-fc2d-489d-94b7-4ed3ee090b7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149913256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.149913256
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3098622363
Short name T1025
Test name
Test status
Simulation time 21540285 ps
CPU time 0.7 seconds
Started Jul 14 07:07:38 PM PDT 24
Finished Jul 14 07:07:44 PM PDT 24
Peak memory 204248 kb
Host smart-dbadf0ff-bba7-4a79-be52-4cad7c446f75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098622363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3098622363
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2490095226
Short name T1129
Test name
Test status
Simulation time 38079203 ps
CPU time 0.7 seconds
Started Jul 14 07:07:40 PM PDT 24
Finished Jul 14 07:07:46 PM PDT 24
Peak memory 204276 kb
Host smart-f2fb76b5-a4a7-4bbb-9bce-d8c018934886
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490095226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2490095226
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1629120371
Short name T1015
Test name
Test status
Simulation time 181125744 ps
CPU time 0.76 seconds
Started Jul 14 07:07:41 PM PDT 24
Finished Jul 14 07:07:47 PM PDT 24
Peak memory 204616 kb
Host smart-b96a9c28-f634-4f5b-9ec9-b5e2caa7815f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629120371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1629120371
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.656201421
Short name T1055
Test name
Test status
Simulation time 25043646 ps
CPU time 0.7 seconds
Started Jul 14 07:07:39 PM PDT 24
Finished Jul 14 07:07:45 PM PDT 24
Peak memory 204280 kb
Host smart-4063c70c-afd8-486c-a896-2cb04e50339e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656201421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.656201421
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.954161335
Short name T1079
Test name
Test status
Simulation time 55550196 ps
CPU time 0.7 seconds
Started Jul 14 07:07:37 PM PDT 24
Finished Jul 14 07:07:41 PM PDT 24
Peak memory 204296 kb
Host smart-37077b22-a2e1-4104-91d4-8cb3f9a73ccd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954161335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.954161335
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2446079923
Short name T1045
Test name
Test status
Simulation time 212399312 ps
CPU time 0.75 seconds
Started Jul 14 07:07:41 PM PDT 24
Finished Jul 14 07:07:47 PM PDT 24
Peak memory 204332 kb
Host smart-7744b661-b1ca-46f1-a446-22d708ca061e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446079923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2446079923
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3040221680
Short name T125
Test name
Test status
Simulation time 237326587 ps
CPU time 14.25 seconds
Started Jul 14 07:07:23 PM PDT 24
Finished Jul 14 07:07:40 PM PDT 24
Peak memory 215648 kb
Host smart-54ac2621-5fe7-4e1d-89d2-a6a438fa7c1c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040221680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3040221680
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2361549188
Short name T1104
Test name
Test status
Simulation time 7243004046 ps
CPU time 25.28 seconds
Started Jul 14 07:07:19 PM PDT 24
Finished Jul 14 07:07:46 PM PDT 24
Peak memory 215776 kb
Host smart-1da38f8f-fe79-46b8-8bc0-3c9490e73951
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361549188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2361549188
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1257682881
Short name T91
Test name
Test status
Simulation time 23346740 ps
CPU time 0.98 seconds
Started Jul 14 07:07:24 PM PDT 24
Finished Jul 14 07:07:27 PM PDT 24
Peak memory 207240 kb
Host smart-ea43e6a8-8140-4a04-9be2-04255df7a0cd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257682881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1257682881
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1538730922
Short name T1097
Test name
Test status
Simulation time 148965979 ps
CPU time 2.5 seconds
Started Jul 14 07:07:21 PM PDT 24
Finished Jul 14 07:07:26 PM PDT 24
Peak memory 217656 kb
Host smart-a156a8ef-c74d-45de-a081-8379b9ef2a8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538730922 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1538730922
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2590323381
Short name T1064
Test name
Test status
Simulation time 437813865 ps
CPU time 2.58 seconds
Started Jul 14 07:07:21 PM PDT 24
Finished Jul 14 07:07:26 PM PDT 24
Peak memory 207432 kb
Host smart-5a4be9ce-c3a9-403c-b3a5-7ea616de8dbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590323381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
590323381
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.629982114
Short name T1087
Test name
Test status
Simulation time 39091361 ps
CPU time 0.71 seconds
Started Jul 14 07:07:21 PM PDT 24
Finished Jul 14 07:07:24 PM PDT 24
Peak memory 204288 kb
Host smart-7389fe0c-3da6-4869-8acf-1dd2326a21ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629982114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.629982114
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2315030802
Short name T122
Test name
Test status
Simulation time 87592653 ps
CPU time 1.71 seconds
Started Jul 14 07:07:20 PM PDT 24
Finished Jul 14 07:07:24 PM PDT 24
Peak memory 215808 kb
Host smart-dfb5c682-3954-4c2b-85a9-e3b4a9785c7c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315030802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2315030802
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2315279638
Short name T1126
Test name
Test status
Simulation time 10988944 ps
CPU time 0.67 seconds
Started Jul 14 07:07:21 PM PDT 24
Finished Jul 14 07:07:25 PM PDT 24
Peak memory 204104 kb
Host smart-3a3927e0-f88c-406e-bbdd-1874b44f86b2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315279638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2315279638
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2901431151
Short name T1098
Test name
Test status
Simulation time 423589224 ps
CPU time 4.35 seconds
Started Jul 14 07:07:19 PM PDT 24
Finished Jul 14 07:07:26 PM PDT 24
Peak memory 215748 kb
Host smart-507e8e92-1868-4292-aad9-3a565521a4e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901431151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2901431151
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.101200157
Short name T109
Test name
Test status
Simulation time 159225617 ps
CPU time 2.91 seconds
Started Jul 14 07:07:25 PM PDT 24
Finished Jul 14 07:07:31 PM PDT 24
Peak memory 215980 kb
Host smart-af2557d2-de20-4067-bf51-d5786ff880e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101200157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.101200157
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.456237901
Short name T176
Test name
Test status
Simulation time 1145678526 ps
CPU time 7.69 seconds
Started Jul 14 07:07:21 PM PDT 24
Finished Jul 14 07:07:31 PM PDT 24
Peak memory 217012 kb
Host smart-e9e2778d-3dbb-45dd-9e0f-2583e4b3836b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456237901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.456237901
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1316533925
Short name T1016
Test name
Test status
Simulation time 44508629 ps
CPU time 0.69 seconds
Started Jul 14 07:07:39 PM PDT 24
Finished Jul 14 07:07:45 PM PDT 24
Peak memory 204624 kb
Host smart-3312af8f-554c-4af6-bcde-2f840e25c8c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316533925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1316533925
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1360651573
Short name T1039
Test name
Test status
Simulation time 51920170 ps
CPU time 0.76 seconds
Started Jul 14 07:07:37 PM PDT 24
Finished Jul 14 07:07:41 PM PDT 24
Peak memory 204608 kb
Host smart-d9c04438-7e96-4e88-bf0d-83d63e7c4f68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360651573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1360651573
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2429444572
Short name T1024
Test name
Test status
Simulation time 36407916 ps
CPU time 0.78 seconds
Started Jul 14 07:07:42 PM PDT 24
Finished Jul 14 07:07:48 PM PDT 24
Peak memory 204080 kb
Host smart-e609791f-99aa-4241-b018-926fc7c0714f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429444572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2429444572
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2367643324
Short name T1054
Test name
Test status
Simulation time 34731023 ps
CPU time 0.76 seconds
Started Jul 14 07:07:40 PM PDT 24
Finished Jul 14 07:07:46 PM PDT 24
Peak memory 204292 kb
Host smart-bc5d1b79-0af0-4f4c-91eb-829273268690
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367643324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2367643324
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2904574004
Short name T1113
Test name
Test status
Simulation time 13633222 ps
CPU time 0.8 seconds
Started Jul 14 07:07:37 PM PDT 24
Finished Jul 14 07:07:42 PM PDT 24
Peak memory 204296 kb
Host smart-5ab6a490-44f0-44c3-bbfd-f6d00ea0b6ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904574004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2904574004
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3496151671
Short name T1035
Test name
Test status
Simulation time 18110806 ps
CPU time 0.81 seconds
Started Jul 14 07:07:39 PM PDT 24
Finished Jul 14 07:07:46 PM PDT 24
Peak memory 204192 kb
Host smart-b0a6a4b7-74f9-4f2c-bc00-6a0c1ecbc4ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496151671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3496151671
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2564952495
Short name T1065
Test name
Test status
Simulation time 58741077 ps
CPU time 0.76 seconds
Started Jul 14 07:07:39 PM PDT 24
Finished Jul 14 07:07:45 PM PDT 24
Peak memory 204196 kb
Host smart-0ff2bc3e-db8d-4982-b5e3-288498b4617a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564952495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2564952495
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1072032714
Short name T1094
Test name
Test status
Simulation time 27965063 ps
CPU time 0.7 seconds
Started Jul 14 07:07:38 PM PDT 24
Finished Jul 14 07:07:44 PM PDT 24
Peak memory 204284 kb
Host smart-ed836627-e615-46a6-9563-aeec0f9a2448
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072032714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1072032714
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2058761323
Short name T1057
Test name
Test status
Simulation time 12747584 ps
CPU time 0.7 seconds
Started Jul 14 07:07:38 PM PDT 24
Finished Jul 14 07:07:44 PM PDT 24
Peak memory 204592 kb
Host smart-b3c107a5-0945-4ac1-bd6b-0698837fa507
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058761323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2058761323
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1788732666
Short name T1099
Test name
Test status
Simulation time 32834625 ps
CPU time 0.72 seconds
Started Jul 14 07:07:42 PM PDT 24
Finished Jul 14 07:07:48 PM PDT 24
Peak memory 204400 kb
Host smart-4ac8fd0d-73b9-45b3-86f8-4321e120b5f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788732666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1788732666
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1476705769
Short name T1101
Test name
Test status
Simulation time 620525666 ps
CPU time 16.46 seconds
Started Jul 14 07:07:23 PM PDT 24
Finished Jul 14 07:07:42 PM PDT 24
Peak memory 215692 kb
Host smart-a5b46bc4-98d1-4ee4-8f11-3626f67da763
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476705769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1476705769
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1296841274
Short name T1017
Test name
Test status
Simulation time 610291802 ps
CPU time 13.22 seconds
Started Jul 14 07:07:21 PM PDT 24
Finished Jul 14 07:07:37 PM PDT 24
Peak memory 207504 kb
Host smart-0ae263f3-88d6-4cc8-90ed-85fa10de2f62
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296841274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1296841274
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.4129076266
Short name T90
Test name
Test status
Simulation time 32380982 ps
CPU time 1.17 seconds
Started Jul 14 07:07:24 PM PDT 24
Finished Jul 14 07:07:28 PM PDT 24
Peak memory 216636 kb
Host smart-c3395b28-fb9f-4584-aa7b-9bb013b02bb9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129076266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.4129076266
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1440001747
Short name T1128
Test name
Test status
Simulation time 87992298 ps
CPU time 2.84 seconds
Started Jul 14 07:07:22 PM PDT 24
Finished Jul 14 07:07:28 PM PDT 24
Peak memory 217556 kb
Host smart-ad9a9c76-cb38-492f-b576-a74ffcb56b1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440001747 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1440001747
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1238762005
Short name T129
Test name
Test status
Simulation time 74138152 ps
CPU time 1.33 seconds
Started Jul 14 07:07:22 PM PDT 24
Finished Jul 14 07:07:26 PM PDT 24
Peak memory 215680 kb
Host smart-94bfc179-1898-4c59-bc04-a93bdbc90542
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238762005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
238762005
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.212352568
Short name T1048
Test name
Test status
Simulation time 79092640 ps
CPU time 0.73 seconds
Started Jul 14 07:07:20 PM PDT 24
Finished Jul 14 07:07:22 PM PDT 24
Peak memory 204256 kb
Host smart-bae2a3eb-de44-4924-a9d5-5081686ae6a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212352568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.212352568
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1161053879
Short name T1026
Test name
Test status
Simulation time 65863766 ps
CPU time 1.26 seconds
Started Jul 14 07:07:24 PM PDT 24
Finished Jul 14 07:07:28 PM PDT 24
Peak memory 215392 kb
Host smart-6031f9d2-af22-44aa-8297-ca7202669bed
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161053879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1161053879
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3926365467
Short name T1082
Test name
Test status
Simulation time 18174805 ps
CPU time 0.68 seconds
Started Jul 14 07:07:24 PM PDT 24
Finished Jul 14 07:07:27 PM PDT 24
Peak memory 204056 kb
Host smart-edf19e5c-67ff-409c-8894-8a3c6215d0e9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926365467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3926365467
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3167171577
Short name T1112
Test name
Test status
Simulation time 178361735 ps
CPU time 2.91 seconds
Started Jul 14 07:07:21 PM PDT 24
Finished Jul 14 07:07:27 PM PDT 24
Peak memory 215756 kb
Host smart-5e7335a3-eacd-438f-945f-d8d2d42cd11c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167171577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3167171577
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2554947522
Short name T110
Test name
Test status
Simulation time 126495599 ps
CPU time 3.14 seconds
Started Jul 14 07:07:19 PM PDT 24
Finished Jul 14 07:07:24 PM PDT 24
Peak memory 216008 kb
Host smart-217f9126-9730-443c-adbd-d430df83c545
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554947522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
554947522
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.317570944
Short name T68
Test name
Test status
Simulation time 525751722 ps
CPU time 14.68 seconds
Started Jul 14 07:07:22 PM PDT 24
Finished Jul 14 07:07:40 PM PDT 24
Peak memory 215700 kb
Host smart-51b48ced-c67c-4fc7-90e8-de9db78fbe74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317570944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.317570944
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3661342388
Short name T1018
Test name
Test status
Simulation time 15572890 ps
CPU time 0.72 seconds
Started Jul 14 07:07:40 PM PDT 24
Finished Jul 14 07:07:46 PM PDT 24
Peak memory 204292 kb
Host smart-cbb0d468-74a5-45b2-970b-5fc6351ff3be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661342388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3661342388
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.876397305
Short name T1021
Test name
Test status
Simulation time 72725034 ps
CPU time 0.7 seconds
Started Jul 14 07:07:38 PM PDT 24
Finished Jul 14 07:07:44 PM PDT 24
Peak memory 204300 kb
Host smart-72831cc3-ae43-439b-b367-9e43c375916c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876397305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.876397305
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2594057506
Short name T1076
Test name
Test status
Simulation time 16870650 ps
CPU time 0.76 seconds
Started Jul 14 07:07:38 PM PDT 24
Finished Jul 14 07:07:44 PM PDT 24
Peak memory 204624 kb
Host smart-c42517d8-25a4-4756-8b66-9f5c7c2e68d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594057506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2594057506
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.555092978
Short name T1111
Test name
Test status
Simulation time 17219844 ps
CPU time 0.73 seconds
Started Jul 14 07:07:39 PM PDT 24
Finished Jul 14 07:07:45 PM PDT 24
Peak memory 204300 kb
Host smart-10adb0dc-907d-4ecb-a154-9a9895719d09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555092978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.555092978
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1262144164
Short name T1011
Test name
Test status
Simulation time 103757463 ps
CPU time 0.67 seconds
Started Jul 14 07:07:38 PM PDT 24
Finished Jul 14 07:07:44 PM PDT 24
Peak memory 204592 kb
Host smart-470b5be4-8973-4e04-8830-a1c107f076d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262144164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1262144164
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1849009686
Short name T1012
Test name
Test status
Simulation time 31091780 ps
CPU time 0.73 seconds
Started Jul 14 07:07:39 PM PDT 24
Finished Jul 14 07:07:45 PM PDT 24
Peak memory 204272 kb
Host smart-130bb7f1-9a08-484b-a0c5-31fffebe13bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849009686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1849009686
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4153988532
Short name T1020
Test name
Test status
Simulation time 27669209 ps
CPU time 0.81 seconds
Started Jul 14 07:07:41 PM PDT 24
Finished Jul 14 07:07:46 PM PDT 24
Peak memory 204240 kb
Host smart-8a40fbd8-0698-4a17-8aac-8afcfb2ea974
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153988532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
4153988532
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1567667812
Short name T1033
Test name
Test status
Simulation time 14186556 ps
CPU time 0.74 seconds
Started Jul 14 07:07:39 PM PDT 24
Finished Jul 14 07:07:45 PM PDT 24
Peak memory 204604 kb
Host smart-a78cb99b-408e-4e87-af61-df4bbba9001e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567667812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1567667812
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3080500929
Short name T1029
Test name
Test status
Simulation time 13405870 ps
CPU time 0.8 seconds
Started Jul 14 07:07:36 PM PDT 24
Finished Jul 14 07:07:40 PM PDT 24
Peak memory 204324 kb
Host smart-382d131b-56e3-4c9e-9510-14d9cf693698
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080500929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3080500929
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.304984173
Short name T1014
Test name
Test status
Simulation time 44767898 ps
CPU time 0.72 seconds
Started Jul 14 07:07:42 PM PDT 24
Finished Jul 14 07:07:48 PM PDT 24
Peak memory 204308 kb
Host smart-45af4800-cc12-41af-bf24-4baf14e3635d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304984173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.304984173
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1004055451
Short name T101
Test name
Test status
Simulation time 26655340 ps
CPU time 1.66 seconds
Started Jul 14 07:07:24 PM PDT 24
Finished Jul 14 07:07:28 PM PDT 24
Peak memory 215860 kb
Host smart-47f80561-909e-4469-97e3-e4cd978fd1e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004055451 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1004055451
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2721313144
Short name T123
Test name
Test status
Simulation time 20764192 ps
CPU time 1.29 seconds
Started Jul 14 07:07:20 PM PDT 24
Finished Jul 14 07:07:24 PM PDT 24
Peak memory 215660 kb
Host smart-8d8f68fb-4db7-4d94-98ce-40c01b999d36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721313144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
721313144
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3950425561
Short name T1066
Test name
Test status
Simulation time 19296576 ps
CPU time 0.72 seconds
Started Jul 14 07:07:21 PM PDT 24
Finished Jul 14 07:07:24 PM PDT 24
Peak memory 204292 kb
Host smart-d2ab4a2b-1e0f-4757-aa16-8e5bda58777a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950425561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
950425561
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4096017416
Short name T144
Test name
Test status
Simulation time 65542581 ps
CPU time 3.79 seconds
Started Jul 14 07:07:21 PM PDT 24
Finished Jul 14 07:07:26 PM PDT 24
Peak memory 215756 kb
Host smart-6f409df4-a4b9-4fba-94df-382fc7a50c89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096017416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.4096017416
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.4220951129
Short name T1059
Test name
Test status
Simulation time 90452552 ps
CPU time 2.68 seconds
Started Jul 14 07:07:18 PM PDT 24
Finished Jul 14 07:07:23 PM PDT 24
Peak memory 215948 kb
Host smart-db9b9609-bc55-4cc1-8eda-d504ed413e69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220951129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.4
220951129
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2628393668
Short name T1075
Test name
Test status
Simulation time 921729691 ps
CPU time 6.48 seconds
Started Jul 14 07:07:21 PM PDT 24
Finished Jul 14 07:07:30 PM PDT 24
Peak memory 215760 kb
Host smart-ada55305-0571-46cd-a8ae-b2875708ad77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628393668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2628393668
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1462816937
Short name T70
Test name
Test status
Simulation time 184461023 ps
CPU time 1.64 seconds
Started Jul 14 07:07:21 PM PDT 24
Finished Jul 14 07:07:26 PM PDT 24
Peak memory 215828 kb
Host smart-6014663c-0fca-4e99-96ae-2e091b7310aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462816937 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1462816937
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1960635005
Short name T1124
Test name
Test status
Simulation time 39815977 ps
CPU time 1.27 seconds
Started Jul 14 07:07:25 PM PDT 24
Finished Jul 14 07:07:29 PM PDT 24
Peak memory 215736 kb
Host smart-9e03bd39-2f7a-419e-ba04-39b734bce4f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960635005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
960635005
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.928080939
Short name T1096
Test name
Test status
Simulation time 15463549 ps
CPU time 0.71 seconds
Started Jul 14 07:07:22 PM PDT 24
Finished Jul 14 07:07:25 PM PDT 24
Peak memory 204280 kb
Host smart-b23ffbf3-4562-4e7c-a3ee-20c1e26d8bf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928080939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.928080939
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1517434285
Short name T1049
Test name
Test status
Simulation time 62505385 ps
CPU time 3.49 seconds
Started Jul 14 07:07:20 PM PDT 24
Finished Jul 14 07:07:26 PM PDT 24
Peak memory 215776 kb
Host smart-c9148833-e4b7-4719-afc8-6ff4ce8d0b2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517434285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1517434285
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1419761969
Short name T173
Test name
Test status
Simulation time 135239474 ps
CPU time 3.37 seconds
Started Jul 14 07:07:21 PM PDT 24
Finished Jul 14 07:07:27 PM PDT 24
Peak memory 215952 kb
Host smart-149a4d2e-4f29-4512-ba3d-5c5079d2c47d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419761969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
419761969
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3873452763
Short name T1023
Test name
Test status
Simulation time 276667484 ps
CPU time 3.96 seconds
Started Jul 14 07:07:26 PM PDT 24
Finished Jul 14 07:07:32 PM PDT 24
Peak memory 218532 kb
Host smart-3941f784-2280-468f-bd58-43f055835167
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873452763 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3873452763
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3042148989
Short name T1100
Test name
Test status
Simulation time 69701742 ps
CPU time 1.35 seconds
Started Jul 14 07:07:24 PM PDT 24
Finished Jul 14 07:07:27 PM PDT 24
Peak memory 207520 kb
Host smart-0165f3e8-7e35-47cf-bcc4-7bc458401775
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042148989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
042148989
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.688291793
Short name T1081
Test name
Test status
Simulation time 11484965 ps
CPU time 0.75 seconds
Started Jul 14 07:07:35 PM PDT 24
Finished Jul 14 07:07:38 PM PDT 24
Peak memory 204324 kb
Host smart-158ba964-a43a-46be-8057-984af4a37876
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688291793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.688291793
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1247631229
Short name T142
Test name
Test status
Simulation time 107647234 ps
CPU time 1.67 seconds
Started Jul 14 07:07:34 PM PDT 24
Finished Jul 14 07:07:38 PM PDT 24
Peak memory 215668 kb
Host smart-405cdead-0dbf-4a85-b090-7a628769fe55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247631229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1247631229
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1286577496
Short name T1068
Test name
Test status
Simulation time 1250534458 ps
CPU time 7.95 seconds
Started Jul 14 07:07:27 PM PDT 24
Finished Jul 14 07:07:37 PM PDT 24
Peak memory 215932 kb
Host smart-ca510900-ec27-4cc1-9b6f-23bc880f223d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286577496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1286577496
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3787084618
Short name T156
Test name
Test status
Simulation time 374460432 ps
CPU time 2.87 seconds
Started Jul 14 07:07:34 PM PDT 24
Finished Jul 14 07:07:39 PM PDT 24
Peak memory 218372 kb
Host smart-83f5d764-f70a-4b24-80eb-de7f970c6c93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787084618 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3787084618
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1047148896
Short name T128
Test name
Test status
Simulation time 450867355 ps
CPU time 2.77 seconds
Started Jul 14 07:07:29 PM PDT 24
Finished Jul 14 07:07:32 PM PDT 24
Peak memory 215680 kb
Host smart-8cd9881e-58c4-4bc9-b517-d2cee622907c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047148896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
047148896
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3892459450
Short name T1072
Test name
Test status
Simulation time 21527231 ps
CPU time 0.7 seconds
Started Jul 14 07:07:33 PM PDT 24
Finished Jul 14 07:07:34 PM PDT 24
Peak memory 204600 kb
Host smart-8c7d474b-6767-414c-9a92-d590aec81e82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892459450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
892459450
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2121428382
Short name T157
Test name
Test status
Simulation time 82919724 ps
CPU time 1.94 seconds
Started Jul 14 07:07:35 PM PDT 24
Finished Jul 14 07:07:39 PM PDT 24
Peak memory 215620 kb
Host smart-7d5f77da-7684-4f0d-8dc6-8cbc3fdba202
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121428382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2121428382
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.900979834
Short name T108
Test name
Test status
Simulation time 350283791 ps
CPU time 4.93 seconds
Started Jul 14 07:07:31 PM PDT 24
Finished Jul 14 07:07:37 PM PDT 24
Peak memory 216028 kb
Host smart-8d7297e8-a5be-426e-a72e-2892041580c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900979834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.900979834
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.412901433
Short name T1040
Test name
Test status
Simulation time 648761417 ps
CPU time 7.44 seconds
Started Jul 14 07:07:26 PM PDT 24
Finished Jul 14 07:07:36 PM PDT 24
Peak memory 215896 kb
Host smart-6fa6d78b-1f39-4915-83b9-4844ab3fcded
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412901433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.412901433
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.746637224
Short name T112
Test name
Test status
Simulation time 164814362 ps
CPU time 2.05 seconds
Started Jul 14 07:07:24 PM PDT 24
Finished Jul 14 07:07:29 PM PDT 24
Peak memory 216852 kb
Host smart-d6613441-8b83-4987-bb42-4f5eb833d7fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746637224 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.746637224
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2597644497
Short name T130
Test name
Test status
Simulation time 30453668 ps
CPU time 1.88 seconds
Started Jul 14 07:07:25 PM PDT 24
Finished Jul 14 07:07:29 PM PDT 24
Peak memory 207500 kb
Host smart-546d469d-edfd-4d79-a1ed-4078b5a20ef0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597644497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
597644497
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3168247663
Short name T1032
Test name
Test status
Simulation time 16993342 ps
CPU time 0.73 seconds
Started Jul 14 07:07:33 PM PDT 24
Finished Jul 14 07:07:35 PM PDT 24
Peak memory 204328 kb
Host smart-61be7533-22b5-40c6-b07d-9c40fe4970f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168247663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
168247663
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1577918510
Short name T153
Test name
Test status
Simulation time 294568949 ps
CPU time 3.24 seconds
Started Jul 14 07:07:33 PM PDT 24
Finished Jul 14 07:07:38 PM PDT 24
Peak memory 215816 kb
Host smart-f9e8ab0d-102b-49d4-8c40-b639febcc207
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577918510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1577918510
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2169222546
Short name T1053
Test name
Test status
Simulation time 46292883 ps
CPU time 1.35 seconds
Started Jul 14 07:07:30 PM PDT 24
Finished Jul 14 07:07:32 PM PDT 24
Peak memory 207820 kb
Host smart-980765fe-cab0-45b5-b60f-30af396a5392
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169222546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
169222546
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.674667135
Short name T103
Test name
Test status
Simulation time 582674806 ps
CPU time 14.35 seconds
Started Jul 14 07:07:26 PM PDT 24
Finished Jul 14 07:07:43 PM PDT 24
Peak memory 216196 kb
Host smart-8b40c065-2dbf-4247-b8f9-469dcb415d15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674667135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.674667135
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3205284340
Short name T710
Test name
Test status
Simulation time 43112247 ps
CPU time 0.69 seconds
Started Jul 14 06:54:30 PM PDT 24
Finished Jul 14 06:54:34 PM PDT 24
Peak memory 204948 kb
Host smart-20f0e578-7352-4743-b2b3-79dfecd75ac3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205284340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
205284340
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2299433113
Short name T907
Test name
Test status
Simulation time 356453770 ps
CPU time 5.39 seconds
Started Jul 14 06:54:41 PM PDT 24
Finished Jul 14 06:54:48 PM PDT 24
Peak memory 224436 kb
Host smart-bffeb9e0-0068-4e16-a7f2-088355868efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299433113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2299433113
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3216525852
Short name T344
Test name
Test status
Simulation time 155313801 ps
CPU time 0.76 seconds
Started Jul 14 06:54:33 PM PDT 24
Finished Jul 14 06:54:37 PM PDT 24
Peak memory 206916 kb
Host smart-53394d49-ee4e-4265-8e99-e4baf3d80189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216525852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3216525852
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2655862134
Short name T465
Test name
Test status
Simulation time 4585527625 ps
CPU time 73.18 seconds
Started Jul 14 06:54:45 PM PDT 24
Finished Jul 14 06:56:01 PM PDT 24
Peak memory 253340 kb
Host smart-ab42729f-5119-4e50-822e-60e587260e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655862134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2655862134
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1426192728
Short name T692
Test name
Test status
Simulation time 5528139251 ps
CPU time 28.02 seconds
Started Jul 14 06:54:34 PM PDT 24
Finished Jul 14 06:55:06 PM PDT 24
Peak memory 219464 kb
Host smart-c4b7bbd7-d895-4020-b194-7e0597d3f9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426192728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1426192728
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3896144344
Short name T943
Test name
Test status
Simulation time 1193069648 ps
CPU time 19.78 seconds
Started Jul 14 06:54:34 PM PDT 24
Finished Jul 14 06:54:58 PM PDT 24
Peak memory 217388 kb
Host smart-1ec25998-be14-45c1-836b-b122d7d30288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896144344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3896144344
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3012953587
Short name T149
Test name
Test status
Simulation time 3794245986 ps
CPU time 39.65 seconds
Started Jul 14 06:54:29 PM PDT 24
Finished Jul 14 06:55:12 PM PDT 24
Peak memory 241008 kb
Host smart-3994f8a5-099c-4399-b962-347861845480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012953587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3012953587
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.2570402006
Short name T219
Test name
Test status
Simulation time 2027441665 ps
CPU time 20.65 seconds
Started Jul 14 06:55:53 PM PDT 24
Finished Jul 14 06:56:15 PM PDT 24
Peak memory 238112 kb
Host smart-7c2a50e0-34cf-410f-ac0c-6bab0a67e3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570402006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.2570402006
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2038991922
Short name T348
Test name
Test status
Simulation time 294704897 ps
CPU time 2.22 seconds
Started Jul 14 06:54:47 PM PDT 24
Finished Jul 14 06:54:52 PM PDT 24
Peak memory 223028 kb
Host smart-c1085367-78d1-4fed-a942-21469401836d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038991922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2038991922
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3713862097
Short name T246
Test name
Test status
Simulation time 2243737029 ps
CPU time 18.97 seconds
Started Jul 14 06:54:30 PM PDT 24
Finished Jul 14 06:54:52 PM PDT 24
Peak memory 238116 kb
Host smart-480b3b70-c6bf-44f5-a504-faa242aa869c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713862097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3713862097
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.775738073
Short name T821
Test name
Test status
Simulation time 450091878 ps
CPU time 4.15 seconds
Started Jul 14 06:54:41 PM PDT 24
Finished Jul 14 06:54:47 PM PDT 24
Peak memory 224404 kb
Host smart-877073da-d4f4-4f52-89e9-6297e7eb64e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775738073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
775738073
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3889793514
Short name T361
Test name
Test status
Simulation time 1336554964 ps
CPU time 3.03 seconds
Started Jul 14 06:54:41 PM PDT 24
Finished Jul 14 06:54:46 PM PDT 24
Peak memory 224452 kb
Host smart-331049e8-b47b-4bac-aec7-572b5755d440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889793514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3889793514
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2513400272
Short name T704
Test name
Test status
Simulation time 2289824511 ps
CPU time 4.5 seconds
Started Jul 14 06:55:38 PM PDT 24
Finished Jul 14 06:55:45 PM PDT 24
Peak memory 222196 kb
Host smart-022cf854-21ec-4742-b358-77a5d117c768
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2513400272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2513400272
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1333030859
Short name T75
Test name
Test status
Simulation time 39656682 ps
CPU time 1 seconds
Started Jul 14 06:54:41 PM PDT 24
Finished Jul 14 06:54:44 PM PDT 24
Peak memory 235896 kb
Host smart-a75c0a8a-fd1b-490b-829e-4ec1a6411fcd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333030859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1333030859
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3545363852
Short name T882
Test name
Test status
Simulation time 54354368713 ps
CPU time 505.94 seconds
Started Jul 14 06:54:54 PM PDT 24
Finished Jul 14 07:03:22 PM PDT 24
Peak memory 270040 kb
Host smart-8ecf9a9c-a37b-4b04-9024-1cb7044d1068
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545363852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3545363852
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2968304799
Short name T441
Test name
Test status
Simulation time 5219370246 ps
CPU time 28.79 seconds
Started Jul 14 06:54:35 PM PDT 24
Finished Jul 14 06:55:07 PM PDT 24
Peak memory 216336 kb
Host smart-d5c2b485-ef94-4fc3-952b-ed7a41f610fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968304799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2968304799
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3714669003
Short name T962
Test name
Test status
Simulation time 1715340129 ps
CPU time 5.32 seconds
Started Jul 14 06:54:51 PM PDT 24
Finished Jul 14 06:54:58 PM PDT 24
Peak memory 216264 kb
Host smart-291b0bcb-8001-420a-adf8-7437ebf5e3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714669003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3714669003
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2899819843
Short name T634
Test name
Test status
Simulation time 163176629 ps
CPU time 5.95 seconds
Started Jul 14 06:54:46 PM PDT 24
Finished Jul 14 06:54:55 PM PDT 24
Peak memory 216284 kb
Host smart-1c8065b0-1228-4f0a-b264-d8e17fec2d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899819843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2899819843
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.790779501
Short name T408
Test name
Test status
Simulation time 14660549 ps
CPU time 0.74 seconds
Started Jul 14 06:54:30 PM PDT 24
Finished Jul 14 06:54:35 PM PDT 24
Peak memory 206000 kb
Host smart-32c3bf70-fead-4953-872b-35473734f9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790779501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.790779501
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.759127078
Short name T577
Test name
Test status
Simulation time 130552136 ps
CPU time 3.04 seconds
Started Jul 14 06:54:40 PM PDT 24
Finished Jul 14 06:54:45 PM PDT 24
Peak memory 224384 kb
Host smart-c38d8584-83ed-41eb-8a33-44743e61146a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759127078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.759127078
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.824755884
Short name T576
Test name
Test status
Simulation time 12328418 ps
CPU time 0.74 seconds
Started Jul 14 06:54:39 PM PDT 24
Finished Jul 14 06:54:42 PM PDT 24
Peak memory 205492 kb
Host smart-5e0c02af-9fce-4b96-8aad-bfc56934ebc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824755884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.824755884
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.940920743
Short name T729
Test name
Test status
Simulation time 380768647 ps
CPU time 3.09 seconds
Started Jul 14 06:54:33 PM PDT 24
Finished Jul 14 06:54:40 PM PDT 24
Peak memory 232676 kb
Host smart-c2ea6989-c55b-4c85-820c-5c4cd643e9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940920743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.940920743
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3285757709
Short name T780
Test name
Test status
Simulation time 26541619 ps
CPU time 0.76 seconds
Started Jul 14 06:54:38 PM PDT 24
Finished Jul 14 06:54:41 PM PDT 24
Peak memory 206584 kb
Host smart-07ba5aed-982e-4774-963d-e705d2093a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285757709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3285757709
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2723418964
Short name T985
Test name
Test status
Simulation time 12601198439 ps
CPU time 84.77 seconds
Started Jul 14 06:54:37 PM PDT 24
Finished Jul 14 06:56:05 PM PDT 24
Peak memory 264888 kb
Host smart-11f3841f-9954-44a8-b454-dce7dbb726f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723418964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2723418964
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2247799912
Short name T86
Test name
Test status
Simulation time 15927055567 ps
CPU time 124.63 seconds
Started Jul 14 06:54:43 PM PDT 24
Finished Jul 14 06:56:50 PM PDT 24
Peak memory 267948 kb
Host smart-5aeeaaf0-9b15-49be-bf49-54a735f68788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247799912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2247799912
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3608509288
Short name T886
Test name
Test status
Simulation time 560212519 ps
CPU time 12.63 seconds
Started Jul 14 06:54:55 PM PDT 24
Finished Jul 14 06:55:09 PM PDT 24
Peak memory 224520 kb
Host smart-98abc6af-767d-482d-9e96-efd49290974f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608509288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3608509288
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.325811817
Short name T195
Test name
Test status
Simulation time 32851812620 ps
CPU time 68.57 seconds
Started Jul 14 06:54:46 PM PDT 24
Finished Jul 14 06:55:58 PM PDT 24
Peak memory 266340 kb
Host smart-979f4ed0-0e0b-49c0-bb95-9adc17d83911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325811817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.
325811817
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1835224272
Short name T329
Test name
Test status
Simulation time 897612550 ps
CPU time 11.22 seconds
Started Jul 14 06:54:44 PM PDT 24
Finished Jul 14 06:54:59 PM PDT 24
Peak memory 232628 kb
Host smart-d2643ca0-01e2-4876-94eb-18c47bf90c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835224272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1835224272
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2423829935
Short name T719
Test name
Test status
Simulation time 1094183573 ps
CPU time 7.28 seconds
Started Jul 14 06:54:40 PM PDT 24
Finished Jul 14 06:54:50 PM PDT 24
Peak memory 224488 kb
Host smart-632a6dab-17cb-4e6b-940a-e0eebb0fc632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423829935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2423829935
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1728045401
Short name T973
Test name
Test status
Simulation time 77136195 ps
CPU time 2.29 seconds
Started Jul 14 06:54:47 PM PDT 24
Finished Jul 14 06:54:52 PM PDT 24
Peak memory 224464 kb
Host smart-517070f2-58ed-40c9-9581-e4144cbd3c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728045401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1728045401
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1097460269
Short name T241
Test name
Test status
Simulation time 5620127385 ps
CPU time 7.05 seconds
Started Jul 14 06:54:30 PM PDT 24
Finished Jul 14 06:54:49 PM PDT 24
Peak memory 239396 kb
Host smart-d17fa305-ab4c-4e52-a185-c73872f525d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097460269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1097460269
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1650506850
Short name T954
Test name
Test status
Simulation time 742904062 ps
CPU time 9.7 seconds
Started Jul 14 06:54:33 PM PDT 24
Finished Jul 14 06:54:46 PM PDT 24
Peak memory 222124 kb
Host smart-2de5c5b0-a0fb-49f8-a780-aacc0f7f4b6e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1650506850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1650506850
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3170261029
Short name T73
Test name
Test status
Simulation time 78520657 ps
CPU time 1.17 seconds
Started Jul 14 06:54:35 PM PDT 24
Finished Jul 14 06:54:44 PM PDT 24
Peak memory 236040 kb
Host smart-0e6c70dd-4ff0-4464-a636-68924871ede8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170261029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3170261029
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2107817821
Short name T438
Test name
Test status
Simulation time 178277130125 ps
CPU time 223.25 seconds
Started Jul 14 06:54:51 PM PDT 24
Finished Jul 14 06:58:37 PM PDT 24
Peak memory 252196 kb
Host smart-8531d0d6-ec75-4f87-aa86-43c111fcd773
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107817821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2107817821
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.852253157
Short name T830
Test name
Test status
Simulation time 49155344063 ps
CPU time 15.67 seconds
Started Jul 14 06:54:42 PM PDT 24
Finished Jul 14 06:54:59 PM PDT 24
Peak memory 216404 kb
Host smart-d41ed7fc-099f-46c1-9526-266c5a5ec246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852253157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.852253157
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.572656670
Short name T346
Test name
Test status
Simulation time 754628296 ps
CPU time 1.51 seconds
Started Jul 14 06:54:51 PM PDT 24
Finished Jul 14 06:54:55 PM PDT 24
Peak memory 207036 kb
Host smart-93391144-1c11-469c-bcd4-9f16adf8ec50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572656670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.572656670
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3251206151
Short name T705
Test name
Test status
Simulation time 156257643 ps
CPU time 1.53 seconds
Started Jul 14 06:54:43 PM PDT 24
Finished Jul 14 06:54:46 PM PDT 24
Peak memory 207936 kb
Host smart-c679a433-1f7d-49bf-9cdf-7c6d44378098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251206151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3251206151
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.757420927
Short name T966
Test name
Test status
Simulation time 16977691 ps
CPU time 0.72 seconds
Started Jul 14 06:54:41 PM PDT 24
Finished Jul 14 06:54:50 PM PDT 24
Peak memory 206000 kb
Host smart-326159a0-7110-4314-8b09-194bef4998b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757420927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.757420927
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3104891170
Short name T935
Test name
Test status
Simulation time 38579414373 ps
CPU time 34.03 seconds
Started Jul 14 06:54:35 PM PDT 24
Finished Jul 14 06:55:13 PM PDT 24
Peak memory 224644 kb
Host smart-3526d491-b39a-43e5-9262-b4243902b9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104891170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3104891170
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2399610975
Short name T732
Test name
Test status
Simulation time 32123613 ps
CPU time 0.72 seconds
Started Jul 14 06:55:19 PM PDT 24
Finished Jul 14 06:55:22 PM PDT 24
Peak memory 205548 kb
Host smart-ad3753a9-9a88-40e3-b752-663457ffc9eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399610975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2399610975
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.4158118958
Short name T754
Test name
Test status
Simulation time 959255034 ps
CPU time 9.98 seconds
Started Jul 14 06:55:12 PM PDT 24
Finished Jul 14 06:55:27 PM PDT 24
Peak memory 224104 kb
Host smart-4b9b1ee9-5784-4cf9-bbd0-6b165e5476bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158118958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.4158118958
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3253058331
Short name T572
Test name
Test status
Simulation time 21749492 ps
CPU time 0.82 seconds
Started Jul 14 06:55:06 PM PDT 24
Finished Jul 14 06:55:12 PM PDT 24
Peak memory 206512 kb
Host smart-29f8b8b5-79e4-43b3-9a4c-29c430d0bca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253058331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3253058331
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2207837443
Short name T390
Test name
Test status
Simulation time 2718901744 ps
CPU time 29.08 seconds
Started Jul 14 06:55:11 PM PDT 24
Finished Jul 14 06:55:45 PM PDT 24
Peak memory 240440 kb
Host smart-bea428a0-53bd-44b5-a75d-054195f9b5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207837443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2207837443
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3382700670
Short name T680
Test name
Test status
Simulation time 21513556254 ps
CPU time 218.94 seconds
Started Jul 14 06:55:19 PM PDT 24
Finished Jul 14 06:59:00 PM PDT 24
Peak memory 256916 kb
Host smart-bcf3ee3a-a50e-4ce4-9194-9129f0ce0612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382700670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3382700670
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2759412530
Short name T140
Test name
Test status
Simulation time 5175121306 ps
CPU time 81.82 seconds
Started Jul 14 06:55:04 PM PDT 24
Finished Jul 14 06:56:30 PM PDT 24
Peak memory 249256 kb
Host smart-05e02f17-e41c-4921-9cd5-b2795a538657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759412530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2759412530
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3228297047
Short name T793
Test name
Test status
Simulation time 224585473 ps
CPU time 3.81 seconds
Started Jul 14 06:55:02 PM PDT 24
Finished Jul 14 06:55:09 PM PDT 24
Peak memory 224464 kb
Host smart-367d370e-e15e-4c96-98de-b46107d82d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228297047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3228297047
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.2388682772
Short name T493
Test name
Test status
Simulation time 29983504758 ps
CPU time 100.95 seconds
Started Jul 14 06:55:15 PM PDT 24
Finished Jul 14 06:56:59 PM PDT 24
Peak memory 250192 kb
Host smart-6c71af9d-fc4f-48ad-8cdf-5ed388ef7c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388682772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.2388682772
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1778699207
Short name T785
Test name
Test status
Simulation time 554438340 ps
CPU time 3.46 seconds
Started Jul 14 06:55:04 PM PDT 24
Finished Jul 14 06:55:13 PM PDT 24
Peak memory 232652 kb
Host smart-48c8c84c-e0e6-4364-bad1-f5f57ef7a0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778699207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1778699207
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.441693425
Short name T495
Test name
Test status
Simulation time 54735539 ps
CPU time 2.44 seconds
Started Jul 14 06:55:04 PM PDT 24
Finished Jul 14 06:55:12 PM PDT 24
Peak memory 232328 kb
Host smart-c133e7bc-fc27-460e-af46-680899312801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441693425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.441693425
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.4198553059
Short name T9
Test name
Test status
Simulation time 1691701985 ps
CPU time 4.01 seconds
Started Jul 14 06:55:04 PM PDT 24
Finished Jul 14 06:55:12 PM PDT 24
Peak memory 232648 kb
Host smart-3646a828-7068-4719-9af8-cada331c8e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198553059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.4198553059
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.565798042
Short name T659
Test name
Test status
Simulation time 607582704 ps
CPU time 2.96 seconds
Started Jul 14 06:55:02 PM PDT 24
Finished Jul 14 06:55:10 PM PDT 24
Peak memory 232672 kb
Host smart-1330084b-8e87-4445-9e53-e17850bf3879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565798042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.565798042
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1973610430
Short name T464
Test name
Test status
Simulation time 14568486899 ps
CPU time 16.25 seconds
Started Jul 14 06:54:52 PM PDT 24
Finished Jul 14 06:55:10 PM PDT 24
Peak memory 222244 kb
Host smart-308ae9b8-408d-4155-a1c7-d7fa4299e947
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1973610430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1973610430
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1586352373
Short name T910
Test name
Test status
Simulation time 21192090660 ps
CPU time 51.05 seconds
Started Jul 14 06:55:00 PM PDT 24
Finished Jul 14 06:55:54 PM PDT 24
Peak memory 216384 kb
Host smart-78428f7c-4ae1-4199-8323-53e87bca18be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586352373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1586352373
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2357815666
Short name T725
Test name
Test status
Simulation time 15113275596 ps
CPU time 10.46 seconds
Started Jul 14 06:55:28 PM PDT 24
Finished Jul 14 06:55:43 PM PDT 24
Peak memory 216348 kb
Host smart-e6dc7b1b-3151-4ddb-8ea4-23a727b128d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357815666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2357815666
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2538924032
Short name T377
Test name
Test status
Simulation time 52700557 ps
CPU time 1.15 seconds
Started Jul 14 06:55:02 PM PDT 24
Finished Jul 14 06:55:08 PM PDT 24
Peak memory 207772 kb
Host smart-0e157db4-7b4e-412c-8c2e-e89606542a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538924032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2538924032
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2109889253
Short name T333
Test name
Test status
Simulation time 37720042 ps
CPU time 0.76 seconds
Started Jul 14 06:54:59 PM PDT 24
Finished Jul 14 06:55:02 PM PDT 24
Peak memory 205956 kb
Host smart-ccf08dbc-beaf-4e94-a0f6-e32f0104b04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109889253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2109889253
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2291438150
Short name T853
Test name
Test status
Simulation time 6644040901 ps
CPU time 8.25 seconds
Started Jul 14 06:55:10 PM PDT 24
Finished Jul 14 06:55:23 PM PDT 24
Peak memory 233852 kb
Host smart-1e9d79f8-97a1-4d88-8ce5-fbf6c1416b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291438150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2291438150
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1841216806
Short name T610
Test name
Test status
Simulation time 185660423 ps
CPU time 2.58 seconds
Started Jul 14 06:55:10 PM PDT 24
Finished Jul 14 06:55:18 PM PDT 24
Peak memory 232624 kb
Host smart-63cf7a75-fa78-4756-a545-14d12a157add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841216806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1841216806
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.59984190
Short name T326
Test name
Test status
Simulation time 39282586 ps
CPU time 0.78 seconds
Started Jul 14 06:55:02 PM PDT 24
Finished Jul 14 06:55:08 PM PDT 24
Peak memory 206600 kb
Host smart-c7ef6e07-7970-4cb0-8e7d-a8c2c6624d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59984190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.59984190
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.613829806
Short name T989
Test name
Test status
Simulation time 509701998677 ps
CPU time 336.36 seconds
Started Jul 14 06:55:19 PM PDT 24
Finished Jul 14 07:00:58 PM PDT 24
Peak memory 256928 kb
Host smart-f8e3cd7c-0535-45d4-8935-08ead239d4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613829806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.613829806
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.180548063
Short name T273
Test name
Test status
Simulation time 31621598214 ps
CPU time 286.36 seconds
Started Jul 14 06:55:16 PM PDT 24
Finished Jul 14 07:00:06 PM PDT 24
Peak memory 252824 kb
Host smart-8d5265c9-33fa-418c-97b7-b764a3f983a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180548063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.180548063
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.319993088
Short name T342
Test name
Test status
Simulation time 140291678580 ps
CPU time 94.47 seconds
Started Jul 14 06:55:14 PM PDT 24
Finished Jul 14 06:56:52 PM PDT 24
Peak memory 249292 kb
Host smart-2c5bd9a3-ce94-43c5-bb8c-0e003afc0441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319993088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.319993088
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.1037653366
Short name T509
Test name
Test status
Simulation time 2503200661 ps
CPU time 11.59 seconds
Started Jul 14 06:55:01 PM PDT 24
Finished Jul 14 06:55:15 PM PDT 24
Peak memory 239584 kb
Host smart-4aac33e6-0ee6-44c3-ab18-9a1acd42e3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037653366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.1037653366
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2270653876
Short name T433
Test name
Test status
Simulation time 740395339 ps
CPU time 8.85 seconds
Started Jul 14 06:55:05 PM PDT 24
Finished Jul 14 06:55:20 PM PDT 24
Peak memory 224396 kb
Host smart-9245ba76-c021-4054-b312-5252d4dae612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270653876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2270653876
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1533487166
Short name T514
Test name
Test status
Simulation time 6100727482 ps
CPU time 60.04 seconds
Started Jul 14 06:55:05 PM PDT 24
Finished Jul 14 06:56:10 PM PDT 24
Peak memory 224532 kb
Host smart-42c22a8f-3b96-45e4-b359-f34f3700433f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533487166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1533487166
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2497526044
Short name T479
Test name
Test status
Simulation time 271935853 ps
CPU time 3.14 seconds
Started Jul 14 06:55:13 PM PDT 24
Finished Jul 14 06:55:20 PM PDT 24
Peak memory 232684 kb
Host smart-bb4d797b-6089-40f8-b0c7-c0a439dca102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497526044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2497526044
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.649799021
Short name T701
Test name
Test status
Simulation time 2981062461 ps
CPU time 11.77 seconds
Started Jul 14 06:55:11 PM PDT 24
Finished Jul 14 06:55:28 PM PDT 24
Peak memory 224556 kb
Host smart-c9ec2d74-83b6-4708-9c81-42fdb8df0d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649799021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.649799021
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2394030235
Short name T770
Test name
Test status
Simulation time 4842278158 ps
CPU time 13.76 seconds
Started Jul 14 06:55:05 PM PDT 24
Finished Jul 14 06:55:24 PM PDT 24
Peak memory 220152 kb
Host smart-7a995ecb-6759-4f02-b9ac-c46fee1317d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2394030235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2394030235
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3345118546
Short name T401
Test name
Test status
Simulation time 51853976806 ps
CPU time 219.87 seconds
Started Jul 14 06:55:01 PM PDT 24
Finished Jul 14 06:58:45 PM PDT 24
Peak memory 249280 kb
Host smart-ef2c0440-102d-4be6-979f-f4907a5264da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345118546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3345118546
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2592487039
Short name T689
Test name
Test status
Simulation time 6558126414 ps
CPU time 27.68 seconds
Started Jul 14 06:55:02 PM PDT 24
Finished Jul 14 06:55:33 PM PDT 24
Peak memory 216376 kb
Host smart-3495d243-16b3-45f5-b0bf-c40f58d7b81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592487039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2592487039
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.309690068
Short name T480
Test name
Test status
Simulation time 16161999738 ps
CPU time 11.74 seconds
Started Jul 14 06:55:08 PM PDT 24
Finished Jul 14 06:55:25 PM PDT 24
Peak memory 216372 kb
Host smart-facb187b-8352-4a68-8606-3f28940a0bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309690068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.309690068
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.994825793
Short name T354
Test name
Test status
Simulation time 99741526 ps
CPU time 1.71 seconds
Started Jul 14 06:55:02 PM PDT 24
Finished Jul 14 06:55:07 PM PDT 24
Peak memory 216136 kb
Host smart-f0855b01-fac1-49f0-a75f-4aef45e69198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994825793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.994825793
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3213652445
Short name T27
Test name
Test status
Simulation time 101011059 ps
CPU time 1.02 seconds
Started Jul 14 06:55:11 PM PDT 24
Finished Jul 14 06:55:18 PM PDT 24
Peak memory 205996 kb
Host smart-520df9be-3745-4e91-b5cb-b349228bd4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213652445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3213652445
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3898460356
Short name T839
Test name
Test status
Simulation time 803425075 ps
CPU time 6.3 seconds
Started Jul 14 06:55:12 PM PDT 24
Finished Jul 14 06:55:23 PM PDT 24
Peak memory 224512 kb
Host smart-3c21fad1-7622-4252-9848-94d2b5d1e571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898460356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3898460356
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.552682400
Short name T508
Test name
Test status
Simulation time 13170870 ps
CPU time 0.77 seconds
Started Jul 14 06:55:15 PM PDT 24
Finished Jul 14 06:55:19 PM PDT 24
Peak memory 204996 kb
Host smart-d7a27a0c-3e54-4ba7-a445-1274a59585f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552682400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.552682400
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1938525239
Short name T315
Test name
Test status
Simulation time 50970670 ps
CPU time 2.75 seconds
Started Jul 14 06:55:05 PM PDT 24
Finished Jul 14 06:55:14 PM PDT 24
Peak memory 232660 kb
Host smart-01bdb9a1-dcad-4f58-bba6-bb408f9c08a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938525239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1938525239
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.4181555134
Short name T351
Test name
Test status
Simulation time 16726933 ps
CPU time 0.79 seconds
Started Jul 14 06:55:12 PM PDT 24
Finished Jul 14 06:55:18 PM PDT 24
Peak memory 206628 kb
Host smart-6d7d57ae-2d76-472b-88db-3145c4c259f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181555134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.4181555134
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1311374869
Short name T840
Test name
Test status
Simulation time 11469690757 ps
CPU time 39.03 seconds
Started Jul 14 06:55:27 PM PDT 24
Finished Jul 14 06:56:11 PM PDT 24
Peak memory 249308 kb
Host smart-8f8b9e4a-181e-4513-a643-0f0abc6ce406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311374869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1311374869
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2699878517
Short name T271
Test name
Test status
Simulation time 51672146921 ps
CPU time 276.99 seconds
Started Jul 14 06:55:20 PM PDT 24
Finished Jul 14 06:59:59 PM PDT 24
Peak memory 255016 kb
Host smart-4c6f15af-9f80-4804-ad3a-3088f6d6c75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699878517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2699878517
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2693043002
Short name T81
Test name
Test status
Simulation time 1981998082 ps
CPU time 27.83 seconds
Started Jul 14 06:55:20 PM PDT 24
Finished Jul 14 06:55:50 PM PDT 24
Peak memory 219416 kb
Host smart-317a9d18-fb01-400e-a474-5342b5f8385b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693043002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2693043002
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2674139219
Short name T809
Test name
Test status
Simulation time 1154053587 ps
CPU time 8.26 seconds
Started Jul 14 06:55:06 PM PDT 24
Finished Jul 14 06:55:25 PM PDT 24
Peak memory 232708 kb
Host smart-421686d7-ee31-4f56-96a5-e82f5d58d51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674139219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2674139219
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.3567293959
Short name T47
Test name
Test status
Simulation time 32707586620 ps
CPU time 250.81 seconds
Started Jul 14 06:55:04 PM PDT 24
Finished Jul 14 06:59:19 PM PDT 24
Peak memory 265344 kb
Host smart-6dfe838c-a261-4008-96b4-fc83de52a5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567293959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.3567293959
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1030435811
Short name T7
Test name
Test status
Simulation time 1193564173 ps
CPU time 15.65 seconds
Started Jul 14 06:55:07 PM PDT 24
Finished Jul 14 06:55:28 PM PDT 24
Peak memory 224436 kb
Host smart-be9044ad-9700-4a12-a028-8307cfaf4c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030435811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1030435811
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1825449318
Short name T861
Test name
Test status
Simulation time 2539968706 ps
CPU time 26.26 seconds
Started Jul 14 06:55:02 PM PDT 24
Finished Jul 14 06:55:32 PM PDT 24
Peak memory 232796 kb
Host smart-21547441-2ac0-4593-ad3e-392b06b0d8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825449318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1825449318
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.4062235103
Short name T152
Test name
Test status
Simulation time 851582566 ps
CPU time 5.04 seconds
Started Jul 14 06:55:21 PM PDT 24
Finished Jul 14 06:55:28 PM PDT 24
Peak memory 232700 kb
Host smart-74f8a6a9-b327-4b65-b7f8-4211900965f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062235103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.4062235103
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1671723336
Short name T218
Test name
Test status
Simulation time 1252509595 ps
CPU time 9.6 seconds
Started Jul 14 06:55:06 PM PDT 24
Finished Jul 14 06:55:21 PM PDT 24
Peak memory 240544 kb
Host smart-6f53010f-2975-41b4-830d-a4c49ce0d61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671723336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1671723336
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.846297559
Short name T945
Test name
Test status
Simulation time 300570455 ps
CPU time 3.42 seconds
Started Jul 14 06:55:04 PM PDT 24
Finished Jul 14 06:55:13 PM PDT 24
Peak memory 218740 kb
Host smart-992c790b-d690-404a-9963-e57ee256790a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=846297559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.846297559
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.4192063440
Short name T159
Test name
Test status
Simulation time 56196076 ps
CPU time 1.07 seconds
Started Jul 14 06:55:07 PM PDT 24
Finished Jul 14 06:55:14 PM PDT 24
Peak memory 207024 kb
Host smart-66e6d1e4-50b8-4254-b5fb-e2a2fab0b8f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192063440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.4192063440
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3393801469
Short name T428
Test name
Test status
Simulation time 978629547 ps
CPU time 12.73 seconds
Started Jul 14 06:55:04 PM PDT 24
Finished Jul 14 06:55:21 PM PDT 24
Peak memory 216176 kb
Host smart-f4f3e9ef-7f11-486d-a507-9ca8aae74f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393801469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3393801469
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.341766370
Short name T942
Test name
Test status
Simulation time 6751834081 ps
CPU time 6.8 seconds
Started Jul 14 06:55:00 PM PDT 24
Finished Jul 14 06:55:09 PM PDT 24
Peak memory 216288 kb
Host smart-6158edc0-5a1b-4616-a16f-baa957b0f8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341766370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.341766370
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.175547539
Short name T798
Test name
Test status
Simulation time 37683702 ps
CPU time 1.05 seconds
Started Jul 14 06:55:05 PM PDT 24
Finished Jul 14 06:55:12 PM PDT 24
Peak memory 207920 kb
Host smart-1884a739-de27-4b0f-b69c-063fe83b2504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175547539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.175547539
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3114799145
Short name T368
Test name
Test status
Simulation time 71418879 ps
CPU time 0.9 seconds
Started Jul 14 06:55:12 PM PDT 24
Finished Jul 14 06:55:18 PM PDT 24
Peak memory 205612 kb
Host smart-9259e4b6-0e01-4d3b-a3dd-6469d884d88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114799145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3114799145
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.3788656155
Short name T359
Test name
Test status
Simulation time 2490561725 ps
CPU time 14.45 seconds
Started Jul 14 06:55:04 PM PDT 24
Finished Jul 14 06:55:24 PM PDT 24
Peak memory 232792 kb
Host smart-8c4ae4e3-e6ac-4df0-a85c-16c72b48ca39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788656155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3788656155
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1121795673
Short name T314
Test name
Test status
Simulation time 47630650 ps
CPU time 0.72 seconds
Started Jul 14 06:55:02 PM PDT 24
Finished Jul 14 06:55:07 PM PDT 24
Peak memory 205560 kb
Host smart-2a063dbf-df3d-46f0-ae6d-bf11686b3f6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121795673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1121795673
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.387834723
Short name T259
Test name
Test status
Simulation time 246945481 ps
CPU time 3.14 seconds
Started Jul 14 06:55:11 PM PDT 24
Finished Jul 14 06:55:19 PM PDT 24
Peak memory 224416 kb
Host smart-006397f5-bf51-41f8-8865-1742c204bfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387834723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.387834723
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.717024452
Short name T14
Test name
Test status
Simulation time 28400962 ps
CPU time 0.75 seconds
Started Jul 14 06:55:19 PM PDT 24
Finished Jul 14 06:55:22 PM PDT 24
Peak memory 205584 kb
Host smart-cbb0c1b7-fdb8-4b23-aa25-5b832ea806cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717024452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.717024452
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1926076943
Short name T948
Test name
Test status
Simulation time 628681353 ps
CPU time 12.46 seconds
Started Jul 14 06:55:20 PM PDT 24
Finished Jul 14 06:55:35 PM PDT 24
Peak memory 224524 kb
Host smart-eec1ff36-7933-4bbc-93b0-eb0bcf552626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926076943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1926076943
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2573692934
Short name T139
Test name
Test status
Simulation time 14627046636 ps
CPU time 116.27 seconds
Started Jul 14 06:55:03 PM PDT 24
Finished Jul 14 06:57:04 PM PDT 24
Peak memory 263712 kb
Host smart-90ab7845-7e6c-45b6-8eac-924b558c0e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573692934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2573692934
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3502104639
Short name T150
Test name
Test status
Simulation time 2102539499 ps
CPU time 31.04 seconds
Started Jul 14 06:55:03 PM PDT 24
Finished Jul 14 06:55:38 PM PDT 24
Peak memory 224504 kb
Host smart-ae613fae-c82e-4bf0-b687-06758dc3da77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502104639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3502104639
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.2636965876
Short name T825
Test name
Test status
Simulation time 86946174 ps
CPU time 0.76 seconds
Started Jul 14 06:55:27 PM PDT 24
Finished Jul 14 06:55:31 PM PDT 24
Peak memory 215792 kb
Host smart-1f88e609-f4f9-45aa-b8e2-b8ae08b3bf62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636965876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.2636965876
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2634317337
Short name T625
Test name
Test status
Simulation time 193359398 ps
CPU time 3.22 seconds
Started Jul 14 06:55:06 PM PDT 24
Finished Jul 14 06:55:15 PM PDT 24
Peak memory 232612 kb
Host smart-610c98aa-e30c-4ed0-bd74-a516f9ecc7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634317337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2634317337
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.837629004
Short name T476
Test name
Test status
Simulation time 26669167182 ps
CPU time 79.22 seconds
Started Jul 14 06:55:04 PM PDT 24
Finished Jul 14 06:56:29 PM PDT 24
Peak memory 224536 kb
Host smart-b2e21d1a-2d01-46cc-badf-50adba3f6596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837629004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.837629004
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3783986514
Short name T774
Test name
Test status
Simulation time 4826200628 ps
CPU time 18.44 seconds
Started Jul 14 06:55:00 PM PDT 24
Finished Jul 14 06:55:21 PM PDT 24
Peak memory 240712 kb
Host smart-358cb03b-3b19-48d9-957d-a436c1fd977e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783986514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3783986514
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.665334021
Short name T258
Test name
Test status
Simulation time 68942261 ps
CPU time 2.97 seconds
Started Jul 14 06:55:13 PM PDT 24
Finished Jul 14 06:55:20 PM PDT 24
Peak memory 232704 kb
Host smart-272b52af-aef0-4982-8056-c6b36ebe3a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665334021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.665334021
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3770319141
Short name T787
Test name
Test status
Simulation time 550558413 ps
CPU time 8.68 seconds
Started Jul 14 06:55:02 PM PDT 24
Finished Jul 14 06:55:15 PM PDT 24
Peak memory 223132 kb
Host smart-0299e82f-10bd-426b-b063-bdd03891def3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3770319141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3770319141
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.4176272144
Short name T186
Test name
Test status
Simulation time 6090347999 ps
CPU time 90.44 seconds
Started Jul 14 06:55:16 PM PDT 24
Finished Jul 14 06:56:49 PM PDT 24
Peak memory 251572 kb
Host smart-4e78e884-c32c-43aa-a14b-44d2c31f48f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176272144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.4176272144
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1273391546
Short name T299
Test name
Test status
Simulation time 1096558749 ps
CPU time 3.18 seconds
Started Jul 14 06:55:20 PM PDT 24
Finished Jul 14 06:55:26 PM PDT 24
Peak memory 216488 kb
Host smart-ef113885-5de0-4184-9727-d45afb4727ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273391546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1273391546
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2493086817
Short name T756
Test name
Test status
Simulation time 2168477973 ps
CPU time 7.92 seconds
Started Jul 14 06:55:05 PM PDT 24
Finished Jul 14 06:55:19 PM PDT 24
Peak memory 216316 kb
Host smart-0093061f-f7e2-4241-9edc-437ce4a2b2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493086817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2493086817
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3769115567
Short name T298
Test name
Test status
Simulation time 100346048 ps
CPU time 1 seconds
Started Jul 14 06:55:01 PM PDT 24
Finished Jul 14 06:55:06 PM PDT 24
Peak memory 207512 kb
Host smart-516a7343-c15b-4f99-a2b1-023d0be16d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769115567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3769115567
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1097060136
Short name T511
Test name
Test status
Simulation time 175089272 ps
CPU time 0.89 seconds
Started Jul 14 06:55:04 PM PDT 24
Finished Jul 14 06:55:09 PM PDT 24
Peak memory 205804 kb
Host smart-6a6c973d-a45d-436f-a91a-ef5f3e0b54cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097060136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1097060136
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.431226492
Short name T767
Test name
Test status
Simulation time 30612741418 ps
CPU time 15.67 seconds
Started Jul 14 06:55:18 PM PDT 24
Finished Jul 14 06:55:36 PM PDT 24
Peak memory 232856 kb
Host smart-b1bb105f-f728-49ea-9c85-feb4919db18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431226492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.431226492
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3644901488
Short name T760
Test name
Test status
Simulation time 13404248 ps
CPU time 0.77 seconds
Started Jul 14 06:55:08 PM PDT 24
Finished Jul 14 06:55:14 PM PDT 24
Peak memory 204912 kb
Host smart-52149f31-8225-4a60-a5f9-a9f9de92b9b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644901488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3644901488
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2660870777
Short name T599
Test name
Test status
Simulation time 2893706198 ps
CPU time 11.65 seconds
Started Jul 14 06:55:07 PM PDT 24
Finished Jul 14 06:55:24 PM PDT 24
Peak memory 224596 kb
Host smart-fb99e7f2-cdb0-4015-a2fa-9e8f9f4c3bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660870777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2660870777
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2232069808
Short name T470
Test name
Test status
Simulation time 59539696 ps
CPU time 0.73 seconds
Started Jul 14 06:55:07 PM PDT 24
Finished Jul 14 06:55:13 PM PDT 24
Peak memory 205948 kb
Host smart-0af04166-8b0f-4062-bda3-7fed9aa46a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232069808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2232069808
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.739081369
Short name T172
Test name
Test status
Simulation time 1932706380 ps
CPU time 33.6 seconds
Started Jul 14 06:55:16 PM PDT 24
Finished Jul 14 06:55:53 PM PDT 24
Peak memory 249136 kb
Host smart-66788c4c-633b-441d-8f85-97aaca421786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739081369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.739081369
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.4268821616
Short name T946
Test name
Test status
Simulation time 9217979667 ps
CPU time 61.23 seconds
Started Jul 14 06:55:10 PM PDT 24
Finished Jul 14 06:56:17 PM PDT 24
Peak memory 254280 kb
Host smart-93e81121-0128-4e00-baf7-687f9b45484e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268821616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.4268821616
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2618055429
Short name T967
Test name
Test status
Simulation time 1416051572 ps
CPU time 24.96 seconds
Started Jul 14 06:55:08 PM PDT 24
Finished Jul 14 06:55:38 PM PDT 24
Peak memory 232816 kb
Host smart-92e3b2c4-dbb8-403b-99d6-ad0172688261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618055429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2618055429
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.300857393
Short name T83
Test name
Test status
Simulation time 466112373 ps
CPU time 5.22 seconds
Started Jul 14 06:55:10 PM PDT 24
Finished Jul 14 06:55:20 PM PDT 24
Peak memory 224492 kb
Host smart-186af76e-d1c9-4478-987a-9a195d9da52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300857393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.300857393
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3568884
Short name T589
Test name
Test status
Simulation time 5651514665 ps
CPU time 28.36 seconds
Started Jul 14 06:55:10 PM PDT 24
Finished Jul 14 06:55:43 PM PDT 24
Peak memory 235564 kb
Host smart-9ac7f266-d23a-449f-8842-12f3a1d77629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds.3568884
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1340942601
Short name T213
Test name
Test status
Simulation time 103022631 ps
CPU time 3.72 seconds
Started Jul 14 06:55:16 PM PDT 24
Finished Jul 14 06:55:23 PM PDT 24
Peak memory 231152 kb
Host smart-eddee165-3f60-446c-8bed-954dc3e933b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340942601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1340942601
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.4022268522
Short name T393
Test name
Test status
Simulation time 7022981461 ps
CPU time 24.61 seconds
Started Jul 14 06:55:02 PM PDT 24
Finished Jul 14 06:55:31 PM PDT 24
Peak memory 240940 kb
Host smart-64c9b553-6813-4406-9c21-90a9ab890814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022268522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.4022268522
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.533308156
Short name T269
Test name
Test status
Simulation time 334303118 ps
CPU time 4.31 seconds
Started Jul 14 06:55:13 PM PDT 24
Finished Jul 14 06:55:21 PM PDT 24
Peak memory 232624 kb
Host smart-70ab452c-163e-4bad-a63c-a23af96e27f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533308156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.533308156
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3436016682
Short name T951
Test name
Test status
Simulation time 485657151 ps
CPU time 2.46 seconds
Started Jul 14 06:55:25 PM PDT 24
Finished Jul 14 06:55:30 PM PDT 24
Peak memory 224436 kb
Host smart-553a6124-962c-42e6-acbc-7ce27d11c717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436016682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3436016682
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1191429213
Short name T803
Test name
Test status
Simulation time 854813019 ps
CPU time 7 seconds
Started Jul 14 06:55:24 PM PDT 24
Finished Jul 14 06:55:33 PM PDT 24
Peak memory 222384 kb
Host smart-02eb7257-e345-4c97-878f-bdbb8d1afac0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1191429213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1191429213
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2511361281
Short name T484
Test name
Test status
Simulation time 8770721937 ps
CPU time 48.2 seconds
Started Jul 14 06:55:02 PM PDT 24
Finished Jul 14 06:55:55 PM PDT 24
Peak memory 220272 kb
Host smart-6b460490-29cb-4310-b8ea-dc1802e59330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511361281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2511361281
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1914183574
Short name T905
Test name
Test status
Simulation time 159964666 ps
CPU time 1.03 seconds
Started Jul 14 06:55:05 PM PDT 24
Finished Jul 14 06:55:12 PM PDT 24
Peak memory 206164 kb
Host smart-9df5cdbf-f107-41d8-8602-f2f584ac1a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914183574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1914183574
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.599721458
Short name T355
Test name
Test status
Simulation time 41452892 ps
CPU time 0.69 seconds
Started Jul 14 06:55:14 PM PDT 24
Finished Jul 14 06:55:18 PM PDT 24
Peak memory 205596 kb
Host smart-3c643b58-5b9c-46f0-b3ef-e8fe6ef42d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599721458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.599721458
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2379583459
Short name T998
Test name
Test status
Simulation time 34685787 ps
CPU time 0.69 seconds
Started Jul 14 06:55:02 PM PDT 24
Finished Jul 14 06:55:07 PM PDT 24
Peak memory 205648 kb
Host smart-7d011cd0-b032-468a-a4c1-087cfecc4241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379583459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2379583459
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.4088447383
Short name T742
Test name
Test status
Simulation time 177287128 ps
CPU time 2.67 seconds
Started Jul 14 06:55:20 PM PDT 24
Finished Jul 14 06:55:24 PM PDT 24
Peak memory 224092 kb
Host smart-e3e9dd16-75ee-4dd9-aad2-d7c5823cea52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088447383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.4088447383
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2752591287
Short name T622
Test name
Test status
Simulation time 77028605 ps
CPU time 0.73 seconds
Started Jul 14 06:55:06 PM PDT 24
Finished Jul 14 06:55:12 PM PDT 24
Peak memory 205888 kb
Host smart-2dec807a-acc5-4a41-85d0-182e658c0595
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752591287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2752591287
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3386307387
Short name T477
Test name
Test status
Simulation time 706817526 ps
CPU time 7.08 seconds
Started Jul 14 06:55:15 PM PDT 24
Finished Jul 14 06:55:29 PM PDT 24
Peak memory 224412 kb
Host smart-bfe8b692-2684-48a6-8a23-7ad6a174942f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386307387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3386307387
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3215824973
Short name T367
Test name
Test status
Simulation time 80183962 ps
CPU time 0.78 seconds
Started Jul 14 06:56:13 PM PDT 24
Finished Jul 14 06:56:16 PM PDT 24
Peak memory 205388 kb
Host smart-fee0c1b3-817d-4c5d-be4c-3f0a7ad279e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215824973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3215824973
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3210312670
Short name T167
Test name
Test status
Simulation time 3744124678 ps
CPU time 50 seconds
Started Jul 14 06:55:10 PM PDT 24
Finished Jul 14 06:56:08 PM PDT 24
Peak memory 249240 kb
Host smart-84182c18-4656-4698-9d20-3c82fe6b9c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210312670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3210312670
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3460461125
Short name T712
Test name
Test status
Simulation time 10571477679 ps
CPU time 95.01 seconds
Started Jul 14 06:55:29 PM PDT 24
Finished Jul 14 06:57:07 PM PDT 24
Peak memory 249292 kb
Host smart-5d078a2e-0a1b-4f42-ba55-e22054609297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460461125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3460461125
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1008952078
Short name T944
Test name
Test status
Simulation time 95169481676 ps
CPU time 279.55 seconds
Started Jul 14 06:55:26 PM PDT 24
Finished Jul 14 07:00:08 PM PDT 24
Peak memory 264896 kb
Host smart-41904965-33ab-4e88-879a-d75bb9abec39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008952078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1008952078
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3569657105
Short name T391
Test name
Test status
Simulation time 202675096 ps
CPU time 4.43 seconds
Started Jul 14 06:55:14 PM PDT 24
Finished Jul 14 06:55:23 PM PDT 24
Peak memory 224432 kb
Host smart-841c9ca5-f54c-480c-8cd7-de48772d8492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569657105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3569657105
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.3477895342
Short name T432
Test name
Test status
Simulation time 19569085606 ps
CPU time 133.54 seconds
Started Jul 14 06:55:25 PM PDT 24
Finished Jul 14 06:57:41 PM PDT 24
Peak memory 249436 kb
Host smart-e3223307-35cb-4195-80e7-b3ac246146fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477895342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.3477895342
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2991362148
Short name T18
Test name
Test status
Simulation time 469439931 ps
CPU time 3.83 seconds
Started Jul 14 06:55:10 PM PDT 24
Finished Jul 14 06:55:18 PM PDT 24
Peak memory 232696 kb
Host smart-9880a7ac-8fb9-4f97-9ff6-fc52c65b219c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991362148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2991362148
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2228169002
Short name T841
Test name
Test status
Simulation time 1344972249 ps
CPU time 5.13 seconds
Started Jul 14 06:55:23 PM PDT 24
Finished Jul 14 06:55:30 PM PDT 24
Peak memory 224508 kb
Host smart-b3b0ca01-6e7b-428a-839c-1875d94f9c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228169002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2228169002
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2592668059
Short name T931
Test name
Test status
Simulation time 10757869650 ps
CPU time 24.4 seconds
Started Jul 14 06:55:25 PM PDT 24
Finished Jul 14 06:55:52 PM PDT 24
Peak memory 252228 kb
Host smart-268cb460-3047-413d-84b8-9fde35fdb27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592668059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2592668059
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2342269795
Short name T239
Test name
Test status
Simulation time 875209274 ps
CPU time 8.8 seconds
Started Jul 14 06:55:34 PM PDT 24
Finished Jul 14 06:55:44 PM PDT 24
Peak memory 240524 kb
Host smart-0e653ee4-a112-4991-8bb1-7db54f56d8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342269795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2342269795
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.962789201
Short name T540
Test name
Test status
Simulation time 97561520 ps
CPU time 3.38 seconds
Started Jul 14 06:56:09 PM PDT 24
Finished Jul 14 06:56:13 PM PDT 24
Peak memory 223360 kb
Host smart-046e1f3d-8d06-4610-9c97-7b59c519cc4a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=962789201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.962789201
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2899185187
Short name T394
Test name
Test status
Simulation time 11209852070 ps
CPU time 17.52 seconds
Started Jul 14 06:55:28 PM PDT 24
Finished Jul 14 06:55:49 PM PDT 24
Peak memory 216304 kb
Host smart-85b924e9-48b0-4f13-a4a4-9a55ce49da05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899185187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2899185187
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2986664193
Short name T95
Test name
Test status
Simulation time 5206503891 ps
CPU time 5 seconds
Started Jul 14 06:55:25 PM PDT 24
Finished Jul 14 06:55:33 PM PDT 24
Peak memory 216332 kb
Host smart-09c416dc-de68-49ff-a856-2f6aa855c3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986664193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2986664193
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3203751890
Short name T688
Test name
Test status
Simulation time 173061679 ps
CPU time 1.2 seconds
Started Jul 14 06:55:26 PM PDT 24
Finished Jul 14 06:55:30 PM PDT 24
Peak memory 216104 kb
Host smart-e0905bcb-32e5-4bd4-8870-492222c7a170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203751890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3203751890
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2444552115
Short name T990
Test name
Test status
Simulation time 43354986 ps
CPU time 0.72 seconds
Started Jul 14 06:55:07 PM PDT 24
Finished Jul 14 06:55:13 PM PDT 24
Peak memory 206008 kb
Host smart-5c7dccae-8eda-4a26-9372-83a03fa03c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444552115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2444552115
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1556423486
Short name T529
Test name
Test status
Simulation time 4920898573 ps
CPU time 14.72 seconds
Started Jul 14 06:55:06 PM PDT 24
Finished Jul 14 06:55:26 PM PDT 24
Peak memory 224648 kb
Host smart-c9f94398-09fa-47bc-9abc-d956e60b6fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556423486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1556423486
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2981506690
Short name T937
Test name
Test status
Simulation time 12511980 ps
CPU time 0.73 seconds
Started Jul 14 06:55:10 PM PDT 24
Finished Jul 14 06:55:17 PM PDT 24
Peak memory 205504 kb
Host smart-8fd5416a-46ec-49cb-b9ee-240c36441ea8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981506690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2981506690
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1798664545
Short name T97
Test name
Test status
Simulation time 29388550130 ps
CPU time 40.19 seconds
Started Jul 14 06:55:27 PM PDT 24
Finished Jul 14 06:56:10 PM PDT 24
Peak memory 224636 kb
Host smart-a6448ac7-754d-4845-ba71-7e1e7fcbe066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798664545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1798664545
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3509767252
Short name T694
Test name
Test status
Simulation time 15837032 ps
CPU time 0.81 seconds
Started Jul 14 06:55:08 PM PDT 24
Finished Jul 14 06:55:15 PM PDT 24
Peak memory 206608 kb
Host smart-ac73cdba-cb12-43d0-8552-ce217b3aa482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509767252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3509767252
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2549378049
Short name T215
Test name
Test status
Simulation time 7720303178 ps
CPU time 51.53 seconds
Started Jul 14 06:55:27 PM PDT 24
Finished Jul 14 06:56:21 PM PDT 24
Peak memory 236120 kb
Host smart-95bc104f-0ccb-4b9a-a7ff-321a22fc26de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549378049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2549378049
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3953451299
Short name T829
Test name
Test status
Simulation time 16652596548 ps
CPU time 170.93 seconds
Started Jul 14 06:55:21 PM PDT 24
Finished Jul 14 06:58:14 PM PDT 24
Peak memory 255148 kb
Host smart-d61a3b03-5b0d-46c1-a46d-ac7c4d35a789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953451299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3953451299
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2701519704
Short name T786
Test name
Test status
Simulation time 174931814 ps
CPU time 7.07 seconds
Started Jul 14 06:55:11 PM PDT 24
Finished Jul 14 06:55:23 PM PDT 24
Peak memory 232592 kb
Host smart-a6e5ad72-69ea-41b2-93cf-c5f0bd5ec8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701519704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2701519704
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.844132960
Short name T766
Test name
Test status
Simulation time 18821900463 ps
CPU time 126.9 seconds
Started Jul 14 06:55:27 PM PDT 24
Finished Jul 14 06:57:38 PM PDT 24
Peak memory 241024 kb
Host smart-19e0cdf1-e036-4473-8e71-5320e7206cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844132960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds
.844132960
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3197238690
Short name T822
Test name
Test status
Simulation time 127475537 ps
CPU time 2.17 seconds
Started Jul 14 06:55:10 PM PDT 24
Finished Jul 14 06:55:17 PM PDT 24
Peak memory 232236 kb
Host smart-43b36a6d-db3d-44c5-ae3d-2791a6bb4f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197238690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3197238690
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.601862803
Short name T986
Test name
Test status
Simulation time 5044711392 ps
CPU time 31.12 seconds
Started Jul 14 06:55:07 PM PDT 24
Finished Jul 14 06:55:44 PM PDT 24
Peak memory 224672 kb
Host smart-ba4debac-da95-4e1d-942f-7720ceb6203c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601862803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.601862803
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.457511744
Short name T975
Test name
Test status
Simulation time 17813020050 ps
CPU time 5.83 seconds
Started Jul 14 06:55:21 PM PDT 24
Finished Jul 14 06:55:29 PM PDT 24
Peak memory 232772 kb
Host smart-2425664c-ba3e-4ad9-8bc1-0e2a30663149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457511744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.457511744
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3661298083
Short name T591
Test name
Test status
Simulation time 1852980529 ps
CPU time 15.53 seconds
Started Jul 14 06:55:25 PM PDT 24
Finished Jul 14 06:55:43 PM PDT 24
Peak memory 240100 kb
Host smart-1770da01-ce61-42d7-9d69-3594b2efa3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661298083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3661298083
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3381022919
Short name T574
Test name
Test status
Simulation time 743420683 ps
CPU time 4.14 seconds
Started Jul 14 06:55:08 PM PDT 24
Finished Jul 14 06:55:18 PM PDT 24
Peak memory 219384 kb
Host smart-b5534077-b5a5-4d46-a32a-00850b72047d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3381022919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3381022919
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.570601303
Short name T517
Test name
Test status
Simulation time 892071182 ps
CPU time 11.65 seconds
Started Jul 14 06:55:25 PM PDT 24
Finished Jul 14 06:55:39 PM PDT 24
Peak memory 217884 kb
Host smart-6038eafd-ecd6-42ee-b0a3-930257d712eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570601303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.570601303
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1586970825
Short name T635
Test name
Test status
Simulation time 12072566158 ps
CPU time 14.59 seconds
Started Jul 14 06:55:07 PM PDT 24
Finished Jul 14 06:55:27 PM PDT 24
Peak memory 216356 kb
Host smart-2b50df0e-21e8-40e0-93bf-bf6aead33f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586970825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1586970825
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.828597554
Short name T317
Test name
Test status
Simulation time 555618289 ps
CPU time 9 seconds
Started Jul 14 06:55:10 PM PDT 24
Finished Jul 14 06:55:24 PM PDT 24
Peak memory 216268 kb
Host smart-3e0512c1-c26f-42f7-be50-66321be7bff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828597554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.828597554
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1434150320
Short name T569
Test name
Test status
Simulation time 42704444 ps
CPU time 0.86 seconds
Started Jul 14 06:55:25 PM PDT 24
Finished Jul 14 06:55:28 PM PDT 24
Peak memory 205972 kb
Host smart-2120892a-4a90-4b98-bd28-4e7812427bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434150320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1434150320
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.4101766969
Short name T475
Test name
Test status
Simulation time 1308215546 ps
CPU time 8.35 seconds
Started Jul 14 06:55:24 PM PDT 24
Finished Jul 14 06:55:34 PM PDT 24
Peak memory 224464 kb
Host smart-20900ec3-f002-4dbd-93c9-e0846747c5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101766969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.4101766969
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3979421437
Short name T971
Test name
Test status
Simulation time 78885733 ps
CPU time 0.71 seconds
Started Jul 14 06:55:28 PM PDT 24
Finished Jul 14 06:55:32 PM PDT 24
Peak memory 205864 kb
Host smart-b4d721c0-4b23-447f-bba0-23eae2cd1792
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979421437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3979421437
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2827285621
Short name T744
Test name
Test status
Simulation time 997689728 ps
CPU time 12.47 seconds
Started Jul 14 06:55:26 PM PDT 24
Finished Jul 14 06:55:42 PM PDT 24
Peak memory 224508 kb
Host smart-5cc83f6a-9533-4fe6-a1ef-6293671bc0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827285621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2827285621
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1135264830
Short name T570
Test name
Test status
Simulation time 16942189 ps
CPU time 0.77 seconds
Started Jul 14 06:55:27 PM PDT 24
Finished Jul 14 06:55:31 PM PDT 24
Peak memory 205564 kb
Host smart-4a6b23dc-390d-4f82-9ec7-4f400929326f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135264830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1135264830
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3629546435
Short name T192
Test name
Test status
Simulation time 11023732081 ps
CPU time 73.41 seconds
Started Jul 14 06:55:15 PM PDT 24
Finished Jul 14 06:56:32 PM PDT 24
Peak memory 264316 kb
Host smart-52d50ebe-5f11-4952-9623-2e6855b17215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629546435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3629546435
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1112140565
Short name T560
Test name
Test status
Simulation time 1814194043 ps
CPU time 29.63 seconds
Started Jul 14 06:55:29 PM PDT 24
Finished Jul 14 06:56:02 PM PDT 24
Peak memory 224528 kb
Host smart-79012702-47b7-4940-80ef-5463b9518253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112140565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1112140565
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.4015723144
Short name T168
Test name
Test status
Simulation time 179498210542 ps
CPU time 239.62 seconds
Started Jul 14 06:55:15 PM PDT 24
Finished Jul 14 06:59:18 PM PDT 24
Peak memory 253640 kb
Host smart-87fd4b75-16af-4fc2-811f-30acfce941ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015723144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.4015723144
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2021437735
Short name T76
Test name
Test status
Simulation time 1202578140 ps
CPU time 15.12 seconds
Started Jul 14 06:55:11 PM PDT 24
Finished Jul 14 06:55:31 PM PDT 24
Peak memory 240864 kb
Host smart-7d2596ba-a6f4-4eda-91cf-a41961bbe9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021437735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2021437735
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.1499847640
Short name T982
Test name
Test status
Simulation time 9718707562 ps
CPU time 106.08 seconds
Started Jul 14 06:55:11 PM PDT 24
Finished Jul 14 06:57:02 PM PDT 24
Peak memory 257396 kb
Host smart-bb815b96-3a3a-4c49-907d-ee43dd671a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499847640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.1499847640
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.393917627
Short name T620
Test name
Test status
Simulation time 189204585 ps
CPU time 3.31 seconds
Started Jul 14 06:55:24 PM PDT 24
Finished Jul 14 06:55:30 PM PDT 24
Peak memory 224528 kb
Host smart-85dc383e-fe2d-4818-8e42-cca03bf115d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393917627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.393917627
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2208328955
Short name T243
Test name
Test status
Simulation time 31019489227 ps
CPU time 59.33 seconds
Started Jul 14 06:55:19 PM PDT 24
Finished Jul 14 06:56:20 PM PDT 24
Peak memory 248744 kb
Host smart-876c2767-9cba-4d32-b459-31736a3d58b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208328955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2208328955
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.740879824
Short name T884
Test name
Test status
Simulation time 8423841165 ps
CPU time 26.13 seconds
Started Jul 14 06:55:14 PM PDT 24
Finished Jul 14 06:55:44 PM PDT 24
Peak memory 240704 kb
Host smart-2cf62cda-fc90-48bd-b51e-610e475869f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740879824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.740879824
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1524342236
Short name T244
Test name
Test status
Simulation time 12829721819 ps
CPU time 5.17 seconds
Started Jul 14 06:55:27 PM PDT 24
Finished Jul 14 06:55:36 PM PDT 24
Peak memory 232788 kb
Host smart-2f9b616a-b1d2-49ca-9a04-aa4ceb80e68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524342236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1524342236
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3800691951
Short name T386
Test name
Test status
Simulation time 255441223 ps
CPU time 5.3 seconds
Started Jul 14 06:55:38 PM PDT 24
Finished Jul 14 06:55:45 PM PDT 24
Peak memory 222748 kb
Host smart-a055c036-32f3-400c-999c-85aa53b26523
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3800691951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3800691951
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.269104527
Short name T245
Test name
Test status
Simulation time 35289373665 ps
CPU time 105.31 seconds
Started Jul 14 06:55:15 PM PDT 24
Finished Jul 14 06:57:04 PM PDT 24
Peak memory 266096 kb
Host smart-7089dd66-71be-4358-b3f4-949eccbb8077
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269104527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.269104527
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3214645587
Short name T887
Test name
Test status
Simulation time 3566021252 ps
CPU time 3.35 seconds
Started Jul 14 06:55:25 PM PDT 24
Finished Jul 14 06:55:30 PM PDT 24
Peak memory 219104 kb
Host smart-591e04ad-a75c-494a-81cf-e0c1ee788b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214645587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3214645587
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.221604832
Short name T757
Test name
Test status
Simulation time 30211873 ps
CPU time 0.71 seconds
Started Jul 14 06:56:19 PM PDT 24
Finished Jul 14 06:56:26 PM PDT 24
Peak memory 205532 kb
Host smart-5eda0934-54ad-464c-a1c8-befeef95d4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221604832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.221604832
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2890744217
Short name T769
Test name
Test status
Simulation time 263356776 ps
CPU time 1.42 seconds
Started Jul 14 06:55:11 PM PDT 24
Finished Jul 14 06:55:17 PM PDT 24
Peak memory 208016 kb
Host smart-918b2627-e7c3-46e3-8296-2cc9c91ebddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890744217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2890744217
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.305680384
Short name T554
Test name
Test status
Simulation time 48847192 ps
CPU time 0.87 seconds
Started Jul 14 06:56:15 PM PDT 24
Finished Jul 14 06:56:18 PM PDT 24
Peak memory 205784 kb
Host smart-b6fb99db-993d-4c14-9361-c1372bbf40c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305680384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.305680384
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.861034655
Short name T541
Test name
Test status
Simulation time 2751969489 ps
CPU time 8.68 seconds
Started Jul 14 06:55:21 PM PDT 24
Finished Jul 14 06:55:32 PM PDT 24
Peak memory 232780 kb
Host smart-9f8b4f55-2ac9-4140-bf6e-a7f36fde40f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861034655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.861034655
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1105688767
Short name T482
Test name
Test status
Simulation time 16767674 ps
CPU time 0.73 seconds
Started Jul 14 06:55:26 PM PDT 24
Finished Jul 14 06:55:29 PM PDT 24
Peak memory 205492 kb
Host smart-a2d0cf90-cab1-4fe5-8206-85ce09324915
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105688767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1105688767
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1555413512
Short name T531
Test name
Test status
Simulation time 436491576 ps
CPU time 4.9 seconds
Started Jul 14 06:55:25 PM PDT 24
Finished Jul 14 06:55:32 PM PDT 24
Peak memory 224456 kb
Host smart-ce1a4a6f-9931-4e4a-9b69-1bc0b28144ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555413512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1555413512
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3334310092
Short name T474
Test name
Test status
Simulation time 55489253 ps
CPU time 0.74 seconds
Started Jul 14 06:55:23 PM PDT 24
Finished Jul 14 06:55:26 PM PDT 24
Peak memory 206584 kb
Host smart-d3117a59-fa9b-4ff7-aea6-f7460f43349f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334310092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3334310092
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3651756670
Short name T660
Test name
Test status
Simulation time 781989125 ps
CPU time 3.69 seconds
Started Jul 14 06:55:28 PM PDT 24
Finished Jul 14 06:55:36 PM PDT 24
Peak memory 224484 kb
Host smart-2ddc828a-82bd-4d1f-b2d6-c916278f4487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651756670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3651756670
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2777572831
Short name T29
Test name
Test status
Simulation time 33429220140 ps
CPU time 74.3 seconds
Started Jul 14 06:55:25 PM PDT 24
Finished Jul 14 06:56:42 PM PDT 24
Peak memory 224656 kb
Host smart-6980c79e-0a89-458e-96ca-4d27b975fea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777572831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2777572831
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.4089890462
Short name T616
Test name
Test status
Simulation time 5526245212 ps
CPU time 14.11 seconds
Started Jul 14 06:55:44 PM PDT 24
Finished Jul 14 06:55:59 PM PDT 24
Peak memory 224592 kb
Host smart-a0448ca5-291d-4a2a-9555-5d0efcfe152e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089890462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.4089890462
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.1457312876
Short name T881
Test name
Test status
Simulation time 112996881568 ps
CPU time 221.32 seconds
Started Jul 14 06:55:29 PM PDT 24
Finished Jul 14 06:59:14 PM PDT 24
Peak memory 249196 kb
Host smart-5916eac4-a74e-4c82-9cbb-48caf593776d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457312876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.1457312876
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1217653265
Short name T573
Test name
Test status
Simulation time 1617140421 ps
CPU time 14.12 seconds
Started Jul 14 06:55:43 PM PDT 24
Finished Jul 14 06:55:58 PM PDT 24
Peak memory 232640 kb
Host smart-38aaba82-afd7-4c3d-895d-74ef431c4dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217653265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1217653265
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.290152452
Short name T341
Test name
Test status
Simulation time 1127480813 ps
CPU time 7.95 seconds
Started Jul 14 06:55:22 PM PDT 24
Finished Jul 14 06:55:32 PM PDT 24
Peak memory 232700 kb
Host smart-c26dcc31-f77c-42d1-a082-4a2fc197fbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290152452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.290152452
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2047623683
Short name T212
Test name
Test status
Simulation time 18628444832 ps
CPU time 15.16 seconds
Started Jul 14 06:55:27 PM PDT 24
Finished Jul 14 06:55:46 PM PDT 24
Peak memory 224656 kb
Host smart-2432bc99-4d0d-4131-b36e-1396b1c92c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047623683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2047623683
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.922777237
Short name T648
Test name
Test status
Simulation time 22576822973 ps
CPU time 30.53 seconds
Started Jul 14 06:55:27 PM PDT 24
Finished Jul 14 06:56:00 PM PDT 24
Peak memory 232792 kb
Host smart-a5ca6377-cb20-495a-a8a4-6f9a94167c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922777237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.922777237
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3580041381
Short name T31
Test name
Test status
Simulation time 21281419980 ps
CPU time 87.31 seconds
Started Jul 14 06:55:25 PM PDT 24
Finished Jul 14 06:56:55 PM PDT 24
Peak memory 257640 kb
Host smart-e8d314ac-b3e7-4e01-b376-35a7ecf7a962
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580041381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3580041381
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1079711039
Short name T858
Test name
Test status
Simulation time 30882582711 ps
CPU time 36.23 seconds
Started Jul 14 06:55:26 PM PDT 24
Finished Jul 14 06:56:05 PM PDT 24
Peak memory 216324 kb
Host smart-a35161e2-75fb-46f9-ad8a-ffad9a0f6214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079711039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1079711039
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.983628403
Short name T703
Test name
Test status
Simulation time 1696548042 ps
CPU time 3.99 seconds
Started Jul 14 06:55:23 PM PDT 24
Finished Jul 14 06:55:29 PM PDT 24
Peak memory 216176 kb
Host smart-3dda90c3-0828-4e72-a7a1-bf1f735d5d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983628403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.983628403
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.368278066
Short name T536
Test name
Test status
Simulation time 21942354 ps
CPU time 0.88 seconds
Started Jul 14 06:55:37 PM PDT 24
Finished Jul 14 06:55:40 PM PDT 24
Peak memory 207024 kb
Host smart-15632b1a-5f41-4ae1-b62c-89b4d6c348ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368278066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.368278066
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_upload.2401243650
Short name T852
Test name
Test status
Simulation time 7242528361 ps
CPU time 23.31 seconds
Started Jul 14 06:55:25 PM PDT 24
Finished Jul 14 06:55:51 PM PDT 24
Peak memory 239724 kb
Host smart-54bda305-04ee-425c-a6c2-d635058f3065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401243650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2401243650
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1868282554
Short name T392
Test name
Test status
Simulation time 13488721 ps
CPU time 0.78 seconds
Started Jul 14 06:55:25 PM PDT 24
Finished Jul 14 06:55:28 PM PDT 24
Peak memory 205840 kb
Host smart-44316caf-59db-4f89-9d74-c709a5f20fef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868282554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1868282554
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3253543456
Short name T77
Test name
Test status
Simulation time 194730345 ps
CPU time 5.47 seconds
Started Jul 14 06:55:30 PM PDT 24
Finished Jul 14 06:55:39 PM PDT 24
Peak memory 232712 kb
Host smart-1d261a03-0b78-4906-be17-c7b95c741f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253543456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3253543456
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1922069947
Short name T789
Test name
Test status
Simulation time 18170639 ps
CPU time 0.73 seconds
Started Jul 14 06:55:26 PM PDT 24
Finished Jul 14 06:55:29 PM PDT 24
Peak memory 206596 kb
Host smart-b1571705-b22e-4b47-a271-07716ed166e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922069947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1922069947
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.971810089
Short name T847
Test name
Test status
Simulation time 15073291179 ps
CPU time 55.38 seconds
Started Jul 14 06:55:24 PM PDT 24
Finished Jul 14 06:56:21 PM PDT 24
Peak memory 235352 kb
Host smart-ef9e35c2-c971-4f17-a02f-ffddaaa2e7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971810089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.971810089
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2288842331
Short name T197
Test name
Test status
Simulation time 17867480717 ps
CPU time 98.04 seconds
Started Jul 14 06:55:33 PM PDT 24
Finished Jul 14 06:57:13 PM PDT 24
Peak memory 257124 kb
Host smart-ad633fdd-25ad-4c82-a527-b810dbb6247c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288842331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2288842331
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2391105302
Short name T288
Test name
Test status
Simulation time 2256201540 ps
CPU time 13.59 seconds
Started Jul 14 06:55:21 PM PDT 24
Finished Jul 14 06:55:37 PM PDT 24
Peak memory 240944 kb
Host smart-f8cb6f70-0655-452e-bde5-334d098e0382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391105302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2391105302
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.1970955784
Short name T374
Test name
Test status
Simulation time 4577313261 ps
CPU time 64.6 seconds
Started Jul 14 06:55:27 PM PDT 24
Finished Jul 14 06:56:36 PM PDT 24
Peak memory 253384 kb
Host smart-0699e37d-370f-4ef0-9ff3-a83a2eda83ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970955784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.1970955784
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3726728444
Short name T557
Test name
Test status
Simulation time 2929255124 ps
CPU time 7.5 seconds
Started Jul 14 06:55:30 PM PDT 24
Finished Jul 14 06:55:41 PM PDT 24
Peak memory 240576 kb
Host smart-392dd69d-a689-48c4-99cc-cbb3ef29830b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726728444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3726728444
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.23956495
Short name T929
Test name
Test status
Simulation time 6106378783 ps
CPU time 6.17 seconds
Started Jul 14 06:55:33 PM PDT 24
Finished Jul 14 06:55:41 PM PDT 24
Peak memory 232716 kb
Host smart-7405f738-f6e0-469c-9e5c-a51f2a34da10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23956495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap.23956495
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.213444221
Short name T214
Test name
Test status
Simulation time 605187566 ps
CPU time 9.88 seconds
Started Jul 14 06:55:40 PM PDT 24
Finished Jul 14 06:55:52 PM PDT 24
Peak memory 240004 kb
Host smart-ddcb7846-41d1-49d6-aa66-09298bae0c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213444221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.213444221
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3761630091
Short name T424
Test name
Test status
Simulation time 357576938 ps
CPU time 4.14 seconds
Started Jul 14 06:55:30 PM PDT 24
Finished Jul 14 06:55:37 PM PDT 24
Peak memory 223612 kb
Host smart-689fd09d-1301-42b0-8ec1-8b77db871390
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3761630091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3761630091
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1045773146
Short name T628
Test name
Test status
Simulation time 18343580484 ps
CPU time 158.99 seconds
Started Jul 14 06:55:26 PM PDT 24
Finished Jul 14 06:58:07 PM PDT 24
Peak memory 249556 kb
Host smart-cd62c921-f746-4724-aee4-978b547a64fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045773146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1045773146
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2634759210
Short name T915
Test name
Test status
Simulation time 17528766668 ps
CPU time 33.42 seconds
Started Jul 14 06:55:48 PM PDT 24
Finished Jul 14 06:56:22 PM PDT 24
Peak memory 216548 kb
Host smart-06117736-a3d8-434e-b23f-187a6022c262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634759210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2634759210
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2584283444
Short name T316
Test name
Test status
Simulation time 443695705 ps
CPU time 2.54 seconds
Started Jul 14 06:55:35 PM PDT 24
Finished Jul 14 06:55:39 PM PDT 24
Peak memory 216168 kb
Host smart-745470fc-bb27-4b13-936b-d496d7d2e200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584283444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2584283444
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.191272636
Short name T379
Test name
Test status
Simulation time 508167866 ps
CPU time 2.58 seconds
Started Jul 14 06:55:30 PM PDT 24
Finished Jul 14 06:55:36 PM PDT 24
Peak memory 216188 kb
Host smart-d5597f79-7b77-4e10-8327-a3b154f6fe0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191272636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.191272636
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.4074588212
Short name T771
Test name
Test status
Simulation time 93188683 ps
CPU time 0.92 seconds
Started Jul 14 06:55:29 PM PDT 24
Finished Jul 14 06:55:34 PM PDT 24
Peak memory 206984 kb
Host smart-65410148-b6a9-4ad3-8947-5e04b5e47a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074588212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.4074588212
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2996099018
Short name T486
Test name
Test status
Simulation time 528401212 ps
CPU time 5.39 seconds
Started Jul 14 06:55:29 PM PDT 24
Finished Jul 14 06:55:38 PM PDT 24
Peak memory 232544 kb
Host smart-e449716f-b6d9-47a5-b34a-79a4145127ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996099018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2996099018
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3863654638
Short name T306
Test name
Test status
Simulation time 18961450 ps
CPU time 0.77 seconds
Started Jul 14 06:54:56 PM PDT 24
Finished Jul 14 06:54:58 PM PDT 24
Peak memory 204960 kb
Host smart-c38a270f-b6c4-4f25-bd0f-bc7ac717eb0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863654638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
863654638
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.4208996488
Short name T151
Test name
Test status
Simulation time 3264413078 ps
CPU time 4.29 seconds
Started Jul 14 06:55:53 PM PDT 24
Finished Jul 14 06:55:59 PM PDT 24
Peak memory 232556 kb
Host smart-e188cc6f-e36c-48b3-b93e-513c81cbcfb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208996488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.4208996488
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1650839655
Short name T1004
Test name
Test status
Simulation time 17645040 ps
CPU time 0.78 seconds
Started Jul 14 06:54:43 PM PDT 24
Finished Jul 14 06:54:47 PM PDT 24
Peak memory 206564 kb
Host smart-9d531481-f0d6-4f7e-9b9f-3837c2cc1e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650839655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1650839655
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.347075156
Short name T305
Test name
Test status
Simulation time 14707901 ps
CPU time 0.81 seconds
Started Jul 14 06:54:44 PM PDT 24
Finished Jul 14 06:54:48 PM PDT 24
Peak memory 215760 kb
Host smart-2a3f4e34-ee8a-4a0b-9602-4afa3971be94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347075156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.347075156
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3785746211
Short name T256
Test name
Test status
Simulation time 3942313610 ps
CPU time 29.56 seconds
Started Jul 14 06:54:37 PM PDT 24
Finished Jul 14 06:55:10 PM PDT 24
Peak memory 249252 kb
Host smart-7af2949d-49a8-44cf-9210-20ed48bd3c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785746211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3785746211
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3574239322
Short name T784
Test name
Test status
Simulation time 205830386 ps
CPU time 4.88 seconds
Started Jul 14 06:54:33 PM PDT 24
Finished Jul 14 06:54:41 PM PDT 24
Peak memory 232756 kb
Host smart-df86016d-6610-4d4f-a530-ea54f1bd938a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574239322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3574239322
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1031910839
Short name T191
Test name
Test status
Simulation time 70341356178 ps
CPU time 399.77 seconds
Started Jul 14 06:54:49 PM PDT 24
Finished Jul 14 07:01:32 PM PDT 24
Peak memory 256072 kb
Host smart-dd4b6fe2-32c1-4e77-bc07-06a3c50d340f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031910839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1031910839
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1017327442
Short name T41
Test name
Test status
Simulation time 116747395 ps
CPU time 2.22 seconds
Started Jul 14 06:54:36 PM PDT 24
Finished Jul 14 06:54:42 PM PDT 24
Peak memory 232316 kb
Host smart-e37d9d0f-4202-414a-a3db-14a41f49cf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017327442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1017327442
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1976866993
Short name T318
Test name
Test status
Simulation time 1464940590 ps
CPU time 11.31 seconds
Started Jul 14 06:54:44 PM PDT 24
Finished Jul 14 06:54:58 PM PDT 24
Peak memory 251224 kb
Host smart-ca6456ec-c86a-4080-a9c7-85ef9580736f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976866993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1976866993
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2417422754
Short name T381
Test name
Test status
Simulation time 62962336 ps
CPU time 2.61 seconds
Started Jul 14 06:54:49 PM PDT 24
Finished Jul 14 06:54:54 PM PDT 24
Peak memory 232700 kb
Host smart-52c284ce-64a8-4816-b6e4-b6c20b0864e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417422754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2417422754
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3562008633
Short name T731
Test name
Test status
Simulation time 103683155 ps
CPU time 2.48 seconds
Started Jul 14 06:54:41 PM PDT 24
Finished Jul 14 06:54:45 PM PDT 24
Peak memory 232364 kb
Host smart-9f7f0e81-d9f1-4206-bfbf-7402f48eb0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562008633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3562008633
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2279983320
Short name T383
Test name
Test status
Simulation time 102568662 ps
CPU time 4.01 seconds
Started Jul 14 06:54:37 PM PDT 24
Finished Jul 14 06:54:44 PM PDT 24
Peak memory 220360 kb
Host smart-fa3002f4-3faf-4f25-8c63-5eb7d2962368
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2279983320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2279983320
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1646299207
Short name T675
Test name
Test status
Simulation time 9755102825 ps
CPU time 93.9 seconds
Started Jul 14 06:54:43 PM PDT 24
Finished Jul 14 06:56:19 PM PDT 24
Peak memory 236880 kb
Host smart-ac06b210-b3c3-4e62-b6e5-1911a97ef54a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646299207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1646299207
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.4120571602
Short name T683
Test name
Test status
Simulation time 5947230521 ps
CPU time 24.14 seconds
Started Jul 14 06:54:43 PM PDT 24
Finished Jul 14 06:55:11 PM PDT 24
Peak memory 216344 kb
Host smart-f4ca9a96-f509-4565-a072-b7a582441633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120571602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.4120571602
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3461536170
Short name T898
Test name
Test status
Simulation time 594567232 ps
CPU time 3.78 seconds
Started Jul 14 06:54:30 PM PDT 24
Finished Jul 14 06:54:37 PM PDT 24
Peak memory 216180 kb
Host smart-91657129-2953-48ce-9c56-94fe7f05f53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461536170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3461536170
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.763261406
Short name T518
Test name
Test status
Simulation time 434021123 ps
CPU time 0.96 seconds
Started Jul 14 06:55:07 PM PDT 24
Finished Jul 14 06:55:13 PM PDT 24
Peak memory 206720 kb
Host smart-bf3803ab-ef2a-413b-89ae-bb8e75e4c651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763261406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.763261406
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3711958471
Short name T722
Test name
Test status
Simulation time 19014487 ps
CPU time 0.74 seconds
Started Jul 14 06:54:43 PM PDT 24
Finished Jul 14 06:54:47 PM PDT 24
Peak memory 205968 kb
Host smart-da45629f-a889-44fc-b136-5be64bbb323e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711958471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3711958471
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.736144291
Short name T53
Test name
Test status
Simulation time 15044231073 ps
CPU time 24.54 seconds
Started Jul 14 06:54:36 PM PDT 24
Finished Jul 14 06:55:04 PM PDT 24
Peak memory 232800 kb
Host smart-83b7e833-3bb2-4368-a9a7-e1d02ccabdab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736144291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.736144291
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.51649414
Short name T753
Test name
Test status
Simulation time 14055402 ps
CPU time 0.68 seconds
Started Jul 14 06:55:35 PM PDT 24
Finished Jul 14 06:55:37 PM PDT 24
Peak memory 205628 kb
Host smart-1f7d6105-aee3-463e-8e64-8bf9ec6e0e42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51649414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.51649414
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1667794079
Short name T407
Test name
Test status
Simulation time 64339352 ps
CPU time 2.53 seconds
Started Jul 14 06:55:26 PM PDT 24
Finished Jul 14 06:55:31 PM PDT 24
Peak memory 232316 kb
Host smart-0ee0774e-3b59-4986-825e-132040e0c80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667794079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1667794079
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2582447030
Short name T350
Test name
Test status
Simulation time 22667492 ps
CPU time 0.8 seconds
Started Jul 14 06:55:23 PM PDT 24
Finished Jul 14 06:55:26 PM PDT 24
Peak memory 206600 kb
Host smart-8e70e261-94f7-4cb2-a791-276cf96712a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582447030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2582447030
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1126433142
Short name T864
Test name
Test status
Simulation time 5915148300 ps
CPU time 25.01 seconds
Started Jul 14 06:55:27 PM PDT 24
Finished Jul 14 06:55:56 PM PDT 24
Peak memory 250328 kb
Host smart-2589174d-73af-4b26-af35-0332418396d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126433142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1126433142
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2134355519
Short name T187
Test name
Test status
Simulation time 25945724249 ps
CPU time 91.99 seconds
Started Jul 14 06:55:34 PM PDT 24
Finished Jul 14 06:57:07 PM PDT 24
Peak memory 263180 kb
Host smart-28164790-6d03-47cd-bd46-b40643c374a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134355519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2134355519
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.56394495
Short name T210
Test name
Test status
Simulation time 57267114775 ps
CPU time 179.97 seconds
Started Jul 14 06:55:31 PM PDT 24
Finished Jul 14 06:58:34 PM PDT 24
Peak memory 267588 kb
Host smart-c683f288-cedf-4349-ad9c-fe6705382445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56394495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle.56394495
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1454964344
Short name T558
Test name
Test status
Simulation time 727615350 ps
CPU time 6.12 seconds
Started Jul 14 06:55:39 PM PDT 24
Finished Jul 14 06:55:47 PM PDT 24
Peak memory 237228 kb
Host smart-4dd71906-9f45-44e7-b714-5020e3930263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454964344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1454964344
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.620016422
Short name T205
Test name
Test status
Simulation time 13584874752 ps
CPU time 91.36 seconds
Started Jul 14 06:55:29 PM PDT 24
Finished Jul 14 06:57:04 PM PDT 24
Peak memory 241036 kb
Host smart-348e9663-b6fe-474f-aa8b-f1e39798f11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620016422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds
.620016422
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1985038927
Short name T443
Test name
Test status
Simulation time 218598865 ps
CPU time 2.88 seconds
Started Jul 14 06:55:37 PM PDT 24
Finished Jul 14 06:55:42 PM PDT 24
Peak memory 232656 kb
Host smart-daacf122-2c1c-483f-ab20-5069e3e181d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985038927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1985038927
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2631806009
Short name T516
Test name
Test status
Simulation time 6973148579 ps
CPU time 41.73 seconds
Started Jul 14 06:55:30 PM PDT 24
Finished Jul 14 06:56:15 PM PDT 24
Peak memory 232680 kb
Host smart-91535368-13e3-455e-947f-e6e4434d2ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631806009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2631806009
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1217919547
Short name T278
Test name
Test status
Simulation time 1016641696 ps
CPU time 9.26 seconds
Started Jul 14 06:55:33 PM PDT 24
Finished Jul 14 06:55:44 PM PDT 24
Peak memory 241296 kb
Host smart-4866855f-d6be-489e-86fc-59a04cc52152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217919547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1217919547
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.746570015
Short name T730
Test name
Test status
Simulation time 500966589 ps
CPU time 8.41 seconds
Started Jul 14 06:55:42 PM PDT 24
Finished Jul 14 06:55:52 PM PDT 24
Peak memory 232656 kb
Host smart-2592dda4-78e7-48e2-9c17-e03bf189dafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746570015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.746570015
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1857217680
Short name T498
Test name
Test status
Simulation time 7890427926 ps
CPU time 23.54 seconds
Started Jul 14 06:55:23 PM PDT 24
Finished Jul 14 06:55:48 PM PDT 24
Peak memory 219108 kb
Host smart-905028b6-5730-46d1-b56d-494bf2a66497
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1857217680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1857217680
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2400139668
Short name T35
Test name
Test status
Simulation time 206919360814 ps
CPU time 516.74 seconds
Started Jul 14 06:55:38 PM PDT 24
Finished Jul 14 07:04:17 PM PDT 24
Peak memory 262588 kb
Host smart-8bf64e43-9f07-4c46-9054-e2cc073d9c4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400139668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2400139668
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2855034704
Short name T294
Test name
Test status
Simulation time 3937485291 ps
CPU time 21.16 seconds
Started Jul 14 06:55:28 PM PDT 24
Finished Jul 14 06:55:53 PM PDT 24
Peak memory 216296 kb
Host smart-89fae8f6-3682-46b0-81b3-7ecda2b085b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855034704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2855034704
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3213521729
Short name T380
Test name
Test status
Simulation time 310074853 ps
CPU time 1.13 seconds
Started Jul 14 06:55:36 PM PDT 24
Finished Jul 14 06:55:39 PM PDT 24
Peak memory 207904 kb
Host smart-b9a80d68-4d72-48b3-80a6-1e9601ee26a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213521729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3213521729
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2247193478
Short name T601
Test name
Test status
Simulation time 34254054 ps
CPU time 1.05 seconds
Started Jul 14 06:55:44 PM PDT 24
Finished Jul 14 06:55:46 PM PDT 24
Peak memory 207436 kb
Host smart-598c8390-6e54-4b13-aa50-9128152bb1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247193478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2247193478
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.408025989
Short name T471
Test name
Test status
Simulation time 167105148 ps
CPU time 0.89 seconds
Started Jul 14 06:55:27 PM PDT 24
Finished Jul 14 06:55:32 PM PDT 24
Peak memory 207020 kb
Host smart-4ed4cc20-75d6-438b-973b-7c7b0d19a1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408025989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.408025989
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3947290554
Short name T553
Test name
Test status
Simulation time 5029981593 ps
CPU time 9.25 seconds
Started Jul 14 06:55:27 PM PDT 24
Finished Jul 14 06:55:39 PM PDT 24
Peak memory 232736 kb
Host smart-83167a51-62c3-4b6f-8b7f-38521515584e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947290554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3947290554
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.689400469
Short name T807
Test name
Test status
Simulation time 23648227 ps
CPU time 0.69 seconds
Started Jul 14 06:55:31 PM PDT 24
Finished Jul 14 06:55:35 PM PDT 24
Peak memory 205492 kb
Host smart-ce4d3752-e821-49c3-a48d-d2bcf162361a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689400469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.689400469
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1875775011
Short name T233
Test name
Test status
Simulation time 423809790 ps
CPU time 2.4 seconds
Started Jul 14 06:55:35 PM PDT 24
Finished Jul 14 06:55:39 PM PDT 24
Peak memory 224404 kb
Host smart-de0fd5ce-aa57-4fb4-8cde-e3dcb8a4e753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875775011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1875775011
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1784954336
Short name T720
Test name
Test status
Simulation time 298673236 ps
CPU time 0.75 seconds
Started Jul 14 06:55:27 PM PDT 24
Finished Jul 14 06:55:31 PM PDT 24
Peak memory 207112 kb
Host smart-70e177be-678e-4049-9943-c38f42bc9931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784954336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1784954336
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3855870366
Short name T912
Test name
Test status
Simulation time 37956768029 ps
CPU time 218.38 seconds
Started Jul 14 06:55:36 PM PDT 24
Finished Jul 14 06:59:17 PM PDT 24
Peak memory 251972 kb
Host smart-0d04f770-7114-4926-ba38-b11f38921dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855870366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3855870366
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1031846236
Short name T921
Test name
Test status
Simulation time 90411428628 ps
CPU time 453.38 seconds
Started Jul 14 06:55:24 PM PDT 24
Finished Jul 14 07:02:59 PM PDT 24
Peak memory 273852 kb
Host smart-525ff28e-7f1e-40db-bd64-e59e681ff647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031846236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1031846236
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.832421674
Short name T283
Test name
Test status
Simulation time 312318764 ps
CPU time 10.49 seconds
Started Jul 14 06:55:28 PM PDT 24
Finished Jul 14 06:55:42 PM PDT 24
Peak memory 232764 kb
Host smart-66a060d1-3296-4dd8-b52c-8dff722e048a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832421674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.832421674
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2518116172
Short name T496
Test name
Test status
Simulation time 423501250 ps
CPU time 5.23 seconds
Started Jul 14 06:55:26 PM PDT 24
Finished Jul 14 06:55:34 PM PDT 24
Peak memory 224424 kb
Host smart-6da74ee0-48a9-49f5-99dc-1a041d332c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518116172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2518116172
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.506040268
Short name T255
Test name
Test status
Simulation time 12228060826 ps
CPU time 82.59 seconds
Started Jul 14 06:55:29 PM PDT 24
Finished Jul 14 06:56:55 PM PDT 24
Peak memory 232808 kb
Host smart-421c0d40-662f-40e5-a0a7-8527e6204ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506040268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.506040268
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3833138257
Short name T815
Test name
Test status
Simulation time 7156626139 ps
CPU time 9.48 seconds
Started Jul 14 06:55:52 PM PDT 24
Finished Jul 14 06:56:02 PM PDT 24
Peak memory 224576 kb
Host smart-fdf36fc6-d7c3-4188-96b7-42c5afa12f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833138257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3833138257
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.4025736623
Short name T874
Test name
Test status
Simulation time 22239169178 ps
CPU time 7.84 seconds
Started Jul 14 06:55:23 PM PDT 24
Finished Jul 14 06:55:33 PM PDT 24
Peak memory 240708 kb
Host smart-67033940-5c88-409a-af7d-0c790465befe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025736623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.4025736623
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3207763015
Short name T968
Test name
Test status
Simulation time 577870317 ps
CPU time 5.28 seconds
Started Jul 14 06:55:35 PM PDT 24
Finished Jul 14 06:55:43 PM PDT 24
Peak memory 220472 kb
Host smart-381ffe88-77e1-4d9a-8ecd-074dc3e15e80
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3207763015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3207763015
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.4263350571
Short name T160
Test name
Test status
Simulation time 204142679377 ps
CPU time 361.35 seconds
Started Jul 14 06:55:35 PM PDT 24
Finished Jul 14 07:01:38 PM PDT 24
Peak memory 269016 kb
Host smart-a68398e0-dbe6-4026-aed9-a43caafbc860
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263350571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.4263350571
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2305676620
Short name T957
Test name
Test status
Simulation time 3930416219 ps
CPU time 27.22 seconds
Started Jul 14 06:55:40 PM PDT 24
Finished Jul 14 06:56:09 PM PDT 24
Peak memory 216356 kb
Host smart-ae07c8f0-607c-44cd-bfbc-021ca6313c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305676620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2305676620
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1829767148
Short name T652
Test name
Test status
Simulation time 26845597379 ps
CPU time 12.64 seconds
Started Jul 14 06:55:45 PM PDT 24
Finished Jul 14 06:55:59 PM PDT 24
Peak memory 218740 kb
Host smart-4d624a6d-15d9-458b-8cb7-a2d433958dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829767148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1829767148
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1242768266
Short name T372
Test name
Test status
Simulation time 1010968715 ps
CPU time 3.23 seconds
Started Jul 14 06:55:28 PM PDT 24
Finished Jul 14 06:55:35 PM PDT 24
Peak memory 216204 kb
Host smart-afee0dde-59ee-40bb-9b61-4091a6122e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242768266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1242768266
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.4228605036
Short name T641
Test name
Test status
Simulation time 238868405 ps
CPU time 1.02 seconds
Started Jul 14 06:55:46 PM PDT 24
Finished Jul 14 06:55:48 PM PDT 24
Peak memory 205956 kb
Host smart-fa5b0025-cb61-421f-9fe8-edb04eb48856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228605036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.4228605036
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1488956818
Short name T549
Test name
Test status
Simulation time 30239450604 ps
CPU time 48.78 seconds
Started Jul 14 06:55:30 PM PDT 24
Finished Jul 14 06:56:22 PM PDT 24
Peak memory 236320 kb
Host smart-8f421594-69d6-4a04-a688-6c618f71ab96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488956818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1488956818
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.261538065
Short name T308
Test name
Test status
Simulation time 15891915 ps
CPU time 0.73 seconds
Started Jul 14 06:55:35 PM PDT 24
Finished Jul 14 06:55:38 PM PDT 24
Peak memory 204916 kb
Host smart-4daef767-f543-41ec-a687-4006e65769a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261538065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.261538065
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.402166779
Short name T605
Test name
Test status
Simulation time 38882385 ps
CPU time 2.62 seconds
Started Jul 14 06:55:30 PM PDT 24
Finished Jul 14 06:55:36 PM PDT 24
Peak memory 232676 kb
Host smart-da49751b-0a84-4f50-8fdb-ebc92e772d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402166779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.402166779
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.127475559
Short name T960
Test name
Test status
Simulation time 29029474 ps
CPU time 0.81 seconds
Started Jul 14 06:55:29 PM PDT 24
Finished Jul 14 06:55:33 PM PDT 24
Peak memory 206620 kb
Host smart-6f519b6a-bc48-4fb6-b159-7f3ae42e68ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127475559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.127475559
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2286523622
Short name T262
Test name
Test status
Simulation time 48424311926 ps
CPU time 220.47 seconds
Started Jul 14 06:55:33 PM PDT 24
Finished Jul 14 06:59:15 PM PDT 24
Peak memory 262004 kb
Host smart-710ef065-2d85-402b-9981-eb2eb1039a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286523622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2286523622
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1435324263
Short name T751
Test name
Test status
Simulation time 29815371651 ps
CPU time 237.18 seconds
Started Jul 14 06:55:55 PM PDT 24
Finished Jul 14 06:59:55 PM PDT 24
Peak memory 236296 kb
Host smart-8de59d34-96f2-4718-9c41-bc8f1e8a1391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435324263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1435324263
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2309914842
Short name T914
Test name
Test status
Simulation time 32147800920 ps
CPU time 160.1 seconds
Started Jul 14 06:55:49 PM PDT 24
Finished Jul 14 06:58:30 PM PDT 24
Peak memory 240232 kb
Host smart-b2189858-5db5-4138-ac14-c5b46cc0003d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309914842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2309914842
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.4035774946
Short name T545
Test name
Test status
Simulation time 89720831 ps
CPU time 4.89 seconds
Started Jul 14 06:55:48 PM PDT 24
Finished Jul 14 06:55:54 PM PDT 24
Peak memory 240080 kb
Host smart-9f14eed3-d9a6-45d5-a24a-00f4a9011c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035774946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.4035774946
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.2904595270
Short name T959
Test name
Test status
Simulation time 8328713372 ps
CPU time 45.18 seconds
Started Jul 14 06:55:42 PM PDT 24
Finished Jul 14 06:56:29 PM PDT 24
Peak memory 241348 kb
Host smart-66f0cfc8-b982-4077-8825-96c2bfd9b818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904595270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.2904595270
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1125652716
Short name T588
Test name
Test status
Simulation time 118122325 ps
CPU time 2.45 seconds
Started Jul 14 06:55:45 PM PDT 24
Finished Jul 14 06:55:49 PM PDT 24
Peak memory 232328 kb
Host smart-71fae473-f6b7-4d5a-961e-23fa2110fe60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125652716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1125652716
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3527046534
Short name T24
Test name
Test status
Simulation time 2162404602 ps
CPU time 12.16 seconds
Started Jul 14 06:55:30 PM PDT 24
Finished Jul 14 06:55:46 PM PDT 24
Peak memory 232712 kb
Host smart-ff4ea67c-f12f-4ba0-bb49-e5af4a1fb717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527046534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3527046534
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.591024839
Short name T473
Test name
Test status
Simulation time 32705258 ps
CPU time 2.46 seconds
Started Jul 14 06:55:30 PM PDT 24
Finished Jul 14 06:55:36 PM PDT 24
Peak memory 232344 kb
Host smart-1d687855-cc00-46b6-8709-1a95f8ba8a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591024839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.591024839
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2951742322
Short name T775
Test name
Test status
Simulation time 5971348830 ps
CPU time 9.01 seconds
Started Jul 14 06:55:30 PM PDT 24
Finished Jul 14 06:55:42 PM PDT 24
Peak memory 240632 kb
Host smart-97bc6ed8-0f70-4194-888b-57f22879addf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951742322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2951742322
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.784132721
Short name T145
Test name
Test status
Simulation time 71946857 ps
CPU time 3.65 seconds
Started Jul 14 06:55:39 PM PDT 24
Finished Jul 14 06:55:45 PM PDT 24
Peak memory 223168 kb
Host smart-7441b2de-f47d-45e7-be31-ec1eb2ca8aea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=784132721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.784132721
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.4075690466
Short name T906
Test name
Test status
Simulation time 125031710 ps
CPU time 1.02 seconds
Started Jul 14 06:55:33 PM PDT 24
Finished Jul 14 06:55:36 PM PDT 24
Peak memory 207720 kb
Host smart-6dce3fda-2174-4f55-9f9f-653eda08e346
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075690466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.4075690466
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3517982280
Short name T523
Test name
Test status
Simulation time 3461725639 ps
CPU time 21.83 seconds
Started Jul 14 06:55:34 PM PDT 24
Finished Jul 14 06:55:57 PM PDT 24
Peak memory 216312 kb
Host smart-7dfeb375-e6f0-4e85-a631-da6303dbe707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517982280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3517982280
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.37375289
Short name T831
Test name
Test status
Simulation time 10576535 ps
CPU time 0.68 seconds
Started Jul 14 06:55:27 PM PDT 24
Finished Jul 14 06:55:32 PM PDT 24
Peak memory 205728 kb
Host smart-ae8038a9-8c77-4e77-baf9-cc895706a4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37375289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.37375289
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1041954589
Short name T25
Test name
Test status
Simulation time 498319752 ps
CPU time 1.65 seconds
Started Jul 14 06:55:45 PM PDT 24
Finished Jul 14 06:55:48 PM PDT 24
Peak memory 216224 kb
Host smart-c97493f1-cb37-437d-951e-fdbfb860b750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041954589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1041954589
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1773015589
Short name T313
Test name
Test status
Simulation time 37721619 ps
CPU time 0.84 seconds
Started Jul 14 06:55:34 PM PDT 24
Finished Jul 14 06:55:37 PM PDT 24
Peak memory 206992 kb
Host smart-608e9d03-8787-4e97-a08d-6da4da68e935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773015589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1773015589
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1857689243
Short name T911
Test name
Test status
Simulation time 357179997 ps
CPU time 6.5 seconds
Started Jul 14 06:55:32 PM PDT 24
Finished Jul 14 06:55:41 PM PDT 24
Peak memory 232652 kb
Host smart-2ea717a1-8ab4-457c-b791-06bf3c3d9c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857689243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1857689243
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.4177861320
Short name T499
Test name
Test status
Simulation time 20018565 ps
CPU time 0.71 seconds
Started Jul 14 06:55:51 PM PDT 24
Finished Jul 14 06:55:53 PM PDT 24
Peak memory 204876 kb
Host smart-afab0f4c-df63-42cd-8b5c-9167d0828620
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177861320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
4177861320
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1986611998
Short name T257
Test name
Test status
Simulation time 1587202735 ps
CPU time 16.33 seconds
Started Jul 14 06:55:47 PM PDT 24
Finished Jul 14 06:56:04 PM PDT 24
Peak memory 232772 kb
Host smart-2f9054bc-fd8c-4dbe-8147-b136b84f6ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986611998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1986611998
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2104520064
Short name T375
Test name
Test status
Simulation time 14693805 ps
CPU time 0.76 seconds
Started Jul 14 06:55:34 PM PDT 24
Finished Jul 14 06:55:37 PM PDT 24
Peak memory 205568 kb
Host smart-03b51b07-27e1-425d-b24e-c7cf2e82ef95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104520064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2104520064
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2898802896
Short name T202
Test name
Test status
Simulation time 268672808505 ps
CPU time 430.22 seconds
Started Jul 14 06:55:29 PM PDT 24
Finished Jul 14 07:02:43 PM PDT 24
Peak memory 253784 kb
Host smart-fdcf3706-af09-4444-a89b-64b21ee1a09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898802896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2898802896
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.4265980678
Short name T636
Test name
Test status
Simulation time 5272636840 ps
CPU time 73.55 seconds
Started Jul 14 06:55:35 PM PDT 24
Finished Jul 14 06:56:51 PM PDT 24
Peak memory 241032 kb
Host smart-81e18350-bbd6-43a5-8376-07186e92f954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265980678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.4265980678
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.4011904179
Short name T270
Test name
Test status
Simulation time 239446528520 ps
CPU time 635.33 seconds
Started Jul 14 06:55:50 PM PDT 24
Finished Jul 14 07:06:26 PM PDT 24
Peak memory 262768 kb
Host smart-66f2ad11-3ae0-415c-9854-af180d54973b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011904179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.4011904179
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.282422307
Short name T819
Test name
Test status
Simulation time 145107563 ps
CPU time 4.86 seconds
Started Jul 14 06:55:35 PM PDT 24
Finished Jul 14 06:55:41 PM PDT 24
Peak memory 237440 kb
Host smart-98dc61b4-10b6-4492-8d8b-8d7ffd793ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282422307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.282422307
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.245611496
Short name T930
Test name
Test status
Simulation time 12573481993 ps
CPU time 106.03 seconds
Started Jul 14 06:55:52 PM PDT 24
Finished Jul 14 06:57:40 PM PDT 24
Peak memory 249408 kb
Host smart-574497cf-95be-4d2a-a307-4bd4af83d6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245611496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds
.245611496
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2541722199
Short name T927
Test name
Test status
Simulation time 513651130 ps
CPU time 4.46 seconds
Started Jul 14 06:55:43 PM PDT 24
Finished Jul 14 06:55:49 PM PDT 24
Peak memory 229108 kb
Host smart-8d97e902-017a-4f10-ac6a-0514f93528c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541722199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2541722199
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.4084762112
Short name T254
Test name
Test status
Simulation time 655814176 ps
CPU time 12.61 seconds
Started Jul 14 06:55:29 PM PDT 24
Finished Jul 14 06:55:45 PM PDT 24
Peak memory 218984 kb
Host smart-8a2ddae2-03e2-43ba-94bb-f43d6a2d3f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084762112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.4084762112
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.4126227285
Short name T702
Test name
Test status
Simulation time 10513167506 ps
CPU time 9.04 seconds
Started Jul 14 06:55:28 PM PDT 24
Finished Jul 14 06:55:41 PM PDT 24
Peak memory 224632 kb
Host smart-5ec9c3ee-33b7-416f-866b-d8cdebc1cd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126227285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.4126227285
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3146515100
Short name T695
Test name
Test status
Simulation time 1738072485 ps
CPU time 8.44 seconds
Started Jul 14 06:55:45 PM PDT 24
Finished Jul 14 06:55:54 PM PDT 24
Peak memory 232672 kb
Host smart-2efcfffa-42ef-48ca-a3ac-088497f58857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146515100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3146515100
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3261484664
Short name T923
Test name
Test status
Simulation time 592279198 ps
CPU time 7.84 seconds
Started Jul 14 06:55:44 PM PDT 24
Finished Jul 14 06:55:53 PM PDT 24
Peak memory 219168 kb
Host smart-cbae918c-8398-4902-86da-639ad74a2274
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3261484664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3261484664
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1899107520
Short name T949
Test name
Test status
Simulation time 166624142 ps
CPU time 1.05 seconds
Started Jul 14 06:55:31 PM PDT 24
Finished Jul 14 06:55:35 PM PDT 24
Peak memory 207156 kb
Host smart-ec632a7a-689e-4784-b111-d48f671cc298
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899107520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1899107520
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3686406654
Short name T291
Test name
Test status
Simulation time 4049271124 ps
CPU time 28.87 seconds
Started Jul 14 06:55:49 PM PDT 24
Finished Jul 14 06:56:19 PM PDT 24
Peak memory 216340 kb
Host smart-8ad41ede-09d1-4c44-91d8-bca57725c105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686406654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3686406654
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.714646688
Short name T835
Test name
Test status
Simulation time 558126149 ps
CPU time 1.28 seconds
Started Jul 14 06:55:56 PM PDT 24
Finished Jul 14 06:56:01 PM PDT 24
Peak memory 207896 kb
Host smart-8c67ecd5-85b3-4193-bd8f-e0edc8abedca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714646688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.714646688
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1993607854
Short name T866
Test name
Test status
Simulation time 1642536489 ps
CPU time 3.32 seconds
Started Jul 14 06:55:35 PM PDT 24
Finished Jul 14 06:55:40 PM PDT 24
Peak memory 216216 kb
Host smart-ee107a0b-8871-4704-95be-e995e8d8fe40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993607854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1993607854
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3156580534
Short name T565
Test name
Test status
Simulation time 366437371 ps
CPU time 0.84 seconds
Started Jul 14 06:55:27 PM PDT 24
Finished Jul 14 06:55:32 PM PDT 24
Peak memory 205940 kb
Host smart-89af3c4c-ac96-4cb3-b1db-363691d063c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156580534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3156580534
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1046310383
Short name T593
Test name
Test status
Simulation time 1029858391 ps
CPU time 4.17 seconds
Started Jul 14 06:55:30 PM PDT 24
Finished Jul 14 06:55:37 PM PDT 24
Peak memory 232728 kb
Host smart-26fc9f16-eefe-4204-a565-67a9c1f826ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046310383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1046310383
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2494507260
Short name T462
Test name
Test status
Simulation time 15748931 ps
CPU time 0.73 seconds
Started Jul 14 06:55:34 PM PDT 24
Finished Jul 14 06:55:36 PM PDT 24
Peak memory 205564 kb
Host smart-0f47a67a-e4e5-4d33-80c1-46e457d6d281
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494507260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2494507260
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.57957281
Short name T981
Test name
Test status
Simulation time 1824897371 ps
CPU time 8.96 seconds
Started Jul 14 06:55:28 PM PDT 24
Finished Jul 14 06:55:41 PM PDT 24
Peak memory 232640 kb
Host smart-89fe5624-38d9-474c-b2dc-bf3aa0b7aec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57957281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.57957281
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3334434515
Short name T4
Test name
Test status
Simulation time 58997350 ps
CPU time 0.77 seconds
Started Jul 14 06:55:55 PM PDT 24
Finished Jul 14 06:55:58 PM PDT 24
Peak memory 206924 kb
Host smart-649ecb33-90b2-454b-8cea-b862c8e72631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334434515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3334434515
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.13092304
Short name T170
Test name
Test status
Simulation time 18048542965 ps
CPU time 117.09 seconds
Started Jul 14 06:55:58 PM PDT 24
Finished Jul 14 06:57:58 PM PDT 24
Peak memory 239592 kb
Host smart-41b767b4-8913-4c41-8193-f6d52032702e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13092304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.13092304
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3328854265
Short name T134
Test name
Test status
Simulation time 4577519978 ps
CPU time 52.56 seconds
Started Jul 14 06:55:32 PM PDT 24
Finished Jul 14 06:56:27 PM PDT 24
Peak memory 232848 kb
Host smart-603e2175-335e-4e5b-b788-812053c866c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328854265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3328854265
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1390457188
Short name T426
Test name
Test status
Simulation time 2461198310 ps
CPU time 51.23 seconds
Started Jul 14 06:55:47 PM PDT 24
Finished Jul 14 06:56:38 PM PDT 24
Peak memory 251004 kb
Host smart-a55e9045-523b-4161-b71b-33709900f050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390457188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1390457188
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2452908951
Short name T563
Test name
Test status
Simulation time 198594561 ps
CPU time 4.39 seconds
Started Jul 14 06:55:47 PM PDT 24
Finished Jul 14 06:55:52 PM PDT 24
Peak memory 232648 kb
Host smart-caacc9a5-9507-45cb-ae74-243dc22943a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452908951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2452908951
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.646468338
Short name T198
Test name
Test status
Simulation time 139859154378 ps
CPU time 166.51 seconds
Started Jul 14 06:55:50 PM PDT 24
Finished Jul 14 06:58:38 PM PDT 24
Peak memory 251944 kb
Host smart-b06cc26f-a9cf-4d36-a211-8d6f966b0389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646468338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds
.646468338
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3380957026
Short name T419
Test name
Test status
Simulation time 4583494643 ps
CPU time 13.62 seconds
Started Jul 14 06:55:42 PM PDT 24
Finished Jul 14 06:55:57 PM PDT 24
Peak memory 224544 kb
Host smart-fb935efb-efd8-452e-8d5a-3c9930cd57f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380957026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3380957026
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3131449817
Short name T723
Test name
Test status
Simulation time 13992321086 ps
CPU time 110.6 seconds
Started Jul 14 06:55:53 PM PDT 24
Finished Jul 14 06:57:45 PM PDT 24
Peak memory 234488 kb
Host smart-83e3bed8-c1bf-4531-b37a-82dd9dc95cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131449817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3131449817
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3099040377
Short name T924
Test name
Test status
Simulation time 322279498 ps
CPU time 3.62 seconds
Started Jul 14 06:55:36 PM PDT 24
Finished Jul 14 06:55:41 PM PDT 24
Peak memory 224496 kb
Host smart-eb052d6d-f737-4600-ad61-b60e22e742d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099040377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3099040377
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.396316458
Short name T727
Test name
Test status
Simulation time 3916859344 ps
CPU time 13.6 seconds
Started Jul 14 06:55:44 PM PDT 24
Finished Jul 14 06:55:59 PM PDT 24
Peak memory 240556 kb
Host smart-518201e4-d02f-4b46-8c0c-904f5bf2de0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396316458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.396316458
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1166946907
Short name T860
Test name
Test status
Simulation time 477092233 ps
CPU time 7.99 seconds
Started Jul 14 06:55:36 PM PDT 24
Finished Jul 14 06:55:46 PM PDT 24
Peak memory 223120 kb
Host smart-60d30a28-cbc6-4305-9824-7f905caf73c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1166946907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1166946907
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.203837976
Short name T163
Test name
Test status
Simulation time 30463928040 ps
CPU time 96.53 seconds
Started Jul 14 06:55:35 PM PDT 24
Finished Jul 14 06:57:13 PM PDT 24
Peak memory 253540 kb
Host smart-6bcf3b40-2782-46e9-9b70-b220542cbe59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203837976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.203837976
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1353071319
Short name T537
Test name
Test status
Simulation time 5623729540 ps
CPU time 36.43 seconds
Started Jul 14 06:55:31 PM PDT 24
Finished Jul 14 06:56:10 PM PDT 24
Peak memory 216344 kb
Host smart-9df2a5c1-bbac-49f0-bef1-72875b182c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353071319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1353071319
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2575999358
Short name T899
Test name
Test status
Simulation time 4967358303 ps
CPU time 7.72 seconds
Started Jul 14 06:55:37 PM PDT 24
Finished Jul 14 06:55:48 PM PDT 24
Peak memory 216384 kb
Host smart-e2bee326-e9e2-40e5-bfc3-161ba0926daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575999358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2575999358
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.351957306
Short name T609
Test name
Test status
Simulation time 137630157 ps
CPU time 1.71 seconds
Started Jul 14 06:55:54 PM PDT 24
Finished Jul 14 06:55:58 PM PDT 24
Peak memory 216216 kb
Host smart-89e3ca2e-e696-4473-ae4e-4e487db3b37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351957306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.351957306
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3751701468
Short name T319
Test name
Test status
Simulation time 41045810 ps
CPU time 0.81 seconds
Started Jul 14 06:55:48 PM PDT 24
Finished Jul 14 06:55:50 PM PDT 24
Peak memory 205980 kb
Host smart-c9422b6d-0fb1-42bd-8e9b-7fa927778708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751701468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3751701468
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3129988504
Short name T452
Test name
Test status
Simulation time 23891852232 ps
CPU time 14.04 seconds
Started Jul 14 06:55:36 PM PDT 24
Finished Jul 14 06:55:53 PM PDT 24
Peak memory 232784 kb
Host smart-46dab1a4-4b11-48ba-ae35-eb25990a5b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129988504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3129988504
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.497138832
Short name T646
Test name
Test status
Simulation time 19473761 ps
CPU time 0.71 seconds
Started Jul 14 06:55:37 PM PDT 24
Finished Jul 14 06:55:40 PM PDT 24
Peak memory 204976 kb
Host smart-a886cea7-bda0-4a37-ac02-bd44d1cfecca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497138832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.497138832
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3979579407
Short name T568
Test name
Test status
Simulation time 4793461886 ps
CPU time 6.22 seconds
Started Jul 14 06:55:36 PM PDT 24
Finished Jul 14 06:55:45 PM PDT 24
Peak memory 224600 kb
Host smart-900e64dd-8a53-461e-bc01-75f0a5de4f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979579407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3979579407
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.335857956
Short name T794
Test name
Test status
Simulation time 43296006 ps
CPU time 0.78 seconds
Started Jul 14 06:55:54 PM PDT 24
Finished Jul 14 06:55:57 PM PDT 24
Peak memory 205656 kb
Host smart-c256e971-5c4c-449a-a824-6d50414ee2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335857956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.335857956
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2613138185
Short name T768
Test name
Test status
Simulation time 6488563177 ps
CPU time 47.27 seconds
Started Jul 14 06:55:48 PM PDT 24
Finished Jul 14 06:56:36 PM PDT 24
Peak memory 233848 kb
Host smart-1859e6d5-feb7-427f-8693-f8196396d2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613138185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2613138185
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2347213706
Short name T362
Test name
Test status
Simulation time 9136353473 ps
CPU time 69.35 seconds
Started Jul 14 06:55:49 PM PDT 24
Finished Jul 14 06:57:00 PM PDT 24
Peak memory 251172 kb
Host smart-ad2aa125-382b-48e2-b003-a4b44dffb3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347213706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2347213706
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.125200585
Short name T410
Test name
Test status
Simulation time 228357376 ps
CPU time 5.86 seconds
Started Jul 14 06:55:54 PM PDT 24
Finished Jul 14 06:56:03 PM PDT 24
Peak memory 234736 kb
Host smart-169d5ba0-a7f4-4a86-9cf6-ddca7088a6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125200585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.125200585
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1764101693
Short name T575
Test name
Test status
Simulation time 5631913602 ps
CPU time 15.01 seconds
Started Jul 14 06:55:38 PM PDT 24
Finished Jul 14 06:55:55 PM PDT 24
Peak memory 235992 kb
Host smart-ce723cc3-20d5-4a8e-a034-b6d71b965fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764101693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1764101693
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.2414340815
Short name T984
Test name
Test status
Simulation time 2614264048 ps
CPU time 28.62 seconds
Started Jul 14 06:55:44 PM PDT 24
Finished Jul 14 06:56:14 PM PDT 24
Peak memory 253948 kb
Host smart-51169952-24be-4a3e-a8c7-1eeb65f74b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414340815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.2414340815
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.766875389
Short name T596
Test name
Test status
Simulation time 1484551916 ps
CPU time 6.18 seconds
Started Jul 14 06:55:36 PM PDT 24
Finished Jul 14 06:55:44 PM PDT 24
Peak memory 232840 kb
Host smart-332e5de3-309c-4a7c-a9ee-49a09a60df38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766875389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.766875389
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2956972211
Short name T193
Test name
Test status
Simulation time 398501644 ps
CPU time 9.93 seconds
Started Jul 14 06:55:39 PM PDT 24
Finished Jul 14 06:55:51 PM PDT 24
Peak memory 224488 kb
Host smart-b9e12a9b-f71c-4627-9ae6-cfdff7133c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956972211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2956972211
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2593172061
Short name T249
Test name
Test status
Simulation time 36494993889 ps
CPU time 29.14 seconds
Started Jul 14 06:55:36 PM PDT 24
Finished Jul 14 06:56:07 PM PDT 24
Peak memory 232804 kb
Host smart-76c6b230-58c6-4796-b3ad-c0d85b3183a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593172061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2593172061
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.4141207777
Short name T995
Test name
Test status
Simulation time 3744390874 ps
CPU time 13.52 seconds
Started Jul 14 06:55:33 PM PDT 24
Finished Jul 14 06:55:49 PM PDT 24
Peak memory 224624 kb
Host smart-64d7e02c-ea0e-4be1-912c-a122a00e30a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141207777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.4141207777
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3586990480
Short name T863
Test name
Test status
Simulation time 3206344784 ps
CPU time 8.11 seconds
Started Jul 14 06:55:52 PM PDT 24
Finished Jul 14 06:56:01 PM PDT 24
Peak memory 219096 kb
Host smart-a0171201-aca0-4865-9a37-736ce38a3092
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3586990480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3586990480
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1577582723
Short name T773
Test name
Test status
Simulation time 123794665250 ps
CPU time 258.87 seconds
Started Jul 14 06:55:52 PM PDT 24
Finished Jul 14 07:00:12 PM PDT 24
Peak memory 251488 kb
Host smart-54198992-ab36-4725-8976-b9144bee50ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577582723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1577582723
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1264426944
Short name T746
Test name
Test status
Simulation time 7085208212 ps
CPU time 39.49 seconds
Started Jul 14 06:55:37 PM PDT 24
Finished Jul 14 06:56:19 PM PDT 24
Peak memory 216356 kb
Host smart-5e830e09-ceb2-4f92-ba9c-0f3c75b4a92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264426944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1264426944
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3846404557
Short name T538
Test name
Test status
Simulation time 4207738037 ps
CPU time 6.85 seconds
Started Jul 14 06:55:36 PM PDT 24
Finished Jul 14 06:55:45 PM PDT 24
Peak memory 216348 kb
Host smart-a9c5e0a0-939a-45a8-8da7-c16e0458ee6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846404557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3846404557
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1091476063
Short name T307
Test name
Test status
Simulation time 248921843 ps
CPU time 6.21 seconds
Started Jul 14 06:55:37 PM PDT 24
Finished Jul 14 06:55:46 PM PDT 24
Peak memory 216168 kb
Host smart-3a6cdedc-7f75-49d1-a10f-af0dfd541f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091476063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1091476063
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3935673788
Short name T328
Test name
Test status
Simulation time 215329501 ps
CPU time 0.85 seconds
Started Jul 14 06:55:37 PM PDT 24
Finished Jul 14 06:55:41 PM PDT 24
Peak memory 206004 kb
Host smart-96a0d886-10b0-4035-85a6-8909b0f6e778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935673788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3935673788
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2279931861
Short name T814
Test name
Test status
Simulation time 5580785113 ps
CPU time 19.44 seconds
Started Jul 14 06:55:52 PM PDT 24
Finished Jul 14 06:56:13 PM PDT 24
Peak memory 232868 kb
Host smart-f3b48ad5-8270-4e77-a043-ac87b74dddd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279931861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2279931861
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.454054138
Short name T867
Test name
Test status
Simulation time 15313965 ps
CPU time 0.9 seconds
Started Jul 14 06:55:43 PM PDT 24
Finished Jul 14 06:55:44 PM PDT 24
Peak memory 204948 kb
Host smart-b8d931cc-44a2-42ba-b72d-5352c97d6afc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454054138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.454054138
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.634074445
Short name T234
Test name
Test status
Simulation time 953962684 ps
CPU time 7 seconds
Started Jul 14 06:55:37 PM PDT 24
Finished Jul 14 06:55:46 PM PDT 24
Peak memory 232632 kb
Host smart-31f548a4-f246-4686-831f-a281c88b3645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634074445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.634074445
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1213954629
Short name T556
Test name
Test status
Simulation time 25492414 ps
CPU time 0.78 seconds
Started Jul 14 06:55:38 PM PDT 24
Finished Jul 14 06:55:41 PM PDT 24
Peak memory 206924 kb
Host smart-c41a282a-db68-4a58-9efb-bba71dd5485d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213954629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1213954629
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1128516903
Short name T395
Test name
Test status
Simulation time 4463869253 ps
CPU time 22.06 seconds
Started Jul 14 06:55:50 PM PDT 24
Finished Jul 14 06:56:13 PM PDT 24
Peak memory 241024 kb
Host smart-e3d4ec52-4a5d-4e3c-916f-87fcdd6532db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128516903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1128516903
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2153830197
Short name T80
Test name
Test status
Simulation time 1627471845 ps
CPU time 22.56 seconds
Started Jul 14 06:55:56 PM PDT 24
Finished Jul 14 06:56:21 PM PDT 24
Peak memory 240072 kb
Host smart-fe04e5d5-144c-4eeb-8f1e-a40af47fb1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153830197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2153830197
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2578539025
Short name T228
Test name
Test status
Simulation time 13259946197 ps
CPU time 132.49 seconds
Started Jul 14 06:55:56 PM PDT 24
Finished Jul 14 06:58:13 PM PDT 24
Peak memory 250564 kb
Host smart-38cc6646-1c3d-4a40-b3c3-e2ca8355c2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578539025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2578539025
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3393316143
Short name T617
Test name
Test status
Simulation time 1725649793 ps
CPU time 20.15 seconds
Started Jul 14 06:55:49 PM PDT 24
Finished Jul 14 06:56:11 PM PDT 24
Peak memory 232700 kb
Host smart-4d2a6f27-145b-4dd2-903e-0ee86b33a888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393316143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3393316143
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1519864344
Short name T200
Test name
Test status
Simulation time 1009686926 ps
CPU time 11.16 seconds
Started Jul 14 06:55:37 PM PDT 24
Finished Jul 14 06:55:50 PM PDT 24
Peak memory 218892 kb
Host smart-9269f474-56a2-4737-963b-09f0b10f735a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519864344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1519864344
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.587514722
Short name T679
Test name
Test status
Simulation time 56365856 ps
CPU time 2.06 seconds
Started Jul 14 06:55:36 PM PDT 24
Finished Jul 14 06:55:41 PM PDT 24
Peak memory 224124 kb
Host smart-70dd35ef-91d1-4043-a0e5-5ce595a046a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587514722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.587514722
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.4048499667
Short name T40
Test name
Test status
Simulation time 40141592802 ps
CPU time 13.47 seconds
Started Jul 14 06:55:37 PM PDT 24
Finished Jul 14 06:55:53 PM PDT 24
Peak memory 232672 kb
Host smart-3c7a110c-e192-4660-83a2-fec16bcd2534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048499667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.4048499667
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3132711056
Short name T533
Test name
Test status
Simulation time 329415198 ps
CPU time 2.26 seconds
Started Jul 14 06:55:55 PM PDT 24
Finished Jul 14 06:56:00 PM PDT 24
Peak memory 232284 kb
Host smart-4c325f4f-6e17-4e89-8150-fbc143d2b43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132711056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3132711056
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3576831990
Short name T548
Test name
Test status
Simulation time 9024780851 ps
CPU time 7.63 seconds
Started Jul 14 06:55:38 PM PDT 24
Finished Jul 14 06:55:48 PM PDT 24
Peak memory 220580 kb
Host smart-436a4821-4030-4e28-982e-071363375472
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3576831990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3576831990
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.4026905978
Short name T290
Test name
Test status
Simulation time 11902091348 ps
CPU time 18.1 seconds
Started Jul 14 06:55:56 PM PDT 24
Finished Jul 14 06:56:17 PM PDT 24
Peak memory 216536 kb
Host smart-f978596f-aa56-4966-ba01-0d278d54801d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026905978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.4026905978
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1922652107
Short name T336
Test name
Test status
Simulation time 34204712 ps
CPU time 0.7 seconds
Started Jul 14 06:55:37 PM PDT 24
Finished Jul 14 06:55:40 PM PDT 24
Peak memory 205704 kb
Host smart-b91218c6-c392-4bad-9c27-73c9dd21ce62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922652107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1922652107
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2254582963
Short name T469
Test name
Test status
Simulation time 182929642 ps
CPU time 5.33 seconds
Started Jul 14 06:55:39 PM PDT 24
Finished Jul 14 06:55:46 PM PDT 24
Peak memory 216212 kb
Host smart-37526664-3b50-4955-a85b-8b655ca30db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254582963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2254582963
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2291269139
Short name T39
Test name
Test status
Simulation time 382910566 ps
CPU time 1.04 seconds
Started Jul 14 06:55:38 PM PDT 24
Finished Jul 14 06:55:41 PM PDT 24
Peak memory 207004 kb
Host smart-c6aa7e04-b97d-49aa-8e61-385baa74db17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291269139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2291269139
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3262297882
Short name T820
Test name
Test status
Simulation time 560435028 ps
CPU time 2.35 seconds
Started Jul 14 06:55:36 PM PDT 24
Finished Jul 14 06:55:41 PM PDT 24
Peak memory 224508 kb
Host smart-fd274cbe-e786-4e23-a075-f59f2151cb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262297882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3262297882
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3869437924
Short name T334
Test name
Test status
Simulation time 42364149 ps
CPU time 0.74 seconds
Started Jul 14 06:55:50 PM PDT 24
Finished Jul 14 06:55:52 PM PDT 24
Peak memory 205536 kb
Host smart-55abb6b3-0520-4d0f-99d7-9e471edef393
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869437924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3869437924
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2367175654
Short name T801
Test name
Test status
Simulation time 114375399 ps
CPU time 2.39 seconds
Started Jul 14 06:55:53 PM PDT 24
Finished Jul 14 06:55:58 PM PDT 24
Peak memory 224456 kb
Host smart-932901ac-2142-4fcc-a5dc-9a955b767650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367175654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2367175654
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1339693775
Short name T440
Test name
Test status
Simulation time 28447831 ps
CPU time 0.74 seconds
Started Jul 14 06:55:56 PM PDT 24
Finished Jul 14 06:56:00 PM PDT 24
Peak memory 206576 kb
Host smart-3a9cf5a0-b726-443d-b4aa-34cea38f1c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339693775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1339693775
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2346855199
Short name T806
Test name
Test status
Simulation time 22382777447 ps
CPU time 170.67 seconds
Started Jul 14 06:55:46 PM PDT 24
Finished Jul 14 06:58:37 PM PDT 24
Peak memory 249192 kb
Host smart-c5aaac92-104d-4fab-b1c5-acbc43960449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346855199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2346855199
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1922143233
Short name T450
Test name
Test status
Simulation time 58658852269 ps
CPU time 297.16 seconds
Started Jul 14 06:55:47 PM PDT 24
Finished Jul 14 07:00:45 PM PDT 24
Peak memory 257360 kb
Host smart-e56548fb-d020-4fe9-9acd-b464c0bc4046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922143233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1922143233
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.1638338114
Short name T733
Test name
Test status
Simulation time 78062578350 ps
CPU time 148.34 seconds
Started Jul 14 06:55:53 PM PDT 24
Finished Jul 14 06:58:23 PM PDT 24
Peak memory 265364 kb
Host smart-f51564c3-c6ca-4fcc-81e9-d474deafe979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638338114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.1638338114
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1894655066
Short name T439
Test name
Test status
Simulation time 768014380 ps
CPU time 11.08 seconds
Started Jul 14 06:55:54 PM PDT 24
Finished Jul 14 06:56:07 PM PDT 24
Peak memory 224500 kb
Host smart-4abf9a25-e743-4ce6-91aa-32dc841202dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894655066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1894655066
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2964801259
Short name T791
Test name
Test status
Simulation time 3641613406 ps
CPU time 21.42 seconds
Started Jul 14 06:55:55 PM PDT 24
Finished Jul 14 06:56:19 PM PDT 24
Peak memory 232820 kb
Host smart-9a1be836-9c9c-46e6-8db1-3ff6a31e1b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964801259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2964801259
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.170368418
Short name T663
Test name
Test status
Simulation time 7046475082 ps
CPU time 7.41 seconds
Started Jul 14 06:55:55 PM PDT 24
Finished Jul 14 06:56:05 PM PDT 24
Peak memory 224536 kb
Host smart-a2131a9e-4d6a-40e3-ae5b-4b9f0a3b87ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170368418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.170368418
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.527652581
Short name T463
Test name
Test status
Simulation time 3745277641 ps
CPU time 14.03 seconds
Started Jul 14 06:55:56 PM PDT 24
Finished Jul 14 06:56:13 PM PDT 24
Peak memory 224516 kb
Host smart-bf321efb-1547-4309-b5bf-e715d5f671e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527652581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.527652581
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3610167497
Short name T724
Test name
Test status
Simulation time 2356425971 ps
CPU time 10.38 seconds
Started Jul 14 06:55:57 PM PDT 24
Finished Jul 14 06:56:10 PM PDT 24
Peak memory 222000 kb
Host smart-65dea929-0246-4f2b-af20-fd176445adcf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3610167497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3610167497
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3049065830
Short name T413
Test name
Test status
Simulation time 168305215 ps
CPU time 0.95 seconds
Started Jul 14 06:55:47 PM PDT 24
Finished Jul 14 06:55:49 PM PDT 24
Peak memory 206992 kb
Host smart-f9c5dc06-1b92-4290-95b7-fd1e3cb47019
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049065830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3049065830
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.323788216
Short name T848
Test name
Test status
Simulation time 45811442 ps
CPU time 0.72 seconds
Started Jul 14 06:55:57 PM PDT 24
Finished Jul 14 06:56:01 PM PDT 24
Peak memory 205712 kb
Host smart-d979a35e-a074-4f5d-aab2-6c6c88510d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323788216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.323788216
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1222068548
Short name T933
Test name
Test status
Simulation time 1347811834 ps
CPU time 6.61 seconds
Started Jul 14 06:55:55 PM PDT 24
Finished Jul 14 06:56:04 PM PDT 24
Peak memory 216164 kb
Host smart-d0de3e5e-42b9-4a4f-8ada-2ed0ef11925f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222068548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1222068548
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1579821750
Short name T642
Test name
Test status
Simulation time 61499140 ps
CPU time 1.46 seconds
Started Jul 14 06:55:52 PM PDT 24
Finished Jul 14 06:55:54 PM PDT 24
Peak memory 216196 kb
Host smart-fce4c4e2-cf02-4f74-9f7e-eb897d1dda5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579821750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1579821750
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1367473041
Short name T321
Test name
Test status
Simulation time 13451347 ps
CPU time 0.71 seconds
Started Jul 14 06:55:57 PM PDT 24
Finished Jul 14 06:56:01 PM PDT 24
Peak memory 205984 kb
Host smart-9e832132-8adc-4b92-8db6-4ada0e2b6696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367473041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1367473041
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2244793145
Short name T1005
Test name
Test status
Simulation time 100862935 ps
CPU time 2.51 seconds
Started Jul 14 06:55:51 PM PDT 24
Finished Jul 14 06:55:55 PM PDT 24
Peak memory 232720 kb
Host smart-d6fb714c-8629-41cb-8e6d-be0d750d90c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244793145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2244793145
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1611277361
Short name T1
Test name
Test status
Simulation time 54002589 ps
CPU time 0.76 seconds
Started Jul 14 06:55:56 PM PDT 24
Finished Jul 14 06:56:00 PM PDT 24
Peak memory 204964 kb
Host smart-4e01e824-bef4-47da-9812-3f61e10f94df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611277361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1611277361
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1181018504
Short name T327
Test name
Test status
Simulation time 1894201435 ps
CPU time 7.62 seconds
Started Jul 14 06:55:50 PM PDT 24
Finished Jul 14 06:55:59 PM PDT 24
Peak memory 224440 kb
Host smart-a73b11af-5b9a-4a07-abc1-5e55bb542969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181018504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1181018504
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3467238757
Short name T106
Test name
Test status
Simulation time 33241551 ps
CPU time 0.78 seconds
Started Jul 14 06:55:41 PM PDT 24
Finished Jul 14 06:55:43 PM PDT 24
Peak memory 206908 kb
Host smart-c068222c-558a-4aef-8395-61b2277b157c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467238757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3467238757
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3280709245
Short name T583
Test name
Test status
Simulation time 2172912969 ps
CPU time 27.8 seconds
Started Jul 14 06:56:18 PM PDT 24
Finished Jul 14 06:56:51 PM PDT 24
Peak memory 249164 kb
Host smart-e2f6719e-0028-49e1-a680-57001aea3487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280709245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3280709245
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.821495377
Short name T232
Test name
Test status
Simulation time 50291691413 ps
CPU time 121.69 seconds
Started Jul 14 06:56:02 PM PDT 24
Finished Jul 14 06:58:05 PM PDT 24
Peak memory 253004 kb
Host smart-713021e8-e42a-4e0a-bb42-3348bd4f2401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821495377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.821495377
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2134386579
Short name T216
Test name
Test status
Simulation time 49058128053 ps
CPU time 97.48 seconds
Started Jul 14 06:55:57 PM PDT 24
Finished Jul 14 06:57:38 PM PDT 24
Peak memory 236732 kb
Host smart-51fa6ef2-6d4f-44f0-8fc0-588cf9b48de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134386579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2134386579
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.95513235
Short name T955
Test name
Test status
Simulation time 6094055975 ps
CPU time 24.89 seconds
Started Jul 14 06:56:03 PM PDT 24
Finished Jul 14 06:56:29 PM PDT 24
Peak memory 235584 kb
Host smart-408fb395-8e71-40ef-a33e-410194b365ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95513235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.95513235
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.2679047910
Short name T658
Test name
Test status
Simulation time 9444602998 ps
CPU time 64.01 seconds
Started Jul 14 06:56:16 PM PDT 24
Finished Jul 14 06:57:25 PM PDT 24
Peak memory 249220 kb
Host smart-1b2691d9-5986-44be-af4c-b41808693f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679047910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.2679047910
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1194688872
Short name T487
Test name
Test status
Simulation time 1565611438 ps
CPU time 10.89 seconds
Started Jul 14 06:55:41 PM PDT 24
Finished Jul 14 06:55:53 PM PDT 24
Peak memory 232636 kb
Host smart-5d49a566-5986-439a-9c59-edd2a2031b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194688872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1194688872
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3342165655
Short name T235
Test name
Test status
Simulation time 33967884963 ps
CPU time 106.13 seconds
Started Jul 14 06:55:55 PM PDT 24
Finished Jul 14 06:57:44 PM PDT 24
Peak memory 249192 kb
Host smart-c4f85a62-2013-4b63-ac9b-37fdeaad851d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342165655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3342165655
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2773205640
Short name T266
Test name
Test status
Simulation time 51714919026 ps
CPU time 28.13 seconds
Started Jul 14 06:55:41 PM PDT 24
Finished Jul 14 06:56:10 PM PDT 24
Peak memory 240956 kb
Host smart-1daf6dc9-efa6-4bd1-aae1-931e3002aaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773205640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2773205640
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3361891218
Short name T992
Test name
Test status
Simulation time 1914172360 ps
CPU time 4.27 seconds
Started Jul 14 06:55:53 PM PDT 24
Finished Jul 14 06:56:00 PM PDT 24
Peak memory 224472 kb
Host smart-d792bbaa-2fc1-4dbf-afd8-2a9283e4c91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361891218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3361891218
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2660785217
Short name T894
Test name
Test status
Simulation time 877772229 ps
CPU time 3.6 seconds
Started Jul 14 06:55:55 PM PDT 24
Finished Jul 14 06:56:01 PM PDT 24
Peak memory 223200 kb
Host smart-1238e78b-a17e-4c62-9bbc-b88a05cfdb3f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2660785217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2660785217
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.23244670
Short name T280
Test name
Test status
Simulation time 19980226206 ps
CPU time 140.13 seconds
Started Jul 14 06:55:55 PM PDT 24
Finished Jul 14 06:58:18 PM PDT 24
Peak memory 254696 kb
Host smart-4fcf1430-c274-40ce-894c-0b50fb1d088f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23244670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stress
_all.23244670
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3581402294
Short name T3
Test name
Test status
Simulation time 5554514876 ps
CPU time 31.88 seconds
Started Jul 14 06:55:50 PM PDT 24
Finished Jul 14 06:56:23 PM PDT 24
Peak memory 216584 kb
Host smart-75dcae2e-6226-4ea4-a56b-689224e73fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581402294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3581402294
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3170334042
Short name T513
Test name
Test status
Simulation time 13708086438 ps
CPU time 21.05 seconds
Started Jul 14 06:55:54 PM PDT 24
Finished Jul 14 06:56:18 PM PDT 24
Peak memory 216316 kb
Host smart-fc0a81f1-dc64-49e9-9100-dec01350ca51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170334042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3170334042
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1421350665
Short name T714
Test name
Test status
Simulation time 225464155 ps
CPU time 3.21 seconds
Started Jul 14 06:55:54 PM PDT 24
Finished Jul 14 06:55:59 PM PDT 24
Peak memory 216224 kb
Host smart-1b700062-0a8c-4699-a3c4-470cb58eac6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421350665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1421350665
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1173732443
Short name T690
Test name
Test status
Simulation time 30801216 ps
CPU time 0.8 seconds
Started Jul 14 06:55:56 PM PDT 24
Finished Jul 14 06:56:00 PM PDT 24
Peak memory 205952 kb
Host smart-582bed5b-eebc-4931-9e42-96d0638c8798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173732443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1173732443
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1513283117
Short name T776
Test name
Test status
Simulation time 185345186 ps
CPU time 3.26 seconds
Started Jul 14 06:55:56 PM PDT 24
Finished Jul 14 06:56:02 PM PDT 24
Peak memory 232660 kb
Host smart-11b51464-000c-4b4c-8218-20a89e56f603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513283117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1513283117
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.532810782
Short name T909
Test name
Test status
Simulation time 24304983 ps
CPU time 0.73 seconds
Started Jul 14 06:55:55 PM PDT 24
Finished Jul 14 06:55:59 PM PDT 24
Peak memory 205464 kb
Host smart-0f6d4854-7fb0-474d-9fd7-a49a01962637
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532810782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.532810782
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2733458438
Short name T137
Test name
Test status
Simulation time 62199639 ps
CPU time 2.33 seconds
Started Jul 14 06:55:54 PM PDT 24
Finished Jul 14 06:55:58 PM PDT 24
Peak memory 224456 kb
Host smart-8258c0d7-2900-4212-b043-b60d7d1e3183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733458438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2733458438
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1814475271
Short name T376
Test name
Test status
Simulation time 50412625 ps
CPU time 0.76 seconds
Started Jul 14 06:55:56 PM PDT 24
Finished Jul 14 06:56:00 PM PDT 24
Peak memory 205856 kb
Host smart-72528a18-d5b8-4c9e-abf5-2e7530294c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814475271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1814475271
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2150516478
Short name T169
Test name
Test status
Simulation time 84257241966 ps
CPU time 151.41 seconds
Started Jul 14 06:56:02 PM PDT 24
Finished Jul 14 06:58:35 PM PDT 24
Peak memory 249608 kb
Host smart-31e8a816-a1a5-4fc4-a33b-cd2636f7f61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150516478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2150516478
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.138156167
Short name T64
Test name
Test status
Simulation time 49328926220 ps
CPU time 250.13 seconds
Started Jul 14 06:55:55 PM PDT 24
Finished Jul 14 07:00:10 PM PDT 24
Peak memory 265968 kb
Host smart-1180c83b-c55f-491c-90f3-45697d7c00c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138156167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.138156167
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3299926240
Short name T598
Test name
Test status
Simulation time 2070944526 ps
CPU time 6.99 seconds
Started Jul 14 06:56:09 PM PDT 24
Finished Jul 14 06:56:17 PM PDT 24
Peak memory 224504 kb
Host smart-7b290fa3-32b7-430d-b068-2022a902ceae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299926240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3299926240
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.17793899
Short name T247
Test name
Test status
Simulation time 40674227914 ps
CPU time 292.65 seconds
Started Jul 14 06:56:08 PM PDT 24
Finished Jul 14 07:01:02 PM PDT 24
Peak memory 265592 kb
Host smart-e52152b8-3d66-4192-8caa-eabd5baa2a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17793899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds.17793899
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.104246072
Short name T750
Test name
Test status
Simulation time 305339196 ps
CPU time 3.27 seconds
Started Jul 14 06:56:19 PM PDT 24
Finished Jul 14 06:56:28 PM PDT 24
Peak memory 224480 kb
Host smart-f95e1ba5-c48e-4778-8787-eaacee2df71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104246072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.104246072
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1803494359
Short name T859
Test name
Test status
Simulation time 6644082766 ps
CPU time 19.23 seconds
Started Jul 14 06:56:00 PM PDT 24
Finished Jul 14 06:56:22 PM PDT 24
Peak memory 224540 kb
Host smart-1a32647c-9cac-4d8e-b0ab-7bc506351ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803494359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1803494359
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.4075356
Short name T673
Test name
Test status
Simulation time 381542967 ps
CPU time 2.7 seconds
Started Jul 14 06:55:55 PM PDT 24
Finished Jul 14 06:56:01 PM PDT 24
Peak memory 224412 kb
Host smart-26fea8bf-db01-43cb-a3d9-be7facb3c1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap.4075356
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3843680904
Short name T339
Test name
Test status
Simulation time 2149111751 ps
CPU time 6.29 seconds
Started Jul 14 06:56:14 PM PDT 24
Finished Jul 14 06:56:23 PM PDT 24
Peak memory 232672 kb
Host smart-f713194a-da48-4f86-93bc-2bdd4487312b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843680904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3843680904
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2778287642
Short name T136
Test name
Test status
Simulation time 1973712455 ps
CPU time 7.35 seconds
Started Jul 14 06:55:54 PM PDT 24
Finished Jul 14 06:56:04 PM PDT 24
Peak memory 222212 kb
Host smart-b5b5a5c1-94c9-4ce9-9848-c5cb9e4f0031
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2778287642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2778287642
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1689893073
Short name T872
Test name
Test status
Simulation time 384345403 ps
CPU time 0.96 seconds
Started Jul 14 06:56:17 PM PDT 24
Finished Jul 14 06:56:22 PM PDT 24
Peak memory 206712 kb
Host smart-998462c8-ac19-4653-a86e-6a74e59be469
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689893073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1689893073
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2215303274
Short name T403
Test name
Test status
Simulation time 6693442681 ps
CPU time 5.34 seconds
Started Jul 14 06:55:52 PM PDT 24
Finished Jul 14 06:55:58 PM PDT 24
Peak memory 216332 kb
Host smart-13c23ce7-f1dc-4bdf-8cec-0f71bb3fc580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215303274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2215303274
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2949792660
Short name T932
Test name
Test status
Simulation time 724960178 ps
CPU time 3.06 seconds
Started Jul 14 06:55:57 PM PDT 24
Finished Jul 14 06:56:04 PM PDT 24
Peak memory 216288 kb
Host smart-120c2486-7fde-4d4e-a650-6f7cbe1f32db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949792660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2949792660
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.545541878
Short name T700
Test name
Test status
Simulation time 512729384 ps
CPU time 1.42 seconds
Started Jul 14 06:55:56 PM PDT 24
Finished Jul 14 06:56:00 PM PDT 24
Peak memory 216208 kb
Host smart-2e1fd7e1-3608-46b5-910d-cbaec5e5490e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545541878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.545541878
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3071418192
Short name T444
Test name
Test status
Simulation time 22019831 ps
CPU time 0.71 seconds
Started Jul 14 06:55:54 PM PDT 24
Finished Jul 14 06:55:58 PM PDT 24
Peak memory 205660 kb
Host smart-f1deec42-8e01-4368-ad1b-90681edd6276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071418192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3071418192
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3658974702
Short name T818
Test name
Test status
Simulation time 6797053061 ps
CPU time 7.25 seconds
Started Jul 14 06:56:12 PM PDT 24
Finished Jul 14 06:56:22 PM PDT 24
Peak memory 236820 kb
Host smart-154e0bb2-5682-4403-960a-2c6c9f714042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658974702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3658974702
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1084272284
Short name T747
Test name
Test status
Simulation time 33862307 ps
CPU time 0.76 seconds
Started Jul 14 06:54:44 PM PDT 24
Finished Jul 14 06:54:49 PM PDT 24
Peak memory 204960 kb
Host smart-aa1c2306-1d7a-451d-bfbe-d0c2a5b5e29a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084272284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
084272284
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3444843379
Short name T994
Test name
Test status
Simulation time 1395517754 ps
CPU time 7.57 seconds
Started Jul 14 06:54:36 PM PDT 24
Finished Jul 14 06:54:47 PM PDT 24
Peak memory 224424 kb
Host smart-ef3bd7a6-f93f-4837-921f-c2071a8bab1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444843379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3444843379
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.365297083
Short name T1009
Test name
Test status
Simulation time 37164332 ps
CPU time 0.76 seconds
Started Jul 14 06:54:37 PM PDT 24
Finished Jul 14 06:54:41 PM PDT 24
Peak memory 206624 kb
Host smart-c5ed5ffd-fa14-49b9-bf0d-7930390c594c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365297083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.365297083
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3467189600
Short name T913
Test name
Test status
Simulation time 4590924436 ps
CPU time 59.94 seconds
Started Jul 14 06:54:49 PM PDT 24
Finished Jul 14 06:55:52 PM PDT 24
Peak memory 254996 kb
Host smart-94574fd7-38a3-465a-8edc-4dde1b1bec99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467189600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3467189600
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3333989384
Short name T649
Test name
Test status
Simulation time 80482217584 ps
CPU time 204.87 seconds
Started Jul 14 06:55:02 PM PDT 24
Finished Jul 14 06:58:32 PM PDT 24
Peak memory 249292 kb
Host smart-d9e9c569-c649-4fde-a0f5-63556bb7d0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333989384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3333989384
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3314094487
Short name T225
Test name
Test status
Simulation time 3430882347 ps
CPU time 37.72 seconds
Started Jul 14 06:54:50 PM PDT 24
Finished Jul 14 06:55:30 PM PDT 24
Peak memory 240368 kb
Host smart-22b06610-fd45-4093-af74-23d4c240240d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314094487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3314094487
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.602140938
Short name T926
Test name
Test status
Simulation time 276434715 ps
CPU time 4.21 seconds
Started Jul 14 06:55:00 PM PDT 24
Finished Jul 14 06:55:06 PM PDT 24
Peak memory 224436 kb
Host smart-cf2aac60-6e2d-49a6-bc27-cf70d4e63130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602140938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.602140938
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.3657596328
Short name T184
Test name
Test status
Simulation time 16559537002 ps
CPU time 122.23 seconds
Started Jul 14 06:54:45 PM PDT 24
Finished Jul 14 06:56:51 PM PDT 24
Peak memory 249256 kb
Host smart-9c4532d6-1fe2-45f3-b2cc-976ea460a8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657596328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.3657596328
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1413177737
Short name T437
Test name
Test status
Simulation time 116761740 ps
CPU time 2.94 seconds
Started Jul 14 06:55:53 PM PDT 24
Finished Jul 14 06:55:58 PM PDT 24
Peak memory 232508 kb
Host smart-59f7a761-aed7-4ac4-831f-a8a8f158382f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413177737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1413177737
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.649656138
Short name T876
Test name
Test status
Simulation time 110125463 ps
CPU time 2.2 seconds
Started Jul 14 06:54:50 PM PDT 24
Finished Jul 14 06:54:54 PM PDT 24
Peak memory 224140 kb
Host smart-08698272-e6bc-43fb-8e42-dd525eadd1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649656138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.649656138
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1976269901
Short name T999
Test name
Test status
Simulation time 5051310410 ps
CPU time 8.9 seconds
Started Jul 14 06:54:43 PM PDT 24
Finished Jul 14 06:54:55 PM PDT 24
Peak memory 232740 kb
Host smart-70728cf8-1894-4b1b-8f3c-37b354581ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976269901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1976269901
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.662533741
Short name T980
Test name
Test status
Simulation time 2708049718 ps
CPU time 9.21 seconds
Started Jul 14 06:54:59 PM PDT 24
Finished Jul 14 06:55:11 PM PDT 24
Peak memory 248888 kb
Host smart-72926fd8-5a09-47b1-b2b9-378993fcbbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662533741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.662533741
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3770464745
Short name T693
Test name
Test status
Simulation time 459971413 ps
CPU time 7.19 seconds
Started Jul 14 06:54:47 PM PDT 24
Finished Jul 14 06:54:58 PM PDT 24
Peak memory 218852 kb
Host smart-cc2f5bef-bcf9-4a6c-989f-fc52b436ca7a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3770464745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3770464745
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1000626259
Short name T74
Test name
Test status
Simulation time 341903230 ps
CPU time 1.06 seconds
Started Jul 14 06:54:37 PM PDT 24
Finished Jul 14 06:54:41 PM PDT 24
Peak memory 235996 kb
Host smart-3993c2c7-c26a-43ae-9e1a-8919af83be80
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000626259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1000626259
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1163251440
Short name T415
Test name
Test status
Simulation time 42049298763 ps
CPU time 252.1 seconds
Started Jul 14 06:55:02 PM PDT 24
Finished Jul 14 06:59:17 PM PDT 24
Peak memory 249260 kb
Host smart-fbb57ed2-f5ca-4776-8f3a-a9c3563a0c25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163251440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1163251440
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.87444501
Short name T706
Test name
Test status
Simulation time 31881022040 ps
CPU time 22.26 seconds
Started Jul 14 06:54:34 PM PDT 24
Finished Jul 14 06:55:00 PM PDT 24
Peak memory 216596 kb
Host smart-9d7b0046-20ea-4c6a-a303-f78551d8f8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87444501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.87444501
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1429855721
Short name T92
Test name
Test status
Simulation time 1835231239 ps
CPU time 6.14 seconds
Started Jul 14 06:54:42 PM PDT 24
Finished Jul 14 06:54:50 PM PDT 24
Peak memory 216244 kb
Host smart-c6f96284-1d0a-4314-9b86-19dfc3e513e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429855721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1429855721
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2634444075
Short name T13
Test name
Test status
Simulation time 35650481 ps
CPU time 0.82 seconds
Started Jul 14 06:54:46 PM PDT 24
Finished Jul 14 06:54:50 PM PDT 24
Peak memory 206800 kb
Host smart-ef0a9c38-3737-4712-866a-815614591c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634444075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2634444075
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.533410018
Short name T400
Test name
Test status
Simulation time 169020258 ps
CPU time 0.94 seconds
Started Jul 14 06:54:40 PM PDT 24
Finished Jul 14 06:54:43 PM PDT 24
Peak memory 206000 kb
Host smart-ead6be79-69a2-4680-8061-2a5a057873de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533410018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.533410018
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1856334458
Short name T592
Test name
Test status
Simulation time 4117652399 ps
CPU time 15.56 seconds
Started Jul 14 06:54:57 PM PDT 24
Finished Jul 14 06:55:14 PM PDT 24
Peak memory 236228 kb
Host smart-1b4cb1d4-9e2a-4597-820f-29f03b47922c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856334458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1856334458
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.560140487
Short name T455
Test name
Test status
Simulation time 15306543 ps
CPU time 0.72 seconds
Started Jul 14 06:56:16 PM PDT 24
Finished Jul 14 06:56:20 PM PDT 24
Peak memory 205856 kb
Host smart-2e179bfd-19c5-4f50-baf4-9e2a5e88b33f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560140487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.560140487
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2479675429
Short name T188
Test name
Test status
Simulation time 630909365 ps
CPU time 5.56 seconds
Started Jul 14 06:56:06 PM PDT 24
Finished Jul 14 06:56:13 PM PDT 24
Peak memory 224424 kb
Host smart-93f6f1f0-9be7-46f7-a64d-0ea092eaef80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479675429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2479675429
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3052069329
Short name T904
Test name
Test status
Simulation time 47879806 ps
CPU time 0.75 seconds
Started Jul 14 06:56:01 PM PDT 24
Finished Jul 14 06:56:04 PM PDT 24
Peak memory 206596 kb
Host smart-14fa40b5-b65d-40ae-ba21-d3a702e5275e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052069329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3052069329
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1252201234
Short name T185
Test name
Test status
Simulation time 348377964 ps
CPU time 5.33 seconds
Started Jul 14 06:56:00 PM PDT 24
Finished Jul 14 06:56:08 PM PDT 24
Peak memory 224544 kb
Host smart-aca1f8ec-6ee8-412e-bc76-165bb0a19a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252201234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1252201234
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.886435735
Short name T141
Test name
Test status
Simulation time 163640988328 ps
CPU time 373.11 seconds
Started Jul 14 06:56:11 PM PDT 24
Finished Jul 14 07:02:25 PM PDT 24
Peak memory 265612 kb
Host smart-d4e855cf-6531-4669-adeb-c253e09fee64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886435735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.886435735
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1697332380
Short name T36
Test name
Test status
Simulation time 7218062539 ps
CPU time 40.58 seconds
Started Jul 14 06:56:10 PM PDT 24
Finished Jul 14 06:56:52 PM PDT 24
Peak memory 257416 kb
Host smart-cd93c2bf-e277-43ff-8395-3b518acc6a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697332380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1697332380
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2100071515
Short name T289
Test name
Test status
Simulation time 889036997 ps
CPU time 7.2 seconds
Started Jul 14 06:55:58 PM PDT 24
Finished Jul 14 06:56:09 PM PDT 24
Peak memory 240868 kb
Host smart-495d7ce7-e703-47e2-ba5b-d5747ad15955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100071515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2100071515
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.972180409
Short name T182
Test name
Test status
Simulation time 292999064 ps
CPU time 9.44 seconds
Started Jul 14 06:56:01 PM PDT 24
Finished Jul 14 06:56:13 PM PDT 24
Peak memory 232664 kb
Host smart-8b67dd24-9646-4c98-a257-a488a71e7305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972180409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds
.972180409
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3149421170
Short name T17
Test name
Test status
Simulation time 774921805 ps
CPU time 6.67 seconds
Started Jul 14 06:56:16 PM PDT 24
Finished Jul 14 06:56:27 PM PDT 24
Peak memory 227476 kb
Host smart-9b684c76-0e9b-4149-b0d0-f48f2c67088f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149421170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3149421170
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1294253762
Short name T808
Test name
Test status
Simulation time 2018347850 ps
CPU time 25.67 seconds
Started Jul 14 06:55:57 PM PDT 24
Finished Jul 14 06:56:26 PM PDT 24
Peak memory 248584 kb
Host smart-5aae6452-2d42-4b1f-b741-13da1efa55cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294253762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1294253762
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2745008157
Short name T854
Test name
Test status
Simulation time 7525423245 ps
CPU time 7.5 seconds
Started Jul 14 06:55:52 PM PDT 24
Finished Jul 14 06:56:01 PM PDT 24
Peak memory 224524 kb
Host smart-fc220089-c476-42e1-8e3e-22113e5ebd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745008157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2745008157
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1165093327
Short name T748
Test name
Test status
Simulation time 32724266407 ps
CPU time 21.11 seconds
Started Jul 14 06:56:16 PM PDT 24
Finished Jul 14 06:56:41 PM PDT 24
Peak memory 248564 kb
Host smart-ce114907-4131-46e9-80f0-4f45fe1c4381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165093327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1165093327
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.4034937025
Short name T637
Test name
Test status
Simulation time 1696623073 ps
CPU time 17.54 seconds
Started Jul 14 06:55:58 PM PDT 24
Finished Jul 14 06:56:19 PM PDT 24
Peak memory 222040 kb
Host smart-f8af191d-9798-4781-bc83-59b2b6599b30
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4034937025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.4034937025
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.474696269
Short name T684
Test name
Test status
Simulation time 9017299055 ps
CPU time 22 seconds
Started Jul 14 06:56:13 PM PDT 24
Finished Jul 14 06:56:38 PM PDT 24
Peak memory 216420 kb
Host smart-9420a4cf-cb9e-480c-9e47-6b6eb817e814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474696269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.474696269
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3447954537
Short name T897
Test name
Test status
Simulation time 2193061690 ps
CPU time 4.44 seconds
Started Jul 14 06:56:12 PM PDT 24
Finished Jul 14 06:56:18 PM PDT 24
Peak memory 216288 kb
Host smart-3b62b22d-6abf-49d6-b653-034309377c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447954537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3447954537
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.898999202
Short name T431
Test name
Test status
Simulation time 40611882 ps
CPU time 0.88 seconds
Started Jul 14 06:56:18 PM PDT 24
Finished Jul 14 06:56:24 PM PDT 24
Peak memory 207044 kb
Host smart-8b77c08b-5c5e-42bf-9a1f-2a060b19d834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898999202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.898999202
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.201943460
Short name T961
Test name
Test status
Simulation time 80411749 ps
CPU time 0.89 seconds
Started Jul 14 06:55:52 PM PDT 24
Finished Jul 14 06:55:55 PM PDT 24
Peak memory 205996 kb
Host smart-2f1748ff-a3c6-4598-8dbd-f74db5a6489f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201943460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.201943460
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1108248888
Short name T472
Test name
Test status
Simulation time 11411666178 ps
CPU time 3.93 seconds
Started Jul 14 06:55:53 PM PDT 24
Finished Jul 14 06:56:00 PM PDT 24
Peak memory 224564 kb
Host smart-d200e35e-19c5-4c8a-8a60-44fd4770d423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108248888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1108248888
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3150860087
Short name T855
Test name
Test status
Simulation time 18452780 ps
CPU time 0.7 seconds
Started Jul 14 06:55:58 PM PDT 24
Finished Jul 14 06:56:01 PM PDT 24
Peak memory 205556 kb
Host smart-a42f659e-ce0b-40c9-b37f-a50541803df7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150860087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3150860087
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.830251762
Short name T454
Test name
Test status
Simulation time 116042610 ps
CPU time 2.63 seconds
Started Jul 14 06:55:57 PM PDT 24
Finished Jul 14 06:56:03 PM PDT 24
Peak memory 232636 kb
Host smart-4a20ab10-4662-48e5-a394-f62e963fd57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830251762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.830251762
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1095663724
Short name T551
Test name
Test status
Simulation time 20712335 ps
CPU time 0.79 seconds
Started Jul 14 06:56:13 PM PDT 24
Finished Jul 14 06:56:16 PM PDT 24
Peak memory 206892 kb
Host smart-28d28908-678c-4142-b9c1-cd2b4ebd34fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095663724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1095663724
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.306528297
Short name T491
Test name
Test status
Simulation time 3775966633 ps
CPU time 34.4 seconds
Started Jul 14 06:56:00 PM PDT 24
Finished Jul 14 06:56:37 PM PDT 24
Peak memory 224660 kb
Host smart-2fec4b1a-c70d-4015-8e62-26c828cbce5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306528297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.306528297
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1913547072
Short name T810
Test name
Test status
Simulation time 1662263054 ps
CPU time 38.03 seconds
Started Jul 14 06:56:01 PM PDT 24
Finished Jul 14 06:56:41 PM PDT 24
Peak memory 251280 kb
Host smart-b84c1d98-d639-48e8-8775-95bb3392caea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913547072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1913547072
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3846742017
Short name T936
Test name
Test status
Simulation time 124589500 ps
CPU time 3.21 seconds
Started Jul 14 06:56:05 PM PDT 24
Finished Jul 14 06:56:09 PM PDT 24
Peak memory 232704 kb
Host smart-5b4c8d84-180d-408c-b02f-34eecfe4c045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846742017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3846742017
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2439307360
Short name T672
Test name
Test status
Simulation time 811626152 ps
CPU time 5.76 seconds
Started Jul 14 06:56:01 PM PDT 24
Finished Jul 14 06:56:09 PM PDT 24
Peak memory 232592 kb
Host smart-cbfc965d-007e-49b1-838e-d9a7273aced1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439307360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2439307360
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3743585940
Short name T856
Test name
Test status
Simulation time 7416084186 ps
CPU time 19.86 seconds
Started Jul 14 06:56:13 PM PDT 24
Finished Jul 14 06:56:35 PM PDT 24
Peak memory 240628 kb
Host smart-a0ea0002-f307-4691-9fe3-ecd45ad09e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743585940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3743585940
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2246353002
Short name T953
Test name
Test status
Simulation time 200396293 ps
CPU time 2.79 seconds
Started Jul 14 06:55:57 PM PDT 24
Finished Jul 14 06:56:03 PM PDT 24
Peak memory 232620 kb
Host smart-270d15cd-82f7-4b2b-88c3-5851278474a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246353002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2246353002
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3858506593
Short name T597
Test name
Test status
Simulation time 1325939453 ps
CPU time 7.54 seconds
Started Jul 14 06:55:58 PM PDT 24
Finished Jul 14 06:56:09 PM PDT 24
Peak memory 232696 kb
Host smart-3a6209e9-c049-4919-b342-34ff491bbe33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858506593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3858506593
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1707399306
Short name T832
Test name
Test status
Simulation time 1347642078 ps
CPU time 11.91 seconds
Started Jul 14 06:56:07 PM PDT 24
Finished Jul 14 06:56:21 PM PDT 24
Peak memory 218896 kb
Host smart-d576024b-c6b0-47e1-a7cc-95d165319549
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1707399306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1707399306
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3889526692
Short name T530
Test name
Test status
Simulation time 1272166635 ps
CPU time 14.14 seconds
Started Jul 14 06:56:18 PM PDT 24
Finished Jul 14 06:56:37 PM PDT 24
Peak memory 216256 kb
Host smart-1ff15e84-c623-42f8-910c-2ec49e712e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889526692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3889526692
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2509683107
Short name T320
Test name
Test status
Simulation time 12582087911 ps
CPU time 18.15 seconds
Started Jul 14 06:56:13 PM PDT 24
Finished Jul 14 06:56:34 PM PDT 24
Peak memory 216328 kb
Host smart-08b2cf7e-fb69-4a93-a8fb-a2930ac377b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509683107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2509683107
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1330708097
Short name T522
Test name
Test status
Simulation time 37832368 ps
CPU time 2.12 seconds
Started Jul 14 06:56:15 PM PDT 24
Finished Jul 14 06:56:20 PM PDT 24
Peak memory 216208 kb
Host smart-52723e55-e2dd-49de-9d6e-d5d3868b0bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330708097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1330708097
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.464315693
Short name T963
Test name
Test status
Simulation time 36894340 ps
CPU time 0.68 seconds
Started Jul 14 06:56:07 PM PDT 24
Finished Jul 14 06:56:09 PM PDT 24
Peak memory 205648 kb
Host smart-5ce3dbb9-2c18-4bd7-9ac6-8149b240c3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464315693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.464315693
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2064652115
Short name T734
Test name
Test status
Simulation time 525001169 ps
CPU time 5.81 seconds
Started Jul 14 06:56:01 PM PDT 24
Finished Jul 14 06:56:09 PM PDT 24
Peak memory 240644 kb
Host smart-31c148a5-c3ba-4be1-bff9-67b6a2f4e6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064652115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2064652115
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3994690628
Short name T427
Test name
Test status
Simulation time 25921562 ps
CPU time 0.72 seconds
Started Jul 14 06:56:15 PM PDT 24
Finished Jul 14 06:56:20 PM PDT 24
Peak memory 204964 kb
Host smart-b012bd4d-56c6-4743-b055-7da953b648fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994690628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3994690628
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.4138638085
Short name T844
Test name
Test status
Simulation time 212953283 ps
CPU time 2.37 seconds
Started Jul 14 06:56:15 PM PDT 24
Finished Jul 14 06:56:21 PM PDT 24
Peak memory 224484 kb
Host smart-e77ee9a0-a765-45b6-af04-00f2fc7fa406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138638085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.4138638085
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1530636994
Short name T779
Test name
Test status
Simulation time 17020111 ps
CPU time 0.79 seconds
Started Jul 14 06:56:10 PM PDT 24
Finished Jul 14 06:56:12 PM PDT 24
Peak memory 206940 kb
Host smart-ba5892ab-4b1b-4603-8310-ee24a5a961fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530636994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1530636994
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3749417189
Short name T539
Test name
Test status
Simulation time 13868366640 ps
CPU time 73.11 seconds
Started Jul 14 06:56:02 PM PDT 24
Finished Jul 14 06:57:17 PM PDT 24
Peak memory 250816 kb
Host smart-ba702d37-658b-4477-a649-c1cfd6a26386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749417189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3749417189
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.176291719
Short name T895
Test name
Test status
Simulation time 58614789701 ps
CPU time 243.46 seconds
Started Jul 14 06:56:13 PM PDT 24
Finished Jul 14 07:00:18 PM PDT 24
Peak memory 257448 kb
Host smart-f027a079-27fe-4fff-a6be-eeb8b8486abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176291719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.176291719
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.386638887
Short name T221
Test name
Test status
Simulation time 283901910150 ps
CPU time 378.09 seconds
Started Jul 14 06:56:10 PM PDT 24
Finished Jul 14 07:02:29 PM PDT 24
Peak memory 254920 kb
Host smart-78a7fc74-3232-4e6c-bc1a-1119f438ef71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386638887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.386638887
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.428631781
Short name T612
Test name
Test status
Simulation time 79455975 ps
CPU time 4 seconds
Started Jul 14 06:56:11 PM PDT 24
Finished Jul 14 06:56:16 PM PDT 24
Peak memory 235052 kb
Host smart-6ec490f8-1470-4171-b52c-c357c0e4660f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428631781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.428631781
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.1073990583
Short name T1000
Test name
Test status
Simulation time 18165005584 ps
CPU time 44.83 seconds
Started Jul 14 06:56:07 PM PDT 24
Finished Jul 14 06:56:53 PM PDT 24
Peak memory 256336 kb
Host smart-24f874d6-b5e4-42ef-ab55-5486dfaf303a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073990583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.1073990583
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1458514332
Short name T650
Test name
Test status
Simulation time 4700935956 ps
CPU time 24.87 seconds
Started Jul 14 06:56:30 PM PDT 24
Finished Jul 14 06:56:58 PM PDT 24
Peak memory 219864 kb
Host smart-5d024b4a-c2f1-4b4b-a5e8-1ebde0b7bf67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458514332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1458514332
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.136792466
Short name T54
Test name
Test status
Simulation time 2136661064 ps
CPU time 30.84 seconds
Started Jul 14 06:56:03 PM PDT 24
Finished Jul 14 06:56:35 PM PDT 24
Peak memory 237960 kb
Host smart-b1ebc6d8-0baa-4ae3-88dc-bf2ce0a5b48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136792466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.136792466
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3553413149
Short name T417
Test name
Test status
Simulation time 540134900 ps
CPU time 3.79 seconds
Started Jul 14 06:55:59 PM PDT 24
Finished Jul 14 06:56:06 PM PDT 24
Peak memory 224452 kb
Host smart-0f67d423-9d12-4b83-af04-37acbd8df75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553413149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3553413149
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.198748593
Short name T248
Test name
Test status
Simulation time 22033492274 ps
CPU time 31.28 seconds
Started Jul 14 06:56:01 PM PDT 24
Finished Jul 14 06:56:34 PM PDT 24
Peak memory 240336 kb
Host smart-c36011ed-da63-45b6-b38d-e2c029bc8b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198748593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.198748593
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2816747139
Short name T917
Test name
Test status
Simulation time 129955972 ps
CPU time 4.73 seconds
Started Jul 14 06:56:05 PM PDT 24
Finished Jul 14 06:56:10 PM PDT 24
Peak memory 224100 kb
Host smart-3697e1f1-a2ef-4dc5-84d8-99bd6106b9e5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2816747139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2816747139
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2533668571
Short name T251
Test name
Test status
Simulation time 58481984085 ps
CPU time 493.59 seconds
Started Jul 14 06:56:08 PM PDT 24
Finished Jul 14 07:04:23 PM PDT 24
Peak memory 258200 kb
Host smart-7515c199-a7bf-4ab6-80fb-d57c2f68e71c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533668571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2533668571
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2425078860
Short name T889
Test name
Test status
Simulation time 9475576805 ps
CPU time 48.73 seconds
Started Jul 14 06:56:12 PM PDT 24
Finished Jul 14 06:57:03 PM PDT 24
Peak memory 216364 kb
Host smart-6ef00e92-3a79-4bf3-8ed5-302c064488d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425078860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2425078860
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3974437130
Short name T947
Test name
Test status
Simulation time 558321286 ps
CPU time 3.37 seconds
Started Jul 14 06:56:08 PM PDT 24
Finished Jul 14 06:56:13 PM PDT 24
Peak memory 216264 kb
Host smart-2b5acc25-180d-4ed9-9aca-7b3b28ec9853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974437130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3974437130
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1874481870
Short name T566
Test name
Test status
Simulation time 16843931 ps
CPU time 0.87 seconds
Started Jul 14 06:56:04 PM PDT 24
Finished Jul 14 06:56:05 PM PDT 24
Peak memory 207008 kb
Host smart-7dfcd964-cdf8-4ff1-b251-3e41f1238829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874481870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1874481870
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1764925760
Short name T301
Test name
Test status
Simulation time 152108764 ps
CPU time 0.87 seconds
Started Jul 14 06:56:14 PM PDT 24
Finished Jul 14 06:56:17 PM PDT 24
Peak memory 206472 kb
Host smart-b0c2a3b6-c71e-4218-97bb-935a0cf6187d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764925760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1764925760
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3780954388
Short name T58
Test name
Test status
Simulation time 72669081 ps
CPU time 2.6 seconds
Started Jul 14 06:56:14 PM PDT 24
Finished Jul 14 06:56:18 PM PDT 24
Peak memory 234324 kb
Host smart-c29f35f0-f8d8-4521-a63b-79c998c214eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780954388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3780954388
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3445696450
Short name T713
Test name
Test status
Simulation time 63140050 ps
CPU time 0.72 seconds
Started Jul 14 06:56:18 PM PDT 24
Finished Jul 14 06:56:24 PM PDT 24
Peak memory 205540 kb
Host smart-e3015f7c-6063-4e5a-9df1-21551976022a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445696450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3445696450
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1575316841
Short name T783
Test name
Test status
Simulation time 504375217 ps
CPU time 3.74 seconds
Started Jul 14 06:56:17 PM PDT 24
Finished Jul 14 06:56:25 PM PDT 24
Peak memory 232664 kb
Host smart-bfcee957-c396-4a61-be91-25ecdc7f9ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575316841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1575316841
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2435600903
Short name T521
Test name
Test status
Simulation time 201029737 ps
CPU time 0.77 seconds
Started Jul 14 06:56:15 PM PDT 24
Finished Jul 14 06:56:19 PM PDT 24
Peak memory 206636 kb
Host smart-5057d00f-eedf-439b-b768-6ffc7ca21ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435600903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2435600903
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1374307886
Short name T411
Test name
Test status
Simulation time 9208293446 ps
CPU time 79.55 seconds
Started Jul 14 06:56:00 PM PDT 24
Finished Jul 14 06:57:22 PM PDT 24
Peak memory 249212 kb
Host smart-c2f8fc4c-c65b-4960-a6e0-4f1bbdbf8496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374307886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1374307886
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.4104041919
Short name T297
Test name
Test status
Simulation time 14971580715 ps
CPU time 52.89 seconds
Started Jul 14 06:56:17 PM PDT 24
Finished Jul 14 06:57:14 PM PDT 24
Peak memory 249272 kb
Host smart-627f7f0e-42d2-4600-8711-d42dc82c094d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104041919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.4104041919
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1497811860
Short name T199
Test name
Test status
Simulation time 375235073028 ps
CPU time 339.73 seconds
Started Jul 14 06:56:19 PM PDT 24
Finished Jul 14 07:02:05 PM PDT 24
Peak memory 257360 kb
Host smart-eda63c36-2946-4a5a-bea2-bbdad242e8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497811860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1497811860
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2496430631
Short name T388
Test name
Test status
Simulation time 331485310 ps
CPU time 3.74 seconds
Started Jul 14 06:56:17 PM PDT 24
Finished Jul 14 06:56:26 PM PDT 24
Peak memory 224484 kb
Host smart-41ff3c8f-1e42-4fb3-b507-27494cf1ed56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496430631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2496430631
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.2414945893
Short name T823
Test name
Test status
Simulation time 11580708036 ps
CPU time 88.27 seconds
Started Jul 14 06:56:24 PM PDT 24
Finished Jul 14 06:57:58 PM PDT 24
Peak memory 249196 kb
Host smart-e3c249f8-d60a-4ef5-864d-bb4f24348ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414945893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.2414945893
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1672304919
Short name T230
Test name
Test status
Simulation time 983330926 ps
CPU time 9.25 seconds
Started Jul 14 06:56:13 PM PDT 24
Finished Jul 14 06:56:24 PM PDT 24
Peak memory 224464 kb
Host smart-e4579a3d-a970-491a-bc85-19232f02613e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672304919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1672304919
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3705818779
Short name T741
Test name
Test status
Simulation time 20806075313 ps
CPU time 42.16 seconds
Started Jul 14 06:56:01 PM PDT 24
Finished Jul 14 06:56:45 PM PDT 24
Peak memory 240992 kb
Host smart-6f56199b-20f4-4a49-ae97-945a68054962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705818779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3705818779
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.708288538
Short name T587
Test name
Test status
Simulation time 557719204 ps
CPU time 5.26 seconds
Started Jul 14 06:56:23 PM PDT 24
Finished Jul 14 06:56:33 PM PDT 24
Peak memory 232636 kb
Host smart-d81fc3ee-4db6-47b9-b488-c80d5a4d1dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708288538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.708288538
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.945993755
Short name T207
Test name
Test status
Simulation time 17693087241 ps
CPU time 14.01 seconds
Started Jul 14 06:56:11 PM PDT 24
Finished Jul 14 06:56:26 PM PDT 24
Peak memory 232796 kb
Host smart-485feb72-b5d7-4c46-87b1-cc44fc004f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945993755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.945993755
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1039049427
Short name T678
Test name
Test status
Simulation time 3780968934 ps
CPU time 9.46 seconds
Started Jul 14 06:56:00 PM PDT 24
Finished Jul 14 06:56:12 PM PDT 24
Peak memory 222784 kb
Host smart-519b9e93-f941-4a7b-8621-66a7e7b12ccb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1039049427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1039049427
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.46190440
Short name T22
Test name
Test status
Simulation time 217545856 ps
CPU time 1.05 seconds
Started Jul 14 06:56:02 PM PDT 24
Finished Jul 14 06:56:04 PM PDT 24
Peak memory 207016 kb
Host smart-46efb9f3-a893-4437-8dbb-95d5d4e2f3a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46190440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stress
_all.46190440
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.190905661
Short name T611
Test name
Test status
Simulation time 462223506 ps
CPU time 7.92 seconds
Started Jul 14 06:56:28 PM PDT 24
Finished Jul 14 06:56:40 PM PDT 24
Peak memory 219148 kb
Host smart-359d5a7b-8786-4457-b17a-ec1641cdcd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190905661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.190905661
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1054655346
Short name T28
Test name
Test status
Simulation time 483336154 ps
CPU time 1.66 seconds
Started Jul 14 06:56:02 PM PDT 24
Finished Jul 14 06:56:05 PM PDT 24
Peak memory 207844 kb
Host smart-20d181c8-27ce-4b3d-bebc-81fe5182964c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054655346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1054655346
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3809165512
Short name T300
Test name
Test status
Simulation time 205940529 ps
CPU time 2.06 seconds
Started Jul 14 06:56:18 PM PDT 24
Finished Jul 14 06:56:25 PM PDT 24
Peak memory 216180 kb
Host smart-ae462626-c786-411d-8649-c654e5a2f3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809165512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3809165512
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2166249767
Short name T466
Test name
Test status
Simulation time 149675065 ps
CPU time 1.05 seconds
Started Jul 14 06:56:23 PM PDT 24
Finished Jul 14 06:56:29 PM PDT 24
Peak memory 205984 kb
Host smart-f7d5b1f1-a3e0-4a36-bd23-88cabbb88325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166249767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2166249767
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2797874057
Short name T849
Test name
Test status
Simulation time 626466274 ps
CPU time 2.22 seconds
Started Jul 14 06:56:13 PM PDT 24
Finished Jul 14 06:56:18 PM PDT 24
Peak memory 224012 kb
Host smart-8d018b75-4cf5-4c8c-b99f-7acfc9674e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797874057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2797874057
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2447852307
Short name T743
Test name
Test status
Simulation time 44236405 ps
CPU time 0.71 seconds
Started Jul 14 06:56:16 PM PDT 24
Finished Jul 14 06:56:21 PM PDT 24
Peak memory 205864 kb
Host smart-e0a15cf3-fcf6-4682-98af-583a52aa1384
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447852307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2447852307
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1677752027
Short name T502
Test name
Test status
Simulation time 1838666655 ps
CPU time 6.7 seconds
Started Jul 14 06:56:21 PM PDT 24
Finished Jul 14 06:56:34 PM PDT 24
Peak memory 232632 kb
Host smart-3b06b1ed-6f7a-440b-a2af-498fa0968165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677752027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1677752027
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1166637373
Short name T369
Test name
Test status
Simulation time 35833266 ps
CPU time 0.79 seconds
Started Jul 14 06:56:17 PM PDT 24
Finished Jul 14 06:56:23 PM PDT 24
Peak memory 206604 kb
Host smart-5854cd39-a30e-40a7-8fb8-f8d96576737f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166637373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1166637373
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1885650001
Short name T544
Test name
Test status
Simulation time 21002864854 ps
CPU time 131.36 seconds
Started Jul 14 06:56:11 PM PDT 24
Finished Jul 14 06:58:23 PM PDT 24
Peak memory 237416 kb
Host smart-b197de67-5929-4270-ab17-42fb08b6f4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885650001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1885650001
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.274297640
Short name T993
Test name
Test status
Simulation time 40578120840 ps
CPU time 151.44 seconds
Started Jul 14 06:56:20 PM PDT 24
Finished Jul 14 06:58:57 PM PDT 24
Peak memory 268568 kb
Host smart-eb12b3bd-900a-4283-890c-bc5819eceb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274297640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.274297640
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1728616374
Short name T595
Test name
Test status
Simulation time 33718279569 ps
CPU time 47.64 seconds
Started Jul 14 06:56:16 PM PDT 24
Finished Jul 14 06:57:08 PM PDT 24
Peak memory 250288 kb
Host smart-0653598c-f26f-49e3-b4db-d1d2c1082c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728616374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1728616374
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.4188851124
Short name T166
Test name
Test status
Simulation time 41186052 ps
CPU time 2.6 seconds
Started Jul 14 06:56:16 PM PDT 24
Finished Jul 14 06:56:22 PM PDT 24
Peak memory 224408 kb
Host smart-ccc0c04c-6547-42b9-8069-ee1f48599ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188851124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.4188851124
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3028978631
Short name T633
Test name
Test status
Simulation time 11769721720 ps
CPU time 41.48 seconds
Started Jul 14 06:56:18 PM PDT 24
Finished Jul 14 06:57:05 PM PDT 24
Peak memory 251596 kb
Host smart-aa82ee9f-56ae-4eb0-a5b1-6b39334b8e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028978631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3028978631
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1167760753
Short name T608
Test name
Test status
Simulation time 2847096188 ps
CPU time 6.88 seconds
Started Jul 14 06:56:11 PM PDT 24
Finished Jul 14 06:56:19 PM PDT 24
Peak memory 224620 kb
Host smart-78ea8bd8-c366-4b8a-abc2-34b852d0907d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167760753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1167760753
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2949253842
Short name T606
Test name
Test status
Simulation time 2389862519 ps
CPU time 23.73 seconds
Started Jul 14 06:56:06 PM PDT 24
Finished Jul 14 06:56:30 PM PDT 24
Peak memory 240676 kb
Host smart-6927bfcd-d3d5-43ce-b783-e158c9a6bfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949253842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2949253842
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.912116056
Short name T761
Test name
Test status
Simulation time 102745549 ps
CPU time 3.35 seconds
Started Jul 14 06:56:13 PM PDT 24
Finished Jul 14 06:56:19 PM PDT 24
Peak memory 232700 kb
Host smart-9dab5188-6207-472e-b37a-57055b1cbf49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912116056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.912116056
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1503294740
Short name T1008
Test name
Test status
Simulation time 287495732 ps
CPU time 2.96 seconds
Started Jul 14 06:56:18 PM PDT 24
Finished Jul 14 06:56:26 PM PDT 24
Peak memory 232664 kb
Host smart-9c3709b5-863c-4051-8c1d-7ddc8356f6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503294740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1503294740
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1776048641
Short name T796
Test name
Test status
Simulation time 734029900 ps
CPU time 4.45 seconds
Started Jul 14 06:56:30 PM PDT 24
Finished Jul 14 06:56:37 PM PDT 24
Peak memory 222316 kb
Host smart-b6016f14-020f-443b-8cac-981de348bace
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1776048641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1776048641
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1018926373
Short name T276
Test name
Test status
Simulation time 140542127066 ps
CPU time 403.87 seconds
Started Jul 14 06:56:07 PM PDT 24
Finished Jul 14 07:02:53 PM PDT 24
Peak memory 265656 kb
Host smart-2f978d51-70fd-420d-81e7-cd8ef39de4fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018926373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1018926373
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3504220228
Short name T133
Test name
Test status
Simulation time 13571537775 ps
CPU time 18.67 seconds
Started Jul 14 06:56:09 PM PDT 24
Finished Jul 14 06:56:28 PM PDT 24
Peak memory 216496 kb
Host smart-76e1936d-27ba-49e9-9bc8-0f19e21ca4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504220228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3504220228
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3197602905
Short name T448
Test name
Test status
Simulation time 5907260839 ps
CPU time 6.69 seconds
Started Jul 14 06:56:15 PM PDT 24
Finished Jul 14 06:56:25 PM PDT 24
Peak memory 216384 kb
Host smart-00eb4344-28db-4f12-941e-f2a5dee45e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197602905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3197602905
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.62263576
Short name T456
Test name
Test status
Simulation time 169098827 ps
CPU time 0.98 seconds
Started Jul 14 06:56:13 PM PDT 24
Finished Jul 14 06:56:16 PM PDT 24
Peak memory 207892 kb
Host smart-336de0a9-9529-4c83-94f2-9c1e0c85450a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62263576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.62263576
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1341827431
Short name T579
Test name
Test status
Simulation time 51331774 ps
CPU time 0.82 seconds
Started Jul 14 06:56:14 PM PDT 24
Finished Jul 14 06:56:17 PM PDT 24
Peak memory 205972 kb
Host smart-4e74191c-89c3-44a4-91cd-a1c8a16c4d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341827431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1341827431
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2808745834
Short name T581
Test name
Test status
Simulation time 1277697515 ps
CPU time 10.93 seconds
Started Jul 14 06:56:18 PM PDT 24
Finished Jul 14 06:56:34 PM PDT 24
Peak memory 232676 kb
Host smart-189f8fc2-c006-49f5-8d1b-035c316b2df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808745834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2808745834
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2874072282
Short name T483
Test name
Test status
Simulation time 17508244 ps
CPU time 0.68 seconds
Started Jul 14 06:56:25 PM PDT 24
Finished Jul 14 06:56:31 PM PDT 24
Peak memory 205520 kb
Host smart-5ebf068c-e520-4e84-896d-ed966eebd790
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874072282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2874072282
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1471978564
Short name T868
Test name
Test status
Simulation time 38330505 ps
CPU time 2.63 seconds
Started Jul 14 06:56:15 PM PDT 24
Finished Jul 14 06:56:21 PM PDT 24
Peak memory 232632 kb
Host smart-9d726675-a932-4cae-9002-bdc46e4aa165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471978564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1471978564
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3817273669
Short name T337
Test name
Test status
Simulation time 15936248 ps
CPU time 0.77 seconds
Started Jul 14 06:56:21 PM PDT 24
Finished Jul 14 06:56:27 PM PDT 24
Peak memory 206608 kb
Host smart-39511997-6770-4415-b596-bb09840b1c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817273669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3817273669
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3917683218
Short name T817
Test name
Test status
Simulation time 1167203402 ps
CPU time 18.55 seconds
Started Jul 14 06:56:16 PM PDT 24
Finished Jul 14 06:56:38 PM PDT 24
Peak memory 238480 kb
Host smart-62964ba5-04ce-4173-87fa-9918d02d0c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917683218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3917683218
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.4248182109
Short name T644
Test name
Test status
Simulation time 3075453041 ps
CPU time 49.44 seconds
Started Jul 14 06:56:25 PM PDT 24
Finished Jul 14 06:57:20 PM PDT 24
Peak memory 250236 kb
Host smart-5bb76819-7cf0-48d1-9d01-a32798c82dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248182109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.4248182109
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2700577707
Short name T813
Test name
Test status
Simulation time 95411762290 ps
CPU time 443.18 seconds
Started Jul 14 06:56:21 PM PDT 24
Finished Jul 14 07:03:49 PM PDT 24
Peak memory 265652 kb
Host smart-f345bbdf-d2ca-4775-b0c5-54dd10409c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700577707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2700577707
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.4170547793
Short name T629
Test name
Test status
Simulation time 1144501327 ps
CPU time 11.46 seconds
Started Jul 14 06:56:26 PM PDT 24
Finished Jul 14 06:56:42 PM PDT 24
Peak memory 232684 kb
Host smart-89af332d-8104-4193-af4e-d8420aa39468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170547793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.4170547793
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3803845713
Short name T885
Test name
Test status
Simulation time 1495397379 ps
CPU time 8.67 seconds
Started Jul 14 06:56:17 PM PDT 24
Finished Jul 14 06:56:30 PM PDT 24
Peak memory 224432 kb
Host smart-6db2613f-897d-4207-8849-f01948d285f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803845713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3803845713
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3100936023
Short name T827
Test name
Test status
Simulation time 35132920 ps
CPU time 1.9 seconds
Started Jul 14 06:56:10 PM PDT 24
Finished Jul 14 06:56:13 PM PDT 24
Peak memory 224132 kb
Host smart-b778833e-a26c-4178-a1a3-0a72ff997193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100936023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3100936023
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2891086649
Short name T275
Test name
Test status
Simulation time 7506095887 ps
CPU time 17.13 seconds
Started Jul 14 06:56:25 PM PDT 24
Finished Jul 14 06:56:47 PM PDT 24
Peak memory 234192 kb
Host smart-998d1c62-f07f-4345-a44c-807a33464683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891086649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2891086649
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3872422527
Short name T615
Test name
Test status
Simulation time 938902274 ps
CPU time 7.44 seconds
Started Jul 14 06:56:12 PM PDT 24
Finished Jul 14 06:56:21 PM PDT 24
Peak memory 240700 kb
Host smart-e775ed96-19aa-4a3e-b2a1-8da9f680bb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872422527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3872422527
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1197874964
Short name T735
Test name
Test status
Simulation time 903723920 ps
CPU time 11.75 seconds
Started Jul 14 06:56:18 PM PDT 24
Finished Jul 14 06:56:36 PM PDT 24
Peak memory 223080 kb
Host smart-1a01ca71-baa3-4e2d-85db-7025914d32e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1197874964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1197874964
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3555450043
Short name T535
Test name
Test status
Simulation time 79104005 ps
CPU time 1.03 seconds
Started Jul 14 06:56:18 PM PDT 24
Finished Jul 14 06:56:24 PM PDT 24
Peak memory 207644 kb
Host smart-c0e44db3-2b8f-44de-a71a-e31e52611e9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555450043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3555450043
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.109930636
Short name T373
Test name
Test status
Simulation time 5565698165 ps
CPU time 13.01 seconds
Started Jul 14 06:56:22 PM PDT 24
Finished Jul 14 06:56:41 PM PDT 24
Peak memory 216320 kb
Host smart-e2f0bf08-18b9-4619-8ac6-a4d39d299e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109930636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.109930636
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2169000018
Short name T412
Test name
Test status
Simulation time 11645622 ps
CPU time 0.68 seconds
Started Jul 14 06:56:20 PM PDT 24
Finished Jul 14 06:56:26 PM PDT 24
Peak memory 205692 kb
Host smart-8648e424-abd5-47fc-a5d0-ea5c45d99995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169000018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2169000018
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3098009216
Short name T442
Test name
Test status
Simulation time 382447399 ps
CPU time 1 seconds
Started Jul 14 06:56:21 PM PDT 24
Finished Jul 14 06:56:27 PM PDT 24
Peak memory 207880 kb
Host smart-f1bed549-2232-4d02-a8fe-20f7cf71d53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098009216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3098009216
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3951273299
Short name T709
Test name
Test status
Simulation time 109048067 ps
CPU time 0.92 seconds
Started Jul 14 06:56:17 PM PDT 24
Finished Jul 14 06:56:22 PM PDT 24
Peak memory 205976 kb
Host smart-76e65e2d-3c83-4c36-8a79-7ea291d060bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951273299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3951273299
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2155259338
Short name T543
Test name
Test status
Simulation time 7765693391 ps
CPU time 5.1 seconds
Started Jul 14 06:56:02 PM PDT 24
Finished Jul 14 06:56:09 PM PDT 24
Peak memory 232868 kb
Host smart-19e68207-b7f8-4d9a-b934-dd03f8d87ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155259338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2155259338
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.4199974394
Short name T364
Test name
Test status
Simulation time 18958378 ps
CPU time 0.78 seconds
Started Jul 14 06:56:21 PM PDT 24
Finished Jul 14 06:56:28 PM PDT 24
Peak memory 205540 kb
Host smart-9644782a-e872-4653-946e-54220bccb496
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199974394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
4199974394
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3874952756
Short name T669
Test name
Test status
Simulation time 918049267 ps
CPU time 5.64 seconds
Started Jul 14 06:56:17 PM PDT 24
Finished Jul 14 06:56:27 PM PDT 24
Peak memory 232644 kb
Host smart-c2d17992-2085-4692-afab-d96c49665a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874952756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3874952756
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2599988432
Short name T833
Test name
Test status
Simulation time 14572072 ps
CPU time 0.79 seconds
Started Jul 14 06:56:18 PM PDT 24
Finished Jul 14 06:56:25 PM PDT 24
Peak memory 206556 kb
Host smart-10097f92-8690-4acd-b0ef-cec223e9fa92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599988432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2599988432
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3473022258
Short name T171
Test name
Test status
Simulation time 12782939592 ps
CPU time 63.98 seconds
Started Jul 14 06:56:26 PM PDT 24
Finished Jul 14 06:57:35 PM PDT 24
Peak memory 249292 kb
Host smart-4b10b357-e20c-4a10-866f-784da0437817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473022258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3473022258
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3648241130
Short name T384
Test name
Test status
Simulation time 12627666489 ps
CPU time 93.09 seconds
Started Jul 14 06:56:15 PM PDT 24
Finished Jul 14 06:57:51 PM PDT 24
Peak memory 249276 kb
Host smart-5fceda06-6102-469b-b7a4-1a86e17f9066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648241130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3648241130
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1677488552
Short name T805
Test name
Test status
Simulation time 8558679264 ps
CPU time 18.86 seconds
Started Jul 14 06:56:15 PM PDT 24
Finished Jul 14 06:56:38 PM PDT 24
Peak memory 232772 kb
Host smart-89368552-1a27-4d39-9f6a-ebbf424d155f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677488552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1677488552
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.2794510380
Short name T449
Test name
Test status
Simulation time 8180681393 ps
CPU time 49.18 seconds
Started Jul 14 06:56:14 PM PDT 24
Finished Jul 14 06:57:06 PM PDT 24
Peak memory 257348 kb
Host smart-687b0334-c5b1-41a1-8c95-31cd37abc17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794510380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.2794510380
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1534116078
Short name T977
Test name
Test status
Simulation time 7761016201 ps
CPU time 18.57 seconds
Started Jul 14 06:56:14 PM PDT 24
Finished Jul 14 06:56:35 PM PDT 24
Peak memory 232776 kb
Host smart-5119bbd6-ef67-4eea-badb-61feec8e32dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534116078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1534116078
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3932468727
Short name T503
Test name
Test status
Simulation time 5659974320 ps
CPU time 21.63 seconds
Started Jul 14 06:56:25 PM PDT 24
Finished Jul 14 06:56:52 PM PDT 24
Peak memory 224608 kb
Host smart-8f1e3fa1-7e1a-449f-8330-565493e57ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932468727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3932468727
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2113317919
Short name T252
Test name
Test status
Simulation time 1905754222 ps
CPU time 7.52 seconds
Started Jul 14 06:56:17 PM PDT 24
Finished Jul 14 06:56:28 PM PDT 24
Peak memory 232624 kb
Host smart-96b11926-1463-4663-8e16-982ae0c8ce47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113317919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2113317919
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.737278191
Short name T879
Test name
Test status
Simulation time 1878337883 ps
CPU time 4.91 seconds
Started Jul 14 06:56:20 PM PDT 24
Finished Jul 14 06:56:31 PM PDT 24
Peak memory 232632 kb
Host smart-e6e0b62a-4514-43ab-8f6f-3cfe14891e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737278191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.737278191
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2981483446
Short name T586
Test name
Test status
Simulation time 798357257 ps
CPU time 3.72 seconds
Started Jul 14 06:56:17 PM PDT 24
Finished Jul 14 06:56:25 PM PDT 24
Peak memory 219988 kb
Host smart-cfc47dcc-a38d-4536-827c-366ff64a8fd6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2981483446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2981483446
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2878773319
Short name T161
Test name
Test status
Simulation time 121630549559 ps
CPU time 602.17 seconds
Started Jul 14 06:56:19 PM PDT 24
Finished Jul 14 07:06:27 PM PDT 24
Peak memory 282044 kb
Host smart-b23ae7c7-673c-433a-95dd-859978463042
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878773319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2878773319
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3242660767
Short name T631
Test name
Test status
Simulation time 3975054907 ps
CPU time 21.51 seconds
Started Jul 14 06:56:24 PM PDT 24
Finished Jul 14 06:56:51 PM PDT 24
Peak memory 216424 kb
Host smart-2446021c-e7c7-4089-a06d-0700c5ac02cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242660767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3242660767
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1391155040
Short name T978
Test name
Test status
Simulation time 5692345563 ps
CPU time 19.85 seconds
Started Jul 14 06:56:21 PM PDT 24
Finished Jul 14 06:56:46 PM PDT 24
Peak memory 216396 kb
Host smart-4608994b-e15c-47ac-965b-e87b2d172e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391155040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1391155040
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2735926942
Short name T547
Test name
Test status
Simulation time 51514746 ps
CPU time 1.03 seconds
Started Jul 14 06:56:16 PM PDT 24
Finished Jul 14 06:56:21 PM PDT 24
Peak memory 207036 kb
Host smart-11d265bb-9733-45aa-97b0-6dfb9db432be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735926942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2735926942
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.44600242
Short name T826
Test name
Test status
Simulation time 36246575 ps
CPU time 0.72 seconds
Started Jul 14 06:56:16 PM PDT 24
Finished Jul 14 06:56:21 PM PDT 24
Peak memory 205972 kb
Host smart-b253a23f-18ec-4061-a436-7d38acc43d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44600242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.44600242
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3106581139
Short name T974
Test name
Test status
Simulation time 828752581 ps
CPU time 9.83 seconds
Started Jul 14 06:56:13 PM PDT 24
Finished Jul 14 06:56:25 PM PDT 24
Peak memory 232756 kb
Host smart-de8100b4-c907-4c6e-b0e4-60bdd2495f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106581139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3106581139
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2367210801
Short name T528
Test name
Test status
Simulation time 140796883 ps
CPU time 0.7 seconds
Started Jul 14 06:56:12 PM PDT 24
Finished Jul 14 06:56:14 PM PDT 24
Peak memory 205840 kb
Host smart-21c67e08-d36a-4cab-9d6d-8b50da0da423
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367210801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2367210801
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2931817766
Short name T687
Test name
Test status
Simulation time 13520118066 ps
CPU time 31.63 seconds
Started Jul 14 06:56:24 PM PDT 24
Finished Jul 14 06:57:01 PM PDT 24
Peak memory 232740 kb
Host smart-16da95e6-1bda-40b2-a6f4-0db331f4c98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931817766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2931817766
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3162398418
Short name T764
Test name
Test status
Simulation time 27844169 ps
CPU time 0.8 seconds
Started Jul 14 06:56:08 PM PDT 24
Finished Jul 14 06:56:10 PM PDT 24
Peak memory 206880 kb
Host smart-0386844e-91bc-4a03-87d4-a6e5cc8772db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162398418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3162398418
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.4032500970
Short name T670
Test name
Test status
Simulation time 2172104196 ps
CPU time 54.91 seconds
Started Jul 14 06:56:20 PM PDT 24
Finished Jul 14 06:57:21 PM PDT 24
Peak memory 257356 kb
Host smart-b5613f4d-700a-41e5-ad4d-2afb87c694cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032500970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.4032500970
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1652534746
Short name T580
Test name
Test status
Simulation time 180869526 ps
CPU time 2.48 seconds
Started Jul 14 06:56:22 PM PDT 24
Finished Jul 14 06:56:31 PM PDT 24
Peak memory 224480 kb
Host smart-af477931-19c6-4c8d-9896-0367549687c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652534746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1652534746
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.3769074668
Short name T602
Test name
Test status
Simulation time 23529461280 ps
CPU time 180.52 seconds
Started Jul 14 06:56:18 PM PDT 24
Finished Jul 14 06:59:24 PM PDT 24
Peak memory 255712 kb
Host smart-91914d32-9e42-4cbb-8969-b66cb92b398d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769074668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.3769074668
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3237854376
Short name T242
Test name
Test status
Simulation time 4720310822 ps
CPU time 21.22 seconds
Started Jul 14 06:56:35 PM PDT 24
Finished Jul 14 06:56:57 PM PDT 24
Peak memory 224624 kb
Host smart-34200917-2b83-4b74-8378-080f16e5e6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237854376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3237854376
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1972443800
Short name T229
Test name
Test status
Simulation time 5633142401 ps
CPU time 37.16 seconds
Started Jul 14 06:56:22 PM PDT 24
Finished Jul 14 06:57:05 PM PDT 24
Peak memory 249192 kb
Host smart-1a4bf2ff-cfb5-4fbf-b6ca-a19900438d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972443800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1972443800
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.645119140
Short name T645
Test name
Test status
Simulation time 865510077 ps
CPU time 4.36 seconds
Started Jul 14 06:56:33 PM PDT 24
Finished Jul 14 06:56:39 PM PDT 24
Peak memory 232620 kb
Host smart-75a189ea-65d4-4c16-a345-a883ad7863a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645119140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.645119140
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3507717402
Short name T79
Test name
Test status
Simulation time 2220851294 ps
CPU time 7.31 seconds
Started Jul 14 06:56:17 PM PDT 24
Finished Jul 14 06:56:29 PM PDT 24
Peak memory 240512 kb
Host smart-8c58171c-8fa6-453a-b11d-bba21c5e012d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507717402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3507717402
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1303998667
Short name T594
Test name
Test status
Simulation time 296756697 ps
CPU time 3.62 seconds
Started Jul 14 06:56:13 PM PDT 24
Finished Jul 14 06:56:19 PM PDT 24
Peak memory 223136 kb
Host smart-3e8c6be1-aa77-4e8c-b8fb-b26600a44f7c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1303998667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1303998667
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2963011626
Short name T699
Test name
Test status
Simulation time 32395001591 ps
CPU time 146.12 seconds
Started Jul 14 06:56:29 PM PDT 24
Finished Jul 14 06:58:59 PM PDT 24
Peak memory 273564 kb
Host smart-4b6c9755-f833-473b-aee7-0ca4579c3226
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963011626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2963011626
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1975758022
Short name T8
Test name
Test status
Simulation time 31666858 ps
CPU time 0.72 seconds
Started Jul 14 06:56:21 PM PDT 24
Finished Jul 14 06:56:28 PM PDT 24
Peak memory 206024 kb
Host smart-748bb051-1265-48f7-b99f-3cc335560f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975758022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1975758022
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.939380848
Short name T352
Test name
Test status
Simulation time 44952475 ps
CPU time 0.97 seconds
Started Jul 14 06:56:18 PM PDT 24
Finished Jul 14 06:56:25 PM PDT 24
Peak memory 206604 kb
Host smart-76780570-a0f2-4ec1-b57e-9c5f038996f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939380848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.939380848
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.413264913
Short name T846
Test name
Test status
Simulation time 57238956 ps
CPU time 1.35 seconds
Started Jul 14 06:56:20 PM PDT 24
Finished Jul 14 06:56:27 PM PDT 24
Peak memory 216272 kb
Host smart-790b3be3-48b3-4a03-ba00-0deaacda4e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413264913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.413264913
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1744922539
Short name T717
Test name
Test status
Simulation time 41616596 ps
CPU time 0.74 seconds
Started Jul 14 06:56:17 PM PDT 24
Finished Jul 14 06:56:23 PM PDT 24
Peak memory 205976 kb
Host smart-99426233-1809-4911-a869-cf9dfb09db4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744922539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1744922539
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1741615143
Short name T896
Test name
Test status
Simulation time 9285926550 ps
CPU time 14.8 seconds
Started Jul 14 06:56:25 PM PDT 24
Finished Jul 14 06:56:45 PM PDT 24
Peak memory 224588 kb
Host smart-705b4e42-545b-4eec-b7ed-3f61e34d674f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741615143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1741615143
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3979889765
Short name T614
Test name
Test status
Simulation time 120993265 ps
CPU time 0.74 seconds
Started Jul 14 06:56:22 PM PDT 24
Finished Jul 14 06:56:28 PM PDT 24
Peak memory 204968 kb
Host smart-5fb7dfac-9d16-4d33-aa1d-c598f2c9a552
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979889765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3979889765
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2084727723
Short name T736
Test name
Test status
Simulation time 34624240 ps
CPU time 2.54 seconds
Started Jul 14 06:56:26 PM PDT 24
Finished Jul 14 06:56:33 PM PDT 24
Peak memory 232664 kb
Host smart-4673631d-d6a5-46e9-8bdc-410b0eb2ed31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084727723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2084727723
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3987763636
Short name T584
Test name
Test status
Simulation time 42724312 ps
CPU time 0.75 seconds
Started Jul 14 06:56:18 PM PDT 24
Finished Jul 14 06:56:25 PM PDT 24
Peak memory 206956 kb
Host smart-18d16cf4-00d9-4e5a-9800-8b9a202770e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987763636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3987763636
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.158840317
Short name T643
Test name
Test status
Simulation time 29362896887 ps
CPU time 234.74 seconds
Started Jul 14 06:56:24 PM PDT 24
Finished Jul 14 07:00:24 PM PDT 24
Peak memory 264832 kb
Host smart-bd85fc6b-0e00-46b9-b948-316d5c0a929b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158840317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.158840317
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.4160710024
Short name T285
Test name
Test status
Simulation time 655054242 ps
CPU time 14.79 seconds
Started Jul 14 06:56:19 PM PDT 24
Finished Jul 14 06:56:39 PM PDT 24
Peak memory 234200 kb
Host smart-cbe7a51c-16d4-4e85-8d66-d5056eeb5702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160710024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.4160710024
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1986801636
Short name T938
Test name
Test status
Simulation time 207348137467 ps
CPU time 224.43 seconds
Started Jul 14 06:56:16 PM PDT 24
Finished Jul 14 07:00:04 PM PDT 24
Peak memory 249448 kb
Host smart-91330812-23bc-4f6c-87b6-0308a4959032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986801636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1986801636
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2526260314
Short name T370
Test name
Test status
Simulation time 940599061 ps
CPU time 7.61 seconds
Started Jul 14 06:56:23 PM PDT 24
Finished Jul 14 06:56:36 PM PDT 24
Peak memory 224440 kb
Host smart-0670b669-09d3-47e8-ace3-a7d23f02a0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526260314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2526260314
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.4250673299
Short name T656
Test name
Test status
Simulation time 8438319738 ps
CPU time 9.52 seconds
Started Jul 14 06:56:21 PM PDT 24
Finished Jul 14 06:56:36 PM PDT 24
Peak memory 232760 kb
Host smart-2ac403d6-77fb-471b-95f6-e079fc4e6d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250673299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.4250673299
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.84946040
Short name T489
Test name
Test status
Simulation time 37564926750 ps
CPU time 24.63 seconds
Started Jul 14 06:56:23 PM PDT 24
Finished Jul 14 06:56:54 PM PDT 24
Peak memory 232772 kb
Host smart-45d8de68-9311-4095-aa47-a7db33d077a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84946040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap.84946040
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2169542454
Short name T991
Test name
Test status
Simulation time 1532493218 ps
CPU time 4.84 seconds
Started Jul 14 06:56:32 PM PDT 24
Finished Jul 14 06:56:39 PM PDT 24
Peak memory 224488 kb
Host smart-7ecbe2fb-30e1-4d4b-b4bb-d45d508f897d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169542454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2169542454
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.293431653
Short name T571
Test name
Test status
Simulation time 748832067 ps
CPU time 3.79 seconds
Started Jul 14 06:56:24 PM PDT 24
Finished Jul 14 06:56:33 PM PDT 24
Peak memory 218812 kb
Host smart-5a7114a1-4df6-4e06-98ec-82c6ede4f406
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=293431653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.293431653
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.315807956
Short name T165
Test name
Test status
Simulation time 29577376418 ps
CPU time 97.91 seconds
Started Jul 14 06:56:33 PM PDT 24
Finished Jul 14 06:58:13 PM PDT 24
Peak memory 257252 kb
Host smart-949b5369-e42e-456e-b22c-70b3ef57d729
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315807956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.315807956
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1242562982
Short name T552
Test name
Test status
Simulation time 897571878 ps
CPU time 5.41 seconds
Started Jul 14 06:56:25 PM PDT 24
Finished Jul 14 06:56:36 PM PDT 24
Peak memory 216304 kb
Host smart-19e81423-cbb5-4ed4-a488-de555b184d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242562982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1242562982
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2180094861
Short name T389
Test name
Test status
Simulation time 1514815143 ps
CPU time 5.33 seconds
Started Jul 14 06:56:23 PM PDT 24
Finished Jul 14 06:56:34 PM PDT 24
Peak memory 216188 kb
Host smart-fd350c81-57e0-44b8-9e55-9c3c0bd7d587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180094861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2180094861
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2407036342
Short name T792
Test name
Test status
Simulation time 164663786 ps
CPU time 1.24 seconds
Started Jul 14 06:56:17 PM PDT 24
Finished Jul 14 06:56:23 PM PDT 24
Peak memory 216196 kb
Host smart-c7b5d40f-dfef-4c38-9f2f-c12b8ebc3610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407036342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2407036342
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2423830736
Short name T405
Test name
Test status
Simulation time 73305785 ps
CPU time 0.91 seconds
Started Jul 14 06:56:15 PM PDT 24
Finished Jul 14 06:56:18 PM PDT 24
Peak memory 205992 kb
Host smart-3b0398bc-a90b-4439-b91b-ad4848bd52b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423830736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2423830736
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3359810690
Short name T902
Test name
Test status
Simulation time 4235676637 ps
CPU time 16.31 seconds
Started Jul 14 06:56:30 PM PDT 24
Finished Jul 14 06:56:49 PM PDT 24
Peak memory 232860 kb
Host smart-6fabd1be-db8b-4f09-ba8a-4cd82ef03408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359810690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3359810690
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2264465868
Short name T526
Test name
Test status
Simulation time 23275476 ps
CPU time 0.71 seconds
Started Jul 14 06:56:47 PM PDT 24
Finished Jul 14 06:56:50 PM PDT 24
Peak memory 205536 kb
Host smart-b76561c7-b3a4-403f-a5ea-ff1c16fd9ca5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264465868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2264465868
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2017227740
Short name T353
Test name
Test status
Simulation time 3504661610 ps
CPU time 7.57 seconds
Started Jul 14 06:56:17 PM PDT 24
Finished Jul 14 06:56:29 PM PDT 24
Peak memory 224516 kb
Host smart-91bdcf5b-aff8-4bcf-a397-616f46fe6061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017227740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2017227740
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3606095717
Short name T324
Test name
Test status
Simulation time 18390675 ps
CPU time 0.85 seconds
Started Jul 14 06:56:23 PM PDT 24
Finished Jul 14 06:56:29 PM PDT 24
Peak memory 206600 kb
Host smart-e5bb2ccd-a54f-481a-b68d-4cd2a4d688b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606095717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3606095717
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1404074346
Short name T322
Test name
Test status
Simulation time 35322427822 ps
CPU time 83.46 seconds
Started Jul 14 06:56:19 PM PDT 24
Finished Jul 14 06:57:48 PM PDT 24
Peak memory 249200 kb
Host smart-78e95109-fe22-42a6-873d-e70971f39b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404074346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1404074346
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2551724921
Short name T613
Test name
Test status
Simulation time 15143683043 ps
CPU time 59.52 seconds
Started Jul 14 06:56:18 PM PDT 24
Finished Jul 14 06:57:22 PM PDT 24
Peak memory 250956 kb
Host smart-e050a1e7-8669-42f5-b329-2313c1248c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551724921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2551724921
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.144770501
Short name T220
Test name
Test status
Simulation time 38335184024 ps
CPU time 90.24 seconds
Started Jul 14 06:56:18 PM PDT 24
Finished Jul 14 06:57:53 PM PDT 24
Peak memory 249216 kb
Host smart-c0b4206d-a638-4ace-a506-2ae1c54c3ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144770501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.144770501
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1227193952
Short name T284
Test name
Test status
Simulation time 460319238 ps
CPU time 7.86 seconds
Started Jul 14 06:56:34 PM PDT 24
Finished Jul 14 06:56:43 PM PDT 24
Peak memory 238000 kb
Host smart-e43cb927-d49d-496d-b5e8-cd9548195bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227193952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1227193952
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.2013847421
Short name T755
Test name
Test status
Simulation time 3637839626 ps
CPU time 81 seconds
Started Jul 14 06:56:23 PM PDT 24
Finished Jul 14 06:57:50 PM PDT 24
Peak memory 266376 kb
Host smart-88cc8dbd-d471-4a13-ac96-76aa0add031d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013847421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.2013847421
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2421292310
Short name T682
Test name
Test status
Simulation time 755715876 ps
CPU time 8.91 seconds
Started Jul 14 06:56:23 PM PDT 24
Finished Jul 14 06:56:38 PM PDT 24
Peak memory 224464 kb
Host smart-604f9757-2d20-4500-8d6c-d34831054d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421292310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2421292310
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3354145622
Short name T800
Test name
Test status
Simulation time 27385896878 ps
CPU time 56.57 seconds
Started Jul 14 06:56:17 PM PDT 24
Finished Jul 14 06:57:18 PM PDT 24
Peak memory 239896 kb
Host smart-a08df3b8-dc2d-4d64-b939-d6ec1f3f75d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354145622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3354145622
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2416081975
Short name T461
Test name
Test status
Simulation time 936635905 ps
CPU time 2.48 seconds
Started Jul 14 06:56:23 PM PDT 24
Finished Jul 14 06:56:31 PM PDT 24
Peak memory 224448 kb
Host smart-b0f423d5-cf5e-4d0e-b60e-d43b7c3dfe7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416081975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2416081975
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1113716792
Short name T434
Test name
Test status
Simulation time 26749716558 ps
CPU time 18.69 seconds
Started Jul 14 06:56:23 PM PDT 24
Finished Jul 14 06:56:48 PM PDT 24
Peak memory 232836 kb
Host smart-9041a888-ffdc-4acc-87df-daacf6b7756f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113716792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1113716792
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.826117464
Short name T338
Test name
Test status
Simulation time 1187562196 ps
CPU time 4.37 seconds
Started Jul 14 06:56:19 PM PDT 24
Finished Jul 14 06:56:29 PM PDT 24
Peak memory 223148 kb
Host smart-8665c9e3-7596-4040-b1de-23d73ec3a60d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=826117464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.826117464
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3089516648
Short name T728
Test name
Test status
Simulation time 36950340 ps
CPU time 0.97 seconds
Started Jul 14 06:56:45 PM PDT 24
Finished Jul 14 06:56:48 PM PDT 24
Peak memory 207560 kb
Host smart-d48b0f18-9182-4c0f-9d53-c66b7a0a7dd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089516648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3089516648
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.784462867
Short name T309
Test name
Test status
Simulation time 47118872 ps
CPU time 0.72 seconds
Started Jul 14 06:56:21 PM PDT 24
Finished Jul 14 06:56:28 PM PDT 24
Peak memory 205684 kb
Host smart-d92b1897-3eff-4358-b8b3-0baa60eee187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784462867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.784462867
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2457435647
Short name T1003
Test name
Test status
Simulation time 985820824 ps
CPU time 6.01 seconds
Started Jul 14 06:56:41 PM PDT 24
Finished Jul 14 06:56:48 PM PDT 24
Peak memory 216168 kb
Host smart-466bd529-69c1-41cd-a9e3-f106d6bd92e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457435647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2457435647
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2475684475
Short name T869
Test name
Test status
Simulation time 266145929 ps
CPU time 5.01 seconds
Started Jul 14 06:56:20 PM PDT 24
Finished Jul 14 06:56:30 PM PDT 24
Peak memory 216200 kb
Host smart-7ff431ff-1c71-4dee-bbfe-0a04ffb88e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475684475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2475684475
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1481517523
Short name T603
Test name
Test status
Simulation time 66177090 ps
CPU time 0.92 seconds
Started Jul 14 06:56:26 PM PDT 24
Finished Jul 14 06:56:32 PM PDT 24
Peak memory 205992 kb
Host smart-03d20532-76b7-493c-97c8-ba9efc090695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481517523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1481517523
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2767742967
Short name T920
Test name
Test status
Simulation time 3689868185 ps
CPU time 10.57 seconds
Started Jul 14 06:56:23 PM PDT 24
Finished Jul 14 06:56:39 PM PDT 24
Peak memory 232780 kb
Host smart-1026665d-98f0-4449-a04f-f58c1332db33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767742967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2767742967
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.4118241175
Short name T310
Test name
Test status
Simulation time 46603293 ps
CPU time 0.74 seconds
Started Jul 14 06:54:50 PM PDT 24
Finished Jul 14 06:54:53 PM PDT 24
Peak memory 205836 kb
Host smart-86913f79-dd94-4eda-83ce-384135a8304c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118241175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.4
118241175
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3697111667
Short name T666
Test name
Test status
Simulation time 151552257 ps
CPU time 3.65 seconds
Started Jul 14 06:55:07 PM PDT 24
Finished Jul 14 06:55:16 PM PDT 24
Peak memory 232676 kb
Host smart-f333b972-778f-4847-b09b-b210f7f93266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697111667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3697111667
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2657346276
Short name T567
Test name
Test status
Simulation time 19336707 ps
CPU time 0.77 seconds
Started Jul 14 06:55:53 PM PDT 24
Finished Jul 14 06:55:56 PM PDT 24
Peak memory 206364 kb
Host smart-870c8f6a-8c7b-4974-9bd3-98e45ed9ca7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657346276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2657346276
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3801464277
Short name T653
Test name
Test status
Simulation time 2359905759 ps
CPU time 11.35 seconds
Started Jul 14 06:54:35 PM PDT 24
Finished Jul 14 06:54:50 PM PDT 24
Peak memory 224544 kb
Host smart-b93a5d9f-baf8-4da2-93ab-2f3f061a14c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801464277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3801464277
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.204600845
Short name T201
Test name
Test status
Simulation time 8295741688 ps
CPU time 62.98 seconds
Started Jul 14 06:54:53 PM PDT 24
Finished Jul 14 06:55:58 PM PDT 24
Peak memory 249256 kb
Host smart-1fd03708-9a35-4b8a-921e-62cb0095857f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204600845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.204600845
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3687678229
Short name T1010
Test name
Test status
Simulation time 39303706388 ps
CPU time 179.27 seconds
Started Jul 14 06:54:40 PM PDT 24
Finished Jul 14 06:57:47 PM PDT 24
Peak memory 261976 kb
Host smart-1f3b68c4-7d76-421b-b9bd-519e6e5058c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687678229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3687678229
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1291595190
Short name T639
Test name
Test status
Simulation time 409713389 ps
CPU time 10.95 seconds
Started Jul 14 06:54:44 PM PDT 24
Finished Jul 14 06:54:59 PM PDT 24
Peak memory 224468 kb
Host smart-82a77b4e-3c71-4711-99b4-a459ed3ed688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291595190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1291595190
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.223407238
Short name T564
Test name
Test status
Simulation time 142033300516 ps
CPU time 147.31 seconds
Started Jul 14 06:55:01 PM PDT 24
Finished Jul 14 06:57:32 PM PDT 24
Peak memory 265020 kb
Host smart-b4660733-6270-49d5-8afb-d4abe2c69e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223407238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.
223407238
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1123697537
Short name T330
Test name
Test status
Simulation time 881177000 ps
CPU time 2.39 seconds
Started Jul 14 06:54:55 PM PDT 24
Finished Jul 14 06:54:59 PM PDT 24
Peak memory 223824 kb
Host smart-97f799df-3c00-4553-91e4-88a9331b7e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123697537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1123697537
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.4228837600
Short name T236
Test name
Test status
Simulation time 28794485614 ps
CPU time 66.69 seconds
Started Jul 14 06:54:51 PM PDT 24
Finished Jul 14 06:55:59 PM PDT 24
Peak memory 232840 kb
Host smart-39c09f5f-9b50-4319-bf4d-59bf360578b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228837600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.4228837600
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2077275541
Short name T281
Test name
Test status
Simulation time 3203366294 ps
CPU time 9.34 seconds
Started Jul 14 06:54:51 PM PDT 24
Finished Jul 14 06:55:02 PM PDT 24
Peak memory 232704 kb
Host smart-0be96a99-f155-460d-a84c-e2b7c487cb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077275541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2077275541
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.118753539
Short name T534
Test name
Test status
Simulation time 116531303 ps
CPU time 2.18 seconds
Started Jul 14 06:54:50 PM PDT 24
Finished Jul 14 06:54:54 PM PDT 24
Peak memory 224064 kb
Host smart-12247974-4f6c-42c0-bf9d-270193f755a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118753539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.118753539
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3294280772
Short name T50
Test name
Test status
Simulation time 14524941600 ps
CPU time 13.65 seconds
Started Jul 14 06:54:45 PM PDT 24
Finished Jul 14 06:55:02 PM PDT 24
Peak memory 222740 kb
Host smart-ce31e2cb-3954-49b7-91e6-146b62e0d89f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3294280772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3294280772
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2729606620
Short name T72
Test name
Test status
Simulation time 78675411 ps
CPU time 1.02 seconds
Started Jul 14 06:55:12 PM PDT 24
Finished Jul 14 06:55:18 PM PDT 24
Peak memory 235980 kb
Host smart-6b35b5dc-2e92-4c3b-be9e-f60ab6ed73ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729606620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2729606620
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1386026346
Short name T422
Test name
Test status
Simulation time 50575895 ps
CPU time 1.13 seconds
Started Jul 14 06:54:58 PM PDT 24
Finished Jul 14 06:55:00 PM PDT 24
Peak memory 206872 kb
Host smart-036ef785-3172-466a-a77a-7f7a3ee02632
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386026346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1386026346
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2831524044
Short name T293
Test name
Test status
Simulation time 1302192689 ps
CPU time 18.76 seconds
Started Jul 14 06:54:40 PM PDT 24
Finished Jul 14 06:55:01 PM PDT 24
Peak memory 219840 kb
Host smart-43dcfee0-7343-4636-a4ae-ad2cf32f21ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831524044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2831524044
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1703019899
Short name T460
Test name
Test status
Simulation time 615707365 ps
CPU time 3.18 seconds
Started Jul 14 06:54:48 PM PDT 24
Finished Jul 14 06:54:54 PM PDT 24
Peak memory 216372 kb
Host smart-14592db4-f89a-4f76-a91c-2aab894be6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703019899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1703019899
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1198531351
Short name T550
Test name
Test status
Simulation time 510314477 ps
CPU time 5.49 seconds
Started Jul 14 06:54:46 PM PDT 24
Finished Jul 14 06:54:55 PM PDT 24
Peak memory 216220 kb
Host smart-fc67f919-4ad9-46e5-af26-9a59180940b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198531351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1198531351
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1264998947
Short name T302
Test name
Test status
Simulation time 132205406 ps
CPU time 0.75 seconds
Started Jul 14 06:54:40 PM PDT 24
Finished Jul 14 06:54:43 PM PDT 24
Peak memory 205996 kb
Host smart-86057f3a-21c9-4095-91cc-c845ab9b4872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264998947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1264998947
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2702070592
Short name T797
Test name
Test status
Simulation time 12824610934 ps
CPU time 13.77 seconds
Started Jul 14 06:54:49 PM PDT 24
Finished Jul 14 06:55:05 PM PDT 24
Peak memory 232796 kb
Host smart-4648eceb-005f-4979-94a2-89ff0fa2fc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702070592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2702070592
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.502646256
Short name T485
Test name
Test status
Simulation time 21625007 ps
CPU time 0.71 seconds
Started Jul 14 06:56:19 PM PDT 24
Finished Jul 14 06:56:26 PM PDT 24
Peak memory 205868 kb
Host smart-67587a9b-a9e0-4875-b5f2-e51a9a22ff4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502646256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.502646256
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2982630525
Short name T84
Test name
Test status
Simulation time 4125299653 ps
CPU time 9.96 seconds
Started Jul 14 06:56:37 PM PDT 24
Finished Jul 14 06:56:47 PM PDT 24
Peak memory 224568 kb
Host smart-3b3d1639-fe3f-45ad-b22a-9d43f0abddea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982630525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2982630525
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3887572500
Short name T430
Test name
Test status
Simulation time 134090247 ps
CPU time 0.77 seconds
Started Jul 14 06:56:25 PM PDT 24
Finished Jul 14 06:56:31 PM PDT 24
Peak memory 206932 kb
Host smart-4918500c-a580-4a69-8d9d-deb419c4a942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887572500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3887572500
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3168089415
Short name T685
Test name
Test status
Simulation time 12429909246 ps
CPU time 119.18 seconds
Started Jul 14 06:56:20 PM PDT 24
Finished Jul 14 06:58:25 PM PDT 24
Peak memory 249172 kb
Host smart-94b21252-5155-4320-beb2-d1d05bafac08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168089415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3168089415
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1200955686
Short name T62
Test name
Test status
Simulation time 198498367757 ps
CPU time 372.18 seconds
Started Jul 14 06:56:46 PM PDT 24
Finished Jul 14 07:03:01 PM PDT 24
Peak memory 266440 kb
Host smart-fd0c727f-ccf0-4c35-9c29-2b4d47ec96c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200955686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1200955686
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2591966432
Short name T976
Test name
Test status
Simulation time 8216878557 ps
CPU time 91.87 seconds
Started Jul 14 06:56:33 PM PDT 24
Finished Jul 14 06:58:07 PM PDT 24
Peak memory 257404 kb
Host smart-32e6629e-5dda-4d7a-accc-6787cd40e6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591966432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2591966432
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.4101187641
Short name T416
Test name
Test status
Simulation time 4456590282 ps
CPU time 7.87 seconds
Started Jul 14 06:56:25 PM PDT 24
Finished Jul 14 06:56:38 PM PDT 24
Peak memory 224556 kb
Host smart-b3560c8c-6caf-421c-b66c-ac5b4073d0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101187641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.4101187641
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.1825499181
Short name T409
Test name
Test status
Simulation time 12735670862 ps
CPU time 47.35 seconds
Started Jul 14 06:56:42 PM PDT 24
Finished Jul 14 06:57:30 PM PDT 24
Peak memory 224548 kb
Host smart-e831fe75-a71a-4070-9bc6-2fb6dd2a4bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825499181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.1825499181
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2397751915
Short name T843
Test name
Test status
Simulation time 253723721 ps
CPU time 3.21 seconds
Started Jul 14 06:56:23 PM PDT 24
Finished Jul 14 06:56:32 PM PDT 24
Peak memory 232716 kb
Host smart-00e282f7-e847-404b-9128-2d7027013ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397751915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2397751915
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.568711889
Short name T759
Test name
Test status
Simulation time 41634977 ps
CPU time 2.35 seconds
Started Jul 14 06:56:45 PM PDT 24
Finished Jul 14 06:56:48 PM PDT 24
Peak memory 232664 kb
Host smart-f1860287-267f-40f1-8e42-237e7102acbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568711889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.568711889
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3109119086
Short name T277
Test name
Test status
Simulation time 530585994 ps
CPU time 7.73 seconds
Started Jul 14 06:56:47 PM PDT 24
Finished Jul 14 06:56:58 PM PDT 24
Peak memory 232664 kb
Host smart-45d0abc1-594e-42b6-9f54-ca0df7662e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109119086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3109119086
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.841485383
Short name T331
Test name
Test status
Simulation time 79375070 ps
CPU time 2.25 seconds
Started Jul 14 06:56:46 PM PDT 24
Finished Jul 14 06:56:51 PM PDT 24
Peak memory 223948 kb
Host smart-77ef7956-0d4b-42da-8d52-b607aeeb5f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841485383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.841485383
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1137585787
Short name T865
Test name
Test status
Simulation time 442572468 ps
CPU time 4.21 seconds
Started Jul 14 06:56:25 PM PDT 24
Finished Jul 14 06:56:34 PM PDT 24
Peak memory 222752 kb
Host smart-86a023ee-2424-421c-bcf2-0965709a62c9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1137585787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1137585787
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3430244516
Short name T708
Test name
Test status
Simulation time 261809231 ps
CPU time 1.05 seconds
Started Jul 14 06:56:20 PM PDT 24
Finished Jul 14 06:56:26 PM PDT 24
Peak memory 206872 kb
Host smart-b9020f5c-ac15-4612-be57-0bd2666659e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430244516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3430244516
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2489092072
Short name T378
Test name
Test status
Simulation time 1562125614 ps
CPU time 21.7 seconds
Started Jul 14 06:56:43 PM PDT 24
Finished Jul 14 06:57:05 PM PDT 24
Peak memory 216232 kb
Host smart-5ba9ff0f-b3c6-4fb3-bf61-95a7524b2585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489092072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2489092072
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3571002476
Short name T506
Test name
Test status
Simulation time 648713864 ps
CPU time 2.46 seconds
Started Jul 14 06:56:23 PM PDT 24
Finished Jul 14 06:56:31 PM PDT 24
Peak memory 207912 kb
Host smart-4b4aa183-abd8-4c29-b05c-1e6070eb6ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571002476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3571002476
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2504571662
Short name T1006
Test name
Test status
Simulation time 161830333 ps
CPU time 2.31 seconds
Started Jul 14 06:56:30 PM PDT 24
Finished Jul 14 06:56:35 PM PDT 24
Peak memory 216268 kb
Host smart-3569339f-ee0c-4268-a901-dd6be26d07e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504571662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2504571662
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1835405503
Short name T347
Test name
Test status
Simulation time 30858793 ps
CPU time 0.83 seconds
Started Jul 14 06:56:19 PM PDT 24
Finished Jul 14 06:56:25 PM PDT 24
Peak memory 205996 kb
Host smart-81b17860-6d6a-41f0-89eb-8b7bc7a13ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835405503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1835405503
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1413357013
Short name T671
Test name
Test status
Simulation time 16845318686 ps
CPU time 15.23 seconds
Started Jul 14 06:56:30 PM PDT 24
Finished Jul 14 06:56:48 PM PDT 24
Peak memory 224540 kb
Host smart-982a81a5-55a5-444b-bb6c-7db078f69282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413357013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1413357013
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.855188122
Short name T691
Test name
Test status
Simulation time 27766040 ps
CPU time 0.68 seconds
Started Jul 14 06:56:31 PM PDT 24
Finished Jul 14 06:56:34 PM PDT 24
Peak memory 205864 kb
Host smart-0d2705fb-ea20-415f-8ddb-0bcba9de6e5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855188122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.855188122
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2125038208
Short name T647
Test name
Test status
Simulation time 120878266 ps
CPU time 2.64 seconds
Started Jul 14 06:56:39 PM PDT 24
Finished Jul 14 06:56:43 PM PDT 24
Peak memory 232676 kb
Host smart-bea4adf2-574d-4ecb-b9b7-a7e032d84825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125038208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2125038208
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1933587731
Short name T132
Test name
Test status
Simulation time 26286183 ps
CPU time 0.76 seconds
Started Jul 14 06:56:23 PM PDT 24
Finished Jul 14 06:56:29 PM PDT 24
Peak memory 205592 kb
Host smart-90bebd89-9070-4687-8fda-9c1c0acbf789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933587731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1933587731
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.309275700
Short name T189
Test name
Test status
Simulation time 6190910190 ps
CPU time 63.27 seconds
Started Jul 14 06:56:35 PM PDT 24
Finished Jul 14 06:57:39 PM PDT 24
Peak memory 249252 kb
Host smart-cb407113-2d80-4098-9c57-56b16c19ef6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309275700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.309275700
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.4137398297
Short name T857
Test name
Test status
Simulation time 200118648024 ps
CPU time 462.39 seconds
Started Jul 14 06:56:17 PM PDT 24
Finished Jul 14 07:04:03 PM PDT 24
Peak memory 254232 kb
Host smart-b2fde6cd-2b83-4e8e-9b3e-6cbad6a1ae63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137398297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.4137398297
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1689223322
Short name T222
Test name
Test status
Simulation time 203371089753 ps
CPU time 461.55 seconds
Started Jul 14 06:56:46 PM PDT 24
Finished Jul 14 07:04:31 PM PDT 24
Peak memory 252240 kb
Host smart-20d33961-e0a6-4a39-8eee-87beb243559d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689223322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1689223322
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.5014926
Short name T148
Test name
Test status
Simulation time 2621502349 ps
CPU time 11.74 seconds
Started Jul 14 06:56:21 PM PDT 24
Finished Jul 14 06:56:38 PM PDT 24
Peak memory 233496 kb
Host smart-56d6c2dc-506e-4ba6-a1a7-34816bda15ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5014926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.5014926
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.4270448862
Short name T837
Test name
Test status
Simulation time 57754885 ps
CPU time 2.54 seconds
Started Jul 14 06:56:44 PM PDT 24
Finished Jul 14 06:56:47 PM PDT 24
Peak memory 232404 kb
Host smart-ec739b83-f042-41ae-a646-e34ea906a2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270448862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.4270448862
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1092106942
Short name T916
Test name
Test status
Simulation time 18957861199 ps
CPU time 185.32 seconds
Started Jul 14 06:56:37 PM PDT 24
Finished Jul 14 06:59:44 PM PDT 24
Peak memory 240256 kb
Host smart-51b6d51e-6aa5-41b3-b1f7-30d077c9e9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092106942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1092106942
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.297872093
Short name T590
Test name
Test status
Simulation time 19473641813 ps
CPU time 15.66 seconds
Started Jul 14 06:56:28 PM PDT 24
Finished Jul 14 06:56:48 PM PDT 24
Peak memory 232756 kb
Host smart-05553a0a-8433-46a2-b76b-0d7ff438bd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297872093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.297872093
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2796657214
Short name T494
Test name
Test status
Simulation time 7949037986 ps
CPU time 6.38 seconds
Started Jul 14 06:56:30 PM PDT 24
Finished Jul 14 06:56:39 PM PDT 24
Peak memory 232788 kb
Host smart-3c28ccf5-d2bf-46b8-b799-659fa83a6414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796657214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2796657214
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.161080061
Short name T845
Test name
Test status
Simulation time 298465955 ps
CPU time 5.39 seconds
Started Jul 14 06:56:38 PM PDT 24
Finished Jul 14 06:56:44 PM PDT 24
Peak memory 220224 kb
Host smart-e5ed3201-65fe-48c0-a181-590e9be2a0a8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=161080061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.161080061
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3787958873
Short name T34
Test name
Test status
Simulation time 16129708694 ps
CPU time 146.2 seconds
Started Jul 14 06:56:27 PM PDT 24
Finished Jul 14 06:58:58 PM PDT 24
Peak memory 255684 kb
Host smart-74a1a860-b5b3-4a4a-8c7a-0d3998b6cf8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787958873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3787958873
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1887576174
Short name T349
Test name
Test status
Simulation time 773446383 ps
CPU time 11.69 seconds
Started Jul 14 06:56:20 PM PDT 24
Finished Jul 14 06:56:37 PM PDT 24
Peak memory 217604 kb
Host smart-fee38e6d-aed9-4250-ba44-91cb3e097574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887576174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1887576174
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.4049938484
Short name T311
Test name
Test status
Simulation time 2080060215 ps
CPU time 4.77 seconds
Started Jul 14 06:56:37 PM PDT 24
Finished Jul 14 06:56:43 PM PDT 24
Peak memory 216224 kb
Host smart-09082251-2328-4276-9f2c-a0947bb64b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049938484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.4049938484
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1563790244
Short name T758
Test name
Test status
Simulation time 23742634 ps
CPU time 0.7 seconds
Started Jul 14 06:56:21 PM PDT 24
Finished Jul 14 06:56:27 PM PDT 24
Peak memory 205840 kb
Host smart-7051d462-2fa7-493d-a938-21afcafb6797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563790244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1563790244
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1329176704
Short name T303
Test name
Test status
Simulation time 86698140 ps
CPU time 0.91 seconds
Started Jul 14 06:56:23 PM PDT 24
Finished Jul 14 06:56:29 PM PDT 24
Peak memory 207008 kb
Host smart-39dd7132-217e-4d28-917f-116f4eda0b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329176704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1329176704
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.606802388
Short name T458
Test name
Test status
Simulation time 3454591124 ps
CPU time 13.71 seconds
Started Jul 14 06:56:32 PM PDT 24
Finished Jul 14 06:56:48 PM PDT 24
Peak memory 224564 kb
Host smart-b6c4b34d-9faa-4289-bb21-d87242131abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606802388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.606802388
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1189138015
Short name T421
Test name
Test status
Simulation time 13919748 ps
CPU time 0.73 seconds
Started Jul 14 06:56:49 PM PDT 24
Finished Jul 14 06:56:54 PM PDT 24
Peak memory 205552 kb
Host smart-9e20e58c-8c52-4cbd-bae9-170124d34889
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189138015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1189138015
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.486167262
Short name T657
Test name
Test status
Simulation time 70839962 ps
CPU time 2.77 seconds
Started Jul 14 06:56:24 PM PDT 24
Finished Jul 14 06:56:33 PM PDT 24
Peak memory 232628 kb
Host smart-f47a3305-eb26-48f8-8c29-56bb191eba6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486167262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.486167262
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3148272311
Short name T762
Test name
Test status
Simulation time 16222525 ps
CPU time 0.77 seconds
Started Jul 14 06:56:37 PM PDT 24
Finished Jul 14 06:56:39 PM PDT 24
Peak memory 205920 kb
Host smart-809e5d4f-c002-42a2-87f0-c284a68ef786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148272311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3148272311
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.4162355478
Short name T515
Test name
Test status
Simulation time 1360524069 ps
CPU time 29.11 seconds
Started Jul 14 06:56:26 PM PDT 24
Finished Jul 14 06:57:00 PM PDT 24
Peak memory 254656 kb
Host smart-8717b703-6494-4a6c-abfd-e04e4beadcbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162355478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.4162355478
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.4014300223
Short name T42
Test name
Test status
Simulation time 99925612851 ps
CPU time 164.87 seconds
Started Jul 14 06:56:39 PM PDT 24
Finished Jul 14 06:59:25 PM PDT 24
Peak memory 255908 kb
Host smart-7cd90b05-8e44-4e4d-9a1b-3ec71c2a4ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014300223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.4014300223
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2822798191
Short name T445
Test name
Test status
Simulation time 56233107 ps
CPU time 3.55 seconds
Started Jul 14 06:56:50 PM PDT 24
Finished Jul 14 06:56:57 PM PDT 24
Peak memory 232632 kb
Host smart-d65a4965-a0ad-420a-82fc-a93385ba4d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822798191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2822798191
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.49318324
Short name T263
Test name
Test status
Simulation time 58385883530 ps
CPU time 239.85 seconds
Started Jul 14 06:56:25 PM PDT 24
Finished Jul 14 07:00:30 PM PDT 24
Peak memory 257360 kb
Host smart-9537828c-a790-48c5-b688-b95e163f652b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49318324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds.49318324
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1060759832
Short name T604
Test name
Test status
Simulation time 367734038 ps
CPU time 5.19 seconds
Started Jul 14 06:56:31 PM PDT 24
Finished Jul 14 06:56:39 PM PDT 24
Peak memory 232648 kb
Host smart-33c2575d-1a09-40b4-b1cd-0ec89df102df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060759832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1060759832
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.8449043
Short name T57
Test name
Test status
Simulation time 15142199641 ps
CPU time 114.98 seconds
Started Jul 14 06:56:29 PM PDT 24
Finished Jul 14 06:58:27 PM PDT 24
Peak memory 232800 kb
Host smart-532cd0e5-df10-4e72-be5d-7835ba049ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8449043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.8449043
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.108052973
Short name T873
Test name
Test status
Simulation time 65548931 ps
CPU time 2.56 seconds
Started Jul 14 06:56:30 PM PDT 24
Finished Jul 14 06:56:36 PM PDT 24
Peak memory 232612 kb
Host smart-4ad10393-0b4c-460c-9d6e-44a29a7c7548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108052973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.108052973
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3127432395
Short name T618
Test name
Test status
Simulation time 125438271 ps
CPU time 2.18 seconds
Started Jul 14 06:56:47 PM PDT 24
Finished Jul 14 06:56:52 PM PDT 24
Peak memory 223988 kb
Host smart-3d33f4ee-fd36-4ccf-a0a0-e30bbfcaf545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127432395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3127432395
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3191742947
Short name T940
Test name
Test status
Simulation time 3561562683 ps
CPU time 6.14 seconds
Started Jul 14 06:56:39 PM PDT 24
Finished Jul 14 06:56:46 PM PDT 24
Peak memory 223356 kb
Host smart-44381d71-92ca-4d2e-9d4a-9fd674729e69
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3191742947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3191742947
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1171760366
Short name T681
Test name
Test status
Simulation time 76490927123 ps
CPU time 393.69 seconds
Started Jul 14 06:56:30 PM PDT 24
Finished Jul 14 07:03:07 PM PDT 24
Peak memory 265856 kb
Host smart-6950018f-18f9-41a4-ae9f-3ad5d9068a05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171760366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1171760366
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.4018793740
Short name T292
Test name
Test status
Simulation time 13667110323 ps
CPU time 39.11 seconds
Started Jul 14 06:56:39 PM PDT 24
Finished Jul 14 06:57:20 PM PDT 24
Peak memory 216372 kb
Host smart-56ceca62-ec09-44d0-b0dc-338e9ba392e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018793740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.4018793740
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2663955334
Short name T956
Test name
Test status
Simulation time 48177451518 ps
CPU time 20.84 seconds
Started Jul 14 06:56:25 PM PDT 24
Finished Jul 14 06:56:51 PM PDT 24
Peak memory 216424 kb
Host smart-4b1bbd6b-7cb0-43e0-84e5-228976b109a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663955334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2663955334
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.4267927857
Short name T715
Test name
Test status
Simulation time 159099628 ps
CPU time 3.71 seconds
Started Jul 14 06:56:50 PM PDT 24
Finished Jul 14 06:56:58 PM PDT 24
Peak memory 216268 kb
Host smart-d3181059-3ab2-4a2f-bc96-4ebf1b2a6b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267927857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.4267927857
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3434125259
Short name T519
Test name
Test status
Simulation time 49595311 ps
CPU time 0.87 seconds
Started Jul 14 06:56:47 PM PDT 24
Finished Jul 14 06:56:54 PM PDT 24
Peak memory 205944 kb
Host smart-370538ca-b758-41fc-9ef0-c777eb849d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434125259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3434125259
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1656551539
Short name T862
Test name
Test status
Simulation time 153303092 ps
CPU time 3.28 seconds
Started Jul 14 06:56:36 PM PDT 24
Finished Jul 14 06:56:40 PM PDT 24
Peak memory 232660 kb
Host smart-4790c4fa-5f03-4bd7-9c2c-84f15a4b3244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656551539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1656551539
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.4271648427
Short name T67
Test name
Test status
Simulation time 65166436 ps
CPU time 0.7 seconds
Started Jul 14 06:56:29 PM PDT 24
Finished Jul 14 06:56:33 PM PDT 24
Peak memory 204996 kb
Host smart-d2807e3a-d51a-4841-a1c3-b1b5fd490ec7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271648427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
4271648427
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2469512766
Short name T385
Test name
Test status
Simulation time 39180167 ps
CPU time 2.46 seconds
Started Jul 14 06:56:31 PM PDT 24
Finished Jul 14 06:56:36 PM PDT 24
Peak memory 232700 kb
Host smart-2d98d62e-8ee4-4803-81b3-cc701d84eb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469512766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2469512766
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.280414934
Short name T335
Test name
Test status
Simulation time 16352497 ps
CPU time 0.79 seconds
Started Jul 14 06:56:27 PM PDT 24
Finished Jul 14 06:56:32 PM PDT 24
Peak memory 206620 kb
Host smart-84a9bcc5-bc10-4732-81b8-158c7d878807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280414934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.280414934
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3332481281
Short name T626
Test name
Test status
Simulation time 12901191139 ps
CPU time 90.92 seconds
Started Jul 14 06:56:40 PM PDT 24
Finished Jul 14 06:58:12 PM PDT 24
Peak memory 249120 kb
Host smart-2d4de2df-1b18-4d3d-94cd-040c20258050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332481281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3332481281
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.4050993579
Short name T811
Test name
Test status
Simulation time 8028834218 ps
CPU time 126.81 seconds
Started Jul 14 06:56:29 PM PDT 24
Finished Jul 14 06:58:39 PM PDT 24
Peak memory 264780 kb
Host smart-a193d6f9-7bf2-443f-a0bc-de646d5f1bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050993579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.4050993579
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1911015184
Short name T928
Test name
Test status
Simulation time 184616407 ps
CPU time 2.82 seconds
Started Jul 14 06:56:47 PM PDT 24
Finished Jul 14 06:56:53 PM PDT 24
Peak memory 232564 kb
Host smart-03d4b428-a7aa-49fb-81c8-73b3ab4b2dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911015184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1911015184
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.263393871
Short name T711
Test name
Test status
Simulation time 4296983472 ps
CPU time 44.01 seconds
Started Jul 14 06:56:46 PM PDT 24
Finished Jul 14 06:57:32 PM PDT 24
Peak memory 250160 kb
Host smart-330ef838-8936-45a6-b4bb-90fe9af375f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263393871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.263393871
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.597349346
Short name T667
Test name
Test status
Simulation time 51608699 ps
CPU time 2.35 seconds
Started Jul 14 06:56:47 PM PDT 24
Finished Jul 14 06:56:53 PM PDT 24
Peak memory 224508 kb
Host smart-e5c23472-aa44-4e47-a7f8-5592e92069f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597349346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.597349346
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1618562312
Short name T627
Test name
Test status
Simulation time 1124040778 ps
CPU time 11.29 seconds
Started Jul 14 06:56:25 PM PDT 24
Finished Jul 14 06:56:42 PM PDT 24
Peak memory 232624 kb
Host smart-4b705540-ed5f-43ed-ab4a-b948357c47f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618562312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1618562312
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.725252555
Short name T204
Test name
Test status
Simulation time 4035466930 ps
CPU time 12.73 seconds
Started Jul 14 06:56:25 PM PDT 24
Finished Jul 14 06:56:43 PM PDT 24
Peak memory 232704 kb
Host smart-afb7c7e9-5842-4558-befa-516240f007be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725252555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.725252555
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1015158109
Short name T78
Test name
Test status
Simulation time 72949871 ps
CPU time 2.25 seconds
Started Jul 14 06:56:27 PM PDT 24
Finished Jul 14 06:56:34 PM PDT 24
Peak memory 224140 kb
Host smart-d70a74d2-4298-4838-b11e-449b45add9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015158109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1015158109
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3606393162
Short name T507
Test name
Test status
Simulation time 588147133 ps
CPU time 7.58 seconds
Started Jul 14 06:56:28 PM PDT 24
Finished Jul 14 06:56:39 PM PDT 24
Peak memory 223072 kb
Host smart-1fc0506e-a384-4742-9ff1-12922b427a56
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3606393162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3606393162
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3836038363
Short name T988
Test name
Test status
Simulation time 16132933476 ps
CPU time 165.08 seconds
Started Jul 14 06:56:27 PM PDT 24
Finished Jul 14 06:59:16 PM PDT 24
Peak memory 265672 kb
Host smart-80b67c51-4b11-4cd0-ba4f-d19e050cebf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836038363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3836038363
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1923044970
Short name T623
Test name
Test status
Simulation time 2179583331 ps
CPU time 17.03 seconds
Started Jul 14 06:56:36 PM PDT 24
Finished Jul 14 06:56:54 PM PDT 24
Peak memory 216620 kb
Host smart-b937da2c-6712-454d-977e-236202a594e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923044970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1923044970
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2679910913
Short name T707
Test name
Test status
Simulation time 2828916106 ps
CPU time 5.53 seconds
Started Jul 14 06:56:31 PM PDT 24
Finished Jul 14 06:56:39 PM PDT 24
Peak memory 216300 kb
Host smart-061c7403-a4a5-4532-b4f8-5a5ae42b31c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679910913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2679910913
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2239726375
Short name T488
Test name
Test status
Simulation time 136388832 ps
CPU time 1.43 seconds
Started Jul 14 06:56:47 PM PDT 24
Finished Jul 14 06:56:51 PM PDT 24
Peak memory 207908 kb
Host smart-dcd696ec-02c6-4f4e-82e2-da61d265f6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239726375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2239726375
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2917147138
Short name T740
Test name
Test status
Simulation time 66756074 ps
CPU time 0.83 seconds
Started Jul 14 06:56:27 PM PDT 24
Finished Jul 14 06:56:32 PM PDT 24
Peak memory 205988 kb
Host smart-82c7880e-7ba3-442a-97ef-6eb332c676fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917147138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2917147138
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.4241779438
Short name T664
Test name
Test status
Simulation time 592678034 ps
CPU time 7.64 seconds
Started Jul 14 06:56:25 PM PDT 24
Finished Jul 14 06:56:38 PM PDT 24
Peak memory 232448 kb
Host smart-7870e940-8059-41ca-9d9b-bcdf37f837f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241779438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.4241779438
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.822814843
Short name T941
Test name
Test status
Simulation time 10429774 ps
CPU time 0.65 seconds
Started Jul 14 06:56:42 PM PDT 24
Finished Jul 14 06:56:43 PM PDT 24
Peak memory 205680 kb
Host smart-e3d0c1af-96fb-4453-97ef-e999dae0d6a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822814843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.822814843
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3760631974
Short name T718
Test name
Test status
Simulation time 700991630 ps
CPU time 8.25 seconds
Started Jul 14 06:56:48 PM PDT 24
Finished Jul 14 06:57:01 PM PDT 24
Peak memory 224352 kb
Host smart-63ec52a7-5271-4d12-b892-b1b13d2c6d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760631974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3760631974
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1746558621
Short name T65
Test name
Test status
Simulation time 153509492 ps
CPU time 0.8 seconds
Started Jul 14 06:56:30 PM PDT 24
Finished Jul 14 06:56:34 PM PDT 24
Peak memory 206588 kb
Host smart-fbc7439a-5715-4618-90be-bb2bcf8c62cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746558621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1746558621
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2754700933
Short name T397
Test name
Test status
Simulation time 15326882 ps
CPU time 0.8 seconds
Started Jul 14 06:56:37 PM PDT 24
Finished Jul 14 06:56:39 PM PDT 24
Peak memory 215788 kb
Host smart-50857ee2-698c-45d7-af5b-c25b8d7d6ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754700933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2754700933
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.806871062
Short name T738
Test name
Test status
Simulation time 142573604675 ps
CPU time 104.34 seconds
Started Jul 14 06:56:49 PM PDT 24
Finished Jul 14 06:58:40 PM PDT 24
Peak memory 257212 kb
Host smart-ef3c4a53-9482-456e-a8b4-6d180e988080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806871062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.806871062
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.4066552364
Short name T45
Test name
Test status
Simulation time 43803396824 ps
CPU time 176.77 seconds
Started Jul 14 06:56:41 PM PDT 24
Finished Jul 14 06:59:39 PM PDT 24
Peak memory 250928 kb
Host smart-5d5ee084-9211-4c22-9410-210fb1dda989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066552364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.4066552364
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3426938710
Short name T1001
Test name
Test status
Simulation time 795584549 ps
CPU time 10.25 seconds
Started Jul 14 06:56:39 PM PDT 24
Finished Jul 14 06:56:51 PM PDT 24
Peak memory 232688 kb
Host smart-62398b86-573c-425b-afe8-3e0503bbc40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426938710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3426938710
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3283945053
Short name T850
Test name
Test status
Simulation time 261921083584 ps
CPU time 118.84 seconds
Started Jul 14 06:56:47 PM PDT 24
Finished Jul 14 06:58:50 PM PDT 24
Peak memory 249116 kb
Host smart-35787e1f-0aae-41c8-938a-cab23a605148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283945053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3283945053
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3916019351
Short name T834
Test name
Test status
Simulation time 4443101532 ps
CPU time 20.18 seconds
Started Jul 14 06:56:29 PM PDT 24
Finished Jul 14 06:56:52 PM PDT 24
Peak memory 232820 kb
Host smart-0fc05128-cd22-4408-ac2e-a60c1ca4830c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916019351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3916019351
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3174357216
Short name T726
Test name
Test status
Simulation time 17911973779 ps
CPU time 50.87 seconds
Started Jul 14 06:56:44 PM PDT 24
Finished Jul 14 06:57:35 PM PDT 24
Peak memory 232792 kb
Host smart-722676c3-ffbe-4e27-840b-f4f49cee03c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174357216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3174357216
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1810919407
Short name T965
Test name
Test status
Simulation time 3098385178 ps
CPU time 4.89 seconds
Started Jul 14 06:56:28 PM PDT 24
Finished Jul 14 06:56:37 PM PDT 24
Peak memory 232744 kb
Host smart-d4f7d7bc-4b39-4db9-8751-6b8c4cd1e29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810919407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1810919407
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3951682534
Short name T668
Test name
Test status
Simulation time 1252287492 ps
CPU time 10.59 seconds
Started Jul 14 06:56:39 PM PDT 24
Finished Jul 14 06:56:51 PM PDT 24
Peak memory 240780 kb
Host smart-a2c758d5-36e7-4cd2-951e-45847a755398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951682534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3951682534
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2176009205
Short name T510
Test name
Test status
Simulation time 13997144161 ps
CPU time 16.89 seconds
Started Jul 14 06:56:34 PM PDT 24
Finished Jul 14 06:56:52 PM PDT 24
Peak memory 221716 kb
Host smart-8f881c3a-e759-4052-aed0-a499a45f83c5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2176009205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2176009205
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.4103239286
Short name T164
Test name
Test status
Simulation time 13668361721 ps
CPU time 83.88 seconds
Started Jul 14 06:56:45 PM PDT 24
Finished Jul 14 06:58:11 PM PDT 24
Peak memory 250736 kb
Host smart-a555cbd3-12af-4868-813a-c9ddf94c67fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103239286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.4103239286
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2274656984
Short name T525
Test name
Test status
Simulation time 6101715253 ps
CPU time 26.95 seconds
Started Jul 14 06:56:27 PM PDT 24
Finished Jul 14 06:56:59 PM PDT 24
Peak memory 216412 kb
Host smart-32fcb935-f8e8-492c-be42-b9e86ef3e45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274656984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2274656984
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.4142072373
Short name T891
Test name
Test status
Simulation time 45056082264 ps
CPU time 16.51 seconds
Started Jul 14 06:56:45 PM PDT 24
Finished Jul 14 06:57:02 PM PDT 24
Peak memory 216444 kb
Host smart-e6d7ff01-7f1f-40b6-b843-c7bbdd6c67b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142072373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.4142072373
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.721824921
Short name T371
Test name
Test status
Simulation time 438996985 ps
CPU time 2.05 seconds
Started Jul 14 06:56:44 PM PDT 24
Finished Jul 14 06:56:47 PM PDT 24
Peak memory 208080 kb
Host smart-9060dfcf-8f5a-4331-aac3-d1703bc8d1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721824921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.721824921
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1798593068
Short name T901
Test name
Test status
Simulation time 11656176 ps
CPU time 0.7 seconds
Started Jul 14 06:56:33 PM PDT 24
Finished Jul 14 06:56:36 PM PDT 24
Peak memory 205608 kb
Host smart-1fd7bb70-9ff9-463f-a97f-fb32fd561609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798593068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1798593068
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3331053963
Short name T451
Test name
Test status
Simulation time 6400495836 ps
CPU time 6.91 seconds
Started Jul 14 06:56:31 PM PDT 24
Finished Jul 14 06:56:40 PM PDT 24
Peak memory 232856 kb
Host smart-e956adb0-be5e-4c77-8f43-609dd0f34c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331053963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3331053963
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2175507279
Short name T878
Test name
Test status
Simulation time 20536611 ps
CPU time 0.71 seconds
Started Jul 14 06:56:42 PM PDT 24
Finished Jul 14 06:56:43 PM PDT 24
Peak memory 205496 kb
Host smart-292bfa91-2e0e-4dc6-a636-14eb5afdc967
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175507279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2175507279
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3131933463
Short name T812
Test name
Test status
Simulation time 106520774 ps
CPU time 2.53 seconds
Started Jul 14 06:56:33 PM PDT 24
Finished Jul 14 06:56:38 PM PDT 24
Peak memory 224424 kb
Host smart-2d017f79-6c82-4f87-b6a0-cc3e654124ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131933463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3131933463
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.692030451
Short name T532
Test name
Test status
Simulation time 18695204 ps
CPU time 0.73 seconds
Started Jul 14 06:56:47 PM PDT 24
Finished Jul 14 06:56:50 PM PDT 24
Peak memory 206396 kb
Host smart-1429b769-a073-4312-8fdf-34b7cfb04969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692030451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.692030451
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1681007634
Short name T224
Test name
Test status
Simulation time 30268262956 ps
CPU time 116.8 seconds
Started Jul 14 06:56:48 PM PDT 24
Finished Jul 14 06:58:48 PM PDT 24
Peak memory 248976 kb
Host smart-a131bd25-dfff-4f9a-a67b-d7480ba55da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681007634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1681007634
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.626192262
Short name T607
Test name
Test status
Simulation time 384989253850 ps
CPU time 156.1 seconds
Started Jul 14 06:56:48 PM PDT 24
Finished Jul 14 06:59:28 PM PDT 24
Peak memory 240840 kb
Host smart-2fba30b7-0ea3-4ff9-8722-fab37f28a801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626192262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.626192262
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.761501537
Short name T739
Test name
Test status
Simulation time 334481158984 ps
CPU time 484.11 seconds
Started Jul 14 06:56:49 PM PDT 24
Finished Jul 14 07:04:57 PM PDT 24
Peak memory 256888 kb
Host smart-19c89146-9c3c-4171-924f-5352bc6bc04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761501537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.761501537
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2567506706
Short name T950
Test name
Test status
Simulation time 44929360716 ps
CPU time 38.18 seconds
Started Jul 14 06:56:50 PM PDT 24
Finished Jul 14 06:57:36 PM PDT 24
Peak memory 239276 kb
Host smart-2dd875db-c8b1-4dee-a322-6de50afda1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567506706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2567506706
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.3906900019
Short name T5
Test name
Test status
Simulation time 2410244410 ps
CPU time 16.69 seconds
Started Jul 14 06:56:47 PM PDT 24
Finished Jul 14 06:57:10 PM PDT 24
Peak memory 224400 kb
Host smart-3853dbad-0071-42ed-a7cc-e1a8bb346a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906900019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.3906900019
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1886848251
Short name T559
Test name
Test status
Simulation time 121602509 ps
CPU time 2.67 seconds
Started Jul 14 06:56:59 PM PDT 24
Finished Jul 14 06:57:04 PM PDT 24
Peak memory 226644 kb
Host smart-d6031a0e-1ff8-4531-b5c8-7f0898fbdf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886848251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1886848251
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3448618368
Short name T360
Test name
Test status
Simulation time 2099570049 ps
CPU time 19.16 seconds
Started Jul 14 06:56:33 PM PDT 24
Finished Jul 14 06:56:54 PM PDT 24
Peak memory 233968 kb
Host smart-2f288714-ee2c-49d2-84d3-8d1e292e5b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448618368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3448618368
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1802646358
Short name T665
Test name
Test status
Simulation time 21101553293 ps
CPU time 29.04 seconds
Started Jul 14 06:56:47 PM PDT 24
Finished Jul 14 06:57:19 PM PDT 24
Peak memory 233768 kb
Host smart-96920e3b-ab77-4f16-968d-bc3d3f04ec24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802646358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1802646358
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2315224724
Short name T520
Test name
Test status
Simulation time 57832551244 ps
CPU time 21.15 seconds
Started Jul 14 06:56:46 PM PDT 24
Finished Jul 14 06:57:09 PM PDT 24
Peak memory 232524 kb
Host smart-7e7daf1a-c050-424e-b843-75698429d0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315224724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2315224724
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.706869034
Short name T772
Test name
Test status
Simulation time 2678171159 ps
CPU time 5.84 seconds
Started Jul 14 06:56:32 PM PDT 24
Finished Jul 14 06:56:40 PM PDT 24
Peak memory 223156 kb
Host smart-3c7f7db2-5caa-4547-9f5e-968963b3abdd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=706869034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.706869034
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.183156182
Short name T908
Test name
Test status
Simulation time 129021533518 ps
CPU time 294.26 seconds
Started Jul 14 06:56:55 PM PDT 24
Finished Jul 14 07:01:52 PM PDT 24
Peak memory 250072 kb
Host smart-4a69822a-58eb-457e-b282-47120cfe1f02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183156182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.183156182
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.965758817
Short name T501
Test name
Test status
Simulation time 1543411559 ps
CPU time 8.95 seconds
Started Jul 14 06:56:38 PM PDT 24
Finished Jul 14 06:56:48 PM PDT 24
Peak memory 216444 kb
Host smart-8990577b-b68f-44cc-baa9-f5fc828ce3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965758817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.965758817
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.741270549
Short name T716
Test name
Test status
Simulation time 199081392 ps
CPU time 1.47 seconds
Started Jul 14 06:56:46 PM PDT 24
Finished Jul 14 06:56:50 PM PDT 24
Peak memory 207300 kb
Host smart-7d53261e-2f07-4738-9e99-6a18df663b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741270549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.741270549
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.4060059104
Short name T404
Test name
Test status
Simulation time 160965572 ps
CPU time 1.21 seconds
Started Jul 14 06:56:48 PM PDT 24
Finished Jul 14 06:56:55 PM PDT 24
Peak memory 207832 kb
Host smart-dffb5e9f-8dd1-4bf4-bebb-f68bb2654071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060059104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.4060059104
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3810435919
Short name T30
Test name
Test status
Simulation time 52286340 ps
CPU time 0.84 seconds
Started Jul 14 06:56:38 PM PDT 24
Finished Jul 14 06:56:40 PM PDT 24
Peak memory 205952 kb
Host smart-5d6572ec-9f51-4673-8556-69ccbbd5453b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810435919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3810435919
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1135025736
Short name T893
Test name
Test status
Simulation time 1585657119 ps
CPU time 5.89 seconds
Started Jul 14 06:56:39 PM PDT 24
Finished Jul 14 06:56:46 PM PDT 24
Peak memory 232660 kb
Host smart-f778febb-b939-4e8a-8354-6b9ebcb0df93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135025736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1135025736
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1012263701
Short name T632
Test name
Test status
Simulation time 30766872 ps
CPU time 0.7 seconds
Started Jul 14 06:56:50 PM PDT 24
Finished Jul 14 06:56:55 PM PDT 24
Peak memory 205528 kb
Host smart-88ebcaea-4fc8-46b2-a815-f46c40966047
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012263701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1012263701
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3781474043
Short name T37
Test name
Test status
Simulation time 1040532385 ps
CPU time 5.23 seconds
Started Jul 14 06:56:45 PM PDT 24
Finished Jul 14 06:56:51 PM PDT 24
Peak memory 224500 kb
Host smart-9f886001-0e55-48f9-8e42-8296ca9d27c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781474043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3781474043
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.526384854
Short name T504
Test name
Test status
Simulation time 55227412 ps
CPU time 0.81 seconds
Started Jul 14 06:56:48 PM PDT 24
Finished Jul 14 06:56:52 PM PDT 24
Peak memory 205568 kb
Host smart-376b94a0-d588-4bca-8584-ef6c72b33be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526384854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.526384854
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3181222972
Short name T546
Test name
Test status
Simulation time 5577418363 ps
CPU time 58.67 seconds
Started Jul 14 06:56:57 PM PDT 24
Finished Jul 14 06:57:57 PM PDT 24
Peak memory 257320 kb
Host smart-6b434ddb-94a4-40dc-9651-69805cd589ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181222972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3181222972
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1101707219
Short name T15
Test name
Test status
Simulation time 19465374297 ps
CPU time 196.19 seconds
Started Jul 14 06:56:46 PM PDT 24
Finished Jul 14 07:00:05 PM PDT 24
Peak memory 249420 kb
Host smart-e6728ecb-bb7c-45ab-ae7d-4e92c6deb217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101707219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1101707219
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1659288677
Short name T365
Test name
Test status
Simulation time 5374756552 ps
CPU time 25.84 seconds
Started Jul 14 06:57:03 PM PDT 24
Finished Jul 14 06:57:29 PM PDT 24
Peak memory 217792 kb
Host smart-9bbec159-e507-4a38-a6f4-c2c8a681d3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659288677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1659288677
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3015301060
Short name T287
Test name
Test status
Simulation time 781996999 ps
CPU time 4.94 seconds
Started Jul 14 06:56:49 PM PDT 24
Finished Jul 14 06:56:59 PM PDT 24
Peak memory 224476 kb
Host smart-211480be-0785-411c-8219-8dd559f50def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015301060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3015301060
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.456419719
Short name T918
Test name
Test status
Simulation time 25975975 ps
CPU time 0.72 seconds
Started Jul 14 06:56:52 PM PDT 24
Finished Jul 14 06:56:56 PM PDT 24
Peak memory 215596 kb
Host smart-15700c0e-884b-4477-a066-e3bbdd702b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456419719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds
.456419719
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2944320705
Short name T227
Test name
Test status
Simulation time 210494805 ps
CPU time 4.68 seconds
Started Jul 14 06:56:47 PM PDT 24
Finished Jul 14 06:56:56 PM PDT 24
Peak memory 232428 kb
Host smart-b6d2f4ec-e5e1-4165-9656-687d5a1a7eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944320705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2944320705
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.569604044
Short name T512
Test name
Test status
Simulation time 36475405152 ps
CPU time 64.27 seconds
Started Jul 14 06:56:47 PM PDT 24
Finished Jul 14 06:57:54 PM PDT 24
Peak memory 224332 kb
Host smart-233b6a5a-09f4-42d3-9355-d9fe6f2c3d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569604044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.569604044
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.274085603
Short name T264
Test name
Test status
Simulation time 19392804161 ps
CPU time 30 seconds
Started Jul 14 06:56:48 PM PDT 24
Finished Jul 14 06:57:22 PM PDT 24
Peak memory 249084 kb
Host smart-f6bb6a11-33fb-4b0f-b576-cefbb952f736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274085603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.274085603
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3624157850
Short name T836
Test name
Test status
Simulation time 5323154346 ps
CPU time 7.02 seconds
Started Jul 14 06:56:37 PM PDT 24
Finished Jul 14 06:56:45 PM PDT 24
Peak memory 224804 kb
Host smart-fa0b5edc-5423-424d-a5df-676b26f0033c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624157850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3624157850
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2496756241
Short name T49
Test name
Test status
Simulation time 568572299 ps
CPU time 5.89 seconds
Started Jul 14 06:56:57 PM PDT 24
Finished Jul 14 06:57:04 PM PDT 24
Peak memory 222508 kb
Host smart-4b5a866a-a5f5-48db-b8c8-b9060319ce42
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2496756241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2496756241
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.168875313
Short name T934
Test name
Test status
Simulation time 124353053311 ps
CPU time 225.75 seconds
Started Jul 14 06:56:49 PM PDT 24
Finished Jul 14 07:00:39 PM PDT 24
Peak memory 239952 kb
Host smart-94fdf982-87bd-41eb-81ed-affbb0fa1ce0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168875313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.168875313
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1029685009
Short name T696
Test name
Test status
Simulation time 5179648819 ps
CPU time 26.84 seconds
Started Jul 14 06:56:48 PM PDT 24
Finished Jul 14 06:57:19 PM PDT 24
Peak memory 216104 kb
Host smart-7807255c-e117-4326-85ef-15c452bc4cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029685009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1029685009
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2396609506
Short name T777
Test name
Test status
Simulation time 421111711 ps
CPU time 3.34 seconds
Started Jul 14 06:56:42 PM PDT 24
Finished Jul 14 06:56:46 PM PDT 24
Peak memory 216248 kb
Host smart-0de02e7a-cd59-4646-ad4c-b74d4e88121c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396609506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2396609506
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3085894811
Short name T435
Test name
Test status
Simulation time 2277786862 ps
CPU time 2.87 seconds
Started Jul 14 06:56:47 PM PDT 24
Finished Jul 14 06:56:53 PM PDT 24
Peak memory 216332 kb
Host smart-f5242179-73f3-4e09-98cb-c555c7d25058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085894811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3085894811
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1348836432
Short name T925
Test name
Test status
Simulation time 136486856 ps
CPU time 0.74 seconds
Started Jul 14 06:56:35 PM PDT 24
Finished Jul 14 06:56:37 PM PDT 24
Peak memory 205784 kb
Host smart-77c85891-c3f7-45d6-af23-855e893a90b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348836432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1348836432
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1015279084
Short name T661
Test name
Test status
Simulation time 20252072363 ps
CPU time 17.93 seconds
Started Jul 14 06:56:46 PM PDT 24
Finished Jul 14 06:57:05 PM PDT 24
Peak memory 232836 kb
Host smart-7139a931-d494-48e0-a6c1-7835fb9bfbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015279084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1015279084
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3864624850
Short name T996
Test name
Test status
Simulation time 14345391 ps
CPU time 0.73 seconds
Started Jul 14 06:56:40 PM PDT 24
Finished Jul 14 06:56:41 PM PDT 24
Peak memory 205020 kb
Host smart-030bb7fb-fbe9-4393-8a48-5657d65e3673
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864624850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3864624850
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.676919278
Short name T983
Test name
Test status
Simulation time 397378157 ps
CPU time 2.32 seconds
Started Jul 14 06:56:47 PM PDT 24
Finished Jul 14 06:56:53 PM PDT 24
Peak memory 224480 kb
Host smart-2ce434a1-574c-473f-98c7-94d648cff01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676919278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.676919278
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.895118427
Short name T979
Test name
Test status
Simulation time 24190825 ps
CPU time 0.82 seconds
Started Jul 14 06:56:52 PM PDT 24
Finished Jul 14 06:56:57 PM PDT 24
Peak memory 206636 kb
Host smart-e11862a2-684b-4e40-a7cb-3b0b1b5b9481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895118427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.895118427
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3805069284
Short name T240
Test name
Test status
Simulation time 416526129676 ps
CPU time 333.36 seconds
Started Jul 14 06:56:53 PM PDT 24
Finished Jul 14 07:02:30 PM PDT 24
Peak memory 257168 kb
Host smart-1367c618-448d-4535-81e6-92392c87c9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805069284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3805069284
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3934283666
Short name T1002
Test name
Test status
Simulation time 27402059177 ps
CPU time 264.84 seconds
Started Jul 14 06:56:44 PM PDT 24
Finished Jul 14 07:01:10 PM PDT 24
Peak memory 251116 kb
Host smart-0e5924dd-d99a-43fa-afe9-64a8ca2c6677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934283666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3934283666
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3961412762
Short name T340
Test name
Test status
Simulation time 526143486 ps
CPU time 3.58 seconds
Started Jul 14 06:56:52 PM PDT 24
Finished Jul 14 06:57:00 PM PDT 24
Peak memory 232504 kb
Host smart-56ed32f9-2cca-4d55-abf0-97bebdca6792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961412762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3961412762
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.2340649785
Short name T382
Test name
Test status
Simulation time 1190571840 ps
CPU time 4.17 seconds
Started Jul 14 06:56:51 PM PDT 24
Finished Jul 14 06:56:59 PM PDT 24
Peak memory 233720 kb
Host smart-05f4af75-6b49-419d-8a04-bf60a5c7e298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340649785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.2340649785
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.4196658329
Short name T676
Test name
Test status
Simulation time 3396201491 ps
CPU time 20.12 seconds
Started Jul 14 06:56:49 PM PDT 24
Finished Jul 14 06:57:18 PM PDT 24
Peak memory 220548 kb
Host smart-850f1f9b-17ec-495d-aa9c-346b2b64e382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196658329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.4196658329
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.761452122
Short name T765
Test name
Test status
Simulation time 2413422627 ps
CPU time 20.99 seconds
Started Jul 14 06:56:54 PM PDT 24
Finished Jul 14 06:57:18 PM PDT 24
Peak memory 236640 kb
Host smart-c89548c2-2e38-4ff1-aabc-3ae59ee24b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761452122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.761452122
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.238396239
Short name T261
Test name
Test status
Simulation time 693120961 ps
CPU time 4.3 seconds
Started Jul 14 06:56:44 PM PDT 24
Finished Jul 14 06:56:49 PM PDT 24
Peak memory 232608 kb
Host smart-3fbc1df8-f3f8-4d0d-b392-a00c133bfa28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238396239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.238396239
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2389945334
Short name T877
Test name
Test status
Simulation time 61656167 ps
CPU time 2.49 seconds
Started Jul 14 06:56:44 PM PDT 24
Finished Jul 14 06:56:47 PM PDT 24
Peak memory 232512 kb
Host smart-9103599d-de5a-453f-8f38-9a747a0e49d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389945334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2389945334
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1273907386
Short name T459
Test name
Test status
Simulation time 605488966 ps
CPU time 8.88 seconds
Started Jul 14 06:56:45 PM PDT 24
Finished Jul 14 06:56:55 PM PDT 24
Peak memory 218704 kb
Host smart-9140409a-dd78-423c-8dfb-93b7376f16f7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1273907386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1273907386
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3530201309
Short name T356
Test name
Test status
Simulation time 3333486909 ps
CPU time 16.97 seconds
Started Jul 14 06:56:50 PM PDT 24
Finished Jul 14 06:57:11 PM PDT 24
Peak memory 216564 kb
Host smart-1b3c6579-5bd9-402a-9ec3-62c426ee8769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530201309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3530201309
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1089433300
Short name T312
Test name
Test status
Simulation time 21802783657 ps
CPU time 14.45 seconds
Started Jul 14 06:56:47 PM PDT 24
Finished Jul 14 06:57:04 PM PDT 24
Peak memory 216352 kb
Host smart-aa465a31-b78b-4a3b-9e79-43eaad2075b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089433300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1089433300
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.4137278599
Short name T418
Test name
Test status
Simulation time 119309492 ps
CPU time 2.24 seconds
Started Jul 14 06:56:45 PM PDT 24
Finished Jul 14 06:56:48 PM PDT 24
Peak memory 216252 kb
Host smart-0659a245-cad0-4ed6-86d3-42b93c99d659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137278599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.4137278599
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3077209466
Short name T562
Test name
Test status
Simulation time 226308796 ps
CPU time 0.85 seconds
Started Jul 14 06:56:46 PM PDT 24
Finished Jul 14 06:56:50 PM PDT 24
Peak memory 205912 kb
Host smart-039c1951-8191-4162-8239-8d8a0782708b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077209466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3077209466
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1584461723
Short name T555
Test name
Test status
Simulation time 2710474113 ps
CPU time 12.53 seconds
Started Jul 14 06:56:50 PM PDT 24
Finished Jul 14 06:57:07 PM PDT 24
Peak memory 232784 kb
Host smart-6ed7895f-d0ac-473c-8329-283776521615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584461723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1584461723
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1324568689
Short name T527
Test name
Test status
Simulation time 30044347 ps
CPU time 0.71 seconds
Started Jul 14 06:56:55 PM PDT 24
Finished Jul 14 06:56:58 PM PDT 24
Peak memory 205856 kb
Host smart-7a7b9237-51a4-481d-ad93-07ee7d498ac4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324568689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1324568689
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1233253080
Short name T447
Test name
Test status
Simulation time 77934708 ps
CPU time 2.7 seconds
Started Jul 14 06:56:49 PM PDT 24
Finished Jul 14 06:56:56 PM PDT 24
Peak memory 232608 kb
Host smart-7af3bd9c-6cd1-4b7c-91b3-c665b1cf7e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233253080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1233253080
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.408464067
Short name T323
Test name
Test status
Simulation time 22493726 ps
CPU time 0.83 seconds
Started Jul 14 06:56:47 PM PDT 24
Finished Jul 14 06:56:50 PM PDT 24
Peak memory 206588 kb
Host smart-74b56797-3a9a-4b43-a155-78811592f17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408464067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.408464067
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.523565370
Short name T816
Test name
Test status
Simulation time 20457847727 ps
CPU time 57.68 seconds
Started Jul 14 06:56:56 PM PDT 24
Finished Jul 14 06:57:56 PM PDT 24
Peak memory 249200 kb
Host smart-6c92018a-396c-4b3a-891d-38c563505dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523565370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.523565370
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1162621894
Short name T802
Test name
Test status
Simulation time 2638331952 ps
CPU time 61.02 seconds
Started Jul 14 06:56:50 PM PDT 24
Finished Jul 14 06:57:55 PM PDT 24
Peak memory 249268 kb
Host smart-e1cf1646-3541-4b43-bce9-c61e549f0a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162621894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1162621894
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1011451983
Short name T788
Test name
Test status
Simulation time 38017837769 ps
CPU time 320.45 seconds
Started Jul 14 06:56:57 PM PDT 24
Finished Jul 14 07:02:20 PM PDT 24
Peak memory 257284 kb
Host smart-5b3862d5-a463-4bdc-853c-dfaac55b57b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011451983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1011451983
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.1672055017
Short name T325
Test name
Test status
Simulation time 22007905761 ps
CPU time 73.94 seconds
Started Jul 14 06:56:49 PM PDT 24
Finished Jul 14 06:58:10 PM PDT 24
Peak memory 240988 kb
Host smart-1b5fd5ac-2eed-4127-b1e3-e10b6d67947d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672055017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.1672055017
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2046068757
Short name T238
Test name
Test status
Simulation time 68941410 ps
CPU time 3.13 seconds
Started Jul 14 06:56:46 PM PDT 24
Finished Jul 14 06:56:52 PM PDT 24
Peak memory 232668 kb
Host smart-e6de7548-39c2-4c62-9b6d-41d5f77cd559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046068757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2046068757
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1253220925
Short name T624
Test name
Test status
Simulation time 2207631162 ps
CPU time 7.88 seconds
Started Jul 14 06:56:49 PM PDT 24
Finished Jul 14 06:57:01 PM PDT 24
Peak memory 232752 kb
Host smart-c8e932b2-f55f-433b-be46-88b1e525fbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253220925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1253220925
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2272381702
Short name T267
Test name
Test status
Simulation time 12424993594 ps
CPU time 11.08 seconds
Started Jul 14 06:56:50 PM PDT 24
Finished Jul 14 06:57:05 PM PDT 24
Peak memory 240884 kb
Host smart-0a1d444d-ff49-4d45-aa7b-fa21e88eed70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272381702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2272381702
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2119625722
Short name T686
Test name
Test status
Simulation time 137822316 ps
CPU time 2.64 seconds
Started Jul 14 06:56:49 PM PDT 24
Finished Jul 14 06:56:56 PM PDT 24
Peak memory 232644 kb
Host smart-668c9fac-2969-4c9d-9846-62ee5641aef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119625722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2119625722
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1941030373
Short name T51
Test name
Test status
Simulation time 328961215 ps
CPU time 6.3 seconds
Started Jul 14 06:56:59 PM PDT 24
Finished Jul 14 06:57:08 PM PDT 24
Peak memory 223068 kb
Host smart-5b6f9b93-4ef0-48cb-b9d5-86015b4d31a8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1941030373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1941030373
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3581527949
Short name T32
Test name
Test status
Simulation time 6190703000 ps
CPU time 53.57 seconds
Started Jul 14 06:56:49 PM PDT 24
Finished Jul 14 06:57:46 PM PDT 24
Peak memory 239204 kb
Host smart-f8a0fafb-d9d5-4ee4-8f3e-4c3977d5929d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581527949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3581527949
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.561653403
Short name T406
Test name
Test status
Simulation time 3230983707 ps
CPU time 11.99 seconds
Started Jul 14 06:56:51 PM PDT 24
Finished Jul 14 06:57:07 PM PDT 24
Peak memory 216340 kb
Host smart-c5d92d29-8f0c-47e2-977c-345f37483aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561653403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.561653403
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2812486369
Short name T600
Test name
Test status
Simulation time 886433384 ps
CPU time 2.37 seconds
Started Jul 14 06:56:55 PM PDT 24
Finished Jul 14 06:57:00 PM PDT 24
Peak memory 216180 kb
Host smart-28daf2c1-8320-4105-a4ba-41293447c22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812486369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2812486369
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.45297648
Short name T11
Test name
Test status
Simulation time 74383020 ps
CPU time 0.97 seconds
Started Jul 14 06:56:50 PM PDT 24
Finished Jul 14 06:56:55 PM PDT 24
Peak memory 207008 kb
Host smart-43f8f7c3-e6c6-4afb-8abc-c959826f1393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45297648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.45297648
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1177318718
Short name T6
Test name
Test status
Simulation time 136551382 ps
CPU time 0.78 seconds
Started Jul 14 06:56:49 PM PDT 24
Finished Jul 14 06:56:54 PM PDT 24
Peak memory 205936 kb
Host smart-7372117e-8e7b-4e08-9cab-1adbb635b470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177318718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1177318718
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.85138652
Short name T640
Test name
Test status
Simulation time 1197715055 ps
CPU time 8.26 seconds
Started Jul 14 06:56:51 PM PDT 24
Finished Jul 14 06:57:03 PM PDT 24
Peak memory 232704 kb
Host smart-1e3fd7de-c678-421d-9fb1-5bae1e050a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85138652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.85138652
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3526862901
Short name T972
Test name
Test status
Simulation time 39267693 ps
CPU time 0.74 seconds
Started Jul 14 06:56:49 PM PDT 24
Finished Jul 14 06:56:56 PM PDT 24
Peak memory 204960 kb
Host smart-e01535ef-ef08-4737-8aca-64bc690bfb0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526862901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3526862901
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1949345664
Short name T423
Test name
Test status
Simulation time 40228314 ps
CPU time 2.36 seconds
Started Jul 14 06:56:56 PM PDT 24
Finished Jul 14 06:57:00 PM PDT 24
Peak memory 232656 kb
Host smart-313f6681-f485-4fab-925d-2690e88a5348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949345664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1949345664
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3225209106
Short name T749
Test name
Test status
Simulation time 49533379 ps
CPU time 0.76 seconds
Started Jul 14 06:56:49 PM PDT 24
Finished Jul 14 06:56:54 PM PDT 24
Peak memory 205608 kb
Host smart-8a2f5e49-742d-45ed-a36c-c991a682cdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225209106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3225209106
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1771011807
Short name T970
Test name
Test status
Simulation time 4201878780 ps
CPU time 41.35 seconds
Started Jul 14 06:57:04 PM PDT 24
Finished Jul 14 06:57:46 PM PDT 24
Peak memory 249228 kb
Host smart-5fc6bdc6-467e-4628-846c-f1efe15dc3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771011807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1771011807
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3467320721
Short name T492
Test name
Test status
Simulation time 49677370180 ps
CPU time 225.76 seconds
Started Jul 14 06:56:52 PM PDT 24
Finished Jul 14 07:00:42 PM PDT 24
Peak memory 252404 kb
Host smart-833d095f-77c7-4e44-b65f-882dbb43088d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467320721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3467320721
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1813090814
Short name T763
Test name
Test status
Simulation time 3662949464 ps
CPU time 12.73 seconds
Started Jul 14 06:56:51 PM PDT 24
Finished Jul 14 06:57:08 PM PDT 24
Peak memory 240920 kb
Host smart-3dd207e4-27b1-41b4-bd45-789c2a8f7496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813090814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1813090814
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.3899554744
Short name T561
Test name
Test status
Simulation time 10317960712 ps
CPU time 36.5 seconds
Started Jul 14 06:56:47 PM PDT 24
Finished Jul 14 06:57:27 PM PDT 24
Peak memory 224636 kb
Host smart-16170149-91e5-40ea-9c0d-613350b9188e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899554744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.3899554744
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1041442801
Short name T211
Test name
Test status
Simulation time 4510582463 ps
CPU time 13.74 seconds
Started Jul 14 06:56:49 PM PDT 24
Finished Jul 14 06:57:07 PM PDT 24
Peak memory 224580 kb
Host smart-f35fbb03-7548-4332-9c46-02863e74b3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041442801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1041442801
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1419185583
Short name T425
Test name
Test status
Simulation time 3125661154 ps
CPU time 22.86 seconds
Started Jul 14 06:56:55 PM PDT 24
Finished Jul 14 06:57:20 PM PDT 24
Peak memory 249024 kb
Host smart-2876c443-5ed5-4a65-aa55-1ced74b265d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419185583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1419185583
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2538545462
Short name T55
Test name
Test status
Simulation time 6247391673 ps
CPU time 14.74 seconds
Started Jul 14 06:56:47 PM PDT 24
Finished Jul 14 06:57:04 PM PDT 24
Peak memory 232824 kb
Host smart-fd004b40-0886-4994-9b0a-6d6dbbd54ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538545462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2538545462
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3216541162
Short name T903
Test name
Test status
Simulation time 164517266 ps
CPU time 2.44 seconds
Started Jul 14 06:56:52 PM PDT 24
Finished Jul 14 06:56:59 PM PDT 24
Peak memory 232668 kb
Host smart-e4ac6983-2566-4004-a9d6-22e4fc7a6ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216541162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3216541162
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1574993915
Short name T420
Test name
Test status
Simulation time 5203703832 ps
CPU time 11.03 seconds
Started Jul 14 06:56:49 PM PDT 24
Finished Jul 14 06:57:05 PM PDT 24
Peak memory 222408 kb
Host smart-708d6585-7c14-4acf-b167-862388c12757
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1574993915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1574993915
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.372388888
Short name T272
Test name
Test status
Simulation time 37024536269 ps
CPU time 270.26 seconds
Started Jul 14 06:56:46 PM PDT 24
Finished Jul 14 07:01:18 PM PDT 24
Peak memory 255212 kb
Host smart-0f24084b-8e2d-4be6-9a56-3548e528ebe2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372388888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.372388888
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1111067228
Short name T135
Test name
Test status
Simulation time 799235484 ps
CPU time 4.87 seconds
Started Jul 14 06:56:57 PM PDT 24
Finished Jul 14 06:57:04 PM PDT 24
Peak memory 216220 kb
Host smart-97e1a0fd-231b-496e-9c19-142157accbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111067228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1111067228
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3971865664
Short name T790
Test name
Test status
Simulation time 909897966 ps
CPU time 4.49 seconds
Started Jul 14 06:56:52 PM PDT 24
Finished Jul 14 06:57:00 PM PDT 24
Peak memory 216228 kb
Host smart-05f726d3-5a1f-445f-a902-9aba98df700a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971865664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3971865664
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3557087708
Short name T138
Test name
Test status
Simulation time 10655076 ps
CPU time 0.65 seconds
Started Jul 14 06:56:50 PM PDT 24
Finished Jul 14 06:56:56 PM PDT 24
Peak memory 205668 kb
Host smart-f339713a-66cb-4950-be6f-dd6d7188144a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557087708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3557087708
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.338624597
Short name T38
Test name
Test status
Simulation time 42427263 ps
CPU time 0.71 seconds
Started Jul 14 06:56:51 PM PDT 24
Finished Jul 14 06:56:56 PM PDT 24
Peak memory 206000 kb
Host smart-3f389ed8-33bc-4a7c-995a-a44cc7c6dbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338624597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.338624597
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2950681521
Short name T237
Test name
Test status
Simulation time 405970449 ps
CPU time 6.32 seconds
Started Jul 14 06:56:59 PM PDT 24
Finished Jul 14 06:57:07 PM PDT 24
Peak memory 232496 kb
Host smart-b1379fa1-c17f-436a-9bdd-fa250864751d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950681521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2950681521
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1495044144
Short name T402
Test name
Test status
Simulation time 42351632 ps
CPU time 0.73 seconds
Started Jul 14 06:55:01 PM PDT 24
Finished Jul 14 06:55:05 PM PDT 24
Peak memory 205484 kb
Host smart-53217695-751a-47cd-b237-87245647e868
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495044144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
495044144
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.265488553
Short name T662
Test name
Test status
Simulation time 480727804 ps
CPU time 4.47 seconds
Started Jul 14 06:55:52 PM PDT 24
Finished Jul 14 06:55:58 PM PDT 24
Peak memory 232416 kb
Host smart-1e8cf6d6-f7b4-4cba-9ed6-c40acc272125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265488553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.265488553
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2215394415
Short name T804
Test name
Test status
Simulation time 19057993 ps
CPU time 0.8 seconds
Started Jul 14 06:54:38 PM PDT 24
Finished Jul 14 06:54:41 PM PDT 24
Peak memory 206900 kb
Host smart-e89ba2c4-7d08-4085-a02e-c5e6b2e294d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215394415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2215394415
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.866810504
Short name T677
Test name
Test status
Simulation time 2382648416 ps
CPU time 52.98 seconds
Started Jul 14 06:54:53 PM PDT 24
Finished Jul 14 06:55:47 PM PDT 24
Peak memory 255468 kb
Host smart-a1825618-b19a-47da-9293-f04c383e0f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866810504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.866810504
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3240645067
Short name T399
Test name
Test status
Simulation time 2641326590 ps
CPU time 30.56 seconds
Started Jul 14 06:55:01 PM PDT 24
Finished Jul 14 06:55:35 PM PDT 24
Peak memory 249276 kb
Host smart-7b3f4b73-aac9-4c2a-95e6-228ef8e7699c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240645067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3240645067
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3004135325
Short name T582
Test name
Test status
Simulation time 3951272820 ps
CPU time 41.38 seconds
Started Jul 14 06:55:08 PM PDT 24
Finished Jul 14 06:55:54 PM PDT 24
Peak memory 241292 kb
Host smart-1d0b5a75-c9b7-4aac-b4a7-268c81a50b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004135325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3004135325
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2303755451
Short name T524
Test name
Test status
Simulation time 2270438264 ps
CPU time 10.02 seconds
Started Jul 14 06:55:08 PM PDT 24
Finished Jul 14 06:55:24 PM PDT 24
Peak memory 232776 kb
Host smart-d296cc5d-ef68-4905-b3d6-aa805327714b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303755451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2303755451
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.2285983589
Short name T782
Test name
Test status
Simulation time 20215641 ps
CPU time 0.79 seconds
Started Jul 14 06:55:03 PM PDT 24
Finished Jul 14 06:55:07 PM PDT 24
Peak memory 215748 kb
Host smart-7c68e90c-d5f0-4ba4-adb3-5256e90226e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285983589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.2285983589
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1562607446
Short name T828
Test name
Test status
Simulation time 1900188256 ps
CPU time 20.8 seconds
Started Jul 14 06:54:35 PM PDT 24
Finished Jul 14 06:55:00 PM PDT 24
Peak memory 224500 kb
Host smart-618f62c8-4876-431c-99c9-3f3f87945002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562607446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1562607446
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.853124897
Short name T888
Test name
Test status
Simulation time 65053407 ps
CPU time 2.17 seconds
Started Jul 14 06:54:55 PM PDT 24
Finished Jul 14 06:54:58 PM PDT 24
Peak memory 232372 kb
Host smart-fd794686-3bb6-479c-9f0a-54b3d6fe12d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853124897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.853124897
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.127596935
Short name T250
Test name
Test status
Simulation time 940215014 ps
CPU time 5.48 seconds
Started Jul 14 06:54:35 PM PDT 24
Finished Jul 14 06:54:44 PM PDT 24
Peak memory 224476 kb
Host smart-d04324ac-e761-4522-beab-c25cc4a0d3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127596935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
127596935
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.4020396570
Short name T890
Test name
Test status
Simulation time 2201824772 ps
CPU time 8.52 seconds
Started Jul 14 06:55:02 PM PDT 24
Finished Jul 14 06:55:14 PM PDT 24
Peak memory 232736 kb
Host smart-84e51279-80c9-4db4-bcd2-5de7d433d588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020396570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.4020396570
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2416831749
Short name T500
Test name
Test status
Simulation time 315950632 ps
CPU time 4.54 seconds
Started Jul 14 06:54:51 PM PDT 24
Finished Jul 14 06:54:57 PM PDT 24
Peak memory 220244 kb
Host smart-d94c1cef-fd0e-4c05-bfdd-7481fda948aa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2416831749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2416831749
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1876954846
Short name T481
Test name
Test status
Simulation time 37403967 ps
CPU time 0.94 seconds
Started Jul 14 06:55:02 PM PDT 24
Finished Jul 14 06:55:07 PM PDT 24
Peak memory 207576 kb
Host smart-b8b0aa06-de9f-4934-bbf8-a3a7484a5308
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876954846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1876954846
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.392080290
Short name T654
Test name
Test status
Simulation time 525867371 ps
CPU time 2.47 seconds
Started Jul 14 06:55:01 PM PDT 24
Finished Jul 14 06:55:07 PM PDT 24
Peak memory 216196 kb
Host smart-1724668b-50e7-40c6-b78c-91b2c45dd285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392080290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.392080290
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.4159058161
Short name T542
Test name
Test status
Simulation time 2289410234 ps
CPU time 4.3 seconds
Started Jul 14 06:54:52 PM PDT 24
Finished Jul 14 06:54:58 PM PDT 24
Peak memory 216340 kb
Host smart-fd6005ff-0ac6-458e-98f9-c53e171b9511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159058161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.4159058161
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2276604753
Short name T745
Test name
Test status
Simulation time 14270029 ps
CPU time 0.7 seconds
Started Jul 14 06:55:54 PM PDT 24
Finished Jul 14 06:55:58 PM PDT 24
Peak memory 205792 kb
Host smart-1f51d1c8-3871-4a68-98d5-ec81e6119c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276604753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2276604753
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.111096280
Short name T870
Test name
Test status
Simulation time 144730525 ps
CPU time 0.86 seconds
Started Jul 14 06:54:46 PM PDT 24
Finished Jul 14 06:54:50 PM PDT 24
Peak memory 206000 kb
Host smart-bee93879-8daa-4077-b1e7-2526c00d2141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111096280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.111096280
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1756964113
Short name T446
Test name
Test status
Simulation time 956116753 ps
CPU time 3.37 seconds
Started Jul 14 06:54:39 PM PDT 24
Finished Jul 14 06:54:45 PM PDT 24
Peak memory 224420 kb
Host smart-53d329bc-3e62-4aca-b0d6-c4b31a21e057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756964113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1756964113
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2615603558
Short name T737
Test name
Test status
Simulation time 12593706 ps
CPU time 0.72 seconds
Started Jul 14 06:54:45 PM PDT 24
Finished Jul 14 06:54:49 PM PDT 24
Peak memory 205548 kb
Host smart-b7f30228-85df-4e81-8070-759c85fce12e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615603558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
615603558
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1329206248
Short name T674
Test name
Test status
Simulation time 2366615390 ps
CPU time 10.09 seconds
Started Jul 14 06:55:01 PM PDT 24
Finished Jul 14 06:55:14 PM PDT 24
Peak memory 232772 kb
Host smart-6196fb96-ccbf-405a-9826-076f153990c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329206248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1329206248
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.4075002909
Short name T655
Test name
Test status
Simulation time 59196921 ps
CPU time 0.78 seconds
Started Jul 14 06:55:05 PM PDT 24
Finished Jul 14 06:55:12 PM PDT 24
Peak memory 206920 kb
Host smart-923f5670-03ae-4dca-855e-564fe7a4f5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075002909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.4075002909
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.182278071
Short name T87
Test name
Test status
Simulation time 188037918753 ps
CPU time 420.22 seconds
Started Jul 14 06:54:49 PM PDT 24
Finished Jul 14 07:01:52 PM PDT 24
Peak memory 265628 kb
Host smart-140ae5bb-6def-471a-b837-106d2ce80f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182278071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.182278071
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2281397391
Short name T880
Test name
Test status
Simulation time 14959359603 ps
CPU time 165.44 seconds
Started Jul 14 06:54:53 PM PDT 24
Finished Jul 14 06:57:39 PM PDT 24
Peak memory 255996 kb
Host smart-3a8f235f-4c7f-4e03-9e6e-a46ccff80a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281397391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2281397391
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.803745306
Short name T875
Test name
Test status
Simulation time 32831432268 ps
CPU time 162.28 seconds
Started Jul 14 06:55:01 PM PDT 24
Finished Jul 14 06:57:47 PM PDT 24
Peak memory 241012 kb
Host smart-d613684e-9480-417c-ae55-86a3d546c5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803745306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
803745306
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2175005985
Short name T286
Test name
Test status
Simulation time 608127087 ps
CPU time 7.03 seconds
Started Jul 14 06:55:00 PM PDT 24
Finished Jul 14 06:55:10 PM PDT 24
Peak memory 224500 kb
Host smart-67106591-e39b-470d-9395-d743c4e84b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175005985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2175005985
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.3653339922
Short name T799
Test name
Test status
Simulation time 397458214 ps
CPU time 5.55 seconds
Started Jul 14 06:54:54 PM PDT 24
Finished Jul 14 06:55:01 PM PDT 24
Peak memory 219736 kb
Host smart-9757920e-e916-413b-b2b6-eb3f1311bd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653339922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.3653339922
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2580911824
Short name T206
Test name
Test status
Simulation time 544393670 ps
CPU time 6.99 seconds
Started Jul 14 06:54:59 PM PDT 24
Finished Jul 14 06:55:08 PM PDT 24
Peak memory 224456 kb
Host smart-2ec97751-76d2-47f5-840f-7f1f1ffeebc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580911824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2580911824
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.4208057028
Short name T795
Test name
Test status
Simulation time 11764985387 ps
CPU time 60.86 seconds
Started Jul 14 06:55:00 PM PDT 24
Finished Jul 14 06:56:03 PM PDT 24
Peak memory 232708 kb
Host smart-e1605742-ed56-49b8-abe5-1a1adf6d5265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208057028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.4208057028
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.4081856134
Short name T987
Test name
Test status
Simulation time 846311678 ps
CPU time 4.49 seconds
Started Jul 14 06:55:00 PM PDT 24
Finished Jul 14 06:55:07 PM PDT 24
Peak memory 224524 kb
Host smart-8bef56a9-19e2-4efc-b603-dfd36e6c342b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081856134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.4081856134
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.346525185
Short name T497
Test name
Test status
Simulation time 3950460175 ps
CPU time 4.47 seconds
Started Jul 14 06:54:58 PM PDT 24
Finished Jul 14 06:55:04 PM PDT 24
Peak memory 218976 kb
Host smart-e1960cfc-18dc-4131-89af-6794337e9deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346525185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.346525185
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2589479150
Short name T117
Test name
Test status
Simulation time 231234548 ps
CPU time 4.6 seconds
Started Jul 14 06:54:55 PM PDT 24
Finished Jul 14 06:55:01 PM PDT 24
Peak memory 222644 kb
Host smart-fc70425b-b591-48e8-88d7-cebbf7a26d17
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2589479150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2589479150
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1915712931
Short name T279
Test name
Test status
Simulation time 99672049619 ps
CPU time 86.94 seconds
Started Jul 14 06:55:13 PM PDT 24
Finished Jul 14 06:56:44 PM PDT 24
Peak memory 249292 kb
Host smart-8989471f-63eb-477f-8a43-e346df066750
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915712931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1915712931
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2889596877
Short name T357
Test name
Test status
Simulation time 5584188324 ps
CPU time 15.43 seconds
Started Jul 14 06:54:49 PM PDT 24
Finished Jul 14 06:55:07 PM PDT 24
Peak memory 216280 kb
Host smart-8e1b5bd8-439d-4e98-9132-d8ae85203c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889596877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2889596877
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2810704856
Short name T851
Test name
Test status
Simulation time 5432273587 ps
CPU time 6.76 seconds
Started Jul 14 06:54:56 PM PDT 24
Finished Jul 14 06:55:04 PM PDT 24
Peak memory 216316 kb
Host smart-341a9264-5dc6-4dbe-bdf7-64ad432311c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810704856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2810704856
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1832459414
Short name T638
Test name
Test status
Simulation time 85531764 ps
CPU time 0.93 seconds
Started Jul 14 06:55:05 PM PDT 24
Finished Jul 14 06:55:12 PM PDT 24
Peak memory 207888 kb
Host smart-3e22c64a-69a0-4bbe-8d3c-50bc70ca638b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832459414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1832459414
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3299991291
Short name T969
Test name
Test status
Simulation time 52993567 ps
CPU time 0.73 seconds
Started Jul 14 06:55:01 PM PDT 24
Finished Jul 14 06:55:05 PM PDT 24
Peak memory 205984 kb
Host smart-3b7a5ede-7429-44c3-b1b7-7bf6a7537d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299991291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3299991291
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3392927963
Short name T922
Test name
Test status
Simulation time 206871789 ps
CPU time 5.53 seconds
Started Jul 14 06:54:57 PM PDT 24
Finished Jul 14 06:55:03 PM PDT 24
Peak memory 232652 kb
Host smart-0074557f-6576-49e9-b8e8-c3d91cc1eaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392927963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3392927963
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3857090403
Short name T952
Test name
Test status
Simulation time 13707460 ps
CPU time 0.74 seconds
Started Jul 14 06:54:53 PM PDT 24
Finished Jul 14 06:54:54 PM PDT 24
Peak memory 205540 kb
Host smart-913a5897-f41e-431d-96e9-0ad04406026a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857090403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
857090403
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2806359964
Short name T304
Test name
Test status
Simulation time 124398772 ps
CPU time 2.47 seconds
Started Jul 14 06:55:05 PM PDT 24
Finished Jul 14 06:55:13 PM PDT 24
Peak memory 232640 kb
Host smart-23451e6b-dffa-4b17-bd20-b6ab1f3072a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806359964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2806359964
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3615364421
Short name T842
Test name
Test status
Simulation time 16245902 ps
CPU time 0.77 seconds
Started Jul 14 06:55:04 PM PDT 24
Finished Jul 14 06:55:11 PM PDT 24
Peak memory 205892 kb
Host smart-bd8a8d80-ddf5-4f24-81f3-9b57fd50bb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615364421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3615364421
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.64426785
Short name T1007
Test name
Test status
Simulation time 101499883132 ps
CPU time 229.44 seconds
Started Jul 14 06:54:58 PM PDT 24
Finished Jul 14 06:58:48 PM PDT 24
Peak memory 263436 kb
Host smart-b74f5b0c-dc02-4802-acc4-803f6c4f580f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64426785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.64426785
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.4092630468
Short name T265
Test name
Test status
Simulation time 90500338799 ps
CPU time 282.3 seconds
Started Jul 14 06:55:11 PM PDT 24
Finished Jul 14 06:59:58 PM PDT 24
Peak memory 273668 kb
Host smart-3d54a2f6-0cec-4b42-9ffb-c026f1726810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092630468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.4092630468
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2141837166
Short name T900
Test name
Test status
Simulation time 7397371412 ps
CPU time 29.04 seconds
Started Jul 14 06:55:03 PM PDT 24
Finished Jul 14 06:55:36 PM PDT 24
Peak memory 224628 kb
Host smart-751842b9-7988-4bab-86d6-98a23202ad71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141837166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2141837166
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.4274455716
Short name T883
Test name
Test status
Simulation time 2474433359 ps
CPU time 12.91 seconds
Started Jul 14 06:54:59 PM PDT 24
Finished Jul 14 06:55:21 PM PDT 24
Peak memory 233368 kb
Host smart-53232b6e-0b0c-4f5f-80dc-c05f415c82ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274455716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.4274455716
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2509696762
Short name T630
Test name
Test status
Simulation time 398736809 ps
CPU time 4.11 seconds
Started Jul 14 06:54:54 PM PDT 24
Finished Jul 14 06:55:00 PM PDT 24
Peak memory 224448 kb
Host smart-00069068-4efa-49c6-9e19-834a3b2f71ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509696762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2509696762
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2517325930
Short name T226
Test name
Test status
Simulation time 15815906065 ps
CPU time 40.16 seconds
Started Jul 14 06:54:48 PM PDT 24
Finished Jul 14 06:55:31 PM PDT 24
Peak memory 233656 kb
Host smart-1f74c97e-1d4a-44fd-93aa-5c0cbfd91f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517325930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2517325930
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2520778714
Short name T490
Test name
Test status
Simulation time 8381163891 ps
CPU time 9.63 seconds
Started Jul 14 06:55:02 PM PDT 24
Finished Jul 14 06:55:16 PM PDT 24
Peak memory 232768 kb
Host smart-c133c0e6-d935-4a0e-9c06-e131ece579cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520778714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2520778714
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1839286320
Short name T209
Test name
Test status
Simulation time 2471960600 ps
CPU time 6.2 seconds
Started Jul 14 06:54:56 PM PDT 24
Finished Jul 14 06:55:04 PM PDT 24
Peak memory 232820 kb
Host smart-351e4eb9-fe74-4528-b6c3-9a919aa0ee47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839286320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1839286320
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2664114291
Short name T345
Test name
Test status
Simulation time 2272137917 ps
CPU time 11.63 seconds
Started Jul 14 06:54:49 PM PDT 24
Finished Jul 14 06:55:03 PM PDT 24
Peak memory 222076 kb
Host smart-dc9ea70f-d4a2-4100-b4cf-2dc299b520ec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2664114291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2664114291
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1095700900
Short name T997
Test name
Test status
Simulation time 35672224055 ps
CPU time 348.93 seconds
Started Jul 14 06:55:04 PM PDT 24
Finished Jul 14 07:01:04 PM PDT 24
Peak memory 271636 kb
Host smart-7458c250-72c9-4a58-ab80-2beeeb352d83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095700900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1095700900
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.918399311
Short name T436
Test name
Test status
Simulation time 21651416328 ps
CPU time 53.56 seconds
Started Jul 14 06:55:08 PM PDT 24
Finished Jul 14 06:56:07 PM PDT 24
Peak memory 216404 kb
Host smart-5fb9ade6-5fe4-432c-9c1b-e1fa96d904bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918399311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.918399311
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1853720476
Short name T824
Test name
Test status
Simulation time 653611829 ps
CPU time 4.62 seconds
Started Jul 14 06:55:07 PM PDT 24
Finished Jul 14 06:55:17 PM PDT 24
Peak memory 216180 kb
Host smart-7180acfe-19c8-4c63-bb23-c7dbf28f282c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853720476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1853720476
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2147718392
Short name T939
Test name
Test status
Simulation time 175418844 ps
CPU time 2.67 seconds
Started Jul 14 06:54:50 PM PDT 24
Finished Jul 14 06:54:55 PM PDT 24
Peak memory 216164 kb
Host smart-eda6a34a-2557-47c1-b590-6588b22e94ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147718392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2147718392
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.70033379
Short name T468
Test name
Test status
Simulation time 283151754 ps
CPU time 0.86 seconds
Started Jul 14 06:54:59 PM PDT 24
Finished Jul 14 06:55:01 PM PDT 24
Peak memory 205996 kb
Host smart-951e5e90-7584-4707-b3c9-bf9e8b7a120c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70033379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.70033379
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1485966238
Short name T12
Test name
Test status
Simulation time 565998028 ps
CPU time 2.94 seconds
Started Jul 14 06:54:56 PM PDT 24
Finished Jul 14 06:55:00 PM PDT 24
Peak memory 224472 kb
Host smart-ebcb6a45-e084-474a-ae55-902d5079bf19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485966238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1485966238
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3757985077
Short name T366
Test name
Test status
Simulation time 15887862 ps
CPU time 0.75 seconds
Started Jul 14 06:55:06 PM PDT 24
Finished Jul 14 06:55:12 PM PDT 24
Peak memory 205532 kb
Host smart-cf38e8cc-8da8-48ef-a598-a018ecbb7834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757985077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
757985077
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.370610682
Short name T578
Test name
Test status
Simulation time 3870327606 ps
CPU time 8.73 seconds
Started Jul 14 06:55:06 PM PDT 24
Finished Jul 14 06:55:20 PM PDT 24
Peak memory 224608 kb
Host smart-03be563e-965b-4816-8395-bf7faf9d646c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370610682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.370610682
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.48492031
Short name T781
Test name
Test status
Simulation time 21898763 ps
CPU time 0.75 seconds
Started Jul 14 06:55:08 PM PDT 24
Finished Jul 14 06:55:14 PM PDT 24
Peak memory 205592 kb
Host smart-517d2229-bec5-4777-bd1b-e0bb695a5f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48492031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.48492031
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2040080598
Short name T752
Test name
Test status
Simulation time 28744641411 ps
CPU time 56.96 seconds
Started Jul 14 06:55:10 PM PDT 24
Finished Jul 14 06:56:12 PM PDT 24
Peak memory 236708 kb
Host smart-cd6cfa30-02f8-43dd-a553-c8a8d75c6f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040080598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2040080598
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3276734647
Short name T457
Test name
Test status
Simulation time 52065419855 ps
CPU time 66.29 seconds
Started Jul 14 06:54:57 PM PDT 24
Finished Jul 14 06:56:04 PM PDT 24
Peak memory 224692 kb
Host smart-0e6df32c-62e4-4af3-942a-20328423bb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276734647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3276734647
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2184143523
Short name T295
Test name
Test status
Simulation time 59245969755 ps
CPU time 255.98 seconds
Started Jul 14 06:54:54 PM PDT 24
Finished Jul 14 06:59:12 PM PDT 24
Peak memory 257388 kb
Host smart-fd039eea-9048-43e7-a0c4-a388e0b7a737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184143523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2184143523
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3575026747
Short name T332
Test name
Test status
Simulation time 2472100973 ps
CPU time 8.51 seconds
Started Jul 14 06:54:59 PM PDT 24
Finished Jul 14 06:55:09 PM PDT 24
Peak memory 224660 kb
Host smart-8c81e284-84c6-42e2-a158-d88f5e480401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575026747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3575026747
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.2858011249
Short name T183
Test name
Test status
Simulation time 56354718127 ps
CPU time 100.07 seconds
Started Jul 14 06:55:02 PM PDT 24
Finished Jul 14 06:56:45 PM PDT 24
Peak memory 249212 kb
Host smart-d5de0a7b-c193-4a0f-a474-6c26ea6e695b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858011249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.2858011249
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.843956617
Short name T343
Test name
Test status
Simulation time 199049514 ps
CPU time 3.78 seconds
Started Jul 14 06:55:07 PM PDT 24
Finished Jul 14 06:55:16 PM PDT 24
Peak memory 232640 kb
Host smart-cd5b5742-fc45-4f62-a204-d8f5c01a839d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843956617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.843956617
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2763779993
Short name T892
Test name
Test status
Simulation time 1818671147 ps
CPU time 15.1 seconds
Started Jul 14 06:55:02 PM PDT 24
Finished Jul 14 06:55:21 PM PDT 24
Peak memory 224492 kb
Host smart-3d855dba-7ba3-400e-9c24-acc6beafb948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763779993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2763779993
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.139707672
Short name T619
Test name
Test status
Simulation time 829026575 ps
CPU time 4.07 seconds
Started Jul 14 06:54:57 PM PDT 24
Finished Jul 14 06:55:02 PM PDT 24
Peak memory 224460 kb
Host smart-33584bab-bfeb-45cb-95af-6a68c6a08fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139707672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
139707672
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3526808409
Short name T260
Test name
Test status
Simulation time 3474411291 ps
CPU time 7.7 seconds
Started Jul 14 06:54:56 PM PDT 24
Finished Jul 14 06:55:05 PM PDT 24
Peak memory 232744 kb
Host smart-a199eb58-fe91-47ea-a96a-0ebbc4ea89c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526808409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3526808409
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.325474941
Short name T919
Test name
Test status
Simulation time 2272629118 ps
CPU time 9.56 seconds
Started Jul 14 06:55:08 PM PDT 24
Finished Jul 14 06:55:23 PM PDT 24
Peak memory 220472 kb
Host smart-a7b2aef7-4baa-4f73-bb6b-e2f61276832c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=325474941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.325474941
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2460205726
Short name T778
Test name
Test status
Simulation time 155517533 ps
CPU time 0.98 seconds
Started Jul 14 06:55:09 PM PDT 24
Finished Jul 14 06:55:15 PM PDT 24
Peak memory 206792 kb
Host smart-dce0a493-0486-4de7-9867-e24e50496366
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460205726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2460205726
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2327651871
Short name T414
Test name
Test status
Simulation time 148999469 ps
CPU time 2.58 seconds
Started Jul 14 06:55:03 PM PDT 24
Finished Jul 14 06:55:10 PM PDT 24
Peak memory 216300 kb
Host smart-557cca62-7bb8-4af0-8e36-ee0cddb002a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327651871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2327651871
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1143652159
Short name T721
Test name
Test status
Simulation time 4803131842 ps
CPU time 12.39 seconds
Started Jul 14 06:55:00 PM PDT 24
Finished Jul 14 06:55:14 PM PDT 24
Peak memory 216276 kb
Host smart-1083a372-3a9c-4a8e-aad5-b30ecc23a5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143652159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1143652159
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.523472443
Short name T621
Test name
Test status
Simulation time 38298208 ps
CPU time 1.12 seconds
Started Jul 14 06:55:02 PM PDT 24
Finished Jul 14 06:55:07 PM PDT 24
Peak memory 207756 kb
Host smart-023cf64a-f451-42fe-ac5e-d126f9e6d01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523472443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.523472443
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.519360739
Short name T387
Test name
Test status
Simulation time 80205321 ps
CPU time 1 seconds
Started Jul 14 06:55:03 PM PDT 24
Finished Jul 14 06:55:09 PM PDT 24
Peak memory 207008 kb
Host smart-db389c5f-392c-488f-b0e5-0f6b2f6f7310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519360739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.519360739
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1121616807
Short name T838
Test name
Test status
Simulation time 420820607 ps
CPU time 6.19 seconds
Started Jul 14 06:55:10 PM PDT 24
Finished Jul 14 06:55:21 PM PDT 24
Peak memory 232664 kb
Host smart-3140417c-f4a6-4034-bf66-4186bce2797e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121616807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1121616807
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3124159607
Short name T958
Test name
Test status
Simulation time 48055625 ps
CPU time 0.73 seconds
Started Jul 14 06:55:25 PM PDT 24
Finished Jul 14 06:55:28 PM PDT 24
Peak memory 205548 kb
Host smart-d95e25b1-57e4-4cb2-a753-bfcb2b8d13f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124159607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
124159607
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.601603510
Short name T453
Test name
Test status
Simulation time 1015668105 ps
CPU time 2.71 seconds
Started Jul 14 06:55:02 PM PDT 24
Finished Jul 14 06:55:09 PM PDT 24
Peak memory 224460 kb
Host smart-d5437ad1-c651-40b8-bfb3-5f99907c3ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601603510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.601603510
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.609493938
Short name T478
Test name
Test status
Simulation time 36206697 ps
CPU time 0.78 seconds
Started Jul 14 06:55:06 PM PDT 24
Finished Jul 14 06:55:12 PM PDT 24
Peak memory 206936 kb
Host smart-63b41b53-6620-4ffa-a0af-5a2267345007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609493938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.609493938
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2180265062
Short name T56
Test name
Test status
Simulation time 222091213698 ps
CPU time 498.9 seconds
Started Jul 14 06:55:09 PM PDT 24
Finished Jul 14 07:03:33 PM PDT 24
Peak memory 265388 kb
Host smart-6b6fd08a-48af-469f-a666-c556a1b16386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180265062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2180265062
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1317195060
Short name T59
Test name
Test status
Simulation time 79896318947 ps
CPU time 158.17 seconds
Started Jul 14 06:55:02 PM PDT 24
Finished Jul 14 06:57:44 PM PDT 24
Peak memory 249280 kb
Host smart-4e8fb079-c990-4944-8dbf-50b500eb8f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317195060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1317195060
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2468372990
Short name T60
Test name
Test status
Simulation time 5925821469 ps
CPU time 71.61 seconds
Started Jul 14 06:55:16 PM PDT 24
Finished Jul 14 06:56:31 PM PDT 24
Peak memory 251412 kb
Host smart-85019f2e-fd6b-4061-88a7-130d4a4f167b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468372990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2468372990
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.3478602165
Short name T429
Test name
Test status
Simulation time 7499380885 ps
CPU time 29.02 seconds
Started Jul 14 06:55:00 PM PDT 24
Finished Jul 14 06:55:30 PM PDT 24
Peak memory 241028 kb
Host smart-9c1e579d-a5c7-496c-aa85-999fc65dc96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478602165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.3478602165
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1446210531
Short name T398
Test name
Test status
Simulation time 656768108 ps
CPU time 5.54 seconds
Started Jul 14 06:54:55 PM PDT 24
Finished Jul 14 06:55:02 PM PDT 24
Peak memory 224500 kb
Host smart-d6d0def4-e451-4aa1-acc2-f25d5f766d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446210531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1446210531
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.330289022
Short name T585
Test name
Test status
Simulation time 41553393 ps
CPU time 2.31 seconds
Started Jul 14 06:55:06 PM PDT 24
Finished Jul 14 06:55:14 PM PDT 24
Peak memory 232328 kb
Host smart-ed6f84f8-abba-4ed6-980c-0602c254329f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330289022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.330289022
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1571742137
Short name T467
Test name
Test status
Simulation time 6640936945 ps
CPU time 21.4 seconds
Started Jul 14 06:55:16 PM PDT 24
Finished Jul 14 06:55:40 PM PDT 24
Peak memory 232804 kb
Host smart-626c7f96-580d-4008-9bf3-5b8f1a1b4d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571742137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1571742137
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3734813753
Short name T505
Test name
Test status
Simulation time 503812665 ps
CPU time 3.89 seconds
Started Jul 14 06:54:57 PM PDT 24
Finished Jul 14 06:55:02 PM PDT 24
Peak memory 232636 kb
Host smart-b67c11df-69a3-45ca-b07d-1c565e4b278e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734813753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3734813753
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.4292229334
Short name T651
Test name
Test status
Simulation time 1067446161 ps
CPU time 3.95 seconds
Started Jul 14 06:54:59 PM PDT 24
Finished Jul 14 06:55:05 PM PDT 24
Peak memory 218860 kb
Host smart-7fc7aca8-0233-4ea1-b362-57a002417660
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4292229334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.4292229334
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.796091465
Short name T871
Test name
Test status
Simulation time 4463357003 ps
CPU time 64.39 seconds
Started Jul 14 06:55:21 PM PDT 24
Finished Jul 14 06:56:27 PM PDT 24
Peak memory 251784 kb
Host smart-095d9385-b472-4716-a118-a3c9a2fd508e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796091465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.796091465
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1075601107
Short name T396
Test name
Test status
Simulation time 482592748 ps
CPU time 6.76 seconds
Started Jul 14 06:55:03 PM PDT 24
Finished Jul 14 06:55:15 PM PDT 24
Peak memory 216196 kb
Host smart-625edaec-b492-4c39-94de-9808c6ec3740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075601107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1075601107
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3832971958
Short name T358
Test name
Test status
Simulation time 1030060064 ps
CPU time 3.95 seconds
Started Jul 14 06:55:13 PM PDT 24
Finished Jul 14 06:55:21 PM PDT 24
Peak memory 216256 kb
Host smart-d5c64508-b31c-4fb3-9f67-2cc0e2079aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832971958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3832971958
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2761258597
Short name T697
Test name
Test status
Simulation time 63359408 ps
CPU time 0.91 seconds
Started Jul 14 06:54:59 PM PDT 24
Finished Jul 14 06:55:02 PM PDT 24
Peak memory 206904 kb
Host smart-340a99f7-4e5b-43fe-90c7-ed8f155c300d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761258597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2761258597
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2020063084
Short name T363
Test name
Test status
Simulation time 25027384 ps
CPU time 0.82 seconds
Started Jul 14 06:55:15 PM PDT 24
Finished Jul 14 06:55:19 PM PDT 24
Peak memory 205996 kb
Host smart-4e32f76b-ea28-471d-8f3f-321f205b41f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020063084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2020063084
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.161618522
Short name T196
Test name
Test status
Simulation time 1077876104 ps
CPU time 4.8 seconds
Started Jul 14 06:54:58 PM PDT 24
Finished Jul 14 06:55:04 PM PDT 24
Peak memory 232648 kb
Host smart-810d6f81-8e6b-407c-b621-fd67a706d78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161618522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.161618522
Directory /workspace/9.spi_device_upload/latest
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