Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2968756	1			T1	9		T2	64		T3	1
all_values[1]	2968756	1			T1	9		T2	64		T3	1
all_values[2]	2968756	1			T1	9		T2	64		T3	1
all_values[3]	2968756	1			T1	9		T2	64		T3	1
all_values[4]	2968756	1			T1	9		T2	64		T3	1
all_values[5]	2968756	1			T1	9		T2	64		T3	1
all_values[6]	2968756	1			T1	9		T2	64		T3	1
all_values[7]	2968756	1			T1	9		T2	64		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23253303

1

T1

45

T2

512

T3

8

auto[1]

496745

1

T1

27

T12

52

T17

24

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23719154

1

T1

58

T2

512

T3

8

auto[1]

30894

1

T1

14

T12

46

T15

114

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2925798	1			T1	3		T2	64		T3	1
all_values[0]	auto[0]	auto[1]	14713	1			T1	1		T12	2		T15	38
all_values[0]	auto[1]	auto[0]	27799	1			T1	4		T12	6		T19	6
all_values[0]	auto[1]	auto[1]	446	1			T1	1		T12	4		T17	2
all_values[1]	auto[0]	auto[0]	2919795	1			T1	5		T2	64		T3	1
all_values[1]	auto[0]	auto[1]	9394	1			T1	4		T12	5		T15	38
all_values[1]	auto[1]	auto[0]	39207	1			T12	2		T17	2		T19	7
all_values[1]	auto[1]	auto[1]	360	1			T12	1		T19	5		T20	1
all_values[2]	auto[0]	auto[0]	2875433	1			T1	3		T2	64		T3	1
all_values[2]	auto[0]	auto[1]	3762	1			T1	2		T12	3		T15	38
all_values[2]	auto[1]	auto[0]	89306	1			T1	2		T12	5		T17	2
all_values[2]	auto[1]	auto[1]	255	1			T1	2		T12	3		T17	2
all_values[3]	auto[0]	auto[0]	2923885	1			T1	7		T2	64		T3	1
all_values[3]	auto[0]	auto[1]	210	1			T12	2		T17	3		T19	7
all_values[3]	auto[1]	auto[0]	44465	1			T1	2		T12	4		T19	5
all_values[3]	auto[1]	auto[1]	196	1			T12	6		T19	7		T20	4
all_values[4]	auto[0]	auto[0]	2878788	1			T1	9		T2	64		T3	1
all_values[4]	auto[0]	auto[1]	183	1			T19	7		T20	2		T21	8
all_values[4]	auto[1]	auto[0]	89584	1			T12	5		T17	7		T19	6
all_values[4]	auto[1]	auto[1]	201	1			T12	5		T17	1		T19	6
all_values[5]	auto[0]	auto[0]	2910991	1			T1	3		T2	64		T3	1
all_values[5]	auto[0]	auto[1]	182	1			T1	1		T12	3		T17	1
all_values[5]	auto[1]	auto[0]	57389	1			T1	4		T17	1		T19	6
all_values[5]	auto[1]	auto[1]	194	1			T1	1		T12	2		T17	2
all_values[6]	auto[0]	auto[0]	2915802	1			T1	4		T2	64		T3	1
all_values[6]	auto[0]	auto[1]	204	1			T12	1		T17	4		T19	7
all_values[6]	auto[1]	auto[0]	52565	1			T1	5		T12	2		T17	1
all_values[6]	auto[1]	auto[1]	185	1			T12	2		T17	1		T19	3
all_values[7]	auto[0]	auto[0]	2873964	1			T1	3		T2	64		T3	1
all_values[7]	auto[0]	auto[1]	199	1			T12	3		T17	1		T19	5
all_values[7]	auto[1]	auto[0]	94383	1			T1	4		T12	1		T17	1
all_values[7]	auto[1]	auto[1]	210	1			T1	2		T12	4		T17	2