Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34874	1			T2	156		T5	4		T6	97
auto[SpiFlashAddrCfg]	7722	1			T2	13		T5	4		T6	9
auto[SpiFlashAddr3b]	9488	1			T2	14		T5	10		T6	6
auto[SpiFlashAddr4b]	7852	1			T2	7		T5	4		T6	6

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34471

1

T2

38

T5

22

T6

62

auto[1]

25465

1

T2

152

T6

56

T11

101

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32082

1

T2

163

T5

2

T6

61

auto[1]

27854

1

T2

27

T5

20

T6

57

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39793	1			T2	168		T5	4		T6	104
values[1]	1175	1			T11	7		T17	2		T43	2
values[2]	1482	1			T2	1		T6	3		T11	6
values[3]	1412	1			T2	5		T6	1		T11	6
values[4]	1458	1			T2	1		T6	1		T11	6
values[5]	1480	1			T2	1		T5	4		T11	3
values[6]	1530	1			T6	4		T11	12		T14	2
values[7]	1444	1			T2	1		T6	2		T11	10
values[8]	10162	1			T2	13		T5	14		T6	3

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30306

1

T5

22

T10

6

T13

12

auto[1]

29630

1

T2

190

T6

118

T11

260

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

56508

1

T2

186

T5

22

T6

110

write

3428

1

T2

4

T6

8

T11

32

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19678

1

T2

29

T5

8

T6

18

valids[0x1]

40258

1

T2

161

T5

14

T6

100

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1582	1			T2	3		T6	1		T11	10
internal_process_ops[0x5a]	1777	1			T2	5		T5	8		T6	2
internal_process_ops[0x05]	20478	1			T2	136		T6	79		T11	11
internal_process_ops[0x35]	1633	1			T2	2		T6	1		T11	9
internal_process_ops[0x15]	1762	1			T2	1		T5	4		T6	1
internal_process_ops[0x03]	1030	1			T5	2		T10	4		T14	2
internal_process_ops[0x0b]	1137	1			T2	2		T10	2		T11	3
internal_process_ops[0x3b]	1059	1			T2	1		T5	2		T11	5
internal_process_ops[0x6b]	1075	1			T2	2		T5	2		T11	3
internal_process_ops[0xbb]	1077	1			T11	6		T15	6		T16	2
internal_process_ops[0xeb]	1086	1			T5	4		T6	1		T11	3

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58306

1

T2

188

T5

22

T6

114

auto[1]

1630

1

T2

2

T6

4

T11

11

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57454

1

T2

182

T5

22

T6

112

auto[1]

2482

1

T2

8

T6

6

T11

21

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10017

1

T5

4

T13

8

T14

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6178

1

T15

14

T36

2

T30

178

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2115

1

T5

4

T10

6

T14

12

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1734

1

T15

9

T36

4

T30

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2597

1

T5

10

T13

4

T14

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2058

1

T15

10

T30

8

T37

19

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2112

1

T5

4

T14

4

T15

9

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1866

1

T15

9

T36

6

T30

11

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

102

1

T37

1

T39

2

T32

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

87

1

T39

3

T41

2

T19

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

71

1

T18

1

T42

2

T32

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

117

1

T30

1

T37

1

T39

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

123

1

T37

3

T41

1

T18

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

89

1

T15

1

T30

1

T37

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

75

1

T18

2

T42

2

T162

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

87

1

T37

2

T39

3

T20

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

138

1

T37

1

T41

3

T20

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

95

1

T30

1

T39

2

T41

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

94

1

T37

1

T41

2

T18

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

106

1

T37

2

T39

4

T18

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

149

1

T30

8

T37

1

T39

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

92

1

T30

2

T39

2

T41

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

100

1

T15

1

T32

3

T163

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

104

1

T30

1

T37

2

T41

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10865

1

T2

21

T6

45

T11

79

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6993

1

T2

133

T6

46

T11

22

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1511

1

T2

4

T6

8

T11

23

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1553

1

T2

8

T6

1

T11

10

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1970

1

T2

7

T6

4

T11

19

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1955

1

T2

6

T6

2

T11

34

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1533

1

T2

3

T6

2

T11

26

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1451

1

T2

4

T6

2

T11

15

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

89

1

T6

3

T11

1

T44

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

113

1

T2

1

T11

1

T17

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

120

1

T2

1

T6

1

T11

7

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

122

1

T6

2

T164

2

T165

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

112

1

T11

1

T17

1

T44

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

107

1

T2

1

T11

2

T43

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

115

1

T11

4

T98

1

T164

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

101

1

T11

2

T45

1

T164

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

129

1

T2

1

T43

3

T45

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

112

1

T11

3

T17

2

T45

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

134

1

T11

4

T17

1

T43

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

100

1

T11

2

T17

1

T98

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

110

1

T11

3

T44

2

T98

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

104

1

T11

1

T43

2

T98

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

137

1

T11

1

T44

1

T45

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

94

1

T6

2

T17

1

T98

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3862	1			T15	15		T16	2		T38	16
auto[0]	values[0]	valids[0x1]	15242	1			T5	4		T10	4		T13	8
auto[0]	values[1]	valids[0x1]	634	1			T30	1		T37	2		T39	6
auto[0]	values[2]	valids[0x0]	554	1			T15	4		T30	1		T37	4
auto[0]	values[2]	valids[0x1]	303	1			T30	2		T37	2		T39	3
auto[0]	values[3]	valids[0x0]	512	1			T14	4		T15	2		T30	3
auto[0]	values[3]	valids[0x1]	311	1			T15	1		T37	3		T99	4
auto[0]	values[4]	valids[0x0]	537	1			T15	6		T37	3		T40	4
auto[0]	values[4]	valids[0x1]	281	1			T30	1		T37	7		T39	6
auto[0]	values[5]	valids[0x0]	528	1			T5	4		T14	4		T15	4
auto[0]	values[5]	valids[0x1]	283	1			T15	4		T37	1		T39	3
auto[0]	values[6]	valids[0x0]	532	1			T30	3		T37	1		T39	8
auto[0]	values[6]	valids[0x1]	299	1			T14	2		T15	2		T30	5
auto[0]	values[7]	valids[0x0]	535	1			T15	1		T30	2		T37	7
auto[0]	values[7]	valids[0x1]	273	1			T37	2		T39	1		T41	4
auto[0]	values[8]	valids[0x0]	3469	1			T5	4		T15	15		T36	2
auto[0]	values[8]	valids[0x1]	2151	1			T5	10		T10	2		T13	4
auto[1]	values[0]	valids[0x0]	4136	1			T2	18		T6	13		T11	59
auto[1]	values[0]	valids[0x1]	16553	1			T2	150		T6	91		T11	89
auto[1]	values[1]	valids[0x1]	541	1			T11	7		T17	2		T43	2
auto[1]	values[2]	valids[0x0]	390	1			T6	1		T11	4		T17	4
auto[1]	values[2]	valids[0x1]	235	1			T2	1		T6	2		T11	2
auto[1]	values[3]	valids[0x0]	370	1			T2	4		T11	3		T17	5
auto[1]	values[3]	valids[0x1]	219	1			T2	1		T6	1		T11	3
auto[1]	values[4]	valids[0x0]	361	1			T2	1		T6	1		T11	3
auto[1]	values[4]	valids[0x1]	279	1			T11	3		T43	3		T44	2
auto[1]	values[5]	valids[0x0]	407	1			T2	1		T11	1		T17	4
auto[1]	values[5]	valids[0x1]	262	1			T11	2		T17	3		T43	2
auto[1]	values[6]	valids[0x0]	423	1			T6	2		T11	6		T17	1
auto[1]	values[6]	valids[0x1]	276	1			T6	2		T11	6		T17	2
auto[1]	values[7]	valids[0x0]	367	1			T2	1		T11	6		T44	2
auto[1]	values[7]	valids[0x1]	269	1			T6	2		T11	4		T44	1
auto[1]	values[8]	valids[0x0]	2695	1			T2	4		T6	1		T11	30
auto[1]	values[8]	valids[0x1]	1847	1			T2	9		T6	2		T11	32