Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3632118

1

T2

1957

T3

1

T5

740

auto[1]

29957

1

T2

130

T6

78

T11

840

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1032465

1

T2

30

T3

1

T5

740

auto[1]

2629610

1

T2

2057

T6

846

T11

12856

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	692969	1			T2	274		T3	1		T5	47
auto[524288:1048575]	461713	1			T2	80		T5	116		T10	478
auto[1048576:1572863]	407657	1			T5	237		T10	5592		T11	3110
auto[1572864:2097151]	400658	1			T5	74		T6	293		T10	16659
auto[2097152:2621439]	486679	1			T2	512		T5	56		T10	6673
auto[2621440:3145727]	355535	1			T2	795		T5	115		T10	7460
auto[3145728:3670015]	444835	1			T2	294		T5	95		T6	264
auto[3670016:4194303]	412029	1			T2	132		T6	289		T11	3615

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2662800

1

T2

2084

T3

1

T5

65

auto[1]

999275

1

T2

3

T5

675

T6

10

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3171956

1

T2

1812

T3

1

T5

740

auto[1]

490119

1

T2

275

T6

2

T11

388

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	194168	1			T2	1		T3	1		T5	47
auto[0]	auto[0]	auto[0:524287]	auto[1]	414898	1			T6	1		T11	27		T15	2795
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	123506	1			T2	6		T5	116		T10	478
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	283298	1			T2	4		T11	1691		T15	130
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	110142	1			T5	237		T10	5592		T11	46
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	243181	1			T11	3038		T15	2639		T16	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	94612	1			T5	74		T6	4		T10	16659
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	244833	1			T6	258		T11	467		T15	1602
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	119265	1			T5	56		T10	6673		T11	36
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	310019	1			T2	512		T11	344		T15	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	117810	1			T2	5		T5	115		T10	7460
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	177955	1			T2	770		T11	518		T17	520
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	127357	1			T2	4		T5	95		T6	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	241057	1			T2	264		T6	257		T11	2198
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	130691	1			T2	2		T6	4		T11	45
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	215761	1			T2	128		T6	258		T11	3570
auto[0]	auto[1]	auto[0:524287]	auto[0]	1572	1			T2	2		T6	1		T118	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	78254	1			T2	257		T30	128		T37	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	3354	1			T11	3		T43	13		T30	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	47117	1			T43	256		T37	2		T98	128
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	572	1			T11	12		T30	7		T118	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	51508	1			T30	2		T37	258		T45	256
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	873	1			T11	51		T43	24		T118	34
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	55156	1			T11	259		T43	386		T37	512
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1767	1			T11	4		T17	3		T43	19
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	51403	1			T17	571		T43	512		T45	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1286	1			T11	44		T15	6		T17	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	55044	1			T11	2		T17	386		T43	618
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	884	1			T6	1		T45	3		T98	5
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	72596	1			T45	1		T31	128		T32	5078
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	602	1			T2	2		T43	10		T45	6
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	61577	1			T45	1072		T18	128		T20	5
auto[1]	auto[0]	auto[0:524287]	auto[0]	529	1			T6	1		T11	7		T17	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2933	1			T6	15		T30	50		T44	70
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	383	1			T2	4		T11	10		T17	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2657	1			T2	66		T11	256		T30	11
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	329	1			T11	12		T43	3		T37	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1262	1			T11	2		T37	9		T165	7
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	362	1			T6	2		T11	8		T43	9
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3013	1			T6	29		T43	50		T30	37
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	510	1			T11	6		T15	1		T44	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	3357	1			T15	8		T44	8		T192	48
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	430	1			T2	2		T11	26		T43	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2524	1			T2	18		T11	484		T43	57
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	368	1			T2	1		T6	1		T11	16
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1771	1			T2	25		T6	3		T17	4
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	375	1			T6	2		T17	2		T30	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2600	1			T6	25		T17	7		T30	6
auto[1]	auto[1]	auto[0:524287]	auto[0]	103	1			T2	1		T37	1		T225	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	512	1			T2	13		T225	51		T27	14
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	128	1			T43	4		T37	2		T41	15
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	1270	1			T37	8		T41	517		T18	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	78	1			T30	2		T37	2		T18	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	585	1			T30	21		T37	8		T18	30
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	87	1			T11	7		T164	3		T41	8
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	1722	1			T164	124		T188	1084		T27	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	81	1			T17	1		T43	2		T164	10
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	277	1			T17	1		T27	1		T83	19
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	59	1			T11	6		T43	3		T164	6
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	427	1			T18	24		T180	16		T217	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	99	1			T98	5		T82	1		T22	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	703	1			T162	2		T83	38		T46	10
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	83	1			T20	1		T205	1		T180	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	340	1			T20	4		T180	51		T187	9

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2156006	1			T2	1694		T3	1		T5	65
auto[0]	auto[0]	auto[1]	992547	1			T2	2		T5	675		T6	5
auto[0]	auto[1]	auto[0]	477490	1			T2	260		T6	2		T11	375
auto[0]	auto[1]	auto[1]	6075	1			T2	1		T30	1		T118	34
auto[1]	auto[0]	auto[0]	22863	1			T2	116		T6	73		T11	818
auto[1]	auto[0]	auto[1]	540	1			T6	5		T11	9		T43	5
auto[1]	auto[1]	auto[0]	6441	1			T2	14		T11	11		T17	1
auto[1]	auto[1]	auto[1]	113	1			T11	2		T17	1		T43	1