Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2968756	1			T1	9		T2	64		T3	1
all_pins[1]	2968756	1			T1	9		T2	64		T3	1
all_pins[2]	2968756	1			T1	9		T2	64		T3	1
all_pins[3]	2968756	1			T1	9		T2	64		T3	1
all_pins[4]	2968756	1			T1	9		T2	64		T3	1
all_pins[5]	2968756	1			T1	9		T2	64		T3	1
all_pins[6]	2968756	1			T1	9		T2	64		T3	1
all_pins[7]	2968756	1			T1	9		T2	64		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	23695368	1			T1	66		T2	512		T3	8
values[0x1]	54680	1			T1	6		T12	27		T17	10
transitions[0x0=>0x1]	52909	1			T1	5		T12	20		T17	9
transitions[0x1=>0x0]	52921	1			T1	5		T12	20		T17	9

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2968271	1			T1	8		T2	64		T3	1
all_pins[0]	values[0x1]	485	1			T1	1		T12	4		T17	2
all_pins[0]	transitions[0x0=>0x1]	255	1			T1	1		T12	4		T17	2
all_pins[0]	transitions[0x1=>0x0]	173	1			T12	1		T19	4		T20	1
all_pins[1]	values[0x0]	2968353	1			T1	9		T2	64		T3	1
all_pins[1]	values[0x1]	403	1			T12	1		T19	5		T20	1
all_pins[1]	transitions[0x0=>0x1]	344	1			T12	1		T19	2		T20	1
all_pins[1]	transitions[0x1=>0x0]	202	1			T1	2		T12	3		T17	2
all_pins[2]	values[0x0]	2968495	1			T1	7		T2	64		T3	1
all_pins[2]	values[0x1]	261	1			T1	2		T12	3		T17	2
all_pins[2]	transitions[0x0=>0x1]	212	1			T1	2		T12	3		T17	2
all_pins[2]	transitions[0x1=>0x0]	147	1			T12	6		T19	5		T20	2
all_pins[3]	values[0x0]	2968560	1			T1	9		T2	64		T3	1
all_pins[3]	values[0x1]	196	1			T12	6		T19	7		T20	4
all_pins[3]	transitions[0x0=>0x1]	142	1			T12	4		T19	6		T20	4
all_pins[3]	transitions[0x1=>0x0]	147	1			T12	3		T17	1		T19	5
all_pins[4]	values[0x0]	2968555	1			T1	9		T2	64		T3	1
all_pins[4]	values[0x1]	201	1			T12	5		T17	1		T19	6
all_pins[4]	transitions[0x0=>0x1]	161	1			T12	4		T17	1		T19	5
all_pins[4]	transitions[0x1=>0x0]	1540	1			T1	1		T12	1		T17	2
all_pins[5]	values[0x0]	2967176	1			T1	8		T2	64		T3	1
all_pins[5]	values[0x1]	1580	1			T1	1		T12	2		T17	2
all_pins[5]	transitions[0x0=>0x1]	348	1			T1	1		T12	1		T17	2
all_pins[5]	transitions[0x1=>0x0]	50112	1			T12	1		T17	1		T19	2
all_pins[6]	values[0x0]	2917412	1			T1	9		T2	64		T3	1
all_pins[6]	values[0x1]	51344	1			T12	2		T17	1		T19	3
all_pins[6]	transitions[0x0=>0x1]	51299	1			T19	3		T20	2		T21	8
all_pins[6]	transitions[0x1=>0x0]	165	1			T1	2		T12	2		T17	1
all_pins[7]	values[0x0]	2968546	1			T1	7		T2	64		T3	1
all_pins[7]	values[0x1]	210	1			T1	2		T12	4		T17	2
all_pins[7]	transitions[0x0=>0x1]	148	1			T1	1		T12	3		T17	2
all_pins[7]	transitions[0x1=>0x0]	435	1			T12	3		T17	2		T19	3