Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17716

1

T5

22

T10

6

T13

12

auto[1]

12590

1

T15

43

T36

12

T30

203

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3338	1			T10	6		T13	12		T30	27
values[1]	3920	1			T37	26		T226	19		T39	40
values[2]	4157	1			T5	22		T16	8		T30	192
values[3]	4045	1			T14	22		T15	40		T36	12
values[4]	3613	1			T37	25		T39	155		T41	40
values[5]	3216	1			T30	50		T37	66		T191	4
values[6]	3715	1			T15	29		T38	16		T118	10
values[7]	4302	1			T15	20		T39	35		T18	114

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3884	1			T30	55		T39	91		T41	20
values[1]	3864	1			T15	20		T16	8		T30	157
values[2]	3962	1			T5	22		T15	20		T37	40
values[3]	4117	1			T30	27		T37	63		T99	14
values[4]	3819	1			T10	6		T36	12		T30	30
values[5]	3296	1			T13	12		T37	26		T226	19
values[6]	3906	1			T14	22		T15	49		T38	16
values[7]	3458	1			T37	20		T39	72		T18	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	224	1			T42	15		T46	14		T55	18
auto[0]	values[0]	values[1]	199	1			T163	12		T184	9		T227	8
auto[0]	values[0]	values[2]	319	1			T19	11		T42	13		T184	11
auto[0]	values[0]	values[3]	256	1			T30	11		T203	16		T180	31
auto[0]	values[0]	values[4]	164	1			T10	6		T18	19		T20	9
auto[0]	values[0]	values[5]	367	1			T13	12		T18	12		T20	49
auto[0]	values[0]	values[6]	205	1			T37	7		T18	12		T187	31
auto[0]	values[0]	values[7]	283	1			T19	14		T22	15		T203	14
auto[0]	values[1]	values[0]	241	1			T39	14		T41	15		T18	17
auto[0]	values[1]	values[1]	345	1			T39	10		T207	18		T162	56
auto[0]	values[1]	values[2]	388	1			T27	9		T180	143		T185	12
auto[0]	values[1]	values[3]	316	1			T138	8		T28	27		T181	9
auto[0]	values[1]	values[4]	197	1			T228	2		T55	12		T214	10
auto[0]	values[1]	values[5]	272	1			T37	12		T226	19		T193	4
auto[0]	values[1]	values[6]	326	1			T41	19		T18	29		T32	5
auto[0]	values[1]	values[7]	330	1			T20	13		T46	64		T55	12
auto[0]	values[2]	values[0]	197	1			T30	13		T189	13		T200	7
auto[0]	values[2]	values[1]	274	1			T16	8		T30	15		T221	15
auto[0]	values[2]	values[2]	208	1			T5	22		T39	8		T163	15
auto[0]	values[2]	values[3]	473	1			T203	11		T229	26		T27	11
auto[0]	values[2]	values[4]	377	1			T39	12		T20	14		T180	72
auto[0]	values[2]	values[5]	229	1			T41	14		T55	11		T189	19
auto[0]	values[2]	values[6]	193	1			T19	10		T141	11		T230	14
auto[0]	values[2]	values[7]	367	1			T203	9		T183	29		T184	12
auto[0]	values[3]	values[0]	363	1			T22	13		T55	13		T231	8
auto[0]	values[3]	values[1]	199	1			T15	11		T20	13		T232	12
auto[0]	values[3]	values[2]	234	1			T37	11		T46	4		T233	14
auto[0]	values[3]	values[3]	265	1			T39	9		T18	17		T22	12
auto[0]	values[3]	values[4]	420	1			T41	8		T42	21		T234	8
auto[0]	values[3]	values[5]	153	1			T46	10		T182	11		T235	14
auto[0]	values[3]	values[6]	394	1			T14	22		T15	10		T37	53
auto[0]	values[3]	values[7]	258	1			T203	15		T211	11		T212	10
auto[0]	values[4]	values[0]	414	1			T19	10		T42	10		T187	36
auto[0]	values[4]	values[1]	163	1			T20	16		T236	14		T212	12
auto[0]	values[4]	values[2]	322	1			T39	56		T41	10		T42	16
auto[0]	values[4]	values[3]	288	1			T37	19		T41	13		T203	9
auto[0]	values[4]	values[4]	229	1			T237	8		T46	31		T181	12
auto[0]	values[4]	values[5]	255	1			T39	67		T42	8		T201	12
auto[0]	values[4]	values[6]	229	1			T189	16		T214	24		T238	12
auto[0]	values[4]	values[7]	160	1			T39	11		T20	9		T42	23
auto[0]	values[5]	values[0]	200	1			T185	17		T46	11		T28	13
auto[0]	values[5]	values[1]	207	1			T30	13		T39	9		T20	7
auto[0]	values[5]	values[2]	168	1			T37	13		T42	10		T208	12
auto[0]	values[5]	values[3]	214	1			T28	24		T141	13		T239	16
auto[0]	values[5]	values[4]	501	1			T30	14		T163	9		T180	19
auto[0]	values[5]	values[5]	106	1			T163	13		T182	9		T142	10
auto[0]	values[5]	values[6]	319	1			T37	34		T191	4		T240	10
auto[0]	values[5]	values[7]	209	1			T39	9		T32	22		T190	18
auto[0]	values[6]	values[0]	281	1			T39	66		T19	9		T187	13
auto[0]	values[6]	values[1]	276	1			T163	7		T241	70		T180	16
auto[0]	values[6]	values[2]	484	1			T136	14		T22	13		T209	15
auto[0]	values[6]	values[3]	227	1			T37	18		T20	11		T27	10
auto[0]	values[6]	values[4]	232	1			T203	16		T180	24		T185	11
auto[0]	values[6]	values[5]	167	1			T209	27		T203	11		T242	12
auto[0]	values[6]	values[6]	339	1			T15	12		T38	16		T118	10
auto[0]	values[6]	values[7]	187	1			T37	12		T19	12		T32	20
auto[0]	values[7]	values[0]	260	1			T18	14		T19	15		T223	16
auto[0]	values[7]	values[1]	358	1			T20	11		T22	11		T162	75
auto[0]	values[7]	values[2]	270	1			T15	13		T19	13		T209	12
auto[0]	values[7]	values[3]	386	1			T39	24		T163	7		T243	14
auto[0]	values[7]	values[4]	267	1			T183	26		T184	11		T244	4
auto[0]	values[7]	values[5]	435	1			T18	62		T20	17		T32	17
auto[0]	values[7]	values[6]	288	1			T245	10		T22	14		T200	9
auto[0]	values[7]	values[7]	239	1			T18	14		T20	15		T42	6
auto[1]	values[0]	values[0]	110	1			T42	5		T46	6		T55	10
auto[1]	values[0]	values[1]	246	1			T163	8		T184	11		T239	53
auto[1]	values[0]	values[2]	204	1			T19	9		T42	7		T184	9
auto[1]	values[0]	values[3]	124	1			T30	16		T203	4		T180	5
auto[1]	values[0]	values[4]	153	1			T18	3		T20	23		T32	10
auto[1]	values[0]	values[5]	137	1			T18	8		T20	6		T27	6
auto[1]	values[0]	values[6]	206	1			T37	13		T18	8		T187	19
auto[1]	values[0]	values[7]	141	1			T19	6		T22	6		T203	6
auto[1]	values[1]	values[0]	189	1			T39	6		T41	5		T18	7
auto[1]	values[1]	values[1]	141	1			T39	10		T162	9		T187	7
auto[1]	values[1]	values[2]	186	1			T27	11		T180	1		T185	8
auto[1]	values[1]	values[3]	308	1			T28	8		T181	13		T194	27
auto[1]	values[1]	values[4]	132	1			T55	18		T214	10		T246	9
auto[1]	values[1]	values[5]	169	1			T37	14		T187	4		T247	21
auto[1]	values[1]	values[6]	229	1			T41	21		T18	5		T32	23
auto[1]	values[1]	values[7]	151	1			T20	7		T46	8		T55	8
auto[1]	values[2]	values[0]	191	1			T30	42		T189	7		T200	13
auto[1]	values[2]	values[1]	496	1			T30	122		T221	12		T214	26
auto[1]	values[2]	values[2]	189	1			T39	12		T163	5		T206	7
auto[1]	values[2]	values[3]	258	1			T203	9		T27	11		T180	23
auto[1]	values[2]	values[4]	159	1			T39	8		T20	6		T180	8
auto[1]	values[2]	values[5]	234	1			T41	6		T55	21		T189	11
auto[1]	values[2]	values[6]	94	1			T19	10		T248	4		T141	9
auto[1]	values[2]	values[7]	218	1			T203	11		T183	23		T184	8
auto[1]	values[3]	values[0]	201	1			T22	12		T55	7		T184	30
auto[1]	values[3]	values[1]	212	1			T15	9		T20	7		T184	9
auto[1]	values[3]	values[2]	181	1			T37	9		T46	16		T249	22
auto[1]	values[3]	values[3]	231	1			T39	11		T18	10		T22	8
auto[1]	values[3]	values[4]	262	1			T36	12		T41	12		T42	19
auto[1]	values[3]	values[5]	153	1			T46	10		T182	9		T204	11
auto[1]	values[3]	values[6]	340	1			T15	10		T37	32		T41	8
auto[1]	values[3]	values[7]	179	1			T203	5		T211	9		T212	10
auto[1]	values[4]	values[0]	261	1			T19	12		T42	10		T187	6
auto[1]	values[4]	values[1]	190	1			T20	11		T250	16		T212	12
auto[1]	values[4]	values[2]	294	1			T39	5		T41	10		T42	4
auto[1]	values[4]	values[3]	198	1			T37	6		T41	7		T203	11
auto[1]	values[4]	values[4]	101	1			T46	7		T181	8		T143	12
auto[1]	values[4]	values[5]	118	1			T39	7		T42	12		T201	8
auto[1]	values[4]	values[6]	116	1			T189	4		T214	6		T215	11
auto[1]	values[4]	values[7]	275	1			T39	9		T20	11		T42	17
auto[1]	values[5]	values[0]	221	1			T185	3		T46	9		T28	38
auto[1]	values[5]	values[1]	182	1			T30	7		T39	11		T20	13
auto[1]	values[5]	values[2]	131	1			T37	7		T42	10		T185	8
auto[1]	values[5]	values[3]	192	1			T28	7		T141	10		T239	10
auto[1]	values[5]	values[4]	176	1			T30	16		T163	11		T180	8
auto[1]	values[5]	values[5]	122	1			T140	18		T163	7		T182	11
auto[1]	values[5]	values[6]	148	1			T37	12		T203	10		T189	10
auto[1]	values[5]	values[7]	120	1			T39	43		T32	10		T163	7
auto[1]	values[6]	values[0]	306	1			T39	5		T19	11		T187	7
auto[1]	values[6]	values[1]	171	1			T163	13		T180	4		T46	3
auto[1]	values[6]	values[2]	180	1			T22	11		T209	7		T28	6
auto[1]	values[6]	values[3]	218	1			T37	20		T99	14		T20	9
auto[1]	values[6]	values[4]	161	1			T203	4		T180	8		T185	9
auto[1]	values[6]	values[5]	95	1			T209	8		T203	9		T239	5
auto[1]	values[6]	values[6]	255	1			T15	17		T185	8		T184	13
auto[1]	values[6]	values[7]	136	1			T37	8		T19	10		T32	32
auto[1]	values[7]	values[0]	225	1			T18	7		T19	5		T180	44
auto[1]	values[7]	values[1]	205	1			T20	9		T22	9		T162	14
auto[1]	values[7]	values[2]	204	1			T15	7		T19	7		T209	8
auto[1]	values[7]	values[3]	163	1			T39	11		T163	13		T51	26
auto[1]	values[7]	values[4]	288	1			T183	9		T184	129		T142	8
auto[1]	values[7]	values[5]	284	1			T18	11		T20	5		T32	11
auto[1]	values[7]	values[6]	225	1			T22	6		T202	14		T200	11
auto[1]	values[7]	values[7]	205	1			T18	6		T20	9		T42	14