Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	436	1			T15	2		T30	4		T37	4
auto[ReadAddrCrossIntoMailbox]	301	1			T15	1		T30	1		T37	3
auto[ReadAddrCrossOutOfMailbox]	313	1			T15	3		T30	1		T37	2
auto[ReadAddrCrossAllMailbox]	233	1			T10	4		T15	3		T30	1
auto[ReadAddrOutsideMailbox]	3537	1			T5	10		T10	2		T14	10

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2402

1

T5

5

T10

3

T14

5

auto[1]

2418

1

T5

5

T10

3

T14

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	776	1			T5	2		T10	4		T14	2
read_ops[0x0b]	852	1			T10	2		T14	4		T15	4
read_ops[0x3b]	797	1			T5	2		T15	3		T37	8
read_ops[0x6b]	796	1			T5	2		T14	4		T15	5
read_ops[0xbb]	799	1			T15	6		T30	4		T37	9
read_ops[0xeb]	800	1			T5	4		T15	2		T30	3

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T30	1		T37	2		T136	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T37	1		T136	1		T163	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T19	2		T42	1		T22	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T15	1		T18	1		T20	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	35	1			T41	1		T19	2		T42	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T18	1		T187	1		T46	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T10	1		T39	1		T41	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T10	1		T136	2		T208	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	268	1			T5	1		T10	1		T14	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	275	1			T5	1		T10	1		T14	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T39	1		T19	1		T32	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T15	1		T30	1		T22	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T136	1		T42	1		T32	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T30	1		T39	1		T136	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T15	1		T19	1		T42	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T27	1		T187	1		T189	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T10	1		T41	1		T18	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T10	1		T30	1		T39	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	317	1			T14	2		T36	2		T30	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	317	1			T14	2		T15	2		T36	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T39	1		T42	1		T162	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T39	1		T41	1		T19	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T20	1		T42	1		T180	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T39	1		T163	1		T22	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T39	2		T19	1		T203	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T211	1		T27	1		T180	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T20	1		T163	1		T212	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T42	1		T185	1		T181	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	300	1			T5	1		T37	6		T99	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	290	1			T5	1		T15	3		T37	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	42	1			T39	2		T41	1		T42	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T37	1		T39	1		T203	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T39	1		T22	2		T185	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	35	1			T37	1		T32	1		T180	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T136	1		T20	1		T42	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T15	2		T41	1		T136	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T185	1		T184	1		T212	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	27	1			T15	1		T39	1		T18	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	306	1			T5	1		T14	2		T15	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	277	1			T5	1		T14	2		T15	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T15	1		T41	1		T19	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T30	1		T20	1		T180	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T37	1		T55	1		T189	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T22	1		T206	1		T189	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T37	1		T19	1		T42	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	15	1			T39	1		T19	1		T183	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T15	1		T39	1		T20	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	9	1			T39	1		T180	1		T185	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	295	1			T15	2		T30	2		T37	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	314	1			T15	2		T30	1		T37	4
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T39	1		T18	1		T20	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T30	1		T39	1		T42	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	32	1			T37	1		T136	1		T20	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T41	1		T136	1		T203	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T39	1		T20	1		T180	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T30	1		T37	1		T18	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T15	1		T41	1		T136	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	26	1			T39	2		T18	1		T136	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	271	1			T5	2		T30	1		T37	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	307	1			T5	2		T15	1		T37	2