Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	839	1			T1	4		T12	10		T17	7
all_values[1]	839	1			T1	4		T12	10		T17	7
all_values[2]	839	1			T1	4		T12	10		T17	7
all_values[3]	839	1			T1	4		T12	10		T17	7
all_values[4]	839	1			T1	4		T12	10		T17	7
all_values[5]	839	1			T1	4		T12	10		T17	7
all_values[6]	839	1			T1	4		T12	10		T17	7
all_values[7]	839	1			T1	4		T12	10		T17	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3457

1

T1

19

T12

42

T17

29

auto[1]

3255

1

T1

13

T12

38

T17

27

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2715

1

T1

16

T12

30

T17

24

auto[1]

3997

1

T1

16

T12

50

T17

32

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3858

1

T1

22

T12

45

T17

33

auto[1]

2854

1

T1

10

T12

35

T17

23

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	157	1			T12	2		T17	1		T19	7
all_values[0]	auto[0]	auto[0]	auto[1]	75	1			T1	1		T17	1		T19	4
all_values[0]	auto[0]	auto[1]	auto[0]	174	1			T1	2		T12	2		T19	1
all_values[0]	auto[0]	auto[1]	auto[1]	89	1			T12	2		T17	1		T19	2
all_values[0]	auto[1]	auto[0]	auto[1]	172	1			T1	1		T12	2		T17	2
all_values[0]	auto[1]	auto[1]	auto[1]	172	1			T12	2		T17	2		T19	3
all_values[1]	auto[0]	auto[0]	auto[0]	183	1			T12	1		T17	3		T19	6
all_values[1]	auto[0]	auto[0]	auto[1]	70	1			T1	2		T12	3		T19	2
all_values[1]	auto[0]	auto[1]	auto[0]	153	1			T12	2		T17	3		T19	4
all_values[1]	auto[0]	auto[1]	auto[1]	81	1			T19	1		T20	1		T21	4
all_values[1]	auto[1]	auto[0]	auto[1]	186	1			T1	2		T12	2		T17	1
all_values[1]	auto[1]	auto[1]	auto[1]	166	1			T12	2		T19	6		T20	1
all_values[2]	auto[0]	auto[0]	auto[0]	163	1			T12	1		T19	2		T21	2
all_values[2]	auto[0]	auto[0]	auto[1]	82	1			T1	1		T12	2		T17	1
all_values[2]	auto[0]	auto[1]	auto[0]	165	1			T12	3		T17	1		T19	11
all_values[2]	auto[0]	auto[1]	auto[1]	72	1			T1	1		T12	1		T17	1
all_values[2]	auto[1]	auto[0]	auto[1]	177	1			T1	1		T12	1		T17	1
all_values[2]	auto[1]	auto[1]	auto[1]	180	1			T1	1		T12	2		T17	3
all_values[3]	auto[0]	auto[0]	auto[0]	137	1			T1	2		T17	4		T19	4
all_values[3]	auto[0]	auto[0]	auto[1]	86	1			T12	1		T17	2		T19	7
all_values[3]	auto[0]	auto[1]	auto[0]	169	1			T12	1		T19	2		T20	2
all_values[3]	auto[0]	auto[1]	auto[1]	76	1			T12	1		T19	1		T20	2
all_values[3]	auto[1]	auto[0]	auto[1]	193	1			T1	1		T12	3		T17	1
all_values[3]	auto[1]	auto[1]	auto[1]	178	1			T1	1		T12	4		T19	5
all_values[4]	auto[0]	auto[0]	auto[0]	155	1			T1	4		T12	2		T17	1
all_values[4]	auto[0]	auto[0]	auto[1]	73	1			T19	3		T20	1		T21	3
all_values[4]	auto[0]	auto[1]	auto[0]	154	1			T12	2		T17	3		T19	2
all_values[4]	auto[0]	auto[1]	auto[1]	85	1			T12	2		T19	3		T21	5
all_values[4]	auto[1]	auto[0]	auto[1]	193	1			T12	2		T19	4		T20	3
all_values[4]	auto[1]	auto[1]	auto[1]	179	1			T12	2		T17	3		T19	5
all_values[5]	auto[0]	auto[0]	auto[0]	250	1			T1	1		T12	5		T17	3
all_values[5]	auto[0]	auto[1]	auto[0]	213	1			T1	1		T17	1		T19	5
all_values[5]	auto[1]	auto[0]	auto[1]	198	1			T12	5		T17	1		T19	6
all_values[5]	auto[1]	auto[1]	auto[1]	178	1			T1	2		T17	2		T19	4
all_values[6]	auto[0]	auto[0]	auto[0]	179	1			T1	2		T12	3		T17	1
all_values[6]	auto[0]	auto[0]	auto[1]	85	1			T17	1		T19	1		T20	3
all_values[6]	auto[0]	auto[1]	auto[0]	157	1			T1	2		T12	3		T19	4
all_values[6]	auto[0]	auto[1]	auto[1]	83	1			T17	1		T21	1		T22	2
all_values[6]	auto[1]	auto[0]	auto[1]	197	1			T12	1		T17	2		T19	7
all_values[6]	auto[1]	auto[1]	auto[1]	138	1			T12	3		T17	2		T19	4
all_values[7]	auto[0]	auto[0]	auto[0]	166	1			T1	1		T12	1		T17	2
all_values[7]	auto[0]	auto[0]	auto[1]	95	1			T12	2		T19	1		T20	1
all_values[7]	auto[0]	auto[1]	auto[0]	140	1			T1	1		T12	2		T17	1
all_values[7]	auto[0]	auto[1]	auto[1]	91	1			T1	1		T12	1		T17	1
all_values[7]	auto[1]	auto[0]	auto[1]	185	1			T12	3		T17	1		T19	7
all_values[7]	auto[1]	auto[1]	auto[1]	162	1			T1	1		T12	1		T17	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal