Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1908

1

T4

3

T7

11

T12

10

auto[1]

1874

1

T4

6

T7

8

T12

9

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1986

1

T7

9

T12

19

T23

3

auto[1]

1796

1

T4

9

T7

10

T15

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3004

1

T4

9

T7

15

T12

10

auto[1]

778

1

T7

4

T12

9

T23

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	728	1			T4	2		T7	6		T12	3
valid[1]	780	1			T7	3		T12	1		T23	1
valid[2]	765	1			T4	1		T7	4		T12	4
valid[3]	711	1			T4	4		T7	4		T12	7
valid[4]	798	1			T4	2		T7	2		T12	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	123	1			T12	1		T37	1		T44	1
auto[0]	auto[0]	valid[0]	auto[1]	173	1			T7	2		T17	1		T91	2
auto[0]	auto[0]	valid[1]	auto[0]	124	1			T7	1		T23	1		T37	1
auto[0]	auto[0]	valid[1]	auto[1]	187	1			T7	1		T15	1		T91	4
auto[0]	auto[0]	valid[2]	auto[0]	131	1			T12	1		T15	1		T37	1
auto[0]	auto[0]	valid[2]	auto[1]	190	1			T4	1		T7	2		T15	1
auto[0]	auto[0]	valid[3]	auto[0]	130	1			T7	1		T12	1		T15	1
auto[0]	auto[0]	valid[3]	auto[1]	151	1			T4	2		T7	1		T44	1
auto[0]	auto[0]	valid[4]	auto[0]	118	1			T12	1		T23	1		T15	1
auto[0]	auto[0]	valid[4]	auto[1]	169	1			T7	1		T91	3		T92	2
auto[0]	auto[1]	valid[0]	auto[0]	102	1			T12	1		T15	1		T45	1
auto[0]	auto[1]	valid[0]	auto[1]	176	1			T4	2		T7	2		T91	4
auto[0]	auto[1]	valid[1]	auto[0]	124	1			T17	1		T37	3		T44	1
auto[0]	auto[1]	valid[1]	auto[1]	195	1			T91	2		T92	5		T309	4
auto[0]	auto[1]	valid[2]	auto[0]	104	1			T7	2		T12	2		T15	1
auto[0]	auto[1]	valid[2]	auto[1]	182	1			T91	6		T92	5		T93	1
auto[0]	auto[1]	valid[3]	auto[0]	115	1			T7	1		T12	2		T37	1
auto[0]	auto[1]	valid[3]	auto[1]	162	1			T4	2		T7	1		T91	2
auto[0]	auto[1]	valid[4]	auto[0]	137	1			T12	1		T15	1		T37	1
auto[0]	auto[1]	valid[4]	auto[1]	211	1			T4	2		T44	2		T91	2
auto[1]	auto[0]	valid[0]	auto[0]	87	1			T7	1		T12	1		T23	1
auto[1]	auto[0]	valid[1]	auto[0]	83	1			T19	1		T20	1		T81	1
auto[1]	auto[0]	valid[2]	auto[0]	93	1			T17	2		T45	1		T19	1
auto[1]	auto[0]	valid[3]	auto[0]	72	1			T12	3		T19	2		T81	1
auto[1]	auto[0]	valid[4]	auto[0]	77	1			T7	1		T12	2		T37	1
auto[1]	auto[1]	valid[0]	auto[0]	67	1			T7	1		T37	2		T18	1
auto[1]	auto[1]	valid[1]	auto[0]	67	1			T7	1		T12	1		T15	2
auto[1]	auto[1]	valid[2]	auto[0]	65	1			T12	1		T37	1		T20	1
auto[1]	auto[1]	valid[3]	auto[0]	81	1			T12	1		T15	1		T17	1
auto[1]	auto[1]	valid[4]	auto[0]	86	1			T15	2		T18	1		T32	3

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal