Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51756

1

T7

315

T8

7

T12

512

auto[1]

18910

1

T4

129

T7

80

T15

44

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51542

1

T4

129

T7

256

T8

3

auto[1]

19124

1

T7

139

T8

4

T12

173

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	36201	1			T4	71		T7	212		T8	4
others[1]	5897	1			T4	8		T7	33		T12	49
others[2]	5979	1			T4	8		T7	34		T8	2
others[3]	6869	1			T4	10		T7	39		T12	46
interest[1]	4000	1			T4	8		T7	22		T12	28
interest[4]	23745	1			T4	53		T7	142		T8	3
interest[64]	11720	1			T4	24		T7	55		T8	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16609	1			T7	95		T8	2		T12	189
auto[0]	auto[0]	others[1]	2727	1			T7	18		T12	31		T15	10
auto[0]	auto[0]	others[2]	2777	1			T7	11		T8	1		T12	29
auto[0]	auto[0]	others[3]	3204	1			T7	18		T12	34		T23	3
auto[0]	auto[0]	interest[1]	1887	1			T7	7		T12	19		T15	8
auto[0]	auto[0]	interest[4]	10867	1			T7	62		T8	1		T12	122
auto[0]	auto[0]	interest[64]	5428	1			T7	27		T12	37		T15	31
auto[0]	auto[1]	others[0]	9753	1			T4	71		T7	44		T15	28
auto[0]	auto[1]	others[1]	1520	1			T4	8		T7	6		T15	3
auto[0]	auto[1]	others[2]	1632	1			T4	8		T7	6		T17	3
auto[0]	auto[1]	others[3]	1810	1			T4	10		T7	8		T15	4
auto[0]	auto[1]	interest[1]	1065	1			T4	8		T7	3		T17	3
auto[0]	auto[1]	interest[4]	6464	1			T4	53		T7	34		T15	18
auto[0]	auto[1]	interest[64]	3130	1			T4	24		T7	13		T15	9
auto[1]	auto[0]	others[0]	9839	1			T7	73		T8	2		T12	81
auto[1]	auto[0]	others[1]	1650	1			T7	9		T12	18		T23	1
auto[1]	auto[0]	others[2]	1570	1			T7	17		T8	1		T12	24
auto[1]	auto[0]	others[3]	1855	1			T7	13		T12	12		T23	1
auto[1]	auto[0]	interest[1]	1048	1			T7	12		T12	9		T15	6
auto[1]	auto[0]	interest[4]	6414	1			T7	46		T8	2		T12	60
auto[1]	auto[0]	interest[64]	3162	1			T7	15		T8	1		T12	29

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal