SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
96.04 | 98.38 | 93.99 | 98.62 | 89.36 | 97.21 | 95.45 | 99.26 |
T158 | /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2143037570 | Jul 15 07:24:52 PM PDT 24 | Jul 15 07:25:32 PM PDT 24 | 168530885 ps | ||
T1029 | /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3638570782 | Jul 15 07:25:15 PM PDT 24 | Jul 15 07:26:00 PM PDT 24 | 61243471 ps | ||
T1030 | /workspace/coverage/cover_reg_top/25.spi_device_intr_test.895495063 | Jul 15 07:25:15 PM PDT 24 | Jul 15 07:25:57 PM PDT 24 | 48091464 ps | ||
T111 | /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.658022260 | Jul 15 07:25:10 PM PDT 24 | Jul 15 07:25:55 PM PDT 24 | 491892902 ps | ||
T1031 | /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2254537639 | Jul 15 07:25:10 PM PDT 24 | Jul 15 07:25:52 PM PDT 24 | 20682401 ps | ||
T1032 | /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3707869703 | Jul 15 07:25:16 PM PDT 24 | Jul 15 07:25:58 PM PDT 24 | 51762981 ps | ||
T126 | /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3334782326 | Jul 15 07:25:06 PM PDT 24 | Jul 15 07:25:48 PM PDT 24 | 85070598 ps | ||
T1033 | /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2854532048 | Jul 15 07:24:55 PM PDT 24 | Jul 15 07:25:35 PM PDT 24 | 29831550 ps | ||
T1034 | /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3407796036 | Jul 15 07:25:06 PM PDT 24 | Jul 15 07:25:53 PM PDT 24 | 1101039008 ps | ||
T166 | /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3239081838 | Jul 15 07:24:52 PM PDT 24 | Jul 15 07:25:35 PM PDT 24 | 1116980484 ps | ||
T107 | /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3549189493 | Jul 15 07:25:06 PM PDT 24 | Jul 15 07:25:47 PM PDT 24 | 104242472 ps | ||
T1035 | /workspace/coverage/cover_reg_top/7.spi_device_intr_test.477490602 | Jul 15 07:25:03 PM PDT 24 | Jul 15 07:25:42 PM PDT 24 | 40952706 ps | ||
T1036 | /workspace/coverage/cover_reg_top/42.spi_device_intr_test.785051498 | Jul 15 07:25:16 PM PDT 24 | Jul 15 07:25:57 PM PDT 24 | 73844854 ps | ||
T1037 | /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3821816828 | Jul 15 07:25:07 PM PDT 24 | Jul 15 07:25:48 PM PDT 24 | 54944975 ps | ||
T127 | /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1561988910 | Jul 15 07:25:07 PM PDT 24 | Jul 15 07:25:49 PM PDT 24 | 45730691 ps | ||
T1038 | /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2975134943 | Jul 15 07:25:02 PM PDT 24 | Jul 15 07:25:41 PM PDT 24 | 15216882 ps | ||
T128 | /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1662692063 | Jul 15 07:25:02 PM PDT 24 | Jul 15 07:25:42 PM PDT 24 | 83271876 ps | ||
T1039 | /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1588325637 | Jul 15 07:24:58 PM PDT 24 | Jul 15 07:25:36 PM PDT 24 | 18700367 ps | ||
T110 | /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3590619295 | Jul 15 07:24:56 PM PDT 24 | Jul 15 07:25:36 PM PDT 24 | 27777882 ps | ||
T1040 | /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1653471871 | Jul 15 07:25:08 PM PDT 24 | Jul 15 07:25:52 PM PDT 24 | 115115769 ps | ||
T129 | /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1815211268 | Jul 15 07:24:57 PM PDT 24 | Jul 15 07:25:36 PM PDT 24 | 71509366 ps | ||
T1041 | /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3226309771 | Jul 15 07:24:58 PM PDT 24 | Jul 15 07:25:38 PM PDT 24 | 104880672 ps | ||
T1042 | /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3571720156 | Jul 15 07:25:06 PM PDT 24 | Jul 15 07:25:46 PM PDT 24 | 12328135 ps | ||
T109 | /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3260782886 | Jul 15 07:25:04 PM PDT 24 | Jul 15 07:25:47 PM PDT 24 | 84538570 ps | ||
T170 | /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1606801593 | Jul 15 07:25:07 PM PDT 24 | Jul 15 07:26:09 PM PDT 24 | 824381219 ps | ||
T1043 | /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2419898006 | Jul 15 07:25:11 PM PDT 24 | Jul 15 07:25:52 PM PDT 24 | 28631163 ps | ||
T1044 | /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1042481445 | Jul 15 07:25:05 PM PDT 24 | Jul 15 07:25:46 PM PDT 24 | 12096851 ps | ||
T130 | /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.315585599 | Jul 15 07:25:02 PM PDT 24 | Jul 15 07:25:43 PM PDT 24 | 142998988 ps | ||
T1045 | /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1582599598 | Jul 15 07:25:04 PM PDT 24 | Jul 15 07:25:45 PM PDT 24 | 17493528 ps | ||
T167 | /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.37887402 | Jul 15 07:25:04 PM PDT 24 | Jul 15 07:25:58 PM PDT 24 | 2286797422 ps | ||
T131 | /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3279089096 | Jul 15 07:24:49 PM PDT 24 | Jul 15 07:25:27 PM PDT 24 | 41750601 ps | ||
T1046 | /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1922516963 | Jul 15 07:24:58 PM PDT 24 | Jul 15 07:25:38 PM PDT 24 | 27284422 ps | ||
T1047 | /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3989535567 | Jul 15 07:25:03 PM PDT 24 | Jul 15 07:25:44 PM PDT 24 | 533602233 ps | ||
T108 | /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3071111749 | Jul 15 07:24:51 PM PDT 24 | Jul 15 07:25:30 PM PDT 24 | 290105376 ps | ||
T1048 | /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1412882427 | Jul 15 07:25:01 PM PDT 24 | Jul 15 07:25:43 PM PDT 24 | 212674854 ps | ||
T112 | /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1065710163 | Jul 15 07:24:49 PM PDT 24 | Jul 15 07:25:29 PM PDT 24 | 617289934 ps | ||
T1049 | /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1185435664 | Jul 15 07:24:49 PM PDT 24 | Jul 15 07:25:27 PM PDT 24 | 14141496 ps | ||
T135 | /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1360904173 | Jul 15 07:24:56 PM PDT 24 | Jul 15 07:25:36 PM PDT 24 | 123893558 ps | ||
T1050 | /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3940728384 | Jul 15 07:25:05 PM PDT 24 | Jul 15 07:25:47 PM PDT 24 | 1052632478 ps | ||
T1051 | /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.985893614 | Jul 15 07:24:59 PM PDT 24 | Jul 15 07:25:40 PM PDT 24 | 251417473 ps | ||
T168 | /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1247326667 | Jul 15 07:25:00 PM PDT 24 | Jul 15 07:25:45 PM PDT 24 | 427641296 ps | ||
T1052 | /workspace/coverage/cover_reg_top/24.spi_device_intr_test.32993029 | Jul 15 07:25:12 PM PDT 24 | Jul 15 07:25:53 PM PDT 24 | 38011955 ps | ||
T1053 | /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2049925213 | Jul 15 07:25:05 PM PDT 24 | Jul 15 07:25:48 PM PDT 24 | 668172178 ps | ||
T1054 | /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.844253590 | Jul 15 07:25:07 PM PDT 24 | Jul 15 07:25:48 PM PDT 24 | 73979275 ps | ||
T1055 | /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1062301967 | Jul 15 07:24:53 PM PDT 24 | Jul 15 07:25:32 PM PDT 24 | 10556933 ps | ||
T1056 | /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3610226687 | Jul 15 07:24:48 PM PDT 24 | Jul 15 07:25:27 PM PDT 24 | 11536501 ps | ||
T1057 | /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1966844736 | Jul 15 07:24:57 PM PDT 24 | Jul 15 07:25:38 PM PDT 24 | 208923793 ps | ||
T1058 | /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2467820144 | Jul 15 07:25:13 PM PDT 24 | Jul 15 07:25:56 PM PDT 24 | 69173953 ps | ||
T1059 | /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.549480638 | Jul 15 07:24:59 PM PDT 24 | Jul 15 07:25:43 PM PDT 24 | 229474070 ps | ||
T1060 | /workspace/coverage/cover_reg_top/14.spi_device_intr_test.4210146310 | Jul 15 07:25:07 PM PDT 24 | Jul 15 07:25:46 PM PDT 24 | 27493342 ps | ||
T1061 | /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.717944510 | Jul 15 07:24:57 PM PDT 24 | Jul 15 07:26:08 PM PDT 24 | 2167880942 ps | ||
T88 | /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3547323982 | Jul 15 07:24:53 PM PDT 24 | Jul 15 07:25:32 PM PDT 24 | 24085109 ps | ||
T134 | /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2918102592 | Jul 15 07:24:51 PM PDT 24 | Jul 15 07:25:29 PM PDT 24 | 106563082 ps | ||
T1062 | /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2778712470 | Jul 15 07:24:59 PM PDT 24 | Jul 15 07:25:39 PM PDT 24 | 145996386 ps | ||
T1063 | /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1198281990 | Jul 15 07:24:51 PM PDT 24 | Jul 15 07:25:30 PM PDT 24 | 73250539 ps | ||
T1064 | /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1940352412 | Jul 15 07:24:57 PM PDT 24 | Jul 15 07:25:36 PM PDT 24 | 11957917 ps | ||
T1065 | /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.865624388 | Jul 15 07:25:09 PM PDT 24 | Jul 15 07:25:51 PM PDT 24 | 163544339 ps | ||
T1066 | /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3307055144 | Jul 15 07:25:09 PM PDT 24 | Jul 15 07:25:49 PM PDT 24 | 14647862 ps | ||
T132 | /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.387893829 | Jul 15 07:25:05 PM PDT 24 | Jul 15 07:25:46 PM PDT 24 | 48105787 ps | ||
T173 | /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1336395030 | Jul 15 07:24:58 PM PDT 24 | Jul 15 07:25:52 PM PDT 24 | 542150405 ps | ||
T1067 | /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.470810356 | Jul 15 07:24:57 PM PDT 24 | Jul 15 07:25:37 PM PDT 24 | 161103081 ps | ||
T133 | /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1224789083 | Jul 15 07:25:07 PM PDT 24 | Jul 15 07:25:47 PM PDT 24 | 47481925 ps | ||
T1068 | /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.552738391 | Jul 15 07:25:02 PM PDT 24 | Jul 15 07:25:42 PM PDT 24 | 28999185 ps | ||
T1069 | /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3083090050 | Jul 15 07:25:03 PM PDT 24 | Jul 15 07:25:43 PM PDT 24 | 98574520 ps | ||
T1070 | /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1810181724 | Jul 15 07:25:13 PM PDT 24 | Jul 15 07:25:55 PM PDT 24 | 11833157 ps | ||
T1071 | /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.4114799747 | Jul 15 07:25:09 PM PDT 24 | Jul 15 07:25:57 PM PDT 24 | 1181155608 ps | ||
T1072 | /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.425627761 | Jul 15 07:24:59 PM PDT 24 | Jul 15 07:25:40 PM PDT 24 | 69090174 ps | ||
T1073 | /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1062187576 | Jul 15 07:25:10 PM PDT 24 | Jul 15 07:25:55 PM PDT 24 | 125519407 ps | ||
T89 | /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2758740346 | Jul 15 07:24:56 PM PDT 24 | Jul 15 07:25:36 PM PDT 24 | 24819962 ps | ||
T1074 | /workspace/coverage/cover_reg_top/3.spi_device_intr_test.876386560 | Jul 15 07:24:58 PM PDT 24 | Jul 15 07:25:38 PM PDT 24 | 45094180 ps | ||
T1075 | /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2227326366 | Jul 15 07:24:59 PM PDT 24 | Jul 15 07:25:40 PM PDT 24 | 45749705 ps | ||
T1076 | /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3537748410 | Jul 15 07:25:06 PM PDT 24 | Jul 15 07:25:46 PM PDT 24 | 14885068 ps | ||
T1077 | /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2243101362 | Jul 15 07:25:07 PM PDT 24 | Jul 15 07:26:07 PM PDT 24 | 836188784 ps | ||
T1078 | /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.152771985 | Jul 15 07:24:51 PM PDT 24 | Jul 15 07:25:29 PM PDT 24 | 68927730 ps | ||
T1079 | /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3502598728 | Jul 15 07:25:00 PM PDT 24 | Jul 15 07:25:39 PM PDT 24 | 43397211 ps | ||
T1080 | /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3738977648 | Jul 15 07:25:07 PM PDT 24 | Jul 15 07:25:50 PM PDT 24 | 170141779 ps | ||
T1081 | /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1909443157 | Jul 15 07:24:51 PM PDT 24 | Jul 15 07:26:02 PM PDT 24 | 2173926402 ps | ||
T1082 | /workspace/coverage/cover_reg_top/46.spi_device_intr_test.523360498 | Jul 15 07:25:17 PM PDT 24 | Jul 15 07:25:58 PM PDT 24 | 15953155 ps | ||
T1083 | /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.4222477798 | Jul 15 07:25:03 PM PDT 24 | Jul 15 07:25:42 PM PDT 24 | 57230378 ps | ||
T1084 | /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1953282108 | Jul 15 07:25:04 PM PDT 24 | Jul 15 07:25:54 PM PDT 24 | 817160663 ps | ||
T1085 | /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3468746619 | Jul 15 07:24:58 PM PDT 24 | Jul 15 07:25:39 PM PDT 24 | 66208245 ps | ||
T1086 | /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.187901939 | Jul 15 07:24:50 PM PDT 24 | Jul 15 07:26:02 PM PDT 24 | 1812587479 ps | ||
T1087 | /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3313908352 | Jul 15 07:25:00 PM PDT 24 | Jul 15 07:25:40 PM PDT 24 | 117548222 ps | ||
T1088 | /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1688635463 | Jul 15 07:25:06 PM PDT 24 | Jul 15 07:25:46 PM PDT 24 | 49225247 ps | ||
T1089 | /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2419273778 | Jul 15 07:25:05 PM PDT 24 | Jul 15 07:25:46 PM PDT 24 | 205892295 ps | ||
T1090 | /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.947863484 | Jul 15 07:24:48 PM PDT 24 | Jul 15 07:25:49 PM PDT 24 | 4845607926 ps | ||
T171 | /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2519941644 | Jul 15 07:25:04 PM PDT 24 | Jul 15 07:25:59 PM PDT 24 | 300275461 ps | ||
T1091 | /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1545434698 | Jul 15 07:25:06 PM PDT 24 | Jul 15 07:25:48 PM PDT 24 | 46873569 ps | ||
T1092 | /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1472685395 | Jul 15 07:25:05 PM PDT 24 | Jul 15 07:25:49 PM PDT 24 | 58333849 ps | ||
T1093 | /workspace/coverage/cover_reg_top/10.spi_device_intr_test.424807875 | Jul 15 07:24:59 PM PDT 24 | Jul 15 07:25:38 PM PDT 24 | 37168517 ps | ||
T1094 | /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2403971095 | Jul 15 07:25:05 PM PDT 24 | Jul 15 07:25:47 PM PDT 24 | 215787085 ps | ||
T1095 | /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1902891887 | Jul 15 07:24:53 PM PDT 24 | Jul 15 07:25:31 PM PDT 24 | 15589016 ps | ||
T1096 | /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2255738366 | Jul 15 07:25:15 PM PDT 24 | Jul 15 07:25:57 PM PDT 24 | 28663273 ps | ||
T1097 | /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2215612090 | Jul 15 07:25:08 PM PDT 24 | Jul 15 07:25:51 PM PDT 24 | 1077961557 ps | ||
T1098 | /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2514472686 | Jul 15 07:25:01 PM PDT 24 | Jul 15 07:26:02 PM PDT 24 | 830450490 ps | ||
T1099 | /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4293684943 | Jul 15 07:25:15 PM PDT 24 | Jul 15 07:25:57 PM PDT 24 | 12755268 ps | ||
T90 | /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3332428616 | Jul 15 07:24:58 PM PDT 24 | Jul 15 07:25:38 PM PDT 24 | 66607294 ps | ||
T1100 | /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3720008772 | Jul 15 07:25:04 PM PDT 24 | Jul 15 07:25:45 PM PDT 24 | 42324063 ps | ||
T1101 | /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3646821788 | Jul 15 07:25:10 PM PDT 24 | Jul 15 07:25:52 PM PDT 24 | 16476948 ps | ||
T1102 | /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.859869269 | Jul 15 07:25:05 PM PDT 24 | Jul 15 07:25:48 PM PDT 24 | 124527058 ps | ||
T169 | /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.547516950 | Jul 15 07:24:55 PM PDT 24 | Jul 15 07:25:39 PM PDT 24 | 286747054 ps | ||
T1103 | /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2043374229 | Jul 15 07:24:51 PM PDT 24 | Jul 15 07:25:28 PM PDT 24 | 36360478 ps | ||
T1104 | /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1967692908 | Jul 15 07:25:16 PM PDT 24 | Jul 15 07:25:58 PM PDT 24 | 14334151 ps | ||
T1105 | /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1708735046 | Jul 15 07:24:58 PM PDT 24 | Jul 15 07:25:40 PM PDT 24 | 284303971 ps | ||
T1106 | /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.716233955 | Jul 15 07:25:04 PM PDT 24 | Jul 15 07:25:48 PM PDT 24 | 264776881 ps | ||
T1107 | /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2579390726 | Jul 15 07:25:10 PM PDT 24 | Jul 15 07:25:52 PM PDT 24 | 15307341 ps | ||
T1108 | /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1490641449 | Jul 15 07:24:55 PM PDT 24 | Jul 15 07:25:34 PM PDT 24 | 97640385 ps | ||
T1109 | /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2524627980 | Jul 15 07:24:51 PM PDT 24 | Jul 15 07:25:44 PM PDT 24 | 1229638511 ps | ||
T1110 | /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3645575802 | Jul 15 07:25:03 PM PDT 24 | Jul 15 07:25:49 PM PDT 24 | 340401791 ps | ||
T1111 | /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.613556232 | Jul 15 07:25:03 PM PDT 24 | Jul 15 07:25:45 PM PDT 24 | 419782697 ps | ||
T1112 | /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3210225538 | Jul 15 07:25:00 PM PDT 24 | Jul 15 07:25:41 PM PDT 24 | 43380827 ps | ||
T1113 | /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3078028299 | Jul 15 07:25:04 PM PDT 24 | Jul 15 07:25:43 PM PDT 24 | 70001045 ps | ||
T1114 | /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1225201466 | Jul 15 07:25:06 PM PDT 24 | Jul 15 07:25:46 PM PDT 24 | 57872904 ps | ||
T1115 | /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1246781197 | Jul 15 07:24:50 PM PDT 24 | Jul 15 07:25:30 PM PDT 24 | 949675807 ps | ||
T1116 | /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2319871909 | Jul 15 07:25:16 PM PDT 24 | Jul 15 07:26:00 PM PDT 24 | 275105528 ps | ||
T1117 | /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.370964837 | Jul 15 07:24:55 PM PDT 24 | Jul 15 07:25:35 PM PDT 24 | 24417913 ps | ||
T1118 | /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1906262335 | Jul 15 07:24:48 PM PDT 24 | Jul 15 07:25:29 PM PDT 24 | 454321544 ps | ||
T1119 | /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1626824682 | Jul 15 07:25:00 PM PDT 24 | Jul 15 07:25:46 PM PDT 24 | 561820043 ps | ||
T1120 | /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2384519705 | Jul 15 07:25:07 PM PDT 24 | Jul 15 07:25:49 PM PDT 24 | 15987363 ps | ||
T172 | /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2690602632 | Jul 15 07:24:59 PM PDT 24 | Jul 15 07:25:58 PM PDT 24 | 3207618128 ps | ||
T1121 | /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1062901742 | Jul 15 07:25:12 PM PDT 24 | Jul 15 07:25:55 PM PDT 24 | 168735773 ps | ||
T1122 | /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2546940434 | Jul 15 07:25:01 PM PDT 24 | Jul 15 07:25:42 PM PDT 24 | 941334178 ps | ||
T1123 | /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3635790446 | Jul 15 07:25:08 PM PDT 24 | Jul 15 07:25:50 PM PDT 24 | 536786462 ps | ||
T1124 | /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1697482059 | Jul 15 07:24:58 PM PDT 24 | Jul 15 07:25:38 PM PDT 24 | 61885051 ps | ||
T1125 | /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.4265985629 | Jul 15 07:25:02 PM PDT 24 | Jul 15 07:25:44 PM PDT 24 | 144563500 ps | ||
T1126 | /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2874301127 | Jul 15 07:25:12 PM PDT 24 | Jul 15 07:25:53 PM PDT 24 | 32746344 ps | ||
T1127 | /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.777475139 | Jul 15 07:25:07 PM PDT 24 | Jul 15 07:25:49 PM PDT 24 | 138463280 ps | ||
T1128 | /workspace/coverage/cover_reg_top/43.spi_device_intr_test.4093499138 | Jul 15 07:25:18 PM PDT 24 | Jul 15 07:26:01 PM PDT 24 | 11898129 ps | ||
T1129 | /workspace/coverage/cover_reg_top/30.spi_device_intr_test.540855786 | Jul 15 07:25:12 PM PDT 24 | Jul 15 07:25:53 PM PDT 24 | 15546315 ps | ||
T1130 | /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2538170710 | Jul 15 07:24:57 PM PDT 24 | Jul 15 07:25:36 PM PDT 24 | 49222573 ps | ||
T1131 | /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2456900596 | Jul 15 07:25:15 PM PDT 24 | Jul 15 07:25:58 PM PDT 24 | 110291267 ps |
Test location | /workspace/coverage/default/25.spi_device_flash_all.2265377752 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 589326807 ps |
CPU time | 13.66 seconds |
Started | Jul 15 06:48:21 PM PDT 24 |
Finished | Jul 15 06:48:35 PM PDT 24 |
Peak memory | 239916 kb |
Host | smart-12ecbcb1-6edd-445e-b416-b67d9ab0ef25 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2265377752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2265377752 |
Directory | /workspace/25.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3104196028 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 3711090323 ps |
CPU time | 49.83 seconds |
Started | Jul 15 06:48:06 PM PDT 24 |
Finished | Jul 15 06:48:57 PM PDT 24 |
Peak memory | 250252 kb |
Host | smart-2b1cc30c-309c-4afe-a871-24c2cd17fab8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3104196028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl e.3104196028 |
Directory | /workspace/23.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/15.spi_device_stress_all.722188941 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 219233720141 ps |
CPU time | 243.97 seconds |
Started | Jul 15 06:46:58 PM PDT 24 |
Finished | Jul 15 06:51:03 PM PDT 24 |
Peak memory | 260664 kb |
Host | smart-b0f108c8-3d01-4dc0-a5e4-6c5df301ce4a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722188941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres s_all.722188941 |
Directory | /workspace/15.spi_device_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.459855312 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 2757124790 ps |
CPU time | 16.48 seconds |
Started | Jul 15 07:24:58 PM PDT 24 |
Finished | Jul 15 07:25:54 PM PDT 24 |
Peak memory | 215904 kb |
Host | smart-428fff00-4496-4ca7-8ac6-29695acd4c4a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459855312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_ tl_intg_err.459855312 |
Directory | /workspace/9.spi_device_tl_intg_err/latest |
Test location | /workspace/coverage/default/3.spi_device_flash_and_tpm.2050278683 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 50010616411 ps |
CPU time | 100.5 seconds |
Started | Jul 15 06:45:04 PM PDT 24 |
Finished | Jul 15 06:46:45 PM PDT 24 |
Peak memory | 249152 kb |
Host | smart-105172c0-0f63-4198-9bb0-e9354ccf8d7a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2050278683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2050278683 |
Directory | /workspace/3.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/39.spi_device_stress_all.1644037947 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 50416421072 ps |
CPU time | 481.85 seconds |
Started | Jul 15 06:50:07 PM PDT 24 |
Finished | Jul 15 06:58:09 PM PDT 24 |
Peak memory | 256300 kb |
Host | smart-dac90662-28cf-4324-b463-7894e3ceb60a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644037947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre ss_all.1644037947 |
Directory | /workspace/39.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/0.spi_device_ram_cfg.3041086121 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 41720458 ps |
CPU time | 0.72 seconds |
Started | Jul 15 06:44:37 PM PDT 24 |
Finished | Jul 15 06:44:38 PM PDT 24 |
Peak memory | 216052 kb |
Host | smart-913a0746-0a24-4559-a50e-6b646f64f163 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3041086121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3041086121 |
Directory | /workspace/0.spi_device_ram_cfg/latest |
Test location | /workspace/coverage/default/32.spi_device_stress_all.1601120144 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 103122610980 ps |
CPU time | 348.34 seconds |
Started | Jul 15 06:49:22 PM PDT 24 |
Finished | Jul 15 06:55:11 PM PDT 24 |
Peak memory | 281964 kb |
Host | smart-25cdefa2-22bf-49e5-8303-1f463b8e1c98 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601120144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre ss_all.1601120144 |
Directory | /workspace/32.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/14.spi_device_flash_all.766667668 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 8905458437 ps |
CPU time | 121.34 seconds |
Started | Jul 15 06:46:50 PM PDT 24 |
Finished | Jul 15 06:48:52 PM PDT 24 |
Peak memory | 267504 kb |
Host | smart-96dd1574-4f1d-422d-9775-5663a6ee24fe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=766667668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.766667668 |
Directory | /workspace/14.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/18.spi_device_stress_all.1738105488 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 153252020190 ps |
CPU time | 386.2 seconds |
Started | Jul 15 06:47:31 PM PDT 24 |
Finished | Jul 15 06:53:57 PM PDT 24 |
Peak memory | 253944 kb |
Host | smart-dfb6edae-a4b7-44ad-bf5b-d3b353028581 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738105488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre ss_all.1738105488 |
Directory | /workspace/18.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.4052251732 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 232245523019 ps |
CPU time | 441.58 seconds |
Started | Jul 15 06:45:15 PM PDT 24 |
Finished | Jul 15 06:52:37 PM PDT 24 |
Peak memory | 257412 kb |
Host | smart-1c3fd35b-ad5c-41cc-aba2-26bae0335353 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4052251732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle .4052251732 |
Directory | /workspace/4.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3841246547 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 919467084 ps |
CPU time | 4.15 seconds |
Started | Jul 15 07:25:04 PM PDT 24 |
Finished | Jul 15 07:25:45 PM PDT 24 |
Peak memory | 215864 kb |
Host | smart-0f3e8655-2b0c-43c0-912c-211fd2fc64d7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841246547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors. 3841246547 |
Directory | /workspace/10.spi_device_tl_errors/latest |
Test location | /workspace/coverage/default/1.spi_device_alert_test.2788710911 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 14087510 ps |
CPU time | 0.72 seconds |
Started | Jul 15 06:44:44 PM PDT 24 |
Finished | Jul 15 06:44:45 PM PDT 24 |
Peak memory | 205468 kb |
Host | smart-9d9d2816-b357-43d0-a8a1-82c27ccaadca |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788710911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2 788710911 |
Directory | /workspace/1.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/21.spi_device_flash_mode.3601461668 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 261538234 ps |
CPU time | 8.78 seconds |
Started | Jul 15 06:47:47 PM PDT 24 |
Finished | Jul 15 06:47:57 PM PDT 24 |
Peak memory | 238568 kb |
Host | smart-c2e4ac3d-12ad-4f4f-a39f-08dc8ea1ec27 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3601461668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3601461668 |
Directory | /workspace/21.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/8.spi_device_stress_all.4037530518 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 72962087012 ps |
CPU time | 220.64 seconds |
Started | Jul 15 06:45:57 PM PDT 24 |
Finished | Jul 15 06:49:38 PM PDT 24 |
Peak memory | 250780 kb |
Host | smart-93265cf3-1026-46e8-b70f-465ed4ab0b9b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037530518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres s_all.4037530518 |
Directory | /workspace/8.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/13.spi_device_flash_and_tpm.1391818442 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 19408009610 ps |
CPU time | 134.34 seconds |
Started | Jul 15 06:46:42 PM PDT 24 |
Finished | Jul 15 06:48:57 PM PDT 24 |
Peak memory | 257660 kb |
Host | smart-d9048466-a77b-4b34-8ea9-b3f5dfabe2b8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1391818442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1391818442 |
Directory | /workspace/13.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.749557363 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 7315162670 ps |
CPU time | 48.22 seconds |
Started | Jul 15 06:44:49 PM PDT 24 |
Finished | Jul 15 06:45:37 PM PDT 24 |
Peak memory | 256360 kb |
Host | smart-d9aad824-97a0-4f56-ae7e-fd85a0f7ae46 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=749557363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds. 749557363 |
Directory | /workspace/2.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.693370039 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 4853066166 ps |
CPU time | 24.33 seconds |
Started | Jul 15 07:24:51 PM PDT 24 |
Finished | Jul 15 07:25:52 PM PDT 24 |
Peak memory | 207696 kb |
Host | smart-41153a18-0c3b-46ba-b41d-fe4dd1837616 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693370039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr _aliasing.693370039 |
Directory | /workspace/1.spi_device_csr_aliasing/latest |
Test location | /workspace/coverage/default/11.spi_device_stress_all.1419714160 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 30017220276 ps |
CPU time | 374.41 seconds |
Started | Jul 15 06:46:21 PM PDT 24 |
Finished | Jul 15 06:52:35 PM PDT 24 |
Peak memory | 266612 kb |
Host | smart-843a30e3-a4a6-43a8-ac4b-559880233ca0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419714160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre ss_all.1419714160 |
Directory | /workspace/11.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/6.spi_device_stress_all.132103265 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 156189352273 ps |
CPU time | 423.49 seconds |
Started | Jul 15 06:45:26 PM PDT 24 |
Finished | Jul 15 06:52:30 PM PDT 24 |
Peak memory | 267092 kb |
Host | smart-abdd6784-ba95-4f28-9015-27caac4f7969 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132103265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress _all.132103265 |
Directory | /workspace/6.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.754346973 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 83667448104 ps |
CPU time | 101.41 seconds |
Started | Jul 15 06:48:46 PM PDT 24 |
Finished | Jul 15 06:50:27 PM PDT 24 |
Peak memory | 264164 kb |
Host | smart-1198fab3-f21c-46d2-b827-4ec750771333 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=754346973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds .754346973 |
Directory | /workspace/28.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.586311287 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 688071476389 ps |
CPU time | 546.33 seconds |
Started | Jul 15 06:50:36 PM PDT 24 |
Finished | Jul 15 06:59:43 PM PDT 24 |
Peak memory | 273676 kb |
Host | smart-218be582-5eca-4ea8-99a7-650746b5fe32 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=586311287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds .586311287 |
Directory | /workspace/44.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/0.spi_device_sec_cm.522966102 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 163377926 ps |
CPU time | 1.04 seconds |
Started | Jul 15 06:44:36 PM PDT 24 |
Finished | Jul 15 06:44:38 PM PDT 24 |
Peak memory | 236496 kb |
Host | smart-1ec7b1a5-592b-4a5c-a15b-17a957546d3b |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522966102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.522966102 |
Directory | /workspace/0.spi_device_sec_cm/latest |
Test location | /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.3932457905 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 38852174965 ps |
CPU time | 277.87 seconds |
Started | Jul 15 06:47:00 PM PDT 24 |
Finished | Jul 15 06:51:39 PM PDT 24 |
Peak memory | 255876 kb |
Host | smart-530907f6-80c3-487a-bcd0-d017f59913f8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3932457905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd s.3932457905 |
Directory | /workspace/16.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2356456373 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 248650011539 ps |
CPU time | 461.23 seconds |
Started | Jul 15 06:44:35 PM PDT 24 |
Finished | Jul 15 06:52:17 PM PDT 24 |
Peak memory | 265608 kb |
Host | smart-7f60a033-6b21-4d0d-b979-2b5633ba42f9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2356456373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle .2356456373 |
Directory | /workspace/0.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.4083745641 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 3463826907 ps |
CPU time | 89.1 seconds |
Started | Jul 15 06:47:42 PM PDT 24 |
Finished | Jul 15 06:49:12 PM PDT 24 |
Peak memory | 273076 kb |
Host | smart-ae4e483f-2acd-4d5a-a2d4-8f3fed888f66 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4083745641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl e.4083745641 |
Directory | /workspace/20.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/35.spi_device_stress_all.1357590544 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 11033195515 ps |
CPU time | 59.44 seconds |
Started | Jul 15 06:49:37 PM PDT 24 |
Finished | Jul 15 06:50:37 PM PDT 24 |
Peak memory | 217692 kb |
Host | smart-65413e0e-2841-45a2-a15b-29b89fb04dc4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357590544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre ss_all.1357590544 |
Directory | /workspace/35.spi_device_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2728532344 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 300042466 ps |
CPU time | 2.25 seconds |
Started | Jul 15 07:24:55 PM PDT 24 |
Finished | Jul 15 07:25:36 PM PDT 24 |
Peak memory | 216996 kb |
Host | smart-15005de7-54fd-4f24-9fa8-e27e817ad797 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728532344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2 728532344 |
Directory | /workspace/6.spi_device_tl_errors/latest |
Test location | /workspace/coverage/default/34.spi_device_flash_and_tpm.2838428238 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 2906414811 ps |
CPU time | 68.09 seconds |
Started | Jul 15 06:49:30 PM PDT 24 |
Finished | Jul 15 06:50:38 PM PDT 24 |
Peak memory | 257340 kb |
Host | smart-6a15c6e3-2d27-4b3f-97eb-a738aa1245d2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2838428238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2838428238 |
Directory | /workspace/34.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.4211556794 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 209498228 ps |
CPU time | 13.02 seconds |
Started | Jul 15 07:24:53 PM PDT 24 |
Finished | Jul 15 07:25:43 PM PDT 24 |
Peak memory | 215744 kb |
Host | smart-1d9514a6-788c-42fa-a44e-de4811303631 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211556794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device _tl_intg_err.4211556794 |
Directory | /workspace/1.spi_device_tl_intg_err/latest |
Test location | /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.3768658021 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 25508136376 ps |
CPU time | 89.79 seconds |
Started | Jul 15 06:46:55 PM PDT 24 |
Finished | Jul 15 06:48:26 PM PDT 24 |
Peak memory | 262096 kb |
Host | smart-37c3a754-07bf-446e-b780-cbc785e5ff45 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3768658021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd s.3768658021 |
Directory | /workspace/15.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/25.spi_device_stress_all.3289689290 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 144169642801 ps |
CPU time | 457.3 seconds |
Started | Jul 15 06:48:30 PM PDT 24 |
Finished | Jul 15 06:56:07 PM PDT 24 |
Peak memory | 283784 kb |
Host | smart-56c3bf0c-e2bd-4826-989f-c6cc6df412fa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289689290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre ss_all.3289689290 |
Directory | /workspace/25.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.85829990 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 15262888605 ps |
CPU time | 127.05 seconds |
Started | Jul 15 06:44:51 PM PDT 24 |
Finished | Jul 15 06:46:59 PM PDT 24 |
Peak memory | 269448 kb |
Host | smart-39c017de-32b2-4fc3-b434-b5e9b90a958e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=85829990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.85829990 |
Directory | /workspace/1.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2388231141 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 139639946680 ps |
CPU time | 90.33 seconds |
Started | Jul 15 06:50:39 PM PDT 24 |
Finished | Jul 15 06:52:10 PM PDT 24 |
Peak memory | 249148 kb |
Host | smart-d1bac624-7596-4a16-9f6e-b50d450e83aa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2388231141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl e.2388231141 |
Directory | /workspace/44.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/40.spi_device_flash_and_tpm.970113383 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 3871594014 ps |
CPU time | 104.32 seconds |
Started | Jul 15 06:50:03 PM PDT 24 |
Finished | Jul 15 06:51:47 PM PDT 24 |
Peak memory | 256664 kb |
Host | smart-4120c02e-c0f2-445e-8a2a-42a681a07fe0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=970113383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.970113383 |
Directory | /workspace/40.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3239081838 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 1116980484 ps |
CPU time | 6.76 seconds |
Started | Jul 15 07:24:52 PM PDT 24 |
Finished | Jul 15 07:25:35 PM PDT 24 |
Peak memory | 215700 kb |
Host | smart-0f43c3b7-d165-4c93-b89c-b1fab31febf7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239081838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device _tl_intg_err.3239081838 |
Directory | /workspace/0.spi_device_tl_intg_err/latest |
Test location | /workspace/coverage/default/20.spi_device_flash_all.1255561345 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 50630043322 ps |
CPU time | 256.32 seconds |
Started | Jul 15 06:47:43 PM PDT 24 |
Finished | Jul 15 06:51:59 PM PDT 24 |
Peak memory | 266068 kb |
Host | smart-36d02762-6e62-477f-9591-cd6db7d0fdf1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1255561345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1255561345 |
Directory | /workspace/20.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/20.spi_device_flash_mode.3057839323 |
Short name | T966 |
Test name | |
Test status | |
Simulation time | 7768123547 ps |
CPU time | 20.31 seconds |
Started | Jul 15 06:47:39 PM PDT 24 |
Finished | Jul 15 06:48:00 PM PDT 24 |
Peak memory | 224500 kb |
Host | smart-98f517c0-4126-4e2f-a3ed-0bf5b48c750a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3057839323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3057839323 |
Directory | /workspace/20.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/34.spi_device_stress_all.2525645956 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 8469630969 ps |
CPU time | 213.92 seconds |
Started | Jul 15 06:49:30 PM PDT 24 |
Finished | Jul 15 06:53:04 PM PDT 24 |
Peak memory | 273484 kb |
Host | smart-237170d4-3da4-4a8d-8bc3-a045ac1fb25f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525645956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre ss_all.2525645956 |
Directory | /workspace/34.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/48.spi_device_flash_all.2608786020 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 3423222753 ps |
CPU time | 84.18 seconds |
Started | Jul 15 06:50:59 PM PDT 24 |
Finished | Jul 15 06:52:23 PM PDT 24 |
Peak memory | 253492 kb |
Host | smart-08467a90-3ecb-4f92-a38b-176c74bf1697 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2608786020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2608786020 |
Directory | /workspace/48.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/21.spi_device_cfg_cmd.322596411 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 287819279 ps |
CPU time | 4.8 seconds |
Started | Jul 15 06:47:45 PM PDT 24 |
Finished | Jul 15 06:47:50 PM PDT 24 |
Peak memory | 224400 kb |
Host | smart-4bec48d2-a634-4bb8-989a-8cdb3c8a808b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=322596411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.322596411 |
Directory | /workspace/21.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2690602632 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 3207618128 ps |
CPU time | 20.07 seconds |
Started | Jul 15 07:24:59 PM PDT 24 |
Finished | Jul 15 07:25:58 PM PDT 24 |
Peak memory | 215920 kb |
Host | smart-73dfd9da-2b11-48f5-b3d2-ce651dd20a48 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690602632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic e_tl_intg_err.2690602632 |
Directory | /workspace/10.spi_device_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.spi_device_flash_mode.1234836926 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 1371724365 ps |
CPU time | 24.63 seconds |
Started | Jul 15 06:44:33 PM PDT 24 |
Finished | Jul 15 06:44:58 PM PDT 24 |
Peak memory | 233808 kb |
Host | smart-32725912-0484-4f21-be0a-ea546a0cdc8a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1234836926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1234836926 |
Directory | /workspace/0.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/15.spi_device_flash_all.832408928 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 23036125654 ps |
CPU time | 62.93 seconds |
Started | Jul 15 06:46:55 PM PDT 24 |
Finished | Jul 15 06:48:00 PM PDT 24 |
Peak memory | 249140 kb |
Host | smart-27a4a5ad-cbef-48cd-92ed-31dd35579ffb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=832408928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.832408928 |
Directory | /workspace/15.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/18.spi_device_flash_all.2982164106 |
Short name | T659 |
Test name | |
Test status | |
Simulation time | 23211260218 ps |
CPU time | 55.67 seconds |
Started | Jul 15 06:47:21 PM PDT 24 |
Finished | Jul 15 06:48:17 PM PDT 24 |
Peak memory | 253096 kb |
Host | smart-c10759d4-2dfa-42b1-80d5-ab576c717fda |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2982164106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2982164106 |
Directory | /workspace/18.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/18.spi_device_flash_mode.2298748654 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 14890846614 ps |
CPU time | 63.33 seconds |
Started | Jul 15 06:47:23 PM PDT 24 |
Finished | Jul 15 06:48:27 PM PDT 24 |
Peak memory | 232904 kb |
Host | smart-1b083ee5-a106-4e31-97e8-ef7ef70d4dd0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2298748654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2298748654 |
Directory | /workspace/18.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1585945764 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 11540792908 ps |
CPU time | 145.63 seconds |
Started | Jul 15 06:49:31 PM PDT 24 |
Finished | Jul 15 06:51:58 PM PDT 24 |
Peak memory | 266676 kb |
Host | smart-f38de024-6666-4636-a553-f70a0c9fb6b2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1585945764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl e.1585945764 |
Directory | /workspace/34.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2340642426 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 36301655316 ps |
CPU time | 156.87 seconds |
Started | Jul 15 06:50:41 PM PDT 24 |
Finished | Jul 15 06:53:18 PM PDT 24 |
Peak memory | 250248 kb |
Host | smart-70d2523a-2244-4656-ac63-ac6dd6b3a934 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2340642426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl e.2340642426 |
Directory | /workspace/45.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3475813166 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 410591384 ps |
CPU time | 5.47 seconds |
Started | Jul 15 06:44:38 PM PDT 24 |
Finished | Jul 15 06:44:44 PM PDT 24 |
Peak memory | 224436 kb |
Host | smart-7c1c3c5b-ecb6-4844-bf93-e350df8b0442 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3475813166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap .3475813166 |
Directory | /workspace/0.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3071111749 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 290105376 ps |
CPU time | 2.33 seconds |
Started | Jul 15 07:24:51 PM PDT 24 |
Finished | Jul 15 07:25:30 PM PDT 24 |
Peak memory | 215920 kb |
Host | smart-f8add542-ebdc-4096-832f-bc87561762df |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071111749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3 071111749 |
Directory | /workspace/0.spi_device_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2758740346 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 24819962 ps |
CPU time | 1.29 seconds |
Started | Jul 15 07:24:56 PM PDT 24 |
Finished | Jul 15 07:25:36 PM PDT 24 |
Peak memory | 207316 kb |
Host | smart-3993bb74-018e-403b-9f51-7ba62dbef40c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758740346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs r_hw_reset.2758740346 |
Directory | /workspace/2.spi_device_csr_hw_reset/latest |
Test location | /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1015641100 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 234517996484 ps |
CPU time | 399.88 seconds |
Started | Jul 15 06:46:49 PM PDT 24 |
Finished | Jul 15 06:53:30 PM PDT 24 |
Peak memory | 269632 kb |
Host | smart-e6edef32-fd62-4c15-ba7a-284e7dcf93d2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1015641100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl e.1015641100 |
Directory | /workspace/14.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.386451334 |
Short name | T1028 |
Test name | |
Test status | |
Simulation time | 112648078 ps |
CPU time | 7.6 seconds |
Started | Jul 15 07:24:50 PM PDT 24 |
Finished | Jul 15 07:25:35 PM PDT 24 |
Peak memory | 215716 kb |
Host | smart-22c3134e-a45d-4261-9ef0-1739083076d5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386451334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr _aliasing.386451334 |
Directory | /workspace/0.spi_device_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1909443157 |
Short name | T1081 |
Test name | |
Test status | |
Simulation time | 2173926402 ps |
CPU time | 34.66 seconds |
Started | Jul 15 07:24:51 PM PDT 24 |
Finished | Jul 15 07:26:02 PM PDT 24 |
Peak memory | 207492 kb |
Host | smart-696dfcf8-8ced-4dfc-bafb-b4cbe0411375 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909443157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs r_bit_bash.1909443157 |
Directory | /workspace/0.spi_device_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3547323982 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 24085109 ps |
CPU time | 1.01 seconds |
Started | Jul 15 07:24:53 PM PDT 24 |
Finished | Jul 15 07:25:32 PM PDT 24 |
Peak memory | 207212 kb |
Host | smart-16511b3c-7988-4e15-a6bb-3befdc44de0b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547323982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs r_hw_reset.3547323982 |
Directory | /workspace/0.spi_device_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1658140216 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 51111087 ps |
CPU time | 1.79 seconds |
Started | Jul 15 07:24:50 PM PDT 24 |
Finished | Jul 15 07:25:29 PM PDT 24 |
Peak memory | 216904 kb |
Host | smart-0e44fd07-3280-40cf-9d3b-55177877cc35 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658140216 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1658140216 |
Directory | /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.152771985 |
Short name | T1078 |
Test name | |
Test status | |
Simulation time | 68927730 ps |
CPU time | 1.31 seconds |
Started | Jul 15 07:24:51 PM PDT 24 |
Finished | Jul 15 07:25:29 PM PDT 24 |
Peak memory | 215636 kb |
Host | smart-74baac75-9da6-4b47-acf0-935dd49fa117 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152771985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.152771985 |
Directory | /workspace/0.spi_device_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3502598728 |
Short name | T1079 |
Test name | |
Test status | |
Simulation time | 43397211 ps |
CPU time | 0.73 seconds |
Started | Jul 15 07:25:00 PM PDT 24 |
Finished | Jul 15 07:25:39 PM PDT 24 |
Peak memory | 204264 kb |
Host | smart-2144191e-6e7e-43aa-9810-b8aa44d2ec00 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502598728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3 502598728 |
Directory | /workspace/0.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2918102592 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 106563082 ps |
CPU time | 1.84 seconds |
Started | Jul 15 07:24:51 PM PDT 24 |
Finished | Jul 15 07:25:29 PM PDT 24 |
Peak memory | 215772 kb |
Host | smart-a3e2ceb3-4a17-4349-8158-c9629f7c7652 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918102592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi _device_mem_partial_access.2918102592 |
Directory | /workspace/0.spi_device_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1902891887 |
Short name | T1095 |
Test name | |
Test status | |
Simulation time | 15589016 ps |
CPU time | 0.69 seconds |
Started | Jul 15 07:24:53 PM PDT 24 |
Finished | Jul 15 07:25:31 PM PDT 24 |
Peak memory | 204380 kb |
Host | smart-812d2b95-582c-418f-90bc-79f4988add76 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902891887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me m_walk.1902891887 |
Directory | /workspace/0.spi_device_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1246781197 |
Short name | T1115 |
Test name | |
Test status | |
Simulation time | 949675807 ps |
CPU time | 2.93 seconds |
Started | Jul 15 07:24:50 PM PDT 24 |
Finished | Jul 15 07:25:30 PM PDT 24 |
Peak memory | 215832 kb |
Host | smart-bce9363a-1ef1-4667-9e16-fd528a20d739 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246781197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s pi_device_same_csr_outstanding.1246781197 |
Directory | /workspace/0.spi_device_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.947863484 |
Short name | T1090 |
Test name | |
Test status | |
Simulation time | 4845607926 ps |
CPU time | 24.85 seconds |
Started | Jul 15 07:24:48 PM PDT 24 |
Finished | Jul 15 07:25:49 PM PDT 24 |
Peak memory | 207556 kb |
Host | smart-d9e5f5b8-c888-456b-a86a-6924adb42030 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947863484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr _bit_bash.947863484 |
Directory | /workspace/1.spi_device_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2939182882 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 15504386 ps |
CPU time | 0.94 seconds |
Started | Jul 15 07:24:51 PM PDT 24 |
Finished | Jul 15 07:25:29 PM PDT 24 |
Peak memory | 207184 kb |
Host | smart-e8109ba4-5ea6-4d8b-ae8f-5cafdba639b0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939182882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs r_hw_reset.2939182882 |
Directory | /workspace/1.spi_device_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2143037570 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 168530885 ps |
CPU time | 3.86 seconds |
Started | Jul 15 07:24:52 PM PDT 24 |
Finished | Jul 15 07:25:32 PM PDT 24 |
Peak memory | 217604 kb |
Host | smart-83ac8c3a-5512-4acc-a57d-ebc40ec14a65 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143037570 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2143037570 |
Directory | /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1198281990 |
Short name | T1063 |
Test name | |
Test status | |
Simulation time | 73250539 ps |
CPU time | 2.12 seconds |
Started | Jul 15 07:24:51 PM PDT 24 |
Finished | Jul 15 07:25:30 PM PDT 24 |
Peak memory | 215664 kb |
Host | smart-96df7973-72f0-43c5-b69a-cab0b33a6658 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198281990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1 198281990 |
Directory | /workspace/1.spi_device_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1185435664 |
Short name | T1049 |
Test name | |
Test status | |
Simulation time | 14141496 ps |
CPU time | 0.73 seconds |
Started | Jul 15 07:24:49 PM PDT 24 |
Finished | Jul 15 07:25:27 PM PDT 24 |
Peak memory | 204592 kb |
Host | smart-976787bf-9b01-4f04-b0d3-e9e4ad203c84 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185435664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1 185435664 |
Directory | /workspace/1.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1360904173 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 123893558 ps |
CPU time | 2.17 seconds |
Started | Jul 15 07:24:56 PM PDT 24 |
Finished | Jul 15 07:25:36 PM PDT 24 |
Peak memory | 215616 kb |
Host | smart-6b0c4e97-e20b-484d-a72e-40cacf53a4a3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360904173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi _device_mem_partial_access.1360904173 |
Directory | /workspace/1.spi_device_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1062301967 |
Short name | T1055 |
Test name | |
Test status | |
Simulation time | 10556933 ps |
CPU time | 0.66 seconds |
Started | Jul 15 07:24:53 PM PDT 24 |
Finished | Jul 15 07:25:32 PM PDT 24 |
Peak memory | 204084 kb |
Host | smart-9056e46f-5295-4e76-80d8-2e54f0d91efa |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062301967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me m_walk.1062301967 |
Directory | /workspace/1.spi_device_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1906262335 |
Short name | T1118 |
Test name | |
Test status | |
Simulation time | 454321544 ps |
CPU time | 2.82 seconds |
Started | Jul 15 07:24:48 PM PDT 24 |
Finished | Jul 15 07:25:29 PM PDT 24 |
Peak memory | 215784 kb |
Host | smart-e990f899-85fb-4e70-a928-44069c0e06c8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906262335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s pi_device_same_csr_outstanding.1906262335 |
Directory | /workspace/1.spi_device_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1065710163 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 617289934 ps |
CPU time | 3.26 seconds |
Started | Jul 15 07:24:49 PM PDT 24 |
Finished | Jul 15 07:25:29 PM PDT 24 |
Peak memory | 215980 kb |
Host | smart-3e1399e8-0f72-4d90-895a-14d9c6c820ce |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065710163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1 065710163 |
Directory | /workspace/1.spi_device_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3708767721 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 60892803 ps |
CPU time | 1.83 seconds |
Started | Jul 15 07:25:03 PM PDT 24 |
Finished | Jul 15 07:25:43 PM PDT 24 |
Peak memory | 215912 kb |
Host | smart-83a3c048-e337-4c54-a91a-60ab5e9990e2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708767721 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3708767721 |
Directory | /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3468746619 |
Short name | T1085 |
Test name | |
Test status | |
Simulation time | 66208245 ps |
CPU time | 2.26 seconds |
Started | Jul 15 07:24:58 PM PDT 24 |
Finished | Jul 15 07:25:39 PM PDT 24 |
Peak memory | 215708 kb |
Host | smart-1a5d263e-78d6-48a2-a15c-b408e69c451c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468746619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw. 3468746619 |
Directory | /workspace/10.spi_device_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.spi_device_intr_test.424807875 |
Short name | T1093 |
Test name | |
Test status | |
Simulation time | 37168517 ps |
CPU time | 0.71 seconds |
Started | Jul 15 07:24:59 PM PDT 24 |
Finished | Jul 15 07:25:38 PM PDT 24 |
Peak memory | 203884 kb |
Host | smart-a0ac1a0d-755d-4c1d-a9af-6e476996eddd |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424807875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.424807875 |
Directory | /workspace/10.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4230540295 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 723453224 ps |
CPU time | 4.01 seconds |
Started | Jul 15 07:24:59 PM PDT 24 |
Finished | Jul 15 07:25:41 PM PDT 24 |
Peak memory | 215792 kb |
Host | smart-f78801fd-fce0-42dc-9adf-70cd4ec51456 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230540295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10. spi_device_same_csr_outstanding.4230540295 |
Directory | /workspace/10.spi_device_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1545434698 |
Short name | T1091 |
Test name | |
Test status | |
Simulation time | 46873569 ps |
CPU time | 2.88 seconds |
Started | Jul 15 07:25:06 PM PDT 24 |
Finished | Jul 15 07:25:48 PM PDT 24 |
Peak memory | 217264 kb |
Host | smart-948c0595-8f72-4ce8-8ef3-b507d23e69c4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545434698 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1545434698 |
Directory | /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.387893829 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 48105787 ps |
CPU time | 1.53 seconds |
Started | Jul 15 07:25:05 PM PDT 24 |
Finished | Jul 15 07:25:46 PM PDT 24 |
Peak memory | 207544 kb |
Host | smart-de9ef07d-2829-4b68-8216-5a68c30746f2 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387893829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.387893829 |
Directory | /workspace/11.spi_device_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1688635463 |
Short name | T1088 |
Test name | |
Test status | |
Simulation time | 49225247 ps |
CPU time | 0.74 seconds |
Started | Jul 15 07:25:06 PM PDT 24 |
Finished | Jul 15 07:25:46 PM PDT 24 |
Peak memory | 204276 kb |
Host | smart-51e225a0-0e0b-462d-bc96-3725391bc29f |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688635463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test. 1688635463 |
Directory | /workspace/11.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1062901742 |
Short name | T1121 |
Test name | |
Test status | |
Simulation time | 168735773 ps |
CPU time | 2.76 seconds |
Started | Jul 15 07:25:12 PM PDT 24 |
Finished | Jul 15 07:25:55 PM PDT 24 |
Peak memory | 215768 kb |
Host | smart-3e93a0da-b428-4047-8ee4-336e094c0ea5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062901742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11. spi_device_same_csr_outstanding.1062901742 |
Directory | /workspace/11.spi_device_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.865624388 |
Short name | T1065 |
Test name | |
Test status | |
Simulation time | 163544339 ps |
CPU time | 2.5 seconds |
Started | Jul 15 07:25:09 PM PDT 24 |
Finished | Jul 15 07:25:51 PM PDT 24 |
Peak memory | 215956 kb |
Host | smart-7358faa5-3778-41e1-b248-71560e1b5e31 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865624388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.865624388 |
Directory | /workspace/11.spi_device_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1606801593 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 824381219 ps |
CPU time | 21.2 seconds |
Started | Jul 15 07:25:07 PM PDT 24 |
Finished | Jul 15 07:26:09 PM PDT 24 |
Peak memory | 215868 kb |
Host | smart-b17f1b94-b765-4e08-a43c-172d7fe8a166 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606801593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic e_tl_intg_err.1606801593 |
Directory | /workspace/11.spi_device_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2419273778 |
Short name | T1089 |
Test name | |
Test status | |
Simulation time | 205892295 ps |
CPU time | 1.72 seconds |
Started | Jul 15 07:25:05 PM PDT 24 |
Finished | Jul 15 07:25:46 PM PDT 24 |
Peak memory | 215856 kb |
Host | smart-4e260721-2682-40cf-b96c-5602112ba27c |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419273778 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2419273778 |
Directory | /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2456900596 |
Short name | T1131 |
Test name | |
Test status | |
Simulation time | 110291267 ps |
CPU time | 1.83 seconds |
Started | Jul 15 07:25:15 PM PDT 24 |
Finished | Jul 15 07:25:58 PM PDT 24 |
Peak memory | 207500 kb |
Host | smart-4756abdc-cf99-4b5b-a17c-f65a726f7c2a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456900596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw. 2456900596 |
Directory | /workspace/12.spi_device_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1225201466 |
Short name | T1114 |
Test name | |
Test status | |
Simulation time | 57872904 ps |
CPU time | 0.78 seconds |
Started | Jul 15 07:25:06 PM PDT 24 |
Finished | Jul 15 07:25:46 PM PDT 24 |
Peak memory | 204184 kb |
Host | smart-36006a25-d67d-4c02-9c2f-e41909792c16 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225201466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test. 1225201466 |
Directory | /workspace/12.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.613556232 |
Short name | T1111 |
Test name | |
Test status | |
Simulation time | 419782697 ps |
CPU time | 3.99 seconds |
Started | Jul 15 07:25:03 PM PDT 24 |
Finished | Jul 15 07:25:45 PM PDT 24 |
Peak memory | 215804 kb |
Host | smart-c6fd94a2-ada5-4d2d-9990-fe8bbf06cf58 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613556232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s pi_device_same_csr_outstanding.613556232 |
Directory | /workspace/12.spi_device_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.777475139 |
Short name | T1127 |
Test name | |
Test status | |
Simulation time | 138463280 ps |
CPU time | 1.73 seconds |
Started | Jul 15 07:25:07 PM PDT 24 |
Finished | Jul 15 07:25:49 PM PDT 24 |
Peak memory | 215912 kb |
Host | smart-0224629f-b751-4a63-87ca-8e7552de11f3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777475139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.777475139 |
Directory | /workspace/12.spi_device_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3645575802 |
Short name | T1110 |
Test name | |
Test status | |
Simulation time | 340401791 ps |
CPU time | 7.84 seconds |
Started | Jul 15 07:25:03 PM PDT 24 |
Finished | Jul 15 07:25:49 PM PDT 24 |
Peak memory | 215880 kb |
Host | smart-69717592-523b-4fcd-9cd8-d22a02681819 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645575802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic e_tl_intg_err.3645575802 |
Directory | /workspace/12.spi_device_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.658022260 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 491892902 ps |
CPU time | 3.62 seconds |
Started | Jul 15 07:25:10 PM PDT 24 |
Finished | Jul 15 07:25:55 PM PDT 24 |
Peak memory | 218568 kb |
Host | smart-b71e9227-06c7-4c63-ab6a-d4153be9fe88 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658022260 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.658022260 |
Directory | /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2403971095 |
Short name | T1094 |
Test name | |
Test status | |
Simulation time | 215787085 ps |
CPU time | 1.94 seconds |
Started | Jul 15 07:25:05 PM PDT 24 |
Finished | Jul 15 07:25:47 PM PDT 24 |
Peak memory | 220096 kb |
Host | smart-6f0c34d8-ff14-425e-a422-8db2acbd34db |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403971095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw. 2403971095 |
Directory | /workspace/13.spi_device_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.spi_device_intr_test.716356053 |
Short name | T1018 |
Test name | |
Test status | |
Simulation time | 15582884 ps |
CPU time | 0.81 seconds |
Started | Jul 15 07:25:04 PM PDT 24 |
Finished | Jul 15 07:25:45 PM PDT 24 |
Peak memory | 204284 kb |
Host | smart-2d665852-aded-42e7-bb7c-f056c981e349 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716356053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.716356053 |
Directory | /workspace/13.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1653471871 |
Short name | T1040 |
Test name | |
Test status | |
Simulation time | 115115769 ps |
CPU time | 3.46 seconds |
Started | Jul 15 07:25:08 PM PDT 24 |
Finished | Jul 15 07:25:52 PM PDT 24 |
Peak memory | 215748 kb |
Host | smart-529f1e14-04da-469a-9108-9e5aa1da8c42 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653471871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13. spi_device_same_csr_outstanding.1653471871 |
Directory | /workspace/13.spi_device_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3989535567 |
Short name | T1047 |
Test name | |
Test status | |
Simulation time | 533602233 ps |
CPU time | 3.27 seconds |
Started | Jul 15 07:25:03 PM PDT 24 |
Finished | Jul 15 07:25:44 PM PDT 24 |
Peak memory | 215968 kb |
Host | smart-0be01f4f-7529-4d62-8cba-659158360117 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989535567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors. 3989535567 |
Directory | /workspace/13.spi_device_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3407796036 |
Short name | T1034 |
Test name | |
Test status | |
Simulation time | 1101039008 ps |
CPU time | 7.92 seconds |
Started | Jul 15 07:25:06 PM PDT 24 |
Finished | Jul 15 07:25:53 PM PDT 24 |
Peak memory | 215912 kb |
Host | smart-ae5fed09-8353-431d-9f36-fa0871012d28 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407796036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic e_tl_intg_err.3407796036 |
Directory | /workspace/13.spi_device_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2761391670 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 88926894 ps |
CPU time | 2.56 seconds |
Started | Jul 15 07:25:06 PM PDT 24 |
Finished | Jul 15 07:25:48 PM PDT 24 |
Peak memory | 217120 kb |
Host | smart-ebf10bf3-af50-46d6-b977-f5ddadd087d5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761391670 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2761391670 |
Directory | /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3940728384 |
Short name | T1050 |
Test name | |
Test status | |
Simulation time | 1052632478 ps |
CPU time | 2.02 seconds |
Started | Jul 15 07:25:05 PM PDT 24 |
Finished | Jul 15 07:25:47 PM PDT 24 |
Peak memory | 215704 kb |
Host | smart-b28adc38-91eb-4eec-82f8-a3a927f9858a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940728384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw. 3940728384 |
Directory | /workspace/14.spi_device_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.spi_device_intr_test.4210146310 |
Short name | T1060 |
Test name | |
Test status | |
Simulation time | 27493342 ps |
CPU time | 0.74 seconds |
Started | Jul 15 07:25:07 PM PDT 24 |
Finished | Jul 15 07:25:46 PM PDT 24 |
Peak memory | 204600 kb |
Host | smart-fff7f9bb-7268-40d9-aaff-b06f5ed9cb79 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210146310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test. 4210146310 |
Directory | /workspace/14.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3466519972 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 72651808 ps |
CPU time | 2.7 seconds |
Started | Jul 15 07:25:06 PM PDT 24 |
Finished | Jul 15 07:25:48 PM PDT 24 |
Peak memory | 215780 kb |
Host | smart-41bf7a60-3a53-4d5c-a5e8-a9c66743772c |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466519972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14. spi_device_same_csr_outstanding.3466519972 |
Directory | /workspace/14.spi_device_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.415101391 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 346357587 ps |
CPU time | 4.69 seconds |
Started | Jul 15 07:25:04 PM PDT 24 |
Finished | Jul 15 07:25:49 PM PDT 24 |
Peak memory | 215984 kb |
Host | smart-d0506618-8b6c-44e6-b609-c71a5f661d7c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415101391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.415101391 |
Directory | /workspace/14.spi_device_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.4114799747 |
Short name | T1071 |
Test name | |
Test status | |
Simulation time | 1181155608 ps |
CPU time | 8.08 seconds |
Started | Jul 15 07:25:09 PM PDT 24 |
Finished | Jul 15 07:25:57 PM PDT 24 |
Peak memory | 215792 kb |
Host | smart-bf07dcdc-873a-4859-a770-646668e7c2c0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114799747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic e_tl_intg_err.4114799747 |
Directory | /workspace/14.spi_device_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1472685395 |
Short name | T1092 |
Test name | |
Test status | |
Simulation time | 58333849 ps |
CPU time | 3.84 seconds |
Started | Jul 15 07:25:05 PM PDT 24 |
Finished | Jul 15 07:25:49 PM PDT 24 |
Peak memory | 218804 kb |
Host | smart-33f6db1d-23d3-4c3c-9e26-164e0791cf13 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472685395 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1472685395 |
Directory | /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3334782326 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 85070598 ps |
CPU time | 2.13 seconds |
Started | Jul 15 07:25:06 PM PDT 24 |
Finished | Jul 15 07:25:48 PM PDT 24 |
Peak memory | 207504 kb |
Host | smart-edf45989-149a-454a-8a37-37d37a1fd417 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334782326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw. 3334782326 |
Directory | /workspace/15.spi_device_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2254537639 |
Short name | T1031 |
Test name | |
Test status | |
Simulation time | 20682401 ps |
CPU time | 0.7 seconds |
Started | Jul 15 07:25:10 PM PDT 24 |
Finished | Jul 15 07:25:52 PM PDT 24 |
Peak memory | 204548 kb |
Host | smart-72e1b20a-1d47-42f0-9497-2e3ecc441c65 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254537639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test. 2254537639 |
Directory | /workspace/15.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2215612090 |
Short name | T1097 |
Test name | |
Test status | |
Simulation time | 1077961557 ps |
CPU time | 2.94 seconds |
Started | Jul 15 07:25:08 PM PDT 24 |
Finished | Jul 15 07:25:51 PM PDT 24 |
Peak memory | 215816 kb |
Host | smart-9a914e85-031d-40b3-97f5-40b898f42248 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215612090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15. spi_device_same_csr_outstanding.2215612090 |
Directory | /workspace/15.spi_device_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3549189493 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 104242472 ps |
CPU time | 1.83 seconds |
Started | Jul 15 07:25:06 PM PDT 24 |
Finished | Jul 15 07:25:47 PM PDT 24 |
Peak memory | 215960 kb |
Host | smart-24b1f1bd-ae42-4273-8361-c7c2b88678de |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549189493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors. 3549189493 |
Directory | /workspace/15.spi_device_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.37887402 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 2286797422 ps |
CPU time | 14.32 seconds |
Started | Jul 15 07:25:04 PM PDT 24 |
Finished | Jul 15 07:25:58 PM PDT 24 |
Peak memory | 218456 kb |
Host | smart-4d497c1d-b616-465d-9976-9ffe3b9b6e21 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37887402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_ tl_intg_err.37887402 |
Directory | /workspace/15.spi_device_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3443094992 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 713808700 ps |
CPU time | 2.59 seconds |
Started | Jul 15 07:25:07 PM PDT 24 |
Finished | Jul 15 07:25:48 PM PDT 24 |
Peak memory | 218284 kb |
Host | smart-8a913746-b635-4647-b17d-8a5929b3489a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443094992 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3443094992 |
Directory | /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3720008772 |
Short name | T1100 |
Test name | |
Test status | |
Simulation time | 42324063 ps |
CPU time | 1.25 seconds |
Started | Jul 15 07:25:04 PM PDT 24 |
Finished | Jul 15 07:25:45 PM PDT 24 |
Peak memory | 207492 kb |
Host | smart-de3140f3-d29f-4548-960f-6e75f529f5d8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720008772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw. 3720008772 |
Directory | /workspace/16.spi_device_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3537748410 |
Short name | T1076 |
Test name | |
Test status | |
Simulation time | 14885068 ps |
CPU time | 0.74 seconds |
Started | Jul 15 07:25:06 PM PDT 24 |
Finished | Jul 15 07:25:46 PM PDT 24 |
Peak memory | 204240 kb |
Host | smart-521fa871-0fb5-49c4-9c7b-46c1b8f2ebe9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537748410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test. 3537748410 |
Directory | /workspace/16.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1062187576 |
Short name | T1073 |
Test name | |
Test status | |
Simulation time | 125519407 ps |
CPU time | 3.9 seconds |
Started | Jul 15 07:25:10 PM PDT 24 |
Finished | Jul 15 07:25:55 PM PDT 24 |
Peak memory | 215672 kb |
Host | smart-43cc461f-a912-42d6-9e93-cb53dd055b54 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062187576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16. spi_device_same_csr_outstanding.1062187576 |
Directory | /workspace/16.spi_device_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3078028299 |
Short name | T1113 |
Test name | |
Test status | |
Simulation time | 70001045 ps |
CPU time | 1.98 seconds |
Started | Jul 15 07:25:04 PM PDT 24 |
Finished | Jul 15 07:25:43 PM PDT 24 |
Peak memory | 216148 kb |
Host | smart-8bc6fb64-bd7c-4276-bb4f-e28c89cbf14d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078028299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors. 3078028299 |
Directory | /workspace/16.spi_device_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2243101362 |
Short name | T1077 |
Test name | |
Test status | |
Simulation time | 836188784 ps |
CPU time | 21.24 seconds |
Started | Jul 15 07:25:07 PM PDT 24 |
Finished | Jul 15 07:26:07 PM PDT 24 |
Peak memory | 215792 kb |
Host | smart-861ffac9-4dea-4973-b55b-3e40d7de506c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243101362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic e_tl_intg_err.2243101362 |
Directory | /workspace/16.spi_device_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2049925213 |
Short name | T1053 |
Test name | |
Test status | |
Simulation time | 668172178 ps |
CPU time | 2.74 seconds |
Started | Jul 15 07:25:05 PM PDT 24 |
Finished | Jul 15 07:25:48 PM PDT 24 |
Peak memory | 217016 kb |
Host | smart-d8a18038-650c-4793-8b93-4bcac88dde2b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049925213 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2049925213 |
Directory | /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.844253590 |
Short name | T1054 |
Test name | |
Test status | |
Simulation time | 73979275 ps |
CPU time | 1.23 seconds |
Started | Jul 15 07:25:07 PM PDT 24 |
Finished | Jul 15 07:25:48 PM PDT 24 |
Peak memory | 207604 kb |
Host | smart-8dfce2c5-56f0-4b5b-af23-1f7df17fe324 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844253590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.844253590 |
Directory | /workspace/17.spi_device_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2761244733 |
Short name | T1017 |
Test name | |
Test status | |
Simulation time | 13996805 ps |
CPU time | 0.75 seconds |
Started | Jul 15 07:25:03 PM PDT 24 |
Finished | Jul 15 07:25:42 PM PDT 24 |
Peak memory | 204276 kb |
Host | smart-2f3daf01-7a1d-40fd-8736-c1d6134ecf8b |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761244733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test. 2761244733 |
Directory | /workspace/17.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.4222477798 |
Short name | T1083 |
Test name | |
Test status | |
Simulation time | 57230378 ps |
CPU time | 1.63 seconds |
Started | Jul 15 07:25:03 PM PDT 24 |
Finished | Jul 15 07:25:42 PM PDT 24 |
Peak memory | 215704 kb |
Host | smart-909097ba-0f9c-44bc-8571-cb3b41e1a55a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222477798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17. spi_device_same_csr_outstanding.4222477798 |
Directory | /workspace/17.spi_device_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.716233955 |
Short name | T1106 |
Test name | |
Test status | |
Simulation time | 264776881 ps |
CPU time | 3.89 seconds |
Started | Jul 15 07:25:04 PM PDT 24 |
Finished | Jul 15 07:25:48 PM PDT 24 |
Peak memory | 216012 kb |
Host | smart-356b413c-5151-4e03-9b3d-8ed86ff72710 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716233955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.716233955 |
Directory | /workspace/17.spi_device_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.403757094 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 583166944 ps |
CPU time | 14.07 seconds |
Started | Jul 15 07:25:06 PM PDT 24 |
Finished | Jul 15 07:26:00 PM PDT 24 |
Peak memory | 215896 kb |
Host | smart-06ab5327-8cf7-4ee9-a1a2-5bf70f372523 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403757094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device _tl_intg_err.403757094 |
Directory | /workspace/17.spi_device_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3738977648 |
Short name | T1080 |
Test name | |
Test status | |
Simulation time | 170141779 ps |
CPU time | 2.6 seconds |
Started | Jul 15 07:25:07 PM PDT 24 |
Finished | Jul 15 07:25:50 PM PDT 24 |
Peak memory | 217648 kb |
Host | smart-50f6af14-8022-4486-bf4f-43e19060bb0c |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738977648 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3738977648 |
Directory | /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1561988910 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 45730691 ps |
CPU time | 1.42 seconds |
Started | Jul 15 07:25:07 PM PDT 24 |
Finished | Jul 15 07:25:49 PM PDT 24 |
Peak memory | 215732 kb |
Host | smart-936122da-bebb-42b4-8b77-594d22bdbdb1 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561988910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw. 1561988910 |
Directory | /workspace/18.spi_device_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1582599598 |
Short name | T1045 |
Test name | |
Test status | |
Simulation time | 17493528 ps |
CPU time | 0.75 seconds |
Started | Jul 15 07:25:04 PM PDT 24 |
Finished | Jul 15 07:25:45 PM PDT 24 |
Peak memory | 204248 kb |
Host | smart-31e926b3-b359-4561-9ba9-efd0c8241c4e |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582599598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test. 1582599598 |
Directory | /workspace/18.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1376678117 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 59673846 ps |
CPU time | 1.67 seconds |
Started | Jul 15 07:25:04 PM PDT 24 |
Finished | Jul 15 07:25:46 PM PDT 24 |
Peak memory | 215680 kb |
Host | smart-847de7a3-4b59-4b59-a95d-0c437533b9d0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376678117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18. spi_device_same_csr_outstanding.1376678117 |
Directory | /workspace/18.spi_device_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3635790446 |
Short name | T1123 |
Test name | |
Test status | |
Simulation time | 536786462 ps |
CPU time | 1.8 seconds |
Started | Jul 15 07:25:08 PM PDT 24 |
Finished | Jul 15 07:25:50 PM PDT 24 |
Peak memory | 216008 kb |
Host | smart-436883d4-b85e-4829-81e0-fa5e52f75bf5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635790446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors. 3635790446 |
Directory | /workspace/18.spi_device_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1963980710 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 400035576 ps |
CPU time | 12.7 seconds |
Started | Jul 15 07:25:06 PM PDT 24 |
Finished | Jul 15 07:25:58 PM PDT 24 |
Peak memory | 216312 kb |
Host | smart-abd1e8b8-214d-4611-872e-363a5870c705 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963980710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic e_tl_intg_err.1963980710 |
Directory | /workspace/18.spi_device_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2319871909 |
Short name | T1116 |
Test name | |
Test status | |
Simulation time | 275105528 ps |
CPU time | 2.74 seconds |
Started | Jul 15 07:25:16 PM PDT 24 |
Finished | Jul 15 07:26:00 PM PDT 24 |
Peak memory | 217744 kb |
Host | smart-95003af1-3c30-4bf4-bc59-83099a003522 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319871909 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2319871909 |
Directory | /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1224789083 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 47481925 ps |
CPU time | 1.74 seconds |
Started | Jul 15 07:25:07 PM PDT 24 |
Finished | Jul 15 07:25:47 PM PDT 24 |
Peak memory | 215692 kb |
Host | smart-da78e4da-c2f1-465e-b056-4322b32bf943 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224789083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw. 1224789083 |
Directory | /workspace/19.spi_device_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3571720156 |
Short name | T1042 |
Test name | |
Test status | |
Simulation time | 12328135 ps |
CPU time | 0.71 seconds |
Started | Jul 15 07:25:06 PM PDT 24 |
Finished | Jul 15 07:25:46 PM PDT 24 |
Peak memory | 204560 kb |
Host | smart-ae48a1b6-77ec-4374-b249-b7f9b0380928 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571720156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test. 3571720156 |
Directory | /workspace/19.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3638570782 |
Short name | T1029 |
Test name | |
Test status | |
Simulation time | 61243471 ps |
CPU time | 3.88 seconds |
Started | Jul 15 07:25:15 PM PDT 24 |
Finished | Jul 15 07:26:00 PM PDT 24 |
Peak memory | 215848 kb |
Host | smart-c582b51d-8202-4bab-8a55-658d02d656ad |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638570782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19. spi_device_same_csr_outstanding.3638570782 |
Directory | /workspace/19.spi_device_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.859869269 |
Short name | T1102 |
Test name | |
Test status | |
Simulation time | 124527058 ps |
CPU time | 3.41 seconds |
Started | Jul 15 07:25:05 PM PDT 24 |
Finished | Jul 15 07:25:48 PM PDT 24 |
Peak memory | 219748 kb |
Host | smart-a1473e82-d179-4618-bc0f-8a5a6a80ffd9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859869269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.859869269 |
Directory | /workspace/19.spi_device_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1953282108 |
Short name | T1084 |
Test name | |
Test status | |
Simulation time | 817160663 ps |
CPU time | 13.21 seconds |
Started | Jul 15 07:25:04 PM PDT 24 |
Finished | Jul 15 07:25:54 PM PDT 24 |
Peak memory | 215792 kb |
Host | smart-9d90c2f9-da6d-4496-9de1-db66f1449cfa |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953282108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic e_tl_intg_err.1953282108 |
Directory | /workspace/19.spi_device_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2524627980 |
Short name | T1109 |
Test name | |
Test status | |
Simulation time | 1229638511 ps |
CPU time | 16.74 seconds |
Started | Jul 15 07:24:51 PM PDT 24 |
Finished | Jul 15 07:25:44 PM PDT 24 |
Peak memory | 207512 kb |
Host | smart-6fad1643-a296-4393-8ebd-b23195315b2f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524627980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs r_aliasing.2524627980 |
Directory | /workspace/2.spi_device_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.187901939 |
Short name | T1086 |
Test name | |
Test status | |
Simulation time | 1812587479 ps |
CPU time | 34.84 seconds |
Started | Jul 15 07:24:50 PM PDT 24 |
Finished | Jul 15 07:26:02 PM PDT 24 |
Peak memory | 207496 kb |
Host | smart-1b70f5b1-9993-427b-9058-2510ecee7e68 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187901939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr _bit_bash.187901939 |
Directory | /workspace/2.spi_device_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3083090050 |
Short name | T1069 |
Test name | |
Test status | |
Simulation time | 98574520 ps |
CPU time | 2.54 seconds |
Started | Jul 15 07:25:03 PM PDT 24 |
Finished | Jul 15 07:25:43 PM PDT 24 |
Peak memory | 217744 kb |
Host | smart-a5c0fc3e-8eef-46e4-93d6-419807374c55 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083090050 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3083090050 |
Directory | /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3279089096 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 41750601 ps |
CPU time | 1.34 seconds |
Started | Jul 15 07:24:49 PM PDT 24 |
Finished | Jul 15 07:25:27 PM PDT 24 |
Peak memory | 207456 kb |
Host | smart-bf0ac2db-482e-4e2b-a641-8d52519cfe58 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279089096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3 279089096 |
Directory | /workspace/2.spi_device_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3610226687 |
Short name | T1056 |
Test name | |
Test status | |
Simulation time | 11536501 ps |
CPU time | 0.73 seconds |
Started | Jul 15 07:24:48 PM PDT 24 |
Finished | Jul 15 07:25:27 PM PDT 24 |
Peak memory | 204252 kb |
Host | smart-bd5902e9-4a88-4dd1-aa9e-0b5629f485d9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610226687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3 610226687 |
Directory | /workspace/2.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1611375578 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 487407203 ps |
CPU time | 2.11 seconds |
Started | Jul 15 07:24:51 PM PDT 24 |
Finished | Jul 15 07:25:30 PM PDT 24 |
Peak memory | 215792 kb |
Host | smart-10adfb7d-8422-4ce4-a106-d5453640ebfa |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611375578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi _device_mem_partial_access.1611375578 |
Directory | /workspace/2.spi_device_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2043374229 |
Short name | T1103 |
Test name | |
Test status | |
Simulation time | 36360478 ps |
CPU time | 0.72 seconds |
Started | Jul 15 07:24:51 PM PDT 24 |
Finished | Jul 15 07:25:28 PM PDT 24 |
Peak memory | 204408 kb |
Host | smart-2a984ab6-f90f-4cb6-ab7b-3a7a35821a22 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043374229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me m_walk.2043374229 |
Directory | /workspace/2.spi_device_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3313908352 |
Short name | T1087 |
Test name | |
Test status | |
Simulation time | 117548222 ps |
CPU time | 1.84 seconds |
Started | Jul 15 07:25:00 PM PDT 24 |
Finished | Jul 15 07:25:40 PM PDT 24 |
Peak memory | 215756 kb |
Host | smart-1cb71e67-afe9-47ba-9d98-5af206729293 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313908352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s pi_device_same_csr_outstanding.3313908352 |
Directory | /workspace/2.spi_device_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1490641449 |
Short name | T1108 |
Test name | |
Test status | |
Simulation time | 97640385 ps |
CPU time | 2.48 seconds |
Started | Jul 15 07:24:55 PM PDT 24 |
Finished | Jul 15 07:25:34 PM PDT 24 |
Peak memory | 216012 kb |
Host | smart-a80f389a-24b3-4062-be4f-592e41f9b1ec |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490641449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1 490641449 |
Directory | /workspace/2.spi_device_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.547516950 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 286747054 ps |
CPU time | 7.1 seconds |
Started | Jul 15 07:24:55 PM PDT 24 |
Finished | Jul 15 07:25:39 PM PDT 24 |
Peak memory | 215928 kb |
Host | smart-cf433664-830a-4516-a106-4e6ff60d93be |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547516950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_ tl_intg_err.547516950 |
Directory | /workspace/2.spi_device_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1748939710 |
Short name | T1021 |
Test name | |
Test status | |
Simulation time | 77796587 ps |
CPU time | 0.75 seconds |
Started | Jul 15 07:25:12 PM PDT 24 |
Finished | Jul 15 07:25:53 PM PDT 24 |
Peak memory | 204440 kb |
Host | smart-27dd27ab-232c-48d9-95e6-7dafdd5d312e |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748939710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test. 1748939710 |
Directory | /workspace/20.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3707869703 |
Short name | T1032 |
Test name | |
Test status | |
Simulation time | 51762981 ps |
CPU time | 0.7 seconds |
Started | Jul 15 07:25:16 PM PDT 24 |
Finished | Jul 15 07:25:58 PM PDT 24 |
Peak memory | 204648 kb |
Host | smart-fd921022-b369-47d9-b41c-55839eaea511 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707869703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test. 3707869703 |
Directory | /workspace/21.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4293684943 |
Short name | T1099 |
Test name | |
Test status | |
Simulation time | 12755268 ps |
CPU time | 0.69 seconds |
Started | Jul 15 07:25:15 PM PDT 24 |
Finished | Jul 15 07:25:57 PM PDT 24 |
Peak memory | 204320 kb |
Host | smart-6ac65546-d085-42fb-b840-5ddae16d2a0d |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293684943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test. 4293684943 |
Directory | /workspace/22.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2255738366 |
Short name | T1096 |
Test name | |
Test status | |
Simulation time | 28663273 ps |
CPU time | 0.77 seconds |
Started | Jul 15 07:25:15 PM PDT 24 |
Finished | Jul 15 07:25:57 PM PDT 24 |
Peak memory | 204328 kb |
Host | smart-d422d361-dc91-4a86-b1a4-552249009629 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255738366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test. 2255738366 |
Directory | /workspace/23.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/24.spi_device_intr_test.32993029 |
Short name | T1052 |
Test name | |
Test status | |
Simulation time | 38011955 ps |
CPU time | 0.73 seconds |
Started | Jul 15 07:25:12 PM PDT 24 |
Finished | Jul 15 07:25:53 PM PDT 24 |
Peak memory | 204516 kb |
Host | smart-7e19fb59-165d-4a0f-a7a3-4fbbb7550569 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32993029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.32993029 |
Directory | /workspace/24.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/25.spi_device_intr_test.895495063 |
Short name | T1030 |
Test name | |
Test status | |
Simulation time | 48091464 ps |
CPU time | 0.68 seconds |
Started | Jul 15 07:25:15 PM PDT 24 |
Finished | Jul 15 07:25:57 PM PDT 24 |
Peak memory | 204324 kb |
Host | smart-16d48bf3-1ed1-4ee8-ba79-08e7a91c2a75 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895495063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.895495063 |
Directory | /workspace/25.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/26.spi_device_intr_test.4122032300 |
Short name | T1023 |
Test name | |
Test status | |
Simulation time | 22297455 ps |
CPU time | 0.71 seconds |
Started | Jul 15 07:25:15 PM PDT 24 |
Finished | Jul 15 07:25:57 PM PDT 24 |
Peak memory | 204328 kb |
Host | smart-13c79606-7968-4360-8108-6572d5abc246 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122032300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test. 4122032300 |
Directory | /workspace/26.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2384519705 |
Short name | T1120 |
Test name | |
Test status | |
Simulation time | 15987363 ps |
CPU time | 0.73 seconds |
Started | Jul 15 07:25:07 PM PDT 24 |
Finished | Jul 15 07:25:49 PM PDT 24 |
Peak memory | 204336 kb |
Host | smart-93e5ee32-7537-4fe7-9e62-c2fe7e344e48 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384519705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test. 2384519705 |
Directory | /workspace/27.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2975134943 |
Short name | T1038 |
Test name | |
Test status | |
Simulation time | 15216882 ps |
CPU time | 0.71 seconds |
Started | Jul 15 07:25:02 PM PDT 24 |
Finished | Jul 15 07:25:41 PM PDT 24 |
Peak memory | 204320 kb |
Host | smart-da5a6af8-5f3e-4081-921c-5bc9ad4c6e73 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975134943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test. 2975134943 |
Directory | /workspace/28.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1042481445 |
Short name | T1044 |
Test name | |
Test status | |
Simulation time | 12096851 ps |
CPU time | 0.69 seconds |
Started | Jul 15 07:25:05 PM PDT 24 |
Finished | Jul 15 07:25:46 PM PDT 24 |
Peak memory | 204292 kb |
Host | smart-ee8cedc3-9447-4033-aab5-573d50660a5d |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042481445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test. 1042481445 |
Directory | /workspace/29.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3188730223 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 326177813 ps |
CPU time | 8.51 seconds |
Started | Jul 15 07:24:58 PM PDT 24 |
Finished | Jul 15 07:25:46 PM PDT 24 |
Peak memory | 207508 kb |
Host | smart-603153a1-4583-457c-aaa8-e9302c51d352 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188730223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs r_aliasing.3188730223 |
Directory | /workspace/3.spi_device_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2309296365 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 10773469069 ps |
CPU time | 39.47 seconds |
Started | Jul 15 07:24:57 PM PDT 24 |
Finished | Jul 15 07:26:14 PM PDT 24 |
Peak memory | 215796 kb |
Host | smart-65a102c8-984f-4734-a810-1ca185e05af0 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309296365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs r_bit_bash.2309296365 |
Directory | /workspace/3.spi_device_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2538170710 |
Short name | T1130 |
Test name | |
Test status | |
Simulation time | 49222573 ps |
CPU time | 1.46 seconds |
Started | Jul 15 07:24:57 PM PDT 24 |
Finished | Jul 15 07:25:36 PM PDT 24 |
Peak memory | 207492 kb |
Host | smart-4a049965-e313-4396-90eb-28593b42af5c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538170710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs r_hw_reset.2538170710 |
Directory | /workspace/3.spi_device_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1708735046 |
Short name | T1105 |
Test name | |
Test status | |
Simulation time | 284303971 ps |
CPU time | 2.37 seconds |
Started | Jul 15 07:24:58 PM PDT 24 |
Finished | Jul 15 07:25:40 PM PDT 24 |
Peak memory | 217492 kb |
Host | smart-6698538e-4ef9-47a3-9df2-8a7db6bd81d7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708735046 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1708735046 |
Directory | /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.817916467 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 68880328 ps |
CPU time | 1.81 seconds |
Started | Jul 15 07:24:58 PM PDT 24 |
Finished | Jul 15 07:25:39 PM PDT 24 |
Peak memory | 207472 kb |
Host | smart-5593e1bb-fa2e-4d51-9d01-3bdf69ab04a8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817916467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.817916467 |
Directory | /workspace/3.spi_device_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.spi_device_intr_test.876386560 |
Short name | T1074 |
Test name | |
Test status | |
Simulation time | 45094180 ps |
CPU time | 0.72 seconds |
Started | Jul 15 07:24:58 PM PDT 24 |
Finished | Jul 15 07:25:38 PM PDT 24 |
Peak memory | 204252 kb |
Host | smart-11e2a8d2-f21c-4744-a0e1-36efdda86218 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876386560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.876386560 |
Directory | /workspace/3.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1059082357 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 252891707 ps |
CPU time | 2.18 seconds |
Started | Jul 15 07:24:59 PM PDT 24 |
Finished | Jul 15 07:25:40 PM PDT 24 |
Peak memory | 215812 kb |
Host | smart-cb8c4d0a-891f-48a2-88c8-bcd33a7f8d0c |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059082357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi _device_mem_partial_access.1059082357 |
Directory | /workspace/3.spi_device_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4032924923 |
Short name | T1019 |
Test name | |
Test status | |
Simulation time | 22302121 ps |
CPU time | 0.67 seconds |
Started | Jul 15 07:25:02 PM PDT 24 |
Finished | Jul 15 07:25:41 PM PDT 24 |
Peak memory | 204400 kb |
Host | smart-763840fe-2992-487e-8c89-fb62ecbc831c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032924923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me m_walk.4032924923 |
Directory | /workspace/3.spi_device_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3261823601 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 921105853 ps |
CPU time | 4.09 seconds |
Started | Jul 15 07:25:02 PM PDT 24 |
Finished | Jul 15 07:25:45 PM PDT 24 |
Peak memory | 215452 kb |
Host | smart-2930c34e-83d4-4aef-8431-56bf4663b0df |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261823601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s pi_device_same_csr_outstanding.3261823601 |
Directory | /workspace/3.spi_device_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.425627761 |
Short name | T1072 |
Test name | |
Test status | |
Simulation time | 69090174 ps |
CPU time | 1.86 seconds |
Started | Jul 15 07:24:59 PM PDT 24 |
Finished | Jul 15 07:25:40 PM PDT 24 |
Peak memory | 215472 kb |
Host | smart-51ece9f6-a5f4-4014-9d5b-cf2ecebf2d1f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425627761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.425627761 |
Directory | /workspace/3.spi_device_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1336395030 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 542150405 ps |
CPU time | 14.57 seconds |
Started | Jul 15 07:24:58 PM PDT 24 |
Finished | Jul 15 07:25:52 PM PDT 24 |
Peak memory | 223852 kb |
Host | smart-54046d7b-7ea8-4ba8-9cdd-bb318f4b3677 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336395030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device _tl_intg_err.1336395030 |
Directory | /workspace/3.spi_device_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/30.spi_device_intr_test.540855786 |
Short name | T1129 |
Test name | |
Test status | |
Simulation time | 15546315 ps |
CPU time | 0.72 seconds |
Started | Jul 15 07:25:12 PM PDT 24 |
Finished | Jul 15 07:25:53 PM PDT 24 |
Peak memory | 204444 kb |
Host | smart-b9123fd0-5bd3-41f3-b7ce-0d772ddd3499 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540855786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.540855786 |
Directory | /workspace/30.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3821816828 |
Short name | T1037 |
Test name | |
Test status | |
Simulation time | 54944975 ps |
CPU time | 0.7 seconds |
Started | Jul 15 07:25:07 PM PDT 24 |
Finished | Jul 15 07:25:48 PM PDT 24 |
Peak memory | 204284 kb |
Host | smart-7ba348ec-622b-44e1-9848-02d493ac56a1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821816828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test. 3821816828 |
Directory | /workspace/31.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/32.spi_device_intr_test.536549710 |
Short name | T1026 |
Test name | |
Test status | |
Simulation time | 16135714 ps |
CPU time | 0.69 seconds |
Started | Jul 15 07:25:12 PM PDT 24 |
Finished | Jul 15 07:25:55 PM PDT 24 |
Peak memory | 204296 kb |
Host | smart-afd170cb-f7ef-4af7-8bad-ffd714d89a35 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536549710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.536549710 |
Directory | /workspace/32.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/33.spi_device_intr_test.21636797 |
Short name | T1014 |
Test name | |
Test status | |
Simulation time | 13054697 ps |
CPU time | 0.7 seconds |
Started | Jul 15 07:25:11 PM PDT 24 |
Finished | Jul 15 07:25:52 PM PDT 24 |
Peak memory | 204576 kb |
Host | smart-79026900-692a-49ee-acf8-5bf036cb326b |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21636797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.21636797 |
Directory | /workspace/33.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1979118097 |
Short name | T1025 |
Test name | |
Test status | |
Simulation time | 11623141 ps |
CPU time | 0.71 seconds |
Started | Jul 15 07:25:10 PM PDT 24 |
Finished | Jul 15 07:25:52 PM PDT 24 |
Peak memory | 204288 kb |
Host | smart-ea5c0988-15f4-4eca-9fb6-f02e63d08252 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979118097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test. 1979118097 |
Directory | /workspace/34.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2874301127 |
Short name | T1126 |
Test name | |
Test status | |
Simulation time | 32746344 ps |
CPU time | 0.77 seconds |
Started | Jul 15 07:25:12 PM PDT 24 |
Finished | Jul 15 07:25:53 PM PDT 24 |
Peak memory | 204356 kb |
Host | smart-3811d311-6e4b-4dd7-a876-cd165173d26d |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874301127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test. 2874301127 |
Directory | /workspace/35.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3646821788 |
Short name | T1101 |
Test name | |
Test status | |
Simulation time | 16476948 ps |
CPU time | 0.79 seconds |
Started | Jul 15 07:25:10 PM PDT 24 |
Finished | Jul 15 07:25:52 PM PDT 24 |
Peak memory | 204244 kb |
Host | smart-3285a31b-6819-4643-9363-823d4439d8bf |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646821788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test. 3646821788 |
Directory | /workspace/36.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1967692908 |
Short name | T1104 |
Test name | |
Test status | |
Simulation time | 14334151 ps |
CPU time | 0.76 seconds |
Started | Jul 15 07:25:16 PM PDT 24 |
Finished | Jul 15 07:25:58 PM PDT 24 |
Peak memory | 204244 kb |
Host | smart-f40e5c1e-8132-4847-a3ad-2b079ead0cf7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967692908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test. 1967692908 |
Directory | /workspace/37.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/38.spi_device_intr_test.4294621120 |
Short name | T1016 |
Test name | |
Test status | |
Simulation time | 15194826 ps |
CPU time | 0.75 seconds |
Started | Jul 15 07:25:12 PM PDT 24 |
Finished | Jul 15 07:25:53 PM PDT 24 |
Peak memory | 204612 kb |
Host | smart-a006c007-16b9-457b-8993-855fe7ae7727 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294621120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test. 4294621120 |
Directory | /workspace/38.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3759168671 |
Short name | T1015 |
Test name | |
Test status | |
Simulation time | 20486907 ps |
CPU time | 0.74 seconds |
Started | Jul 15 07:25:11 PM PDT 24 |
Finished | Jul 15 07:25:52 PM PDT 24 |
Peak memory | 204272 kb |
Host | smart-8dc388d2-00a8-40a1-bf70-a2f5d6e44fa0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759168671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test. 3759168671 |
Directory | /workspace/39.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1626824682 |
Short name | T1119 |
Test name | |
Test status | |
Simulation time | 561820043 ps |
CPU time | 8.08 seconds |
Started | Jul 15 07:25:00 PM PDT 24 |
Finished | Jul 15 07:25:46 PM PDT 24 |
Peak memory | 207424 kb |
Host | smart-279aa0b5-b46a-4124-ab59-1e7e0a812c67 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626824682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs r_aliasing.1626824682 |
Directory | /workspace/4.spi_device_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.717944510 |
Short name | T1061 |
Test name | |
Test status | |
Simulation time | 2167880942 ps |
CPU time | 33.37 seconds |
Started | Jul 15 07:24:57 PM PDT 24 |
Finished | Jul 15 07:26:08 PM PDT 24 |
Peak memory | 207568 kb |
Host | smart-56349e09-f93b-4c77-82ec-63c4c4169fe2 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717944510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr _bit_bash.717944510 |
Directory | /workspace/4.spi_device_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3332428616 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 66607294 ps |
CPU time | 1.12 seconds |
Started | Jul 15 07:24:58 PM PDT 24 |
Finished | Jul 15 07:25:38 PM PDT 24 |
Peak memory | 207464 kb |
Host | smart-ac27f1e5-0ec5-40d6-9850-936d0a850b62 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332428616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs r_hw_reset.3332428616 |
Directory | /workspace/4.spi_device_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3175698357 |
Short name | T1027 |
Test name | |
Test status | |
Simulation time | 175926646 ps |
CPU time | 2.81 seconds |
Started | Jul 15 07:24:55 PM PDT 24 |
Finished | Jul 15 07:25:37 PM PDT 24 |
Peak memory | 218416 kb |
Host | smart-dfaae9c0-c261-44bc-9848-a459d3565760 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175698357 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3175698357 |
Directory | /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.370964837 |
Short name | T1117 |
Test name | |
Test status | |
Simulation time | 24417913 ps |
CPU time | 1.36 seconds |
Started | Jul 15 07:24:55 PM PDT 24 |
Finished | Jul 15 07:25:35 PM PDT 24 |
Peak memory | 207512 kb |
Host | smart-e904a469-a1fd-4ded-9cec-886e302f71f8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370964837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.370964837 |
Directory | /workspace/4.spi_device_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1697482059 |
Short name | T1124 |
Test name | |
Test status | |
Simulation time | 61885051 ps |
CPU time | 0.74 seconds |
Started | Jul 15 07:24:58 PM PDT 24 |
Finished | Jul 15 07:25:38 PM PDT 24 |
Peak memory | 204236 kb |
Host | smart-a427cb83-2858-4e48-83bb-bb59f5082990 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697482059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1 697482059 |
Directory | /workspace/4.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1815211268 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 71509366 ps |
CPU time | 1.33 seconds |
Started | Jul 15 07:24:57 PM PDT 24 |
Finished | Jul 15 07:25:36 PM PDT 24 |
Peak memory | 215720 kb |
Host | smart-bb5b5569-3bab-4d74-9ee3-334e9212efaa |
User | root |
Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815211268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi _device_mem_partial_access.1815211268 |
Directory | /workspace/4.spi_device_mem_partial_access/latest |
Test location | /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1940352412 |
Short name | T1064 |
Test name | |
Test status | |
Simulation time | 11957917 ps |
CPU time | 0.68 seconds |
Started | Jul 15 07:24:57 PM PDT 24 |
Finished | Jul 15 07:25:36 PM PDT 24 |
Peak memory | 204436 kb |
Host | smart-973c7ef4-72f2-4bbc-b858-60ca62e397bc |
User | root |
Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940352412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me m_walk.1940352412 |
Directory | /workspace/4.spi_device_mem_walk/latest |
Test location | /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.470810356 |
Short name | T1067 |
Test name | |
Test status | |
Simulation time | 161103081 ps |
CPU time | 1.73 seconds |
Started | Jul 15 07:24:57 PM PDT 24 |
Finished | Jul 15 07:25:37 PM PDT 24 |
Peak memory | 215772 kb |
Host | smart-288177f2-2a0e-4795-803b-eed568202f16 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470810356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp i_device_same_csr_outstanding.470810356 |
Directory | /workspace/4.spi_device_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.852539535 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 256285232 ps |
CPU time | 3.29 seconds |
Started | Jul 15 07:24:57 PM PDT 24 |
Finished | Jul 15 07:25:38 PM PDT 24 |
Peak memory | 216912 kb |
Host | smart-e8f08711-3f15-459c-b775-62b0a8fc2464 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852539535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.852539535 |
Directory | /workspace/4.spi_device_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.4171356847 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 664715428 ps |
CPU time | 14.02 seconds |
Started | Jul 15 07:25:00 PM PDT 24 |
Finished | Jul 15 07:25:52 PM PDT 24 |
Peak memory | 215812 kb |
Host | smart-d51e54d1-3870-4bc7-a2d0-a1fcc3eb19c2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171356847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device _tl_intg_err.4171356847 |
Directory | /workspace/4.spi_device_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1810181724 |
Short name | T1070 |
Test name | |
Test status | |
Simulation time | 11833157 ps |
CPU time | 0.72 seconds |
Started | Jul 15 07:25:13 PM PDT 24 |
Finished | Jul 15 07:25:55 PM PDT 24 |
Peak memory | 204284 kb |
Host | smart-be4b2e00-f47f-46d8-b07f-f8944fe89c70 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810181724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test. 1810181724 |
Directory | /workspace/40.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3307055144 |
Short name | T1066 |
Test name | |
Test status | |
Simulation time | 14647862 ps |
CPU time | 0.73 seconds |
Started | Jul 15 07:25:09 PM PDT 24 |
Finished | Jul 15 07:25:49 PM PDT 24 |
Peak memory | 204292 kb |
Host | smart-2d0bf726-e090-4936-8fe4-c3d4e1128d50 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307055144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test. 3307055144 |
Directory | /workspace/41.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/42.spi_device_intr_test.785051498 |
Short name | T1036 |
Test name | |
Test status | |
Simulation time | 73844854 ps |
CPU time | 0.71 seconds |
Started | Jul 15 07:25:16 PM PDT 24 |
Finished | Jul 15 07:25:57 PM PDT 24 |
Peak memory | 204248 kb |
Host | smart-6341a080-3d08-4bc2-bbb0-0cd35706bab9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785051498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.785051498 |
Directory | /workspace/42.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/43.spi_device_intr_test.4093499138 |
Short name | T1128 |
Test name | |
Test status | |
Simulation time | 11898129 ps |
CPU time | 0.7 seconds |
Started | Jul 15 07:25:18 PM PDT 24 |
Finished | Jul 15 07:26:01 PM PDT 24 |
Peak memory | 204300 kb |
Host | smart-6ece2a21-215e-4c41-9da5-51586688d816 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093499138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test. 4093499138 |
Directory | /workspace/43.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3473630767 |
Short name | T1022 |
Test name | |
Test status | |
Simulation time | 14380080 ps |
CPU time | 0.68 seconds |
Started | Jul 15 07:25:11 PM PDT 24 |
Finished | Jul 15 07:25:52 PM PDT 24 |
Peak memory | 204292 kb |
Host | smart-25325ef9-26ea-42d2-9603-2dfa245c1f7f |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473630767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test. 3473630767 |
Directory | /workspace/44.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2419898006 |
Short name | T1043 |
Test name | |
Test status | |
Simulation time | 28631163 ps |
CPU time | 0.73 seconds |
Started | Jul 15 07:25:11 PM PDT 24 |
Finished | Jul 15 07:25:52 PM PDT 24 |
Peak memory | 204252 kb |
Host | smart-88667f0e-903b-4ffb-9cd0-880e886c47ad |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419898006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test. 2419898006 |
Directory | /workspace/45.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/46.spi_device_intr_test.523360498 |
Short name | T1082 |
Test name | |
Test status | |
Simulation time | 15953155 ps |
CPU time | 0.74 seconds |
Started | Jul 15 07:25:17 PM PDT 24 |
Finished | Jul 15 07:25:58 PM PDT 24 |
Peak memory | 204304 kb |
Host | smart-da002e0a-9918-463e-be8b-28fba9ed3449 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523360498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.523360498 |
Directory | /workspace/46.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2467820144 |
Short name | T1058 |
Test name | |
Test status | |
Simulation time | 69173953 ps |
CPU time | 0.67 seconds |
Started | Jul 15 07:25:13 PM PDT 24 |
Finished | Jul 15 07:25:56 PM PDT 24 |
Peak memory | 204252 kb |
Host | smart-a232c984-505f-4344-a536-3dee6d559e95 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467820144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test. 2467820144 |
Directory | /workspace/47.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2579390726 |
Short name | T1107 |
Test name | |
Test status | |
Simulation time | 15307341 ps |
CPU time | 0.75 seconds |
Started | Jul 15 07:25:10 PM PDT 24 |
Finished | Jul 15 07:25:52 PM PDT 24 |
Peak memory | 204228 kb |
Host | smart-57f7e833-fa4a-4bec-ba4f-a7c6878cb2de |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579390726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test. 2579390726 |
Directory | /workspace/48.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/49.spi_device_intr_test.684796550 |
Short name | T1020 |
Test name | |
Test status | |
Simulation time | 12794384 ps |
CPU time | 0.72 seconds |
Started | Jul 15 07:25:12 PM PDT 24 |
Finished | Jul 15 07:25:53 PM PDT 24 |
Peak memory | 204616 kb |
Host | smart-a2a5622a-dcbd-47f7-a33d-7ed257dc5efd |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684796550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.684796550 |
Directory | /workspace/49.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3453264901 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 89021359 ps |
CPU time | 3.03 seconds |
Started | Jul 15 07:24:57 PM PDT 24 |
Finished | Jul 15 07:25:37 PM PDT 24 |
Peak memory | 218920 kb |
Host | smart-7d76f2d8-fd83-4d35-9839-2e4d1392d7b9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453264901 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3453264901 |
Directory | /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1662692063 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 83271876 ps |
CPU time | 1.99 seconds |
Started | Jul 15 07:25:02 PM PDT 24 |
Finished | Jul 15 07:25:42 PM PDT 24 |
Peak memory | 207484 kb |
Host | smart-6c6a1645-a136-4da5-ad27-1d511ea64e20 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662692063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1 662692063 |
Directory | /workspace/5.spi_device_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2854532048 |
Short name | T1033 |
Test name | |
Test status | |
Simulation time | 29831550 ps |
CPU time | 0.75 seconds |
Started | Jul 15 07:24:55 PM PDT 24 |
Finished | Jul 15 07:25:35 PM PDT 24 |
Peak memory | 204312 kb |
Host | smart-c4c6bc0f-aa96-412f-b0d2-9575246bd54b |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854532048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2 854532048 |
Directory | /workspace/5.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.985893614 |
Short name | T1051 |
Test name | |
Test status | |
Simulation time | 251417473 ps |
CPU time | 1.85 seconds |
Started | Jul 15 07:24:59 PM PDT 24 |
Finished | Jul 15 07:25:40 PM PDT 24 |
Peak memory | 215752 kb |
Host | smart-a97771d4-2282-4dc2-bdce-581fa63bb134 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985893614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp i_device_same_csr_outstanding.985893614 |
Directory | /workspace/5.spi_device_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3590619295 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 27777882 ps |
CPU time | 1.87 seconds |
Started | Jul 15 07:24:56 PM PDT 24 |
Finished | Jul 15 07:25:36 PM PDT 24 |
Peak memory | 215972 kb |
Host | smart-26ebb297-c597-42d8-926a-96b8f139f84e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590619295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3 590619295 |
Directory | /workspace/5.spi_device_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2519941644 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 300275461 ps |
CPU time | 17.65 seconds |
Started | Jul 15 07:25:04 PM PDT 24 |
Finished | Jul 15 07:25:59 PM PDT 24 |
Peak memory | 215724 kb |
Host | smart-3d89c462-557a-4756-ade9-a16e9bc8a888 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519941644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device _tl_intg_err.2519941644 |
Directory | /workspace/5.spi_device_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3226309771 |
Short name | T1041 |
Test name | |
Test status | |
Simulation time | 104880672 ps |
CPU time | 2.7 seconds |
Started | Jul 15 07:24:58 PM PDT 24 |
Finished | Jul 15 07:25:38 PM PDT 24 |
Peak memory | 218564 kb |
Host | smart-6c6092fb-7e51-4ae4-bdc7-b85cf7451c6b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226309771 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3226309771 |
Directory | /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2778712470 |
Short name | T1062 |
Test name | |
Test status | |
Simulation time | 145996386 ps |
CPU time | 1.33 seconds |
Started | Jul 15 07:24:59 PM PDT 24 |
Finished | Jul 15 07:25:39 PM PDT 24 |
Peak memory | 207520 kb |
Host | smart-48a2ad62-f63c-4762-bd3c-3fe5cd176aeb |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778712470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2 778712470 |
Directory | /workspace/6.spi_device_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1588325637 |
Short name | T1039 |
Test name | |
Test status | |
Simulation time | 18700367 ps |
CPU time | 0.73 seconds |
Started | Jul 15 07:24:58 PM PDT 24 |
Finished | Jul 15 07:25:36 PM PDT 24 |
Peak memory | 204304 kb |
Host | smart-b9c8fd13-6452-4de9-8492-73f4ac8d2657 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588325637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1 588325637 |
Directory | /workspace/6.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.552738391 |
Short name | T1068 |
Test name | |
Test status | |
Simulation time | 28999185 ps |
CPU time | 1.74 seconds |
Started | Jul 15 07:25:02 PM PDT 24 |
Finished | Jul 15 07:25:42 PM PDT 24 |
Peak memory | 215784 kb |
Host | smart-422a7fb0-ff6c-4a73-9c1f-f286ee56aa99 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552738391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ= spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp i_device_same_csr_outstanding.552738391 |
Directory | /workspace/6.spi_device_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1920332894 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 849570938 ps |
CPU time | 15.42 seconds |
Started | Jul 15 07:25:00 PM PDT 24 |
Finished | Jul 15 07:25:54 PM PDT 24 |
Peak memory | 215864 kb |
Host | smart-88459d2e-0706-42a8-ab44-c85e331ff1a4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920332894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device _tl_intg_err.1920332894 |
Directory | /workspace/6.spi_device_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1343123579 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 23938848 ps |
CPU time | 1.51 seconds |
Started | Jul 15 07:25:00 PM PDT 24 |
Finished | Jul 15 07:25:40 PM PDT 24 |
Peak memory | 215872 kb |
Host | smart-1887895b-daea-4a52-b079-6f6bc2e9d40d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343123579 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1343123579 |
Directory | /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.601509619 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 82028341 ps |
CPU time | 1.94 seconds |
Started | Jul 15 07:25:01 PM PDT 24 |
Finished | Jul 15 07:25:42 PM PDT 24 |
Peak memory | 215688 kb |
Host | smart-40a968a1-e1ee-4ae5-b0d2-1278795e0341 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601509619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.601509619 |
Directory | /workspace/7.spi_device_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.spi_device_intr_test.477490602 |
Short name | T1035 |
Test name | |
Test status | |
Simulation time | 40952706 ps |
CPU time | 0.69 seconds |
Started | Jul 15 07:25:03 PM PDT 24 |
Finished | Jul 15 07:25:42 PM PDT 24 |
Peak memory | 204300 kb |
Host | smart-4af86bfd-eb06-47f4-a5e6-da6b5d553af6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477490602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.477490602 |
Directory | /workspace/7.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1412882427 |
Short name | T1048 |
Test name | |
Test status | |
Simulation time | 212674854 ps |
CPU time | 2.67 seconds |
Started | Jul 15 07:25:01 PM PDT 24 |
Finished | Jul 15 07:25:43 PM PDT 24 |
Peak memory | 215716 kb |
Host | smart-22ac25fc-d61e-4f87-b21f-37315f5049ce |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412882427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s pi_device_same_csr_outstanding.1412882427 |
Directory | /workspace/7.spi_device_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3260782886 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 84538570 ps |
CPU time | 2.52 seconds |
Started | Jul 15 07:25:04 PM PDT 24 |
Finished | Jul 15 07:25:47 PM PDT 24 |
Peak memory | 216092 kb |
Host | smart-8587051e-1fe7-4ed5-b76d-53d2784d7fbd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260782886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3 260782886 |
Directory | /workspace/7.spi_device_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1247326667 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 427641296 ps |
CPU time | 6.72 seconds |
Started | Jul 15 07:25:00 PM PDT 24 |
Finished | Jul 15 07:25:45 PM PDT 24 |
Peak memory | 215784 kb |
Host | smart-275ebd9c-a657-4393-a61d-2e9c8122fbf2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247326667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device _tl_intg_err.1247326667 |
Directory | /workspace/7.spi_device_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.4265985629 |
Short name | T1125 |
Test name | |
Test status | |
Simulation time | 144563500 ps |
CPU time | 3.61 seconds |
Started | Jul 15 07:25:02 PM PDT 24 |
Finished | Jul 15 07:25:44 PM PDT 24 |
Peak memory | 217820 kb |
Host | smart-e4fc241f-71c7-44a8-ae69-b881f612cb4f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265985629 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.4265985629 |
Directory | /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2338672534 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 29404747 ps |
CPU time | 1.88 seconds |
Started | Jul 15 07:25:03 PM PDT 24 |
Finished | Jul 15 07:25:43 PM PDT 24 |
Peak memory | 215756 kb |
Host | smart-2120e6ce-3596-4f65-817d-16e80019c4cb |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338672534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2 338672534 |
Directory | /workspace/8.spi_device_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.spi_device_intr_test.4210764241 |
Short name | T1024 |
Test name | |
Test status | |
Simulation time | 46519944 ps |
CPU time | 0.72 seconds |
Started | Jul 15 07:24:59 PM PDT 24 |
Finished | Jul 15 07:25:38 PM PDT 24 |
Peak memory | 204304 kb |
Host | smart-7c5f516d-6d54-4969-8699-85afb05ccacc |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210764241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.4 210764241 |
Directory | /workspace/8.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2227326366 |
Short name | T1075 |
Test name | |
Test status | |
Simulation time | 45749705 ps |
CPU time | 2.8 seconds |
Started | Jul 15 07:24:59 PM PDT 24 |
Finished | Jul 15 07:25:40 PM PDT 24 |
Peak memory | 215728 kb |
Host | smart-30b3289a-2f2d-4963-a9ea-8c144a45c4c4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227326366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s pi_device_same_csr_outstanding.2227326366 |
Directory | /workspace/8.spi_device_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2546940434 |
Short name | T1122 |
Test name | |
Test status | |
Simulation time | 941334178 ps |
CPU time | 3.43 seconds |
Started | Jul 15 07:25:01 PM PDT 24 |
Finished | Jul 15 07:25:42 PM PDT 24 |
Peak memory | 216128 kb |
Host | smart-81eee131-658f-47d3-8978-08366364a379 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546940434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2 546940434 |
Directory | /workspace/8.spi_device_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2514472686 |
Short name | T1098 |
Test name | |
Test status | |
Simulation time | 830450490 ps |
CPU time | 21.75 seconds |
Started | Jul 15 07:25:01 PM PDT 24 |
Finished | Jul 15 07:26:02 PM PDT 24 |
Peak memory | 215824 kb |
Host | smart-231b053b-3df5-4d30-9f3e-72b04dfeecc2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514472686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device _tl_intg_err.2514472686 |
Directory | /workspace/8.spi_device_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3210225538 |
Short name | T1112 |
Test name | |
Test status | |
Simulation time | 43380827 ps |
CPU time | 2.72 seconds |
Started | Jul 15 07:25:00 PM PDT 24 |
Finished | Jul 15 07:25:41 PM PDT 24 |
Peak memory | 218576 kb |
Host | smart-4af6de34-685a-4b28-bb7c-623e851e2476 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210225538 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3210225538 |
Directory | /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.315585599 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 142998988 ps |
CPU time | 2.28 seconds |
Started | Jul 15 07:25:02 PM PDT 24 |
Finished | Jul 15 07:25:43 PM PDT 24 |
Peak memory | 215696 kb |
Host | smart-7abfcb4f-941b-4c1a-9f05-39172ec8d635 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315585599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.315585599 |
Directory | /workspace/9.spi_device_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1922516963 |
Short name | T1046 |
Test name | |
Test status | |
Simulation time | 27284422 ps |
CPU time | 0.7 seconds |
Started | Jul 15 07:24:58 PM PDT 24 |
Finished | Jul 15 07:25:38 PM PDT 24 |
Peak memory | 204588 kb |
Host | smart-d2f1df2d-7915-40f7-9666-373c1bc75375 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922516963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1 922516963 |
Directory | /workspace/9.spi_device_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1966844736 |
Short name | T1057 |
Test name | |
Test status | |
Simulation time | 208923793 ps |
CPU time | 3 seconds |
Started | Jul 15 07:24:57 PM PDT 24 |
Finished | Jul 15 07:25:38 PM PDT 24 |
Peak memory | 215712 kb |
Host | smart-d4a8aed5-6d67-48a6-83a0-3021e8b95ce8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966844736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ =spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s pi_device_same_csr_outstanding.1966844736 |
Directory | /workspace/9.spi_device_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.549480638 |
Short name | T1059 |
Test name | |
Test status | |
Simulation time | 229474070 ps |
CPU time | 5.16 seconds |
Started | Jul 15 07:24:59 PM PDT 24 |
Finished | Jul 15 07:25:43 PM PDT 24 |
Peak memory | 215948 kb |
Host | smart-d1785857-ae44-4e5f-bce9-de90bcc430c2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549480638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.549480638 |
Directory | /workspace/9.spi_device_tl_errors/latest |
Test location | /workspace/coverage/default/0.spi_device_alert_test.1812933459 |
Short name | T621 |
Test name | |
Test status | |
Simulation time | 13368026 ps |
CPU time | 0.71 seconds |
Started | Jul 15 06:44:42 PM PDT 24 |
Finished | Jul 15 06:44:43 PM PDT 24 |
Peak memory | 204900 kb |
Host | smart-5846f0de-d3e7-45d9-a1af-2df70a714d87 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812933459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1 812933459 |
Directory | /workspace/0.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/0.spi_device_cfg_cmd.1576150515 |
Short name | T731 |
Test name | |
Test status | |
Simulation time | 1644862899 ps |
CPU time | 10.75 seconds |
Started | Jul 15 06:44:36 PM PDT 24 |
Finished | Jul 15 06:44:47 PM PDT 24 |
Peak memory | 232664 kb |
Host | smart-64d4bad5-0973-421b-b134-2000c3768adc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1576150515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1576150515 |
Directory | /workspace/0.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/0.spi_device_csb_read.636186668 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 15310167 ps |
CPU time | 0.81 seconds |
Started | Jul 15 06:44:34 PM PDT 24 |
Finished | Jul 15 06:44:36 PM PDT 24 |
Peak memory | 206576 kb |
Host | smart-9ca5c65b-2c43-4157-8d77-56f3565f1671 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=636186668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.636186668 |
Directory | /workspace/0.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/0.spi_device_flash_all.2547249295 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 3545314123 ps |
CPU time | 47.07 seconds |
Started | Jul 15 06:44:35 PM PDT 24 |
Finished | Jul 15 06:45:22 PM PDT 24 |
Peak memory | 250672 kb |
Host | smart-b600a645-94da-4261-86f4-5d4dbb60acac |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2547249295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2547249295 |
Directory | /workspace/0.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/0.spi_device_flash_and_tpm.4064669200 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 3842521928 ps |
CPU time | 100.85 seconds |
Started | Jul 15 06:44:32 PM PDT 24 |
Finished | Jul 15 06:46:13 PM PDT 24 |
Peak memory | 257368 kb |
Host | smart-b53ae250-6a36-42f5-a4a0-f546e9fb10aa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4064669200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.4064669200 |
Directory | /workspace/0.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.4086881993 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 49289540413 ps |
CPU time | 356.24 seconds |
Started | Jul 15 06:44:37 PM PDT 24 |
Finished | Jul 15 06:50:34 PM PDT 24 |
Peak memory | 264088 kb |
Host | smart-09e97ad8-7dcc-43cf-8d90-88730548e10a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4086881993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds .4086881993 |
Directory | /workspace/0.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/0.spi_device_intercept.993968535 |
Short name | T674 |
Test name | |
Test status | |
Simulation time | 1154507658 ps |
CPU time | 6.98 seconds |
Started | Jul 15 06:44:35 PM PDT 24 |
Finished | Jul 15 06:44:43 PM PDT 24 |
Peak memory | 232640 kb |
Host | smart-a0760d18-2fe8-4de4-81ae-0e7803481e57 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=993968535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.993968535 |
Directory | /workspace/0.spi_device_intercept/latest |
Test location | /workspace/coverage/default/0.spi_device_mailbox.2400620767 |
Short name | T873 |
Test name | |
Test status | |
Simulation time | 368224062 ps |
CPU time | 5.49 seconds |
Started | Jul 15 06:44:37 PM PDT 24 |
Finished | Jul 15 06:44:43 PM PDT 24 |
Peak memory | 232672 kb |
Host | smart-744d5a91-9227-4ab1-8ecd-f41e89100df1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2400620767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2400620767 |
Directory | /workspace/0.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2597460286 |
Short name | T974 |
Test name | |
Test status | |
Simulation time | 4313358017 ps |
CPU time | 16.51 seconds |
Started | Jul 15 06:44:34 PM PDT 24 |
Finished | Jul 15 06:44:51 PM PDT 24 |
Peak memory | 232776 kb |
Host | smart-ed138810-ea55-48b6-afc7-65075713566c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2597460286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2597460286 |
Directory | /workspace/0.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/0.spi_device_read_buffer_direct.112842702 |
Short name | T950 |
Test name | |
Test status | |
Simulation time | 2967466953 ps |
CPU time | 18.22 seconds |
Started | Jul 15 06:44:36 PM PDT 24 |
Finished | Jul 15 06:44:55 PM PDT 24 |
Peak memory | 219476 kb |
Host | smart-c26098c1-f99c-4eab-9c55-45cc8c6a0f17 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=112842702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc t.112842702 |
Directory | /workspace/0.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/0.spi_device_stress_all.3577147404 |
Short name | T505 |
Test name | |
Test status | |
Simulation time | 86001505 ps |
CPU time | 1.06 seconds |
Started | Jul 15 06:44:37 PM PDT 24 |
Finished | Jul 15 06:44:38 PM PDT 24 |
Peak memory | 206856 kb |
Host | smart-ad67366f-5157-4313-8de0-d9443fa57782 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577147404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres s_all.3577147404 |
Directory | /workspace/0.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/0.spi_device_tpm_all.75736799 |
Short name | T640 |
Test name | |
Test status | |
Simulation time | 13904535848 ps |
CPU time | 21.76 seconds |
Started | Jul 15 06:44:36 PM PDT 24 |
Finished | Jul 15 06:44:58 PM PDT 24 |
Peak memory | 216560 kb |
Host | smart-a1b3b9a6-519d-4677-9328-2e9d117788b5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=75736799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.75736799 |
Directory | /workspace/0.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3028118673 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 14306128715 ps |
CPU time | 21.42 seconds |
Started | Jul 15 06:44:37 PM PDT 24 |
Finished | Jul 15 06:44:59 PM PDT 24 |
Peak memory | 216296 kb |
Host | smart-b35b24bc-05d1-46b8-bf96-040256fddcae |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3028118673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3028118673 |
Directory | /workspace/0.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/0.spi_device_tpm_rw.643820918 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 47887097 ps |
CPU time | 0.86 seconds |
Started | Jul 15 06:44:37 PM PDT 24 |
Finished | Jul 15 06:44:38 PM PDT 24 |
Peak memory | 206976 kb |
Host | smart-a33b6af4-5b53-41ef-9bd2-024abe866d81 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=643820918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.643820918 |
Directory | /workspace/0.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/0.spi_device_tpm_sts_read.2428164814 |
Short name | T980 |
Test name | |
Test status | |
Simulation time | 49615506 ps |
CPU time | 0.83 seconds |
Started | Jul 15 06:44:35 PM PDT 24 |
Finished | Jul 15 06:44:36 PM PDT 24 |
Peak memory | 205924 kb |
Host | smart-bf788687-3085-4bb4-bf8d-b61f182c2a84 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2428164814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2428164814 |
Directory | /workspace/0.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/0.spi_device_upload.3778778079 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 1030785083 ps |
CPU time | 9.33 seconds |
Started | Jul 15 06:44:37 PM PDT 24 |
Finished | Jul 15 06:44:47 PM PDT 24 |
Peak memory | 248976 kb |
Host | smart-986e8274-ea9f-4c1f-ac4f-501ebc93a925 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3778778079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3778778079 |
Directory | /workspace/0.spi_device_upload/latest |
Test location | /workspace/coverage/default/1.spi_device_cfg_cmd.2864219337 |
Short name | T654 |
Test name | |
Test status | |
Simulation time | 428023505 ps |
CPU time | 6.78 seconds |
Started | Jul 15 06:44:39 PM PDT 24 |
Finished | Jul 15 06:44:46 PM PDT 24 |
Peak memory | 232700 kb |
Host | smart-7d0e5bc4-1ae4-4598-b316-3ec5ad1d991d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2864219337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2864219337 |
Directory | /workspace/1.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/1.spi_device_csb_read.699902314 |
Short name | T778 |
Test name | |
Test status | |
Simulation time | 71508537 ps |
CPU time | 0.76 seconds |
Started | Jul 15 06:44:41 PM PDT 24 |
Finished | Jul 15 06:44:42 PM PDT 24 |
Peak memory | 206876 kb |
Host | smart-c723eaf0-9b80-4be2-b0ef-e63a54c6ddb9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=699902314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.699902314 |
Directory | /workspace/1.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/1.spi_device_flash_all.1556963307 |
Short name | T655 |
Test name | |
Test status | |
Simulation time | 3486540281 ps |
CPU time | 48.8 seconds |
Started | Jul 15 06:44:45 PM PDT 24 |
Finished | Jul 15 06:45:34 PM PDT 24 |
Peak memory | 251788 kb |
Host | smart-3c1e298e-ffd4-4fa3-bc2f-adcccdd9c890 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1556963307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1556963307 |
Directory | /workspace/1.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/1.spi_device_flash_and_tpm.3666807566 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 16074000054 ps |
CPU time | 25.55 seconds |
Started | Jul 15 06:44:46 PM PDT 24 |
Finished | Jul 15 06:45:12 PM PDT 24 |
Peak memory | 224468 kb |
Host | smart-5984cffe-73f1-464b-b2d2-e09059d5921e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3666807566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3666807566 |
Directory | /workspace/1.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/1.spi_device_flash_mode.2442580866 |
Short name | T919 |
Test name | |
Test status | |
Simulation time | 576577453 ps |
CPU time | 7.03 seconds |
Started | Jul 15 06:44:42 PM PDT 24 |
Finished | Jul 15 06:44:50 PM PDT 24 |
Peak memory | 236924 kb |
Host | smart-53e0ffd1-bfff-478e-bc06-c2728792ca4c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2442580866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2442580866 |
Directory | /workspace/1.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.736487310 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 11057683405 ps |
CPU time | 104.83 seconds |
Started | Jul 15 06:44:44 PM PDT 24 |
Finished | Jul 15 06:46:29 PM PDT 24 |
Peak memory | 241296 kb |
Host | smart-897f1b8b-02b6-4f2d-b981-960ba3e015ba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=736487310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds. 736487310 |
Directory | /workspace/1.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/1.spi_device_intercept.97378073 |
Short name | T494 |
Test name | |
Test status | |
Simulation time | 12312490348 ps |
CPU time | 8.08 seconds |
Started | Jul 15 06:44:42 PM PDT 24 |
Finished | Jul 15 06:44:51 PM PDT 24 |
Peak memory | 224512 kb |
Host | smart-29da72dd-8499-44a9-9f81-0fe69922ce27 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=97378073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.97378073 |
Directory | /workspace/1.spi_device_intercept/latest |
Test location | /workspace/coverage/default/1.spi_device_mailbox.3171209490 |
Short name | T732 |
Test name | |
Test status | |
Simulation time | 15692768815 ps |
CPU time | 191.3 seconds |
Started | Jul 15 06:44:41 PM PDT 24 |
Finished | Jul 15 06:47:52 PM PDT 24 |
Peak memory | 233740 kb |
Host | smart-558a204d-ede3-49fe-a49d-b9cd1e10989f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3171209490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3171209490 |
Directory | /workspace/1.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1109433104 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 6110754872 ps |
CPU time | 8.46 seconds |
Started | Jul 15 06:44:41 PM PDT 24 |
Finished | Jul 15 06:44:50 PM PDT 24 |
Peak memory | 224508 kb |
Host | smart-1e7e45ef-0c26-41a4-9e23-a3701e40bbfd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1109433104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap .1109433104 |
Directory | /workspace/1.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/1.spi_device_pass_cmd_filtering.659743060 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 10653476287 ps |
CPU time | 6.62 seconds |
Started | Jul 15 06:44:39 PM PDT 24 |
Finished | Jul 15 06:44:46 PM PDT 24 |
Peak memory | 224480 kb |
Host | smart-30a8f259-bc4a-4173-a894-e26107b22240 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=659743060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.659743060 |
Directory | /workspace/1.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/1.spi_device_read_buffer_direct.1859295271 |
Short name | T608 |
Test name | |
Test status | |
Simulation time | 735228014 ps |
CPU time | 9.67 seconds |
Started | Jul 15 06:44:51 PM PDT 24 |
Finished | Jul 15 06:45:01 PM PDT 24 |
Peak memory | 223020 kb |
Host | smart-3ce69eee-aebc-401d-add0-a32001c58df0 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1859295271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire ct.1859295271 |
Directory | /workspace/1.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/1.spi_device_sec_cm.283583767 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 169687469 ps |
CPU time | 1.13 seconds |
Started | Jul 15 06:44:51 PM PDT 24 |
Finished | Jul 15 06:44:53 PM PDT 24 |
Peak memory | 236032 kb |
Host | smart-805f3ee3-22e5-4937-bcc6-792e8f2751e1 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283583767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.283583767 |
Directory | /workspace/1.spi_device_sec_cm/latest |
Test location | /workspace/coverage/default/1.spi_device_stress_all.2055865873 |
Short name | T493 |
Test name | |
Test status | |
Simulation time | 177147742 ps |
CPU time | 0.91 seconds |
Started | Jul 15 06:44:51 PM PDT 24 |
Finished | Jul 15 06:44:53 PM PDT 24 |
Peak memory | 205868 kb |
Host | smart-b7ad475a-e6b8-4946-9c73-a5d38b68149c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055865873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres s_all.2055865873 |
Directory | /workspace/1.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/1.spi_device_tpm_all.2013088755 |
Short name | T769 |
Test name | |
Test status | |
Simulation time | 8732486965 ps |
CPU time | 24.73 seconds |
Started | Jul 15 06:44:42 PM PDT 24 |
Finished | Jul 15 06:45:07 PM PDT 24 |
Peak memory | 216552 kb |
Host | smart-94ead9c2-31f9-4652-aa5c-152669f0b6c4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2013088755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2013088755 |
Directory | /workspace/1.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1368268542 |
Short name | T722 |
Test name | |
Test status | |
Simulation time | 2354338012 ps |
CPU time | 1.55 seconds |
Started | Jul 15 06:44:37 PM PDT 24 |
Finished | Jul 15 06:44:39 PM PDT 24 |
Peak memory | 207972 kb |
Host | smart-c85041e5-47f4-4cf8-9212-295a4d4574ad |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1368268542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1368268542 |
Directory | /workspace/1.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/1.spi_device_tpm_rw.3500382783 |
Short name | T768 |
Test name | |
Test status | |
Simulation time | 14383904 ps |
CPU time | 0.75 seconds |
Started | Jul 15 06:44:40 PM PDT 24 |
Finished | Jul 15 06:44:41 PM PDT 24 |
Peak memory | 205948 kb |
Host | smart-56a0fe7a-40e4-433f-9c4a-e873392486ce |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3500382783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3500382783 |
Directory | /workspace/1.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/1.spi_device_tpm_sts_read.304642947 |
Short name | T581 |
Test name | |
Test status | |
Simulation time | 137438566 ps |
CPU time | 0.82 seconds |
Started | Jul 15 06:44:41 PM PDT 24 |
Finished | Jul 15 06:44:42 PM PDT 24 |
Peak memory | 205936 kb |
Host | smart-b48d9cef-ec60-4e38-b0e5-e39def3070cd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=304642947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.304642947 |
Directory | /workspace/1.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/1.spi_device_upload.3733417108 |
Short name | T691 |
Test name | |
Test status | |
Simulation time | 2135485199 ps |
CPU time | 11.28 seconds |
Started | Jul 15 06:44:42 PM PDT 24 |
Finished | Jul 15 06:44:54 PM PDT 24 |
Peak memory | 232520 kb |
Host | smart-c99ce7ab-9bf8-4588-b875-00eb5037bdc0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3733417108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3733417108 |
Directory | /workspace/1.spi_device_upload/latest |
Test location | /workspace/coverage/default/10.spi_device_alert_test.2214709078 |
Short name | T805 |
Test name | |
Test status | |
Simulation time | 33464464 ps |
CPU time | 0.77 seconds |
Started | Jul 15 06:46:13 PM PDT 24 |
Finished | Jul 15 06:46:14 PM PDT 24 |
Peak memory | 205792 kb |
Host | smart-03640646-e52b-4781-b9c4-cd8d2c639568 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214709078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test. 2214709078 |
Directory | /workspace/10.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/10.spi_device_cfg_cmd.3858401772 |
Short name | T992 |
Test name | |
Test status | |
Simulation time | 270348416 ps |
CPU time | 2.69 seconds |
Started | Jul 15 06:46:08 PM PDT 24 |
Finished | Jul 15 06:46:12 PM PDT 24 |
Peak memory | 224408 kb |
Host | smart-4a900006-f979-47f2-91b0-2701380b1331 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3858401772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3858401772 |
Directory | /workspace/10.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/10.spi_device_csb_read.1080132048 |
Short name | T637 |
Test name | |
Test status | |
Simulation time | 21726010 ps |
CPU time | 0.83 seconds |
Started | Jul 15 06:45:57 PM PDT 24 |
Finished | Jul 15 06:46:00 PM PDT 24 |
Peak memory | 206512 kb |
Host | smart-9264e7a1-4b1a-45ad-97ba-e16789399a8e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1080132048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1080132048 |
Directory | /workspace/10.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/10.spi_device_flash_all.221445896 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 53877416017 ps |
CPU time | 158.51 seconds |
Started | Jul 15 06:46:08 PM PDT 24 |
Finished | Jul 15 06:48:48 PM PDT 24 |
Peak memory | 250724 kb |
Host | smart-4c31dde9-1d11-40d3-a2bf-7d338470639b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=221445896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.221445896 |
Directory | /workspace/10.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/10.spi_device_flash_and_tpm.2052381580 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 35649849126 ps |
CPU time | 352.21 seconds |
Started | Jul 15 06:46:08 PM PDT 24 |
Finished | Jul 15 06:52:01 PM PDT 24 |
Peak memory | 254284 kb |
Host | smart-e40edf8c-e385-4da3-aa54-44aa52c4b552 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2052381580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2052381580 |
Directory | /workspace/10.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1049670674 |
Short name | T720 |
Test name | |
Test status | |
Simulation time | 243609595719 ps |
CPU time | 623.3 seconds |
Started | Jul 15 06:46:15 PM PDT 24 |
Finished | Jul 15 06:56:39 PM PDT 24 |
Peak memory | 266628 kb |
Host | smart-9f41a56c-ff3b-42cb-89eb-74b5c0476b2e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1049670674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl e.1049670674 |
Directory | /workspace/10.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/10.spi_device_flash_mode.72656217 |
Short name | T554 |
Test name | |
Test status | |
Simulation time | 404289596 ps |
CPU time | 10.06 seconds |
Started | Jul 15 06:46:08 PM PDT 24 |
Finished | Jul 15 06:46:20 PM PDT 24 |
Peak memory | 232552 kb |
Host | smart-6123303e-821d-4103-af66-18af96396977 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=72656217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.72656217 |
Directory | /workspace/10.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.971169373 |
Short name | T663 |
Test name | |
Test status | |
Simulation time | 589596805 ps |
CPU time | 12.97 seconds |
Started | Jul 15 06:46:07 PM PDT 24 |
Finished | Jul 15 06:46:21 PM PDT 24 |
Peak memory | 249020 kb |
Host | smart-ee403488-bfb9-4c03-9a9c-52ebc1b6a94a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=971169373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds .971169373 |
Directory | /workspace/10.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/10.spi_device_intercept.910138483 |
Short name | T727 |
Test name | |
Test status | |
Simulation time | 2067641732 ps |
CPU time | 8.32 seconds |
Started | Jul 15 06:46:05 PM PDT 24 |
Finished | Jul 15 06:46:15 PM PDT 24 |
Peak memory | 224400 kb |
Host | smart-02a4c5e3-bf2e-4254-8e84-d4cc2ada5f13 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=910138483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.910138483 |
Directory | /workspace/10.spi_device_intercept/latest |
Test location | /workspace/coverage/default/10.spi_device_mailbox.3116447412 |
Short name | T690 |
Test name | |
Test status | |
Simulation time | 1347622744 ps |
CPU time | 11.04 seconds |
Started | Jul 15 06:46:04 PM PDT 24 |
Finished | Jul 15 06:46:16 PM PDT 24 |
Peak memory | 232588 kb |
Host | smart-5ce37398-4316-4e85-a36c-019b275b935f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3116447412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3116447412 |
Directory | /workspace/10.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3470615313 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 3005444936 ps |
CPU time | 7.2 seconds |
Started | Jul 15 06:46:04 PM PDT 24 |
Finished | Jul 15 06:46:12 PM PDT 24 |
Peak memory | 239468 kb |
Host | smart-0b9ddf10-143d-4669-aa5b-79c0173a53ce |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3470615313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa p.3470615313 |
Directory | /workspace/10.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3638690652 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 2901245476 ps |
CPU time | 6.98 seconds |
Started | Jul 15 06:46:05 PM PDT 24 |
Finished | Jul 15 06:46:14 PM PDT 24 |
Peak memory | 232612 kb |
Host | smart-11ed1ab9-f4e4-4188-aabc-d347528beed3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3638690652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3638690652 |
Directory | /workspace/10.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/10.spi_device_read_buffer_direct.1744143041 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 1178893964 ps |
CPU time | 10.92 seconds |
Started | Jul 15 06:46:07 PM PDT 24 |
Finished | Jul 15 06:46:19 PM PDT 24 |
Peak memory | 222144 kb |
Host | smart-c5cdc3bb-c36c-49d4-aab2-cf12f00e8d59 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1744143041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir ect.1744143041 |
Directory | /workspace/10.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/10.spi_device_stress_all.1631133798 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 46106512112 ps |
CPU time | 178.22 seconds |
Started | Jul 15 06:46:13 PM PDT 24 |
Finished | Jul 15 06:49:12 PM PDT 24 |
Peak memory | 266848 kb |
Host | smart-91ba1f14-d5da-418b-a253-0b6e6ba0a53d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631133798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre ss_all.1631133798 |
Directory | /workspace/10.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/10.spi_device_tpm_all.168816645 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 13397012492 ps |
CPU time | 22.9 seconds |
Started | Jul 15 06:46:05 PM PDT 24 |
Finished | Jul 15 06:46:30 PM PDT 24 |
Peak memory | 216420 kb |
Host | smart-27623164-4cf3-47fc-be18-25f7caf9752e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=168816645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.168816645 |
Directory | /workspace/10.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2629942829 |
Short name | T986 |
Test name | |
Test status | |
Simulation time | 104184186813 ps |
CPU time | 16.8 seconds |
Started | Jul 15 06:46:05 PM PDT 24 |
Finished | Jul 15 06:46:24 PM PDT 24 |
Peak memory | 216364 kb |
Host | smart-fcb4b091-0031-406a-b5f9-127b82b6a947 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2629942829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2629942829 |
Directory | /workspace/10.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/10.spi_device_tpm_rw.1438827293 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 65588572 ps |
CPU time | 1.13 seconds |
Started | Jul 15 06:46:07 PM PDT 24 |
Finished | Jul 15 06:46:10 PM PDT 24 |
Peak memory | 216024 kb |
Host | smart-ff1783f4-a704-4baa-bc23-96fc6599c014 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1438827293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1438827293 |
Directory | /workspace/10.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/10.spi_device_tpm_sts_read.4171270509 |
Short name | T995 |
Test name | |
Test status | |
Simulation time | 73479085 ps |
CPU time | 0.8 seconds |
Started | Jul 15 06:46:07 PM PDT 24 |
Finished | Jul 15 06:46:09 PM PDT 24 |
Peak memory | 205960 kb |
Host | smart-feed8299-5371-4a9f-be30-9bdbabc061b7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4171270509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.4171270509 |
Directory | /workspace/10.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/10.spi_device_upload.2896878436 |
Short name | T909 |
Test name | |
Test status | |
Simulation time | 8689053234 ps |
CPU time | 7.07 seconds |
Started | Jul 15 06:46:04 PM PDT 24 |
Finished | Jul 15 06:46:12 PM PDT 24 |
Peak memory | 224564 kb |
Host | smart-530b3cb5-392d-4228-ad5c-c951b8013f2e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2896878436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2896878436 |
Directory | /workspace/10.spi_device_upload/latest |
Test location | /workspace/coverage/default/11.spi_device_alert_test.3496413229 |
Short name | T488 |
Test name | |
Test status | |
Simulation time | 13532557 ps |
CPU time | 0.73 seconds |
Started | Jul 15 06:46:19 PM PDT 24 |
Finished | Jul 15 06:46:20 PM PDT 24 |
Peak memory | 205500 kb |
Host | smart-706be01d-c68c-4766-a5bb-d3bb84337634 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496413229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test. 3496413229 |
Directory | /workspace/11.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/11.spi_device_cfg_cmd.4201111436 |
Short name | T667 |
Test name | |
Test status | |
Simulation time | 73898547 ps |
CPU time | 2.13 seconds |
Started | Jul 15 06:46:15 PM PDT 24 |
Finished | Jul 15 06:46:18 PM PDT 24 |
Peak memory | 224000 kb |
Host | smart-efd1f073-a6ef-4b2c-b178-9e02466dbfd7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4201111436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.4201111436 |
Directory | /workspace/11.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/11.spi_device_csb_read.442766554 |
Short name | T996 |
Test name | |
Test status | |
Simulation time | 27350594 ps |
CPU time | 0.81 seconds |
Started | Jul 15 06:46:14 PM PDT 24 |
Finished | Jul 15 06:46:15 PM PDT 24 |
Peak memory | 206544 kb |
Host | smart-b13e3ad9-b24f-4a94-94c9-4f1a1cfd8369 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=442766554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.442766554 |
Directory | /workspace/11.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/11.spi_device_flash_all.777011332 |
Short name | T882 |
Test name | |
Test status | |
Simulation time | 33168058631 ps |
CPU time | 121.24 seconds |
Started | Jul 15 06:46:22 PM PDT 24 |
Finished | Jul 15 06:48:23 PM PDT 24 |
Peak memory | 254936 kb |
Host | smart-e1298e6c-bd43-456a-bd39-62d387dbdf90 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=777011332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.777011332 |
Directory | /workspace/11.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/11.spi_device_flash_and_tpm.4051719686 |
Short name | T836 |
Test name | |
Test status | |
Simulation time | 234927164351 ps |
CPU time | 482.19 seconds |
Started | Jul 15 06:46:19 PM PDT 24 |
Finished | Jul 15 06:54:22 PM PDT 24 |
Peak memory | 272268 kb |
Host | smart-46e3d93b-a158-403d-a141-1a317ef29632 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4051719686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.4051719686 |
Directory | /workspace/11.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.448672190 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 53909900474 ps |
CPU time | 71.15 seconds |
Started | Jul 15 06:46:20 PM PDT 24 |
Finished | Jul 15 06:47:31 PM PDT 24 |
Peak memory | 252124 kb |
Host | smart-ae7d0370-b8fa-47c4-bc15-b9c43074d4a7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=448672190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle .448672190 |
Directory | /workspace/11.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/11.spi_device_flash_mode.2521896752 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 1911204778 ps |
CPU time | 8.95 seconds |
Started | Jul 15 06:46:12 PM PDT 24 |
Finished | Jul 15 06:46:21 PM PDT 24 |
Peak memory | 224404 kb |
Host | smart-41e8b3ea-5bc4-46f0-b39a-88b6081f0bd1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2521896752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2521896752 |
Directory | /workspace/11.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.1139372962 |
Short name | T815 |
Test name | |
Test status | |
Simulation time | 2601073490 ps |
CPU time | 55.89 seconds |
Started | Jul 15 06:46:24 PM PDT 24 |
Finished | Jul 15 06:47:21 PM PDT 24 |
Peak memory | 265312 kb |
Host | smart-08985e95-fb99-41ff-81df-70b0b7572160 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1139372962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd s.1139372962 |
Directory | /workspace/11.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/11.spi_device_intercept.3523624619 |
Short name | T726 |
Test name | |
Test status | |
Simulation time | 342797403 ps |
CPU time | 5.77 seconds |
Started | Jul 15 06:46:13 PM PDT 24 |
Finished | Jul 15 06:46:19 PM PDT 24 |
Peak memory | 224396 kb |
Host | smart-81b166f2-7d84-4feb-8e46-08c681c62568 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3523624619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3523624619 |
Directory | /workspace/11.spi_device_intercept/latest |
Test location | /workspace/coverage/default/11.spi_device_mailbox.3770319257 |
Short name | T466 |
Test name | |
Test status | |
Simulation time | 978016046 ps |
CPU time | 12.44 seconds |
Started | Jul 15 06:46:13 PM PDT 24 |
Finished | Jul 15 06:46:26 PM PDT 24 |
Peak memory | 240344 kb |
Host | smart-1ae29afb-4a68-4369-85db-d033661806b6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3770319257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3770319257 |
Directory | /workspace/11.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3280793435 |
Short name | T890 |
Test name | |
Test status | |
Simulation time | 168949366 ps |
CPU time | 3.48 seconds |
Started | Jul 15 06:46:11 PM PDT 24 |
Finished | Jul 15 06:46:15 PM PDT 24 |
Peak memory | 232616 kb |
Host | smart-6c54ae31-bd2d-4c4b-84e6-b2aeef996b47 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3280793435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa p.3280793435 |
Directory | /workspace/11.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3143114358 |
Short name | T571 |
Test name | |
Test status | |
Simulation time | 2069781121 ps |
CPU time | 9.06 seconds |
Started | Jul 15 06:46:15 PM PDT 24 |
Finished | Jul 15 06:46:25 PM PDT 24 |
Peak memory | 232572 kb |
Host | smart-8e29aa81-8fb6-4786-bae6-cc7c2bcf89a1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3143114358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3143114358 |
Directory | /workspace/11.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/11.spi_device_read_buffer_direct.740866261 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 3701807897 ps |
CPU time | 14.47 seconds |
Started | Jul 15 06:46:23 PM PDT 24 |
Finished | Jul 15 06:46:38 PM PDT 24 |
Peak memory | 222688 kb |
Host | smart-4a14e28f-cbb9-48f9-9933-0bb06a7475b1 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=740866261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire ct.740866261 |
Directory | /workspace/11.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/11.spi_device_tpm_all.1967272815 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 5172509946 ps |
CPU time | 22.19 seconds |
Started | Jul 15 06:46:12 PM PDT 24 |
Finished | Jul 15 06:46:34 PM PDT 24 |
Peak memory | 216332 kb |
Host | smart-4ebb38cd-fc68-4570-8ec3-d6b81c0bf689 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1967272815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1967272815 |
Directory | /workspace/11.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.320046115 |
Short name | T527 |
Test name | |
Test status | |
Simulation time | 12117162 ps |
CPU time | 0.73 seconds |
Started | Jul 15 06:46:15 PM PDT 24 |
Finished | Jul 15 06:46:17 PM PDT 24 |
Peak memory | 205640 kb |
Host | smart-a725e843-81f8-4cec-bb5a-3cc55cf10978 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=320046115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.320046115 |
Directory | /workspace/11.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/11.spi_device_tpm_rw.745595800 |
Short name | T695 |
Test name | |
Test status | |
Simulation time | 90384281 ps |
CPU time | 0.75 seconds |
Started | Jul 15 06:46:14 PM PDT 24 |
Finished | Jul 15 06:46:16 PM PDT 24 |
Peak memory | 205584 kb |
Host | smart-27e8a92b-4929-4351-bc23-efb6dcf38003 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=745595800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.745595800 |
Directory | /workspace/11.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/11.spi_device_tpm_sts_read.923418661 |
Short name | T1007 |
Test name | |
Test status | |
Simulation time | 20461867 ps |
CPU time | 0.74 seconds |
Started | Jul 15 06:46:15 PM PDT 24 |
Finished | Jul 15 06:46:17 PM PDT 24 |
Peak memory | 205916 kb |
Host | smart-b74f0648-de3f-4a92-bf5a-cd648f820b1e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=923418661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.923418661 |
Directory | /workspace/11.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/11.spi_device_upload.2603417500 |
Short name | T578 |
Test name | |
Test status | |
Simulation time | 4751769416 ps |
CPU time | 14.52 seconds |
Started | Jul 15 06:46:14 PM PDT 24 |
Finished | Jul 15 06:46:29 PM PDT 24 |
Peak memory | 233168 kb |
Host | smart-ee403fc0-91ad-490e-989a-2e22bb9c544e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2603417500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2603417500 |
Directory | /workspace/11.spi_device_upload/latest |
Test location | /workspace/coverage/default/12.spi_device_alert_test.1209994729 |
Short name | T470 |
Test name | |
Test status | |
Simulation time | 15484324 ps |
CPU time | 0.77 seconds |
Started | Jul 15 06:46:31 PM PDT 24 |
Finished | Jul 15 06:46:32 PM PDT 24 |
Peak memory | 204944 kb |
Host | smart-acda2694-3d05-4c94-864c-12bd5f7a2727 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209994729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test. 1209994729 |
Directory | /workspace/12.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/12.spi_device_cfg_cmd.1778149076 |
Short name | T518 |
Test name | |
Test status | |
Simulation time | 2929485910 ps |
CPU time | 27.26 seconds |
Started | Jul 15 06:46:25 PM PDT 24 |
Finished | Jul 15 06:46:53 PM PDT 24 |
Peak memory | 232748 kb |
Host | smart-c74e60ff-cfde-44ec-b968-a8dae76d4a1d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1778149076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1778149076 |
Directory | /workspace/12.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/12.spi_device_csb_read.997070694 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 16753859 ps |
CPU time | 0.76 seconds |
Started | Jul 15 06:46:26 PM PDT 24 |
Finished | Jul 15 06:46:27 PM PDT 24 |
Peak memory | 205864 kb |
Host | smart-4e18d17a-6d38-48d2-b0f3-b49ee1b5779f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=997070694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.997070694 |
Directory | /workspace/12.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/12.spi_device_flash_all.2209017437 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 5783811747 ps |
CPU time | 63.35 seconds |
Started | Jul 15 06:46:29 PM PDT 24 |
Finished | Jul 15 06:47:33 PM PDT 24 |
Peak memory | 249148 kb |
Host | smart-224e789a-086b-4fcb-b084-ca237838e469 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2209017437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2209017437 |
Directory | /workspace/12.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/12.spi_device_flash_and_tpm.1859201992 |
Short name | T590 |
Test name | |
Test status | |
Simulation time | 68689792009 ps |
CPU time | 195.49 seconds |
Started | Jul 15 06:46:34 PM PDT 24 |
Finished | Jul 15 06:49:50 PM PDT 24 |
Peak memory | 255056 kb |
Host | smart-daa197df-6c08-4724-9db6-420023f40a62 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1859201992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1859201992 |
Directory | /workspace/12.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.931103734 |
Short name | T591 |
Test name | |
Test status | |
Simulation time | 71190659745 ps |
CPU time | 116.18 seconds |
Started | Jul 15 06:46:35 PM PDT 24 |
Finished | Jul 15 06:48:32 PM PDT 24 |
Peak memory | 240996 kb |
Host | smart-dcac964a-489b-41fc-9395-3cdad94005f8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=931103734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle .931103734 |
Directory | /workspace/12.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/12.spi_device_flash_mode.3716654820 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 539109947 ps |
CPU time | 7.22 seconds |
Started | Jul 15 06:46:27 PM PDT 24 |
Finished | Jul 15 06:46:35 PM PDT 24 |
Peak memory | 240784 kb |
Host | smart-14030afd-6942-4e74-8a3f-d30925237b5b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3716654820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3716654820 |
Directory | /workspace/12.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.4030948946 |
Short name | T976 |
Test name | |
Test status | |
Simulation time | 517353465 ps |
CPU time | 10.92 seconds |
Started | Jul 15 06:46:26 PM PDT 24 |
Finished | Jul 15 06:46:38 PM PDT 24 |
Peak memory | 240812 kb |
Host | smart-7cd67a3d-8b73-48bc-8405-946eb689d2b7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4030948946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd s.4030948946 |
Directory | /workspace/12.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/12.spi_device_intercept.512371319 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 284298670 ps |
CPU time | 5.15 seconds |
Started | Jul 15 06:46:28 PM PDT 24 |
Finished | Jul 15 06:46:33 PM PDT 24 |
Peak memory | 232528 kb |
Host | smart-9a867e04-990c-4183-b40a-61d590f4a242 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=512371319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.512371319 |
Directory | /workspace/12.spi_device_intercept/latest |
Test location | /workspace/coverage/default/12.spi_device_mailbox.3865395740 |
Short name | T762 |
Test name | |
Test status | |
Simulation time | 21560498234 ps |
CPU time | 60.53 seconds |
Started | Jul 15 06:46:29 PM PDT 24 |
Finished | Jul 15 06:47:30 PM PDT 24 |
Peak memory | 232820 kb |
Host | smart-e492ecdd-72fe-4de8-a9c5-bce7999138cb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3865395740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3865395740 |
Directory | /workspace/12.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3417355110 |
Short name | T609 |
Test name | |
Test status | |
Simulation time | 3897784322 ps |
CPU time | 13.16 seconds |
Started | Jul 15 06:46:20 PM PDT 24 |
Finished | Jul 15 06:46:34 PM PDT 24 |
Peak memory | 232748 kb |
Host | smart-c9b5f860-4b9f-4ec4-ae95-84cfe7ddcc56 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3417355110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa p.3417355110 |
Directory | /workspace/12.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1499985884 |
Short name | T657 |
Test name | |
Test status | |
Simulation time | 10075299037 ps |
CPU time | 6.7 seconds |
Started | Jul 15 06:46:23 PM PDT 24 |
Finished | Jul 15 06:46:30 PM PDT 24 |
Peak memory | 224532 kb |
Host | smart-c3250f19-e34c-4a09-bbc7-5ec2c878b24b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1499985884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1499985884 |
Directory | /workspace/12.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/12.spi_device_read_buffer_direct.516036298 |
Short name | T612 |
Test name | |
Test status | |
Simulation time | 640926155 ps |
CPU time | 3.9 seconds |
Started | Jul 15 06:46:24 PM PDT 24 |
Finished | Jul 15 06:46:29 PM PDT 24 |
Peak memory | 220200 kb |
Host | smart-4ca07dfe-6608-41bd-90ff-e9ee83be1ab4 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=516036298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire ct.516036298 |
Directory | /workspace/12.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/12.spi_device_stress_all.2851392034 |
Short name | T886 |
Test name | |
Test status | |
Simulation time | 573951778095 ps |
CPU time | 1008.67 seconds |
Started | Jul 15 06:46:34 PM PDT 24 |
Finished | Jul 15 07:03:23 PM PDT 24 |
Peak memory | 286080 kb |
Host | smart-5103c3cc-2749-4b40-b1a5-520c0dc97f67 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851392034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre ss_all.2851392034 |
Directory | /workspace/12.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/12.spi_device_tpm_all.2726791567 |
Short name | T583 |
Test name | |
Test status | |
Simulation time | 22365408422 ps |
CPU time | 19.86 seconds |
Started | Jul 15 06:46:21 PM PDT 24 |
Finished | Jul 15 06:46:41 PM PDT 24 |
Peak memory | 216308 kb |
Host | smart-7cab4dd5-7618-4429-9610-28cd0cd961fc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2726791567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2726791567 |
Directory | /workspace/12.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3194544416 |
Short name | T757 |
Test name | |
Test status | |
Simulation time | 1993100265 ps |
CPU time | 6.66 seconds |
Started | Jul 15 06:46:21 PM PDT 24 |
Finished | Jul 15 06:46:28 PM PDT 24 |
Peak memory | 216172 kb |
Host | smart-42689a8f-dd53-4d00-988d-cac41781ab75 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3194544416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3194544416 |
Directory | /workspace/12.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/12.spi_device_tpm_rw.2593059764 |
Short name | T994 |
Test name | |
Test status | |
Simulation time | 29635419 ps |
CPU time | 1.68 seconds |
Started | Jul 15 06:46:21 PM PDT 24 |
Finished | Jul 15 06:46:23 PM PDT 24 |
Peak memory | 216112 kb |
Host | smart-0d983b17-9cc8-4c2c-9c7b-c55c81e7b9a4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2593059764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2593059764 |
Directory | /workspace/12.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/12.spi_device_tpm_sts_read.3965552348 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 182166899 ps |
CPU time | 0.88 seconds |
Started | Jul 15 06:46:20 PM PDT 24 |
Finished | Jul 15 06:46:21 PM PDT 24 |
Peak memory | 205960 kb |
Host | smart-f5598347-7760-4644-b4e8-92fee9f9fc99 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3965552348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3965552348 |
Directory | /workspace/12.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/12.spi_device_upload.3842306534 |
Short name | T570 |
Test name | |
Test status | |
Simulation time | 164825000 ps |
CPU time | 2.49 seconds |
Started | Jul 15 06:46:28 PM PDT 24 |
Finished | Jul 15 06:46:31 PM PDT 24 |
Peak memory | 224452 kb |
Host | smart-f8b49f34-b9f5-47b7-8357-ea1d6e94a042 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3842306534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3842306534 |
Directory | /workspace/12.spi_device_upload/latest |
Test location | /workspace/coverage/default/13.spi_device_alert_test.969231418 |
Short name | T476 |
Test name | |
Test status | |
Simulation time | 18426062 ps |
CPU time | 0.72 seconds |
Started | Jul 15 06:46:44 PM PDT 24 |
Finished | Jul 15 06:46:45 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-856c6003-f355-40c1-9440-ca99eabbcaa9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969231418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.969231418 |
Directory | /workspace/13.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/13.spi_device_cfg_cmd.461962404 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 1126130578 ps |
CPU time | 6.94 seconds |
Started | Jul 15 06:46:44 PM PDT 24 |
Finished | Jul 15 06:46:51 PM PDT 24 |
Peak memory | 232612 kb |
Host | smart-ff07de79-e2b1-4aed-9f16-32cbb19dde2e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=461962404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.461962404 |
Directory | /workspace/13.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/13.spi_device_csb_read.1080981793 |
Short name | T869 |
Test name | |
Test status | |
Simulation time | 40232752 ps |
CPU time | 0.82 seconds |
Started | Jul 15 06:46:33 PM PDT 24 |
Finished | Jul 15 06:46:34 PM PDT 24 |
Peak memory | 206864 kb |
Host | smart-68197f16-3f04-498d-a0f2-8416dc170055 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1080981793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1080981793 |
Directory | /workspace/13.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/13.spi_device_flash_all.264367883 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 612872685636 ps |
CPU time | 242.51 seconds |
Started | Jul 15 06:46:42 PM PDT 24 |
Finished | Jul 15 06:50:45 PM PDT 24 |
Peak memory | 249160 kb |
Host | smart-a07ccb0d-f65f-48ba-914f-c14f3b810f77 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=264367883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.264367883 |
Directory | /workspace/13.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2576463509 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 11548602984 ps |
CPU time | 107.34 seconds |
Started | Jul 15 06:46:42 PM PDT 24 |
Finished | Jul 15 06:48:30 PM PDT 24 |
Peak memory | 264172 kb |
Host | smart-4a6a3edc-d39d-4003-a838-3d82cce94dc6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2576463509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl e.2576463509 |
Directory | /workspace/13.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/13.spi_device_flash_mode.348276542 |
Short name | T712 |
Test name | |
Test status | |
Simulation time | 124673667 ps |
CPU time | 3.69 seconds |
Started | Jul 15 06:46:41 PM PDT 24 |
Finished | Jul 15 06:46:45 PM PDT 24 |
Peak memory | 232640 kb |
Host | smart-59227420-1ac0-43da-9fda-d144ef855c40 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=348276542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.348276542 |
Directory | /workspace/13.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.2232949779 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 21477640390 ps |
CPU time | 49.44 seconds |
Started | Jul 15 06:46:43 PM PDT 24 |
Finished | Jul 15 06:47:33 PM PDT 24 |
Peak memory | 241120 kb |
Host | smart-1763002b-6f72-4c95-9676-b4a7cc5528e2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2232949779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd s.2232949779 |
Directory | /workspace/13.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/13.spi_device_intercept.1209972083 |
Short name | T801 |
Test name | |
Test status | |
Simulation time | 126987150 ps |
CPU time | 3.46 seconds |
Started | Jul 15 06:46:35 PM PDT 24 |
Finished | Jul 15 06:46:39 PM PDT 24 |
Peak memory | 232612 kb |
Host | smart-579f4fb8-09fc-4fd8-93b7-86e43f1afd61 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1209972083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1209972083 |
Directory | /workspace/13.spi_device_intercept/latest |
Test location | /workspace/coverage/default/13.spi_device_mailbox.2843808433 |
Short name | T585 |
Test name | |
Test status | |
Simulation time | 363002850 ps |
CPU time | 3.87 seconds |
Started | Jul 15 06:46:43 PM PDT 24 |
Finished | Jul 15 06:46:47 PM PDT 24 |
Peak memory | 224456 kb |
Host | smart-a417f388-dd00-400c-af56-084821c9e77f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2843808433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2843808433 |
Directory | /workspace/13.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2079331555 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 534205256 ps |
CPU time | 7.56 seconds |
Started | Jul 15 06:46:34 PM PDT 24 |
Finished | Jul 15 06:46:42 PM PDT 24 |
Peak memory | 232624 kb |
Host | smart-122cc415-5b7c-40a3-a81e-cbdbe85a298b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2079331555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa p.2079331555 |
Directory | /workspace/13.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2419083360 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 2375600569 ps |
CPU time | 10.27 seconds |
Started | Jul 15 06:46:35 PM PDT 24 |
Finished | Jul 15 06:46:46 PM PDT 24 |
Peak memory | 240264 kb |
Host | smart-ccf0585f-aadd-4c11-b9f3-ddb2de48286d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2419083360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2419083360 |
Directory | /workspace/13.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/13.spi_device_read_buffer_direct.3266543298 |
Short name | T539 |
Test name | |
Test status | |
Simulation time | 184537442 ps |
CPU time | 4.89 seconds |
Started | Jul 15 06:46:42 PM PDT 24 |
Finished | Jul 15 06:46:47 PM PDT 24 |
Peak memory | 223048 kb |
Host | smart-56659466-a4d6-48b9-b15d-c681815875b8 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3266543298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir ect.3266543298 |
Directory | /workspace/13.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/13.spi_device_stress_all.2420741248 |
Short name | T891 |
Test name | |
Test status | |
Simulation time | 40095086 ps |
CPU time | 0.92 seconds |
Started | Jul 15 06:46:43 PM PDT 24 |
Finished | Jul 15 06:46:44 PM PDT 24 |
Peak memory | 205592 kb |
Host | smart-7c5b55e0-2972-4cfc-8b43-455b80e52dff |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420741248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre ss_all.2420741248 |
Directory | /workspace/13.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/13.spi_device_tpm_all.3455196002 |
Short name | T866 |
Test name | |
Test status | |
Simulation time | 7066166087 ps |
CPU time | 20.06 seconds |
Started | Jul 15 06:46:36 PM PDT 24 |
Finished | Jul 15 06:46:57 PM PDT 24 |
Peak memory | 216264 kb |
Host | smart-a9c7b8ab-fca8-4b04-a586-60586c03ec3f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3455196002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3455196002 |
Directory | /workspace/13.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3078652827 |
Short name | T774 |
Test name | |
Test status | |
Simulation time | 4098698483 ps |
CPU time | 11.51 seconds |
Started | Jul 15 06:46:38 PM PDT 24 |
Finished | Jul 15 06:46:49 PM PDT 24 |
Peak memory | 216312 kb |
Host | smart-694ccfb1-c485-4181-8e96-06015822429c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3078652827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3078652827 |
Directory | /workspace/13.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/13.spi_device_tpm_rw.4212158889 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 115754687 ps |
CPU time | 1.25 seconds |
Started | Jul 15 06:46:37 PM PDT 24 |
Finished | Jul 15 06:46:38 PM PDT 24 |
Peak memory | 207876 kb |
Host | smart-a5afbb7d-a79e-4df6-851f-d1fcfb3f74ba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4212158889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.4212158889 |
Directory | /workspace/13.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/13.spi_device_tpm_sts_read.662687179 |
Short name | T579 |
Test name | |
Test status | |
Simulation time | 14219266 ps |
CPU time | 0.74 seconds |
Started | Jul 15 06:46:34 PM PDT 24 |
Finished | Jul 15 06:46:36 PM PDT 24 |
Peak memory | 205948 kb |
Host | smart-340d23e0-99b2-4fcb-b514-26a4ee776e85 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=662687179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.662687179 |
Directory | /workspace/13.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/13.spi_device_upload.918032910 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 19734127639 ps |
CPU time | 15.65 seconds |
Started | Jul 15 06:46:44 PM PDT 24 |
Finished | Jul 15 06:47:00 PM PDT 24 |
Peak memory | 232772 kb |
Host | smart-10b367c6-ee08-4294-954f-aed90d42d5c3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=918032910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.918032910 |
Directory | /workspace/13.spi_device_upload/latest |
Test location | /workspace/coverage/default/14.spi_device_alert_test.2578596199 |
Short name | T704 |
Test name | |
Test status | |
Simulation time | 25357862 ps |
CPU time | 0.75 seconds |
Started | Jul 15 06:46:55 PM PDT 24 |
Finished | Jul 15 06:46:56 PM PDT 24 |
Peak memory | 205536 kb |
Host | smart-bd12bd21-3b57-4bdb-9b4a-33b2b937e037 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578596199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test. 2578596199 |
Directory | /workspace/14.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/14.spi_device_cfg_cmd.1350898169 |
Short name | T733 |
Test name | |
Test status | |
Simulation time | 183432459 ps |
CPU time | 2.72 seconds |
Started | Jul 15 06:46:47 PM PDT 24 |
Finished | Jul 15 06:46:50 PM PDT 24 |
Peak memory | 224400 kb |
Host | smart-28b5880d-111a-45f2-8e41-b80bfa051b3d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1350898169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1350898169 |
Directory | /workspace/14.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/14.spi_device_csb_read.914761847 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 39967116 ps |
CPU time | 0.76 seconds |
Started | Jul 15 06:46:43 PM PDT 24 |
Finished | Jul 15 06:46:44 PM PDT 24 |
Peak memory | 206572 kb |
Host | smart-a0150004-a7d4-428a-b051-4f8ba51fd8eb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=914761847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.914761847 |
Directory | /workspace/14.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/14.spi_device_flash_and_tpm.2432260834 |
Short name | T923 |
Test name | |
Test status | |
Simulation time | 5631253644 ps |
CPU time | 15.23 seconds |
Started | Jul 15 06:46:48 PM PDT 24 |
Finished | Jul 15 06:47:03 PM PDT 24 |
Peak memory | 217484 kb |
Host | smart-2f3d4e96-9284-42ee-b83c-83fec7944eef |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2432260834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2432260834 |
Directory | /workspace/14.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/14.spi_device_flash_mode.448075142 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 1703092114 ps |
CPU time | 9.7 seconds |
Started | Jul 15 06:46:48 PM PDT 24 |
Finished | Jul 15 06:46:58 PM PDT 24 |
Peak memory | 232608 kb |
Host | smart-ea58f34e-475a-48aa-8a17-068fb8a0a033 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=448075142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.448075142 |
Directory | /workspace/14.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.2873246891 |
Short name | T743 |
Test name | |
Test status | |
Simulation time | 17164705085 ps |
CPU time | 151.25 seconds |
Started | Jul 15 06:46:49 PM PDT 24 |
Finished | Jul 15 06:49:20 PM PDT 24 |
Peak memory | 265032 kb |
Host | smart-c266cb4c-5e03-4071-8c97-9cbe3ea4aa8f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2873246891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd s.2873246891 |
Directory | /workspace/14.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/14.spi_device_intercept.2762410728 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 1582494251 ps |
CPU time | 7.04 seconds |
Started | Jul 15 06:46:49 PM PDT 24 |
Finished | Jul 15 06:46:56 PM PDT 24 |
Peak memory | 224384 kb |
Host | smart-66a53cf4-58f4-4640-a4a1-0e2300210cb9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2762410728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2762410728 |
Directory | /workspace/14.spi_device_intercept/latest |
Test location | /workspace/coverage/default/14.spi_device_mailbox.631795009 |
Short name | T761 |
Test name | |
Test status | |
Simulation time | 3957960144 ps |
CPU time | 33.23 seconds |
Started | Jul 15 06:46:48 PM PDT 24 |
Finished | Jul 15 06:47:22 PM PDT 24 |
Peak memory | 224512 kb |
Host | smart-acfd3dd5-9515-43a2-bb39-fde442625bef |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=631795009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.631795009 |
Directory | /workspace/14.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2359431178 |
Short name | T870 |
Test name | |
Test status | |
Simulation time | 350423356 ps |
CPU time | 4.3 seconds |
Started | Jul 15 06:46:49 PM PDT 24 |
Finished | Jul 15 06:46:53 PM PDT 24 |
Peak memory | 224368 kb |
Host | smart-46f3ee5f-c6ca-4f51-8e47-f842c4562513 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2359431178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa p.2359431178 |
Directory | /workspace/14.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2487779577 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 1765384593 ps |
CPU time | 3.38 seconds |
Started | Jul 15 06:46:47 PM PDT 24 |
Finished | Jul 15 06:46:51 PM PDT 24 |
Peak memory | 224456 kb |
Host | smart-d0172eb5-5b58-47d5-912b-df6e820c74cd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2487779577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2487779577 |
Directory | /workspace/14.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/14.spi_device_read_buffer_direct.3569096073 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 138854452 ps |
CPU time | 3.82 seconds |
Started | Jul 15 06:46:48 PM PDT 24 |
Finished | Jul 15 06:46:52 PM PDT 24 |
Peak memory | 224216 kb |
Host | smart-31b5b434-ea72-4ae8-b756-7e4eb9a06a62 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3569096073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir ect.3569096073 |
Directory | /workspace/14.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/14.spi_device_stress_all.3508215527 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 21768454320 ps |
CPU time | 80.73 seconds |
Started | Jul 15 06:46:49 PM PDT 24 |
Finished | Jul 15 06:48:11 PM PDT 24 |
Peak memory | 249232 kb |
Host | smart-d2c2b348-30ae-4d74-9d39-2f17ea066447 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508215527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre ss_all.3508215527 |
Directory | /workspace/14.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/14.spi_device_tpm_all.454867570 |
Short name | T682 |
Test name | |
Test status | |
Simulation time | 3813070022 ps |
CPU time | 33.19 seconds |
Started | Jul 15 06:46:42 PM PDT 24 |
Finished | Jul 15 06:47:15 PM PDT 24 |
Peak memory | 216272 kb |
Host | smart-c0ac0e22-fb3f-4710-9377-ead36fd7a44f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=454867570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.454867570 |
Directory | /workspace/14.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2385928161 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 761846901 ps |
CPU time | 5.91 seconds |
Started | Jul 15 06:46:41 PM PDT 24 |
Finished | Jul 15 06:46:48 PM PDT 24 |
Peak memory | 216092 kb |
Host | smart-ce65e172-92eb-47e3-9f6d-33ee06cf3890 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2385928161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2385928161 |
Directory | /workspace/14.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/14.spi_device_tpm_rw.3781079714 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 89818924 ps |
CPU time | 2.26 seconds |
Started | Jul 15 06:46:41 PM PDT 24 |
Finished | Jul 15 06:46:44 PM PDT 24 |
Peak memory | 216124 kb |
Host | smart-79a2d664-5d16-43ea-af0e-980caf51dd4c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3781079714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3781079714 |
Directory | /workspace/14.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/14.spi_device_tpm_sts_read.3195577207 |
Short name | T766 |
Test name | |
Test status | |
Simulation time | 97548150 ps |
CPU time | 0.79 seconds |
Started | Jul 15 06:46:40 PM PDT 24 |
Finished | Jul 15 06:46:41 PM PDT 24 |
Peak memory | 205920 kb |
Host | smart-52c3bc90-f1f3-4a9b-9e03-bca9293f9ac9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3195577207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3195577207 |
Directory | /workspace/14.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/14.spi_device_upload.1663885825 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 2174838509 ps |
CPU time | 10.73 seconds |
Started | Jul 15 06:46:46 PM PDT 24 |
Finished | Jul 15 06:46:57 PM PDT 24 |
Peak memory | 240784 kb |
Host | smart-7f944142-0ce0-4002-b780-8d4a954d611a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1663885825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1663885825 |
Directory | /workspace/14.spi_device_upload/latest |
Test location | /workspace/coverage/default/15.spi_device_alert_test.2953347083 |
Short name | T1011 |
Test name | |
Test status | |
Simulation time | 13771396 ps |
CPU time | 0.71 seconds |
Started | Jul 15 06:47:02 PM PDT 24 |
Finished | Jul 15 06:47:04 PM PDT 24 |
Peak memory | 204940 kb |
Host | smart-b021097f-47bd-4a5f-86b5-bbe01ceea622 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953347083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test. 2953347083 |
Directory | /workspace/15.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/15.spi_device_cfg_cmd.410899197 |
Short name | T792 |
Test name | |
Test status | |
Simulation time | 284548304 ps |
CPU time | 3.22 seconds |
Started | Jul 15 06:46:53 PM PDT 24 |
Finished | Jul 15 06:46:57 PM PDT 24 |
Peak memory | 232556 kb |
Host | smart-2b0675d9-5c22-4df9-b78a-90253639f2eb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=410899197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.410899197 |
Directory | /workspace/15.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/15.spi_device_csb_read.2515597013 |
Short name | T707 |
Test name | |
Test status | |
Simulation time | 67790102 ps |
CPU time | 0.77 seconds |
Started | Jul 15 06:46:56 PM PDT 24 |
Finished | Jul 15 06:46:58 PM PDT 24 |
Peak memory | 206888 kb |
Host | smart-a670eebc-61d7-4ecc-9f8c-1b4dfa5eb765 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2515597013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2515597013 |
Directory | /workspace/15.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/15.spi_device_flash_and_tpm.1412405661 |
Short name | T949 |
Test name | |
Test status | |
Simulation time | 84069708662 ps |
CPU time | 310.51 seconds |
Started | Jul 15 06:47:04 PM PDT 24 |
Finished | Jul 15 06:52:15 PM PDT 24 |
Peak memory | 257384 kb |
Host | smart-a02ead7c-a4bf-4fa0-909d-346595f4850b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1412405661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1412405661 |
Directory | /workspace/15.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3735102468 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 44948613347 ps |
CPU time | 377.93 seconds |
Started | Jul 15 06:46:59 PM PDT 24 |
Finished | Jul 15 06:53:18 PM PDT 24 |
Peak memory | 249196 kb |
Host | smart-04051ea7-7188-40c8-b141-bf6e400e676a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3735102468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl e.3735102468 |
Directory | /workspace/15.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/15.spi_device_flash_mode.1345594319 |
Short name | T1008 |
Test name | |
Test status | |
Simulation time | 105122428 ps |
CPU time | 3.03 seconds |
Started | Jul 15 06:46:55 PM PDT 24 |
Finished | Jul 15 06:46:59 PM PDT 24 |
Peak memory | 224384 kb |
Host | smart-370162a4-4737-46fb-9fda-64046f858a84 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1345594319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1345594319 |
Directory | /workspace/15.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/15.spi_device_intercept.3884173947 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 243171680 ps |
CPU time | 5.94 seconds |
Started | Jul 15 06:46:56 PM PDT 24 |
Finished | Jul 15 06:47:03 PM PDT 24 |
Peak memory | 229632 kb |
Host | smart-6957aa67-1b09-4fa4-93e6-8d82ebce73ec |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3884173947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3884173947 |
Directory | /workspace/15.spi_device_intercept/latest |
Test location | /workspace/coverage/default/15.spi_device_mailbox.1462344476 |
Short name | T910 |
Test name | |
Test status | |
Simulation time | 1501699292 ps |
CPU time | 7.1 seconds |
Started | Jul 15 06:46:53 PM PDT 24 |
Finished | Jul 15 06:47:01 PM PDT 24 |
Peak memory | 239552 kb |
Host | smart-ab476000-d776-43b4-a60f-d8e1f2ec12e9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1462344476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1462344476 |
Directory | /workspace/15.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1734667862 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 102721779 ps |
CPU time | 2.32 seconds |
Started | Jul 15 06:46:54 PM PDT 24 |
Finished | Jul 15 06:46:57 PM PDT 24 |
Peak memory | 224036 kb |
Host | smart-67c7e0c8-8e26-41d5-bb9f-65d9bf259486 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1734667862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa p.1734667862 |
Directory | /workspace/15.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1576515600 |
Short name | T598 |
Test name | |
Test status | |
Simulation time | 286190338 ps |
CPU time | 4.84 seconds |
Started | Jul 15 06:46:51 PM PDT 24 |
Finished | Jul 15 06:46:57 PM PDT 24 |
Peak memory | 232580 kb |
Host | smart-e4c6635c-af45-40ee-908c-52a16ac0b53e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1576515600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1576515600 |
Directory | /workspace/15.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/15.spi_device_read_buffer_direct.2981852556 |
Short name | T997 |
Test name | |
Test status | |
Simulation time | 4440815354 ps |
CPU time | 17.13 seconds |
Started | Jul 15 06:46:54 PM PDT 24 |
Finished | Jul 15 06:47:11 PM PDT 24 |
Peak memory | 219396 kb |
Host | smart-03bb66e6-659a-4b75-8e76-24c0c9dabee5 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2981852556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir ect.2981852556 |
Directory | /workspace/15.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/15.spi_device_tpm_all.3221692781 |
Short name | T813 |
Test name | |
Test status | |
Simulation time | 4075989628 ps |
CPU time | 24.03 seconds |
Started | Jul 15 06:46:55 PM PDT 24 |
Finished | Jul 15 06:47:21 PM PDT 24 |
Peak memory | 216140 kb |
Host | smart-35e68149-4b07-4f5b-b84c-76be41de5b32 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3221692781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3221692781 |
Directory | /workspace/15.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.228326587 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 1348326620 ps |
CPU time | 6.16 seconds |
Started | Jul 15 06:46:57 PM PDT 24 |
Finished | Jul 15 06:47:04 PM PDT 24 |
Peak memory | 216180 kb |
Host | smart-77695bab-dc35-44a0-9d7b-a0cbc82eeedb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=228326587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.228326587 |
Directory | /workspace/15.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/15.spi_device_tpm_rw.655894152 |
Short name | T851 |
Test name | |
Test status | |
Simulation time | 83982927 ps |
CPU time | 1.81 seconds |
Started | Jul 15 06:46:56 PM PDT 24 |
Finished | Jul 15 06:46:59 PM PDT 24 |
Peak memory | 216208 kb |
Host | smart-5fa67950-0138-4a03-b385-ecb317fef45d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=655894152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.655894152 |
Directory | /workspace/15.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/15.spi_device_tpm_sts_read.4157566156 |
Short name | T760 |
Test name | |
Test status | |
Simulation time | 49597017 ps |
CPU time | 0.77 seconds |
Started | Jul 15 06:46:55 PM PDT 24 |
Finished | Jul 15 06:46:57 PM PDT 24 |
Peak memory | 205872 kb |
Host | smart-4d5dd92f-25a2-414f-9e42-5738ee9be866 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4157566156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.4157566156 |
Directory | /workspace/15.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/15.spi_device_upload.3118074549 |
Short name | T839 |
Test name | |
Test status | |
Simulation time | 2148619431 ps |
CPU time | 8.62 seconds |
Started | Jul 15 06:46:55 PM PDT 24 |
Finished | Jul 15 06:47:05 PM PDT 24 |
Peak memory | 232644 kb |
Host | smart-9e32676c-6a10-42c7-8bad-067c043967ad |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3118074549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3118074549 |
Directory | /workspace/15.spi_device_upload/latest |
Test location | /workspace/coverage/default/16.spi_device_alert_test.3184424916 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 34999364 ps |
CPU time | 0.68 seconds |
Started | Jul 15 06:47:08 PM PDT 24 |
Finished | Jul 15 06:47:09 PM PDT 24 |
Peak memory | 205864 kb |
Host | smart-0dc5e1af-6f0b-4fbb-9745-8abca9e6c002 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184424916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test. 3184424916 |
Directory | /workspace/16.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/16.spi_device_cfg_cmd.319584780 |
Short name | T943 |
Test name | |
Test status | |
Simulation time | 249488611 ps |
CPU time | 2.33 seconds |
Started | Jul 15 06:47:00 PM PDT 24 |
Finished | Jul 15 06:47:03 PM PDT 24 |
Peak memory | 224404 kb |
Host | smart-841d7f98-8eb8-40a8-9f11-8a919a6315b6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=319584780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.319584780 |
Directory | /workspace/16.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/16.spi_device_csb_read.84491456 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 21681664 ps |
CPU time | 0.82 seconds |
Started | Jul 15 06:47:03 PM PDT 24 |
Finished | Jul 15 06:47:05 PM PDT 24 |
Peak memory | 206524 kb |
Host | smart-d8d5f333-9b2a-4eb2-8566-9b9a1e9c957c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=84491456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.84491456 |
Directory | /workspace/16.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/16.spi_device_flash_all.1208492833 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 3944238756 ps |
CPU time | 84.88 seconds |
Started | Jul 15 06:47:09 PM PDT 24 |
Finished | Jul 15 06:48:34 PM PDT 24 |
Peak memory | 266920 kb |
Host | smart-40681d17-0bd5-4320-81db-2202a2fb2fc3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1208492833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1208492833 |
Directory | /workspace/16.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/16.spi_device_flash_and_tpm.2531908834 |
Short name | T519 |
Test name | |
Test status | |
Simulation time | 1149072149 ps |
CPU time | 3.85 seconds |
Started | Jul 15 06:47:06 PM PDT 24 |
Finished | Jul 15 06:47:10 PM PDT 24 |
Peak memory | 217536 kb |
Host | smart-ac544d73-c592-43d3-a13e-fd125afdcadd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2531908834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2531908834 |
Directory | /workspace/16.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1660797818 |
Short name | T565 |
Test name | |
Test status | |
Simulation time | 3536203832 ps |
CPU time | 56.17 seconds |
Started | Jul 15 06:47:07 PM PDT 24 |
Finished | Jul 15 06:48:04 PM PDT 24 |
Peak memory | 254744 kb |
Host | smart-69fda8b8-7da6-4e65-bf72-a4b30bd1e25b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1660797818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl e.1660797818 |
Directory | /workspace/16.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/16.spi_device_flash_mode.966826397 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 321051074 ps |
CPU time | 6.73 seconds |
Started | Jul 15 06:47:01 PM PDT 24 |
Finished | Jul 15 06:47:09 PM PDT 24 |
Peak memory | 239720 kb |
Host | smart-a49551f0-6013-4edf-9e92-f82622b99bfe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=966826397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.966826397 |
Directory | /workspace/16.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/16.spi_device_intercept.2940213122 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 788776690 ps |
CPU time | 4.09 seconds |
Started | Jul 15 06:47:01 PM PDT 24 |
Finished | Jul 15 06:47:06 PM PDT 24 |
Peak memory | 232552 kb |
Host | smart-eb0a3050-823c-4b7a-9466-0f084bc6c4a1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2940213122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2940213122 |
Directory | /workspace/16.spi_device_intercept/latest |
Test location | /workspace/coverage/default/16.spi_device_mailbox.3725401179 |
Short name | T876 |
Test name | |
Test status | |
Simulation time | 1215865457 ps |
CPU time | 10.67 seconds |
Started | Jul 15 06:47:01 PM PDT 24 |
Finished | Jul 15 06:47:13 PM PDT 24 |
Peak memory | 224452 kb |
Host | smart-7fdd04e5-3966-49da-b7fc-00200a18edfd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3725401179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3725401179 |
Directory | /workspace/16.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1848719343 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 1978279439 ps |
CPU time | 6.49 seconds |
Started | Jul 15 06:47:01 PM PDT 24 |
Finished | Jul 15 06:47:08 PM PDT 24 |
Peak memory | 232556 kb |
Host | smart-0f15ee24-bb5e-43f5-9d8d-fedfea375d77 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1848719343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa p.1848719343 |
Directory | /workspace/16.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2725436516 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 430447622 ps |
CPU time | 6.17 seconds |
Started | Jul 15 06:47:01 PM PDT 24 |
Finished | Jul 15 06:47:08 PM PDT 24 |
Peak memory | 240360 kb |
Host | smart-297b8031-74c4-4d36-b2bc-e008e84c116b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2725436516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2725436516 |
Directory | /workspace/16.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/16.spi_device_read_buffer_direct.2536598961 |
Short name | T800 |
Test name | |
Test status | |
Simulation time | 2264290569 ps |
CPU time | 14.6 seconds |
Started | Jul 15 06:47:07 PM PDT 24 |
Finished | Jul 15 06:47:23 PM PDT 24 |
Peak memory | 220572 kb |
Host | smart-703db8bf-d1fa-4b04-bb8d-1f822d3cdaf0 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2536598961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir ect.2536598961 |
Directory | /workspace/16.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/16.spi_device_stress_all.2158804054 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 120169916913 ps |
CPU time | 112.73 seconds |
Started | Jul 15 06:47:08 PM PDT 24 |
Finished | Jul 15 06:49:02 PM PDT 24 |
Peak memory | 240996 kb |
Host | smart-264edac1-b1db-4e74-872b-1a126c6ac717 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158804054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre ss_all.2158804054 |
Directory | /workspace/16.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/16.spi_device_tpm_all.1443397616 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 3006592503 ps |
CPU time | 16.17 seconds |
Started | Jul 15 06:46:58 PM PDT 24 |
Finished | Jul 15 06:47:15 PM PDT 24 |
Peak memory | 216304 kb |
Host | smart-793382a3-faf4-4861-b468-dea49ddc26cb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1443397616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1443397616 |
Directory | /workspace/16.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1343926924 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 9656407570 ps |
CPU time | 16 seconds |
Started | Jul 15 06:47:00 PM PDT 24 |
Finished | Jul 15 06:47:16 PM PDT 24 |
Peak memory | 216276 kb |
Host | smart-38af1c6f-1964-4962-b11f-241080615338 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1343926924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1343926924 |
Directory | /workspace/16.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/16.spi_device_tpm_rw.3414351454 |
Short name | T794 |
Test name | |
Test status | |
Simulation time | 129410160 ps |
CPU time | 1.59 seconds |
Started | Jul 15 06:47:01 PM PDT 24 |
Finished | Jul 15 06:47:04 PM PDT 24 |
Peak memory | 216148 kb |
Host | smart-c20f8c29-f889-405c-841c-825da9329d64 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3414351454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3414351454 |
Directory | /workspace/16.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/16.spi_device_tpm_sts_read.1308714660 |
Short name | T826 |
Test name | |
Test status | |
Simulation time | 70090455 ps |
CPU time | 0.92 seconds |
Started | Jul 15 06:47:00 PM PDT 24 |
Finished | Jul 15 06:47:02 PM PDT 24 |
Peak memory | 206376 kb |
Host | smart-9e1ee738-aa44-4c2b-81d3-63c4ec98de93 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1308714660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1308714660 |
Directory | /workspace/16.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/16.spi_device_upload.748376865 |
Short name | T477 |
Test name | |
Test status | |
Simulation time | 1631956260 ps |
CPU time | 5.86 seconds |
Started | Jul 15 06:47:02 PM PDT 24 |
Finished | Jul 15 06:47:09 PM PDT 24 |
Peak memory | 224376 kb |
Host | smart-c2f749f2-3f5c-4ab4-8d14-4f138c371204 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=748376865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.748376865 |
Directory | /workspace/16.spi_device_upload/latest |
Test location | /workspace/coverage/default/17.spi_device_alert_test.3250816028 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 34452965 ps |
CPU time | 0.67 seconds |
Started | Jul 15 06:47:12 PM PDT 24 |
Finished | Jul 15 06:47:13 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-7a2f35a3-eff5-488a-b22d-0aa7a207cd4d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250816028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test. 3250816028 |
Directory | /workspace/17.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/17.spi_device_cfg_cmd.289607997 |
Short name | T897 |
Test name | |
Test status | |
Simulation time | 10707744215 ps |
CPU time | 7.02 seconds |
Started | Jul 15 06:47:13 PM PDT 24 |
Finished | Jul 15 06:47:21 PM PDT 24 |
Peak memory | 224552 kb |
Host | smart-6cec61d5-04c1-4d8f-a6c1-5e409725dc4d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=289607997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.289607997 |
Directory | /workspace/17.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/17.spi_device_csb_read.864896464 |
Short name | T751 |
Test name | |
Test status | |
Simulation time | 18407751 ps |
CPU time | 0.8 seconds |
Started | Jul 15 06:47:04 PM PDT 24 |
Finished | Jul 15 06:47:06 PM PDT 24 |
Peak memory | 206484 kb |
Host | smart-f027c459-f6e4-4ca2-9151-53ce7bc64a54 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=864896464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.864896464 |
Directory | /workspace/17.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/17.spi_device_flash_all.371985950 |
Short name | T576 |
Test name | |
Test status | |
Simulation time | 4774862593 ps |
CPU time | 53.07 seconds |
Started | Jul 15 06:47:15 PM PDT 24 |
Finished | Jul 15 06:48:08 PM PDT 24 |
Peak memory | 250748 kb |
Host | smart-6822532a-f900-48eb-bd94-53c85e91abcb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=371985950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.371985950 |
Directory | /workspace/17.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/17.spi_device_flash_and_tpm.1239898775 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 4301811973 ps |
CPU time | 82.03 seconds |
Started | Jul 15 06:47:15 PM PDT 24 |
Finished | Jul 15 06:48:38 PM PDT 24 |
Peak memory | 272980 kb |
Host | smart-c7b76cbd-07ff-4d6f-b120-c408803494ef |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1239898775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1239898775 |
Directory | /workspace/17.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1040089801 |
Short name | T589 |
Test name | |
Test status | |
Simulation time | 11584809547 ps |
CPU time | 34.99 seconds |
Started | Jul 15 06:47:16 PM PDT 24 |
Finished | Jul 15 06:47:52 PM PDT 24 |
Peak memory | 222820 kb |
Host | smart-422fef3a-31db-4fab-9d6f-0be1ee7d769e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1040089801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl e.1040089801 |
Directory | /workspace/17.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/17.spi_device_flash_mode.1432619531 |
Short name | T737 |
Test name | |
Test status | |
Simulation time | 916909497 ps |
CPU time | 20.12 seconds |
Started | Jul 15 06:47:13 PM PDT 24 |
Finished | Jul 15 06:47:34 PM PDT 24 |
Peak memory | 251844 kb |
Host | smart-9d36e7b7-b0df-47e0-ab88-422c3f08508a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1432619531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1432619531 |
Directory | /workspace/17.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.2621982328 |
Short name | T814 |
Test name | |
Test status | |
Simulation time | 7878942372 ps |
CPU time | 54.77 seconds |
Started | Jul 15 06:47:14 PM PDT 24 |
Finished | Jul 15 06:48:09 PM PDT 24 |
Peak memory | 256032 kb |
Host | smart-3e511bf9-fef6-4710-bb83-a070bfb504dd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2621982328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd s.2621982328 |
Directory | /workspace/17.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/17.spi_device_intercept.3341329135 |
Short name | T797 |
Test name | |
Test status | |
Simulation time | 2789956904 ps |
CPU time | 13.71 seconds |
Started | Jul 15 06:47:16 PM PDT 24 |
Finished | Jul 15 06:47:30 PM PDT 24 |
Peak memory | 232716 kb |
Host | smart-419ae5f3-422c-4815-bbd9-6beac932b2ba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3341329135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3341329135 |
Directory | /workspace/17.spi_device_intercept/latest |
Test location | /workspace/coverage/default/17.spi_device_mailbox.600589430 |
Short name | T719 |
Test name | |
Test status | |
Simulation time | 56084085414 ps |
CPU time | 67.29 seconds |
Started | Jul 15 06:47:13 PM PDT 24 |
Finished | Jul 15 06:48:21 PM PDT 24 |
Peak memory | 232772 kb |
Host | smart-df99723c-8393-409c-a847-efcea51dfa26 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=600589430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.600589430 |
Directory | /workspace/17.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1832508033 |
Short name | T845 |
Test name | |
Test status | |
Simulation time | 2270099159 ps |
CPU time | 3.49 seconds |
Started | Jul 15 06:47:08 PM PDT 24 |
Finished | Jul 15 06:47:12 PM PDT 24 |
Peak memory | 232640 kb |
Host | smart-b5c91060-1eaa-4dbc-9b0f-e2de83a6b9c3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1832508033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa p.1832508033 |
Directory | /workspace/17.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1192824543 |
Short name | T781 |
Test name | |
Test status | |
Simulation time | 344649953 ps |
CPU time | 2.25 seconds |
Started | Jul 15 06:47:07 PM PDT 24 |
Finished | Jul 15 06:47:11 PM PDT 24 |
Peak memory | 223736 kb |
Host | smart-3770664f-3542-4f6b-8b8a-95bf7f243f3a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1192824543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1192824543 |
Directory | /workspace/17.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/17.spi_device_read_buffer_direct.893522533 |
Short name | T569 |
Test name | |
Test status | |
Simulation time | 681277980 ps |
CPU time | 3.93 seconds |
Started | Jul 15 06:47:13 PM PDT 24 |
Finished | Jul 15 06:47:18 PM PDT 24 |
Peak memory | 220508 kb |
Host | smart-b7efe375-6ab1-472a-98aa-f157deff18b4 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=893522533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire ct.893522533 |
Directory | /workspace/17.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/17.spi_device_stress_all.433510211 |
Short name | T830 |
Test name | |
Test status | |
Simulation time | 6979473585 ps |
CPU time | 39.19 seconds |
Started | Jul 15 06:47:13 PM PDT 24 |
Finished | Jul 15 06:47:53 PM PDT 24 |
Peak memory | 253756 kb |
Host | smart-24c4d655-19a8-4e9a-9964-2f511aecbec8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433510211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres s_all.433510211 |
Directory | /workspace/17.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/17.spi_device_tpm_all.1207619755 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 8136500850 ps |
CPU time | 48.52 seconds |
Started | Jul 15 06:47:07 PM PDT 24 |
Finished | Jul 15 06:47:57 PM PDT 24 |
Peak memory | 221148 kb |
Host | smart-03fae9e2-5e21-4442-baaa-66706b4dafcb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1207619755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1207619755 |
Directory | /workspace/17.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3605085169 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 4403057878 ps |
CPU time | 14.78 seconds |
Started | Jul 15 06:47:06 PM PDT 24 |
Finished | Jul 15 06:47:22 PM PDT 24 |
Peak memory | 216256 kb |
Host | smart-331948a4-0bb3-453f-9271-5367f7a69a56 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3605085169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3605085169 |
Directory | /workspace/17.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/17.spi_device_tpm_rw.2061193340 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 27049941 ps |
CPU time | 1.39 seconds |
Started | Jul 15 06:47:08 PM PDT 24 |
Finished | Jul 15 06:47:10 PM PDT 24 |
Peak memory | 216160 kb |
Host | smart-356f285f-fba0-4265-ae40-9ab69eb6b050 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2061193340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2061193340 |
Directory | /workspace/17.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/17.spi_device_tpm_sts_read.2997320278 |
Short name | T749 |
Test name | |
Test status | |
Simulation time | 38368175 ps |
CPU time | 0.84 seconds |
Started | Jul 15 06:47:09 PM PDT 24 |
Finished | Jul 15 06:47:11 PM PDT 24 |
Peak memory | 205880 kb |
Host | smart-aa8812c2-5a40-4f6e-8258-c0a288d40659 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2997320278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2997320278 |
Directory | /workspace/17.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/17.spi_device_upload.1372810831 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 1630164590 ps |
CPU time | 13.13 seconds |
Started | Jul 15 06:47:13 PM PDT 24 |
Finished | Jul 15 06:47:26 PM PDT 24 |
Peak memory | 232644 kb |
Host | smart-93b0ca30-4a50-4a0e-b061-5fab670619e1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1372810831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1372810831 |
Directory | /workspace/17.spi_device_upload/latest |
Test location | /workspace/coverage/default/18.spi_device_alert_test.4037592781 |
Short name | T862 |
Test name | |
Test status | |
Simulation time | 13636144 ps |
CPU time | 0.71 seconds |
Started | Jul 15 06:47:31 PM PDT 24 |
Finished | Jul 15 06:47:32 PM PDT 24 |
Peak memory | 205764 kb |
Host | smart-535abb05-c8f3-4ed6-9860-7d8b2f99d496 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037592781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test. 4037592781 |
Directory | /workspace/18.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/18.spi_device_cfg_cmd.4087621644 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 2255859955 ps |
CPU time | 3.71 seconds |
Started | Jul 15 06:47:24 PM PDT 24 |
Finished | Jul 15 06:47:28 PM PDT 24 |
Peak memory | 232624 kb |
Host | smart-d9167db6-68af-4971-86ac-fa6c130e5ee4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4087621644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.4087621644 |
Directory | /workspace/18.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/18.spi_device_csb_read.3512509632 |
Short name | T475 |
Test name | |
Test status | |
Simulation time | 43554164 ps |
CPU time | 0.75 seconds |
Started | Jul 15 06:47:14 PM PDT 24 |
Finished | Jul 15 06:47:15 PM PDT 24 |
Peak memory | 205520 kb |
Host | smart-86116b5b-46b1-4417-88e8-c482fd807170 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3512509632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3512509632 |
Directory | /workspace/18.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/18.spi_device_flash_and_tpm.1517331694 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 13084227121 ps |
CPU time | 137.93 seconds |
Started | Jul 15 06:47:28 PM PDT 24 |
Finished | Jul 15 06:49:47 PM PDT 24 |
Peak memory | 265448 kb |
Host | smart-4c2fdb38-6c70-470b-8403-c268d3a7abb8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1517331694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1517331694 |
Directory | /workspace/18.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.4032176515 |
Short name | T564 |
Test name | |
Test status | |
Simulation time | 335293508558 ps |
CPU time | 343.62 seconds |
Started | Jul 15 06:47:28 PM PDT 24 |
Finished | Jul 15 06:53:12 PM PDT 24 |
Peak memory | 255556 kb |
Host | smart-e2a8205e-b36f-4b28-a693-d2fe1e77e8c2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4032176515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl e.4032176515 |
Directory | /workspace/18.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.3266930923 |
Short name | T725 |
Test name | |
Test status | |
Simulation time | 20318482976 ps |
CPU time | 94.72 seconds |
Started | Jul 15 06:47:22 PM PDT 24 |
Finished | Jul 15 06:48:57 PM PDT 24 |
Peak memory | 249136 kb |
Host | smart-84e082c5-937c-4a96-9124-2e73b2e7f23c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3266930923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd s.3266930923 |
Directory | /workspace/18.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/18.spi_device_intercept.630821710 |
Short name | T917 |
Test name | |
Test status | |
Simulation time | 1520091332 ps |
CPU time | 14.4 seconds |
Started | Jul 15 06:47:24 PM PDT 24 |
Finished | Jul 15 06:47:39 PM PDT 24 |
Peak memory | 232616 kb |
Host | smart-bbf0c2b7-3456-4cd5-8915-2cfad44903fe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=630821710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.630821710 |
Directory | /workspace/18.spi_device_intercept/latest |
Test location | /workspace/coverage/default/18.spi_device_mailbox.1511836796 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 8800298975 ps |
CPU time | 89 seconds |
Started | Jul 15 06:47:23 PM PDT 24 |
Finished | Jul 15 06:48:52 PM PDT 24 |
Peak memory | 232768 kb |
Host | smart-7e610c8e-fd35-4564-b738-78ce328f95a3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1511836796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1511836796 |
Directory | /workspace/18.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.488119457 |
Short name | T983 |
Test name | |
Test status | |
Simulation time | 54288463254 ps |
CPU time | 20.79 seconds |
Started | Jul 15 06:47:23 PM PDT 24 |
Finished | Jul 15 06:47:44 PM PDT 24 |
Peak memory | 232672 kb |
Host | smart-d1b669d5-efd5-473c-96ad-22bdcd3ca31b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=488119457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap .488119457 |
Directory | /workspace/18.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3049210093 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 10633281509 ps |
CPU time | 9.83 seconds |
Started | Jul 15 06:47:23 PM PDT 24 |
Finished | Jul 15 06:47:33 PM PDT 24 |
Peak memory | 232708 kb |
Host | smart-d19f582a-2708-46e9-bd34-54a255a8ac1d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3049210093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3049210093 |
Directory | /workspace/18.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/18.spi_device_read_buffer_direct.2499183129 |
Short name | T687 |
Test name | |
Test status | |
Simulation time | 107385462 ps |
CPU time | 4.79 seconds |
Started | Jul 15 06:47:21 PM PDT 24 |
Finished | Jul 15 06:47:26 PM PDT 24 |
Peak memory | 219180 kb |
Host | smart-0f300125-7082-4021-8e39-397103ef4d56 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2499183129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir ect.2499183129 |
Directory | /workspace/18.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/18.spi_device_tpm_all.1326093806 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 62228361413 ps |
CPU time | 55.22 seconds |
Started | Jul 15 06:47:25 PM PDT 24 |
Finished | Jul 15 06:48:20 PM PDT 24 |
Peak memory | 216348 kb |
Host | smart-eef00219-3162-4ae7-ab7e-a3298051bfaa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1326093806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1326093806 |
Directory | /workspace/18.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.4241627560 |
Short name | T838 |
Test name | |
Test status | |
Simulation time | 10463096111 ps |
CPU time | 7.59 seconds |
Started | Jul 15 06:47:23 PM PDT 24 |
Finished | Jul 15 06:47:31 PM PDT 24 |
Peak memory | 216232 kb |
Host | smart-8739ccc3-344c-4c6c-a3c3-9e7a7bc87cf2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4241627560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.4241627560 |
Directory | /workspace/18.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/18.spi_device_tpm_rw.4005207027 |
Short name | T627 |
Test name | |
Test status | |
Simulation time | 103911847 ps |
CPU time | 0.7 seconds |
Started | Jul 15 06:47:23 PM PDT 24 |
Finished | Jul 15 06:47:24 PM PDT 24 |
Peak memory | 205556 kb |
Host | smart-38e11442-b95b-45c1-9466-df2fc9671644 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4005207027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.4005207027 |
Directory | /workspace/18.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/18.spi_device_tpm_sts_read.1801465305 |
Short name | T533 |
Test name | |
Test status | |
Simulation time | 24150243 ps |
CPU time | 0.75 seconds |
Started | Jul 15 06:47:19 PM PDT 24 |
Finished | Jul 15 06:47:20 PM PDT 24 |
Peak memory | 205964 kb |
Host | smart-18c30675-5605-47a5-a915-6791e5f98956 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1801465305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1801465305 |
Directory | /workspace/18.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/18.spi_device_upload.3253026531 |
Short name | T567 |
Test name | |
Test status | |
Simulation time | 153552264 ps |
CPU time | 2.21 seconds |
Started | Jul 15 06:47:21 PM PDT 24 |
Finished | Jul 15 06:47:24 PM PDT 24 |
Peak memory | 224364 kb |
Host | smart-23b90558-f1cd-4a08-aa81-4eeeb766f81c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3253026531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3253026531 |
Directory | /workspace/18.spi_device_upload/latest |
Test location | /workspace/coverage/default/19.spi_device_alert_test.3609571643 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 12286247 ps |
CPU time | 0.7 seconds |
Started | Jul 15 06:47:36 PM PDT 24 |
Finished | Jul 15 06:47:37 PM PDT 24 |
Peak memory | 204924 kb |
Host | smart-76f30da6-1cf6-46d9-9c78-30c753e09beb |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609571643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test. 3609571643 |
Directory | /workspace/19.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/19.spi_device_cfg_cmd.2037741633 |
Short name | T529 |
Test name | |
Test status | |
Simulation time | 289409751 ps |
CPU time | 6.26 seconds |
Started | Jul 15 06:47:36 PM PDT 24 |
Finished | Jul 15 06:47:44 PM PDT 24 |
Peak memory | 232596 kb |
Host | smart-a189673c-ac20-46c7-92c6-4736e8db2313 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2037741633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2037741633 |
Directory | /workspace/19.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/19.spi_device_csb_read.969883537 |
Short name | T543 |
Test name | |
Test status | |
Simulation time | 29860642 ps |
CPU time | 0.77 seconds |
Started | Jul 15 06:47:29 PM PDT 24 |
Finished | Jul 15 06:47:31 PM PDT 24 |
Peak memory | 205560 kb |
Host | smart-2e58f60f-727e-475e-8efd-d7d77d7a46fd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=969883537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.969883537 |
Directory | /workspace/19.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/19.spi_device_flash_all.1219820012 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 2371426051 ps |
CPU time | 33.15 seconds |
Started | Jul 15 06:47:35 PM PDT 24 |
Finished | Jul 15 06:48:09 PM PDT 24 |
Peak memory | 252344 kb |
Host | smart-563c5dbb-5163-4a3f-8cda-a97882f9b521 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1219820012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1219820012 |
Directory | /workspace/19.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/19.spi_device_flash_and_tpm.3534145174 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 36141846664 ps |
CPU time | 239.86 seconds |
Started | Jul 15 06:47:35 PM PDT 24 |
Finished | Jul 15 06:51:35 PM PDT 24 |
Peak memory | 250596 kb |
Host | smart-f0f7ae22-e7d8-4c70-a3d6-f8dc483f76b6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3534145174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3534145174 |
Directory | /workspace/19.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.674724289 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 10475550635 ps |
CPU time | 175.98 seconds |
Started | Jul 15 06:47:40 PM PDT 24 |
Finished | Jul 15 06:50:37 PM PDT 24 |
Peak memory | 265212 kb |
Host | smart-a3951cd6-75dc-42e1-8717-6eb90cc69c9c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=674724289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle .674724289 |
Directory | /workspace/19.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/19.spi_device_flash_mode.2515718817 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 550184916 ps |
CPU time | 6.16 seconds |
Started | Jul 15 06:47:36 PM PDT 24 |
Finished | Jul 15 06:47:43 PM PDT 24 |
Peak memory | 224364 kb |
Host | smart-b3b158e7-3fe7-49a0-beca-342bf71ff33d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2515718817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2515718817 |
Directory | /workspace/19.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.3062013457 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 19532347298 ps |
CPU time | 129.99 seconds |
Started | Jul 15 06:47:35 PM PDT 24 |
Finished | Jul 15 06:49:46 PM PDT 24 |
Peak memory | 255084 kb |
Host | smart-6498331f-b711-40f9-bb09-ffa6540c3323 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3062013457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd s.3062013457 |
Directory | /workspace/19.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/19.spi_device_intercept.123506805 |
Short name | T968 |
Test name | |
Test status | |
Simulation time | 108048665 ps |
CPU time | 2.43 seconds |
Started | Jul 15 06:47:27 PM PDT 24 |
Finished | Jul 15 06:47:30 PM PDT 24 |
Peak memory | 222836 kb |
Host | smart-9b4b5187-9598-4760-888a-0ae023a6a2e2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=123506805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.123506805 |
Directory | /workspace/19.spi_device_intercept/latest |
Test location | /workspace/coverage/default/19.spi_device_mailbox.1874856933 |
Short name | T775 |
Test name | |
Test status | |
Simulation time | 3176925425 ps |
CPU time | 11.58 seconds |
Started | Jul 15 06:47:39 PM PDT 24 |
Finished | Jul 15 06:47:51 PM PDT 24 |
Peak memory | 224632 kb |
Host | smart-63d4e88c-728d-4601-9334-6461ea25bcb5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1874856933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1874856933 |
Directory | /workspace/19.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2338404690 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 9828823290 ps |
CPU time | 9.42 seconds |
Started | Jul 15 06:47:29 PM PDT 24 |
Finished | Jul 15 06:47:39 PM PDT 24 |
Peak memory | 232680 kb |
Host | smart-d851d611-0e6c-4a15-a87d-f3a611981f61 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2338404690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa p.2338404690 |
Directory | /workspace/19.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3687295588 |
Short name | T819 |
Test name | |
Test status | |
Simulation time | 13752441294 ps |
CPU time | 12.06 seconds |
Started | Jul 15 06:47:30 PM PDT 24 |
Finished | Jul 15 06:47:42 PM PDT 24 |
Peak memory | 232744 kb |
Host | smart-f7cffd7a-f668-44de-ac89-d09406e7eb00 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3687295588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3687295588 |
Directory | /workspace/19.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/19.spi_device_read_buffer_direct.2220633967 |
Short name | T841 |
Test name | |
Test status | |
Simulation time | 1062539148 ps |
CPU time | 9.78 seconds |
Started | Jul 15 06:47:33 PM PDT 24 |
Finished | Jul 15 06:47:43 PM PDT 24 |
Peak memory | 221944 kb |
Host | smart-e7dd4c0a-623e-4958-8356-b5cef4d5fc1c |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2220633967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir ect.2220633967 |
Directory | /workspace/19.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/19.spi_device_stress_all.3406415807 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 72849481739 ps |
CPU time | 250.99 seconds |
Started | Jul 15 06:47:33 PM PDT 24 |
Finished | Jul 15 06:51:45 PM PDT 24 |
Peak memory | 254200 kb |
Host | smart-e507898a-9b3a-456b-872c-40b8199143e1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406415807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre ss_all.3406415807 |
Directory | /workspace/19.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/19.spi_device_tpm_all.535644126 |
Short name | T496 |
Test name | |
Test status | |
Simulation time | 5993139155 ps |
CPU time | 33.83 seconds |
Started | Jul 15 06:47:26 PM PDT 24 |
Finished | Jul 15 06:48:00 PM PDT 24 |
Peak memory | 217540 kb |
Host | smart-ff93eaaa-b46d-4e60-a247-3be70f2b639c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=535644126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.535644126 |
Directory | /workspace/19.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1145011565 |
Short name | T788 |
Test name | |
Test status | |
Simulation time | 4446513240 ps |
CPU time | 7.15 seconds |
Started | Jul 15 06:47:31 PM PDT 24 |
Finished | Jul 15 06:47:38 PM PDT 24 |
Peak memory | 216164 kb |
Host | smart-0d75aa08-47bc-485f-a3af-fbda4cb52947 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1145011565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1145011565 |
Directory | /workspace/19.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/19.spi_device_tpm_rw.2630501538 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 106161478 ps |
CPU time | 2.97 seconds |
Started | Jul 15 06:47:31 PM PDT 24 |
Finished | Jul 15 06:47:35 PM PDT 24 |
Peak memory | 216144 kb |
Host | smart-00fdabec-b5ac-4107-91d2-1c046579c51d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2630501538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2630501538 |
Directory | /workspace/19.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/19.spi_device_tpm_sts_read.3307060430 |
Short name | T803 |
Test name | |
Test status | |
Simulation time | 70161943 ps |
CPU time | 0.75 seconds |
Started | Jul 15 06:47:29 PM PDT 24 |
Finished | Jul 15 06:47:30 PM PDT 24 |
Peak memory | 205908 kb |
Host | smart-f5fc2a87-da8e-45bc-8546-3b56e4c2e19b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3307060430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3307060430 |
Directory | /workspace/19.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/19.spi_device_upload.2329135112 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 5489147900 ps |
CPU time | 5.52 seconds |
Started | Jul 15 06:47:36 PM PDT 24 |
Finished | Jul 15 06:47:43 PM PDT 24 |
Peak memory | 224504 kb |
Host | smart-057b7bb1-575a-478f-85f6-0e7a5e68c414 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2329135112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2329135112 |
Directory | /workspace/19.spi_device_upload/latest |
Test location | /workspace/coverage/default/2.spi_device_alert_test.593542041 |
Short name | T615 |
Test name | |
Test status | |
Simulation time | 11758551 ps |
CPU time | 0.74 seconds |
Started | Jul 15 06:45:03 PM PDT 24 |
Finished | Jul 15 06:45:04 PM PDT 24 |
Peak memory | 205664 kb |
Host | smart-89d64f61-535b-4aec-aa51-05d8b4968c80 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593542041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.593542041 |
Directory | /workspace/2.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/2.spi_device_cfg_cmd.1852383779 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 1038446034 ps |
CPU time | 4.83 seconds |
Started | Jul 15 06:44:55 PM PDT 24 |
Finished | Jul 15 06:45:01 PM PDT 24 |
Peak memory | 224432 kb |
Host | smart-c37b7bca-b7f2-4e06-b82a-fea28fa44080 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1852383779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1852383779 |
Directory | /workspace/2.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/2.spi_device_csb_read.1706133511 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 17021255 ps |
CPU time | 0.82 seconds |
Started | Jul 15 06:44:53 PM PDT 24 |
Finished | Jul 15 06:44:55 PM PDT 24 |
Peak memory | 206564 kb |
Host | smart-0298230d-ecee-4347-9cfc-f49362baf14f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1706133511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1706133511 |
Directory | /workspace/2.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/2.spi_device_flash_all.2211638994 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 5401871666 ps |
CPU time | 54.99 seconds |
Started | Jul 15 06:45:04 PM PDT 24 |
Finished | Jul 15 06:46:00 PM PDT 24 |
Peak memory | 254476 kb |
Host | smart-227e9109-8d9c-4b67-ba9f-b74d06e73dde |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2211638994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2211638994 |
Directory | /workspace/2.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/2.spi_device_flash_and_tpm.2807228501 |
Short name | T515 |
Test name | |
Test status | |
Simulation time | 97854239849 ps |
CPU time | 261.33 seconds |
Started | Jul 15 06:45:03 PM PDT 24 |
Finished | Jul 15 06:49:25 PM PDT 24 |
Peak memory | 265616 kb |
Host | smart-606b67a2-98ed-40fd-8f67-1be75ee32c99 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2807228501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2807228501 |
Directory | /workspace/2.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2767610099 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 24084009361 ps |
CPU time | 83.1 seconds |
Started | Jul 15 06:45:01 PM PDT 24 |
Finished | Jul 15 06:46:25 PM PDT 24 |
Peak memory | 249912 kb |
Host | smart-dc23aaf7-b2c7-4589-af88-7ae4d43d5e4f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2767610099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle .2767610099 |
Directory | /workspace/2.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/2.spi_device_flash_mode.4205150481 |
Short name | T867 |
Test name | |
Test status | |
Simulation time | 180248748 ps |
CPU time | 5.49 seconds |
Started | Jul 15 06:44:52 PM PDT 24 |
Finished | Jul 15 06:44:58 PM PDT 24 |
Peak memory | 233704 kb |
Host | smart-a41c587f-a564-4d75-a281-b16acefb0faf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4205150481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.4205150481 |
Directory | /workspace/2.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/2.spi_device_intercept.2268488747 |
Short name | T739 |
Test name | |
Test status | |
Simulation time | 727448034 ps |
CPU time | 10.29 seconds |
Started | Jul 15 06:44:51 PM PDT 24 |
Finished | Jul 15 06:45:01 PM PDT 24 |
Peak memory | 224400 kb |
Host | smart-921a9ea1-2e60-4f19-8a85-c5d51b8a2c38 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2268488747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2268488747 |
Directory | /workspace/2.spi_device_intercept/latest |
Test location | /workspace/coverage/default/2.spi_device_mailbox.3606935497 |
Short name | T741 |
Test name | |
Test status | |
Simulation time | 21651189197 ps |
CPU time | 88.16 seconds |
Started | Jul 15 06:44:52 PM PDT 24 |
Finished | Jul 15 06:46:21 PM PDT 24 |
Peak memory | 249964 kb |
Host | smart-aa20c109-0c2b-4462-83ad-f3a68cec38f5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3606935497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3606935497 |
Directory | /workspace/2.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2601780883 |
Short name | T592 |
Test name | |
Test status | |
Simulation time | 3133667947 ps |
CPU time | 8.88 seconds |
Started | Jul 15 06:44:50 PM PDT 24 |
Finished | Jul 15 06:44:59 PM PDT 24 |
Peak memory | 232696 kb |
Host | smart-80ea72b8-6d57-408d-b043-1ddab01f7036 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2601780883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap .2601780883 |
Directory | /workspace/2.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/2.spi_device_pass_cmd_filtering.258098303 |
Short name | T512 |
Test name | |
Test status | |
Simulation time | 2591976081 ps |
CPU time | 3.84 seconds |
Started | Jul 15 06:44:53 PM PDT 24 |
Finished | Jul 15 06:44:58 PM PDT 24 |
Peak memory | 224432 kb |
Host | smart-7b6b4c2f-c3a3-40c8-9bd2-774acfed53de |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=258098303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.258098303 |
Directory | /workspace/2.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/2.spi_device_read_buffer_direct.555539410 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 1045204000 ps |
CPU time | 12.56 seconds |
Started | Jul 15 06:45:03 PM PDT 24 |
Finished | Jul 15 06:45:17 PM PDT 24 |
Peak memory | 221996 kb |
Host | smart-b5a12207-080f-45c6-90cd-fb3f8a204938 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=555539410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc t.555539410 |
Directory | /workspace/2.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/2.spi_device_sec_cm.577570866 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 54355957 ps |
CPU time | 0.98 seconds |
Started | Jul 15 06:45:03 PM PDT 24 |
Finished | Jul 15 06:45:04 PM PDT 24 |
Peak memory | 236508 kb |
Host | smart-e192d661-dcc2-4e88-bdc7-157b8f870a06 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577570866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.577570866 |
Directory | /workspace/2.spi_device_sec_cm/latest |
Test location | /workspace/coverage/default/2.spi_device_stress_all.685821369 |
Short name | T911 |
Test name | |
Test status | |
Simulation time | 56060593518 ps |
CPU time | 186.44 seconds |
Started | Jul 15 06:45:01 PM PDT 24 |
Finished | Jul 15 06:48:08 PM PDT 24 |
Peak memory | 265552 kb |
Host | smart-052af47e-a08b-4ec4-b102-18d35713aab1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685821369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress _all.685821369 |
Directory | /workspace/2.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/2.spi_device_tpm_all.983027763 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 1714675210 ps |
CPU time | 3.03 seconds |
Started | Jul 15 06:44:50 PM PDT 24 |
Finished | Jul 15 06:44:53 PM PDT 24 |
Peak memory | 216220 kb |
Host | smart-0f9a3f57-7c21-4ec8-980e-8f960f26562e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=983027763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.983027763 |
Directory | /workspace/2.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1212525495 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 9783308189 ps |
CPU time | 28.83 seconds |
Started | Jul 15 06:44:51 PM PDT 24 |
Finished | Jul 15 06:45:20 PM PDT 24 |
Peak memory | 216256 kb |
Host | smart-3ad999ca-f6fc-4693-9bf8-efca9110a9b9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1212525495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1212525495 |
Directory | /workspace/2.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/2.spi_device_tpm_rw.1746152218 |
Short name | T546 |
Test name | |
Test status | |
Simulation time | 103627899 ps |
CPU time | 0.9 seconds |
Started | Jul 15 06:44:49 PM PDT 24 |
Finished | Jul 15 06:44:50 PM PDT 24 |
Peak memory | 205904 kb |
Host | smart-d1d39d0b-bf18-47d6-9d93-1ef7a1a660a3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1746152218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1746152218 |
Directory | /workspace/2.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/2.spi_device_tpm_sts_read.2854827483 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 60585894 ps |
CPU time | 0.78 seconds |
Started | Jul 15 06:44:50 PM PDT 24 |
Finished | Jul 15 06:44:51 PM PDT 24 |
Peak memory | 205956 kb |
Host | smart-6d3827e1-d0eb-44bb-862f-4fd62d5f43b6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2854827483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2854827483 |
Directory | /workspace/2.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/2.spi_device_upload.3400735330 |
Short name | T880 |
Test name | |
Test status | |
Simulation time | 26169651113 ps |
CPU time | 10.65 seconds |
Started | Jul 15 06:44:52 PM PDT 24 |
Finished | Jul 15 06:45:03 PM PDT 24 |
Peak memory | 232748 kb |
Host | smart-86a9eaaa-9dc5-4033-8d97-343f870448ee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3400735330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3400735330 |
Directory | /workspace/2.spi_device_upload/latest |
Test location | /workspace/coverage/default/20.spi_device_alert_test.1990352726 |
Short name | T553 |
Test name | |
Test status | |
Simulation time | 80836100 ps |
CPU time | 0.7 seconds |
Started | Jul 15 06:47:44 PM PDT 24 |
Finished | Jul 15 06:47:45 PM PDT 24 |
Peak memory | 205488 kb |
Host | smart-e85ed53b-9091-4fac-98ef-627f24762afd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990352726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test. 1990352726 |
Directory | /workspace/20.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/20.spi_device_cfg_cmd.3642934237 |
Short name | T514 |
Test name | |
Test status | |
Simulation time | 140521548 ps |
CPU time | 2.73 seconds |
Started | Jul 15 06:47:40 PM PDT 24 |
Finished | Jul 15 06:47:43 PM PDT 24 |
Peak memory | 224280 kb |
Host | smart-c18d58e7-c99e-4617-9335-c574cbe8a142 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3642934237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3642934237 |
Directory | /workspace/20.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/20.spi_device_csb_read.3445018654 |
Short name | T793 |
Test name | |
Test status | |
Simulation time | 32124472 ps |
CPU time | 0.79 seconds |
Started | Jul 15 06:47:33 PM PDT 24 |
Finished | Jul 15 06:47:34 PM PDT 24 |
Peak memory | 206528 kb |
Host | smart-8370f7e3-8989-415a-b99f-c96227a163f0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3445018654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3445018654 |
Directory | /workspace/20.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/20.spi_device_flash_and_tpm.3121758881 |
Short name | T673 |
Test name | |
Test status | |
Simulation time | 17519749557 ps |
CPU time | 191.3 seconds |
Started | Jul 15 06:47:40 PM PDT 24 |
Finished | Jul 15 06:50:52 PM PDT 24 |
Peak memory | 254440 kb |
Host | smart-6052ca9c-5314-40d9-8f03-01cf00681f38 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3121758881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3121758881 |
Directory | /workspace/20.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.4011564631 |
Short name | T491 |
Test name | |
Test status | |
Simulation time | 18533842998 ps |
CPU time | 59.71 seconds |
Started | Jul 15 06:47:42 PM PDT 24 |
Finished | Jul 15 06:48:43 PM PDT 24 |
Peak memory | 257332 kb |
Host | smart-0298eee5-7827-444c-9bef-efd240767e49 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4011564631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd s.4011564631 |
Directory | /workspace/20.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/20.spi_device_intercept.956709195 |
Short name | T742 |
Test name | |
Test status | |
Simulation time | 4958223667 ps |
CPU time | 12.96 seconds |
Started | Jul 15 06:47:38 PM PDT 24 |
Finished | Jul 15 06:47:51 PM PDT 24 |
Peak memory | 232792 kb |
Host | smart-bdac9be7-6bc8-452c-acc0-50473de83433 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=956709195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.956709195 |
Directory | /workspace/20.spi_device_intercept/latest |
Test location | /workspace/coverage/default/20.spi_device_mailbox.967084944 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 122248387 ps |
CPU time | 2.64 seconds |
Started | Jul 15 06:47:36 PM PDT 24 |
Finished | Jul 15 06:47:40 PM PDT 24 |
Peak memory | 232268 kb |
Host | smart-4a452bdc-1f39-4c09-9c51-d8d48a3a083d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=967084944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.967084944 |
Directory | /workspace/20.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2257253171 |
Short name | T474 |
Test name | |
Test status | |
Simulation time | 5112439808 ps |
CPU time | 10.19 seconds |
Started | Jul 15 06:47:35 PM PDT 24 |
Finished | Jul 15 06:47:47 PM PDT 24 |
Peak memory | 232704 kb |
Host | smart-d0fb550b-210a-478c-8f02-3aaabc4d7a31 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2257253171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa p.2257253171 |
Directory | /workspace/20.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1799900391 |
Short name | T610 |
Test name | |
Test status | |
Simulation time | 1109182657 ps |
CPU time | 7.4 seconds |
Started | Jul 15 06:47:36 PM PDT 24 |
Finished | Jul 15 06:47:44 PM PDT 24 |
Peak memory | 232648 kb |
Host | smart-c901d057-4285-45a9-aed6-68a846ba467f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1799900391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1799900391 |
Directory | /workspace/20.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/20.spi_device_read_buffer_direct.3937618655 |
Short name | T651 |
Test name | |
Test status | |
Simulation time | 774428945 ps |
CPU time | 5.65 seconds |
Started | Jul 15 06:47:43 PM PDT 24 |
Finished | Jul 15 06:47:49 PM PDT 24 |
Peak memory | 223028 kb |
Host | smart-4f045016-7033-4356-ab8e-90a21f8f58f4 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3937618655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir ect.3937618655 |
Directory | /workspace/20.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/20.spi_device_stress_all.882046894 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 10091407249 ps |
CPU time | 62.21 seconds |
Started | Jul 15 06:47:41 PM PDT 24 |
Finished | Jul 15 06:48:43 PM PDT 24 |
Peak memory | 224512 kb |
Host | smart-4725b5ac-3d91-47e4-ad23-6a683f5fc70d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882046894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stres s_all.882046894 |
Directory | /workspace/20.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/20.spi_device_tpm_all.662305279 |
Short name | T967 |
Test name | |
Test status | |
Simulation time | 26911190067 ps |
CPU time | 33.93 seconds |
Started | Jul 15 06:47:34 PM PDT 24 |
Finished | Jul 15 06:48:09 PM PDT 24 |
Peak memory | 216232 kb |
Host | smart-7560c746-b981-4a95-a2c1-5c68a04545a6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=662305279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.662305279 |
Directory | /workspace/20.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1159058440 |
Short name | T905 |
Test name | |
Test status | |
Simulation time | 4150624835 ps |
CPU time | 3.16 seconds |
Started | Jul 15 06:47:39 PM PDT 24 |
Finished | Jul 15 06:47:43 PM PDT 24 |
Peak memory | 216288 kb |
Host | smart-02a03de7-6c6a-4f9a-b70d-df3b04f710b9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1159058440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1159058440 |
Directory | /workspace/20.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/20.spi_device_tpm_rw.1964281177 |
Short name | T902 |
Test name | |
Test status | |
Simulation time | 61305938 ps |
CPU time | 0.91 seconds |
Started | Jul 15 06:47:34 PM PDT 24 |
Finished | Jul 15 06:47:36 PM PDT 24 |
Peak memory | 207156 kb |
Host | smart-1e50f274-fb9a-417a-b33f-3d5d271c1283 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1964281177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1964281177 |
Directory | /workspace/20.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/20.spi_device_tpm_sts_read.3980484818 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 63187889 ps |
CPU time | 0.76 seconds |
Started | Jul 15 06:47:35 PM PDT 24 |
Finished | Jul 15 06:47:37 PM PDT 24 |
Peak memory | 205892 kb |
Host | smart-222970df-a026-49c4-b7cc-dedbf409d554 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3980484818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3980484818 |
Directory | /workspace/20.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/20.spi_device_upload.3204505472 |
Short name | T670 |
Test name | |
Test status | |
Simulation time | 167594841 ps |
CPU time | 4.13 seconds |
Started | Jul 15 06:47:40 PM PDT 24 |
Finished | Jul 15 06:47:45 PM PDT 24 |
Peak memory | 232624 kb |
Host | smart-b687eaad-db3c-4abb-97fb-fbbc13807e69 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3204505472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3204505472 |
Directory | /workspace/20.spi_device_upload/latest |
Test location | /workspace/coverage/default/21.spi_device_alert_test.3340719507 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 21308604 ps |
CPU time | 0.75 seconds |
Started | Jul 15 06:47:48 PM PDT 24 |
Finished | Jul 15 06:47:49 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-28e63a2f-4ff1-4d5a-97c2-95af347b7dea |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340719507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test. 3340719507 |
Directory | /workspace/21.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/21.spi_device_csb_read.399766885 |
Short name | T685 |
Test name | |
Test status | |
Simulation time | 103662745 ps |
CPU time | 0.77 seconds |
Started | Jul 15 06:47:39 PM PDT 24 |
Finished | Jul 15 06:47:40 PM PDT 24 |
Peak memory | 206488 kb |
Host | smart-2954b370-b9b5-4a42-a3cd-f09ba5980aee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=399766885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.399766885 |
Directory | /workspace/21.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/21.spi_device_flash_all.2427379656 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 65766671548 ps |
CPU time | 454.87 seconds |
Started | Jul 15 06:47:47 PM PDT 24 |
Finished | Jul 15 06:55:23 PM PDT 24 |
Peak memory | 267000 kb |
Host | smart-ba8e479a-aa99-4f9f-a0f0-a73867f07b7f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2427379656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2427379656 |
Directory | /workspace/21.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/21.spi_device_flash_and_tpm.1646377775 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 4816141672 ps |
CPU time | 22.06 seconds |
Started | Jul 15 06:47:48 PM PDT 24 |
Finished | Jul 15 06:48:11 PM PDT 24 |
Peak memory | 217644 kb |
Host | smart-2946f419-f595-4d60-a423-e116006ce80b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1646377775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1646377775 |
Directory | /workspace/21.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1027483134 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 22751714893 ps |
CPU time | 69.68 seconds |
Started | Jul 15 06:47:48 PM PDT 24 |
Finished | Jul 15 06:48:58 PM PDT 24 |
Peak memory | 249212 kb |
Host | smart-cc4d0109-5699-451b-9e3e-e2ebcf4231a0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1027483134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl e.1027483134 |
Directory | /workspace/21.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.865387186 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 71245959072 ps |
CPU time | 142.82 seconds |
Started | Jul 15 06:47:48 PM PDT 24 |
Finished | Jul 15 06:50:12 PM PDT 24 |
Peak memory | 249172 kb |
Host | smart-fe90219c-132d-48fe-b81c-169fa1b915f1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=865387186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds .865387186 |
Directory | /workspace/21.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/21.spi_device_intercept.225824111 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 930523318 ps |
CPU time | 6.9 seconds |
Started | Jul 15 06:47:40 PM PDT 24 |
Finished | Jul 15 06:47:48 PM PDT 24 |
Peak memory | 232564 kb |
Host | smart-d9bc52b0-d312-4f23-9de4-767cd1c0e305 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=225824111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.225824111 |
Directory | /workspace/21.spi_device_intercept/latest |
Test location | /workspace/coverage/default/21.spi_device_mailbox.1084682791 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 56881899 ps |
CPU time | 2.58 seconds |
Started | Jul 15 06:47:47 PM PDT 24 |
Finished | Jul 15 06:47:50 PM PDT 24 |
Peak memory | 232300 kb |
Host | smart-8099889d-c328-4054-b963-cb8377b4b097 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1084682791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1084682791 |
Directory | /workspace/21.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1265478768 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 1226786489 ps |
CPU time | 5.74 seconds |
Started | Jul 15 06:47:41 PM PDT 24 |
Finished | Jul 15 06:47:47 PM PDT 24 |
Peak memory | 224384 kb |
Host | smart-779e0538-6e9b-4cac-9add-905969046e80 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1265478768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa p.1265478768 |
Directory | /workspace/21.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3480912682 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 365024569 ps |
CPU time | 5.7 seconds |
Started | Jul 15 06:47:44 PM PDT 24 |
Finished | Jul 15 06:47:50 PM PDT 24 |
Peak memory | 240640 kb |
Host | smart-af0327be-2a73-4006-ba4d-9fb232a08314 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3480912682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3480912682 |
Directory | /workspace/21.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/21.spi_device_read_buffer_direct.2038281901 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 147563353 ps |
CPU time | 3.82 seconds |
Started | Jul 15 06:47:46 PM PDT 24 |
Finished | Jul 15 06:47:50 PM PDT 24 |
Peak memory | 218716 kb |
Host | smart-7453c777-8b09-4845-9bea-0c506b689c41 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2038281901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir ect.2038281901 |
Directory | /workspace/21.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/21.spi_device_stress_all.1299908254 |
Short name | T566 |
Test name | |
Test status | |
Simulation time | 2645696313 ps |
CPU time | 66.5 seconds |
Started | Jul 15 06:47:47 PM PDT 24 |
Finished | Jul 15 06:48:55 PM PDT 24 |
Peak memory | 251940 kb |
Host | smart-b7b523de-00b1-43cb-bb32-5dbc0ce68ae7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299908254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre ss_all.1299908254 |
Directory | /workspace/21.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/21.spi_device_tpm_all.907897601 |
Short name | T745 |
Test name | |
Test status | |
Simulation time | 6542153137 ps |
CPU time | 41.77 seconds |
Started | Jul 15 06:47:43 PM PDT 24 |
Finished | Jul 15 06:48:26 PM PDT 24 |
Peak memory | 216280 kb |
Host | smart-e3313763-f631-4ff5-993e-e79776884478 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=907897601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.907897601 |
Directory | /workspace/21.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1035134116 |
Short name | T678 |
Test name | |
Test status | |
Simulation time | 4207534238 ps |
CPU time | 13.29 seconds |
Started | Jul 15 06:47:40 PM PDT 24 |
Finished | Jul 15 06:47:54 PM PDT 24 |
Peak memory | 216248 kb |
Host | smart-ffd48c79-4456-4aac-8bcf-55c4839c7d85 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1035134116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1035134116 |
Directory | /workspace/21.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/21.spi_device_tpm_rw.1974140189 |
Short name | T573 |
Test name | |
Test status | |
Simulation time | 49891517 ps |
CPU time | 0.95 seconds |
Started | Jul 15 06:47:41 PM PDT 24 |
Finished | Jul 15 06:47:42 PM PDT 24 |
Peak memory | 206988 kb |
Host | smart-a2c741c9-3e03-4b9d-a142-aa42a62b05f8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1974140189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1974140189 |
Directory | /workspace/21.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/21.spi_device_tpm_sts_read.2814110106 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 705383183 ps |
CPU time | 0.87 seconds |
Started | Jul 15 06:47:41 PM PDT 24 |
Finished | Jul 15 06:47:43 PM PDT 24 |
Peak memory | 205932 kb |
Host | smart-465a0c4f-f3c8-43a8-82a8-75358597ea91 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2814110106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2814110106 |
Directory | /workspace/21.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/21.spi_device_upload.72221437 |
Short name | T734 |
Test name | |
Test status | |
Simulation time | 1629010285 ps |
CPU time | 7.64 seconds |
Started | Jul 15 06:47:48 PM PDT 24 |
Finished | Jul 15 06:47:56 PM PDT 24 |
Peak memory | 232576 kb |
Host | smart-25c48a47-2169-4eb2-ace2-b228bdfe403b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=72221437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.72221437 |
Directory | /workspace/21.spi_device_upload/latest |
Test location | /workspace/coverage/default/22.spi_device_alert_test.2348545606 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 15713813 ps |
CPU time | 0.74 seconds |
Started | Jul 15 06:47:57 PM PDT 24 |
Finished | Jul 15 06:47:58 PM PDT 24 |
Peak memory | 205524 kb |
Host | smart-684b7382-54e6-42eb-83c4-b4bf160cbfad |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348545606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test. 2348545606 |
Directory | /workspace/22.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/22.spi_device_cfg_cmd.710350639 |
Short name | T811 |
Test name | |
Test status | |
Simulation time | 1492214528 ps |
CPU time | 3.54 seconds |
Started | Jul 15 06:47:52 PM PDT 24 |
Finished | Jul 15 06:47:56 PM PDT 24 |
Peak memory | 232620 kb |
Host | smart-00f4195c-2d40-4b82-bb5c-4bea7e966650 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=710350639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.710350639 |
Directory | /workspace/22.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/22.spi_device_csb_read.3330096880 |
Short name | T559 |
Test name | |
Test status | |
Simulation time | 51766593 ps |
CPU time | 0.8 seconds |
Started | Jul 15 06:47:48 PM PDT 24 |
Finished | Jul 15 06:47:50 PM PDT 24 |
Peak memory | 206556 kb |
Host | smart-8eb6a75c-fe56-451c-be04-b6e34c1a9849 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3330096880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3330096880 |
Directory | /workspace/22.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/22.spi_device_flash_all.4265880639 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 6172489275 ps |
CPU time | 44.64 seconds |
Started | Jul 15 06:47:59 PM PDT 24 |
Finished | Jul 15 06:48:44 PM PDT 24 |
Peak memory | 252292 kb |
Host | smart-4691a7b4-5657-4bcd-91b4-e429522a7c77 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4265880639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.4265880639 |
Directory | /workspace/22.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/22.spi_device_flash_and_tpm.2724432975 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 32422135191 ps |
CPU time | 88.69 seconds |
Started | Jul 15 06:47:58 PM PDT 24 |
Finished | Jul 15 06:49:27 PM PDT 24 |
Peak memory | 249212 kb |
Host | smart-788d6316-1dc8-4049-a759-605bc357609b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2724432975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2724432975 |
Directory | /workspace/22.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.4121714232 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 17791079496 ps |
CPU time | 176.37 seconds |
Started | Jul 15 06:47:59 PM PDT 24 |
Finished | Jul 15 06:50:56 PM PDT 24 |
Peak memory | 249204 kb |
Host | smart-6a4fc934-cc00-4a7f-8f51-9e0f6eb991c0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4121714232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl e.4121714232 |
Directory | /workspace/22.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/22.spi_device_flash_mode.2939279012 |
Short name | T597 |
Test name | |
Test status | |
Simulation time | 264439109 ps |
CPU time | 6.99 seconds |
Started | Jul 15 06:47:54 PM PDT 24 |
Finished | Jul 15 06:48:01 PM PDT 24 |
Peak memory | 224384 kb |
Host | smart-c6ca2756-ee32-46a6-82b1-09cc1945cce6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2939279012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2939279012 |
Directory | /workspace/22.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.2622851743 |
Short name | T850 |
Test name | |
Test status | |
Simulation time | 3835386297 ps |
CPU time | 25.04 seconds |
Started | Jul 15 06:47:52 PM PDT 24 |
Finished | Jul 15 06:48:17 PM PDT 24 |
Peak memory | 237600 kb |
Host | smart-d7e6e842-fff7-4d86-86e5-76bb49392923 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2622851743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd s.2622851743 |
Directory | /workspace/22.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/22.spi_device_intercept.431419798 |
Short name | T548 |
Test name | |
Test status | |
Simulation time | 349808725 ps |
CPU time | 4.43 seconds |
Started | Jul 15 06:47:53 PM PDT 24 |
Finished | Jul 15 06:47:58 PM PDT 24 |
Peak memory | 224332 kb |
Host | smart-028f9058-69d9-4c8c-aebd-52712ad12cf0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=431419798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.431419798 |
Directory | /workspace/22.spi_device_intercept/latest |
Test location | /workspace/coverage/default/22.spi_device_mailbox.932034530 |
Short name | T899 |
Test name | |
Test status | |
Simulation time | 669826541 ps |
CPU time | 10.71 seconds |
Started | Jul 15 06:47:53 PM PDT 24 |
Finished | Jul 15 06:48:04 PM PDT 24 |
Peak memory | 240428 kb |
Host | smart-1480d16f-b434-48eb-a035-2565637f154a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=932034530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.932034530 |
Directory | /workspace/22.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.513016722 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 34682008346 ps |
CPU time | 11.85 seconds |
Started | Jul 15 06:47:52 PM PDT 24 |
Finished | Jul 15 06:48:05 PM PDT 24 |
Peak memory | 224536 kb |
Host | smart-25c5d55a-6c17-4f24-9287-310278eb2633 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=513016722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap .513016722 |
Directory | /workspace/22.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1680108366 |
Short name | T881 |
Test name | |
Test status | |
Simulation time | 5287967850 ps |
CPU time | 12.62 seconds |
Started | Jul 15 06:47:54 PM PDT 24 |
Finished | Jul 15 06:48:07 PM PDT 24 |
Peak memory | 232708 kb |
Host | smart-0874e396-c11f-4dd7-ae7c-8d386e8f7164 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1680108366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1680108366 |
Directory | /workspace/22.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/22.spi_device_read_buffer_direct.759930613 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 1192811431 ps |
CPU time | 14.16 seconds |
Started | Jul 15 06:47:51 PM PDT 24 |
Finished | Jul 15 06:48:06 PM PDT 24 |
Peak memory | 220516 kb |
Host | smart-3a350e18-3a77-4c38-a37f-69ee3c225069 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=759930613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire ct.759930613 |
Directory | /workspace/22.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/22.spi_device_stress_all.3985621010 |
Short name | T933 |
Test name | |
Test status | |
Simulation time | 74439627 ps |
CPU time | 1.18 seconds |
Started | Jul 15 06:47:59 PM PDT 24 |
Finished | Jul 15 06:48:01 PM PDT 24 |
Peak memory | 206904 kb |
Host | smart-52bf6d37-a6fb-419c-9f0a-741860f72e29 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985621010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre ss_all.3985621010 |
Directory | /workspace/22.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/22.spi_device_tpm_all.1839096731 |
Short name | T613 |
Test name | |
Test status | |
Simulation time | 6652358069 ps |
CPU time | 35.76 seconds |
Started | Jul 15 06:47:47 PM PDT 24 |
Finished | Jul 15 06:48:23 PM PDT 24 |
Peak memory | 216316 kb |
Host | smart-7b4e8d66-7000-452c-aca8-80bca6db90f3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1839096731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1839096731 |
Directory | /workspace/22.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.900999863 |
Short name | T626 |
Test name | |
Test status | |
Simulation time | 323154771 ps |
CPU time | 2.89 seconds |
Started | Jul 15 06:47:47 PM PDT 24 |
Finished | Jul 15 06:47:50 PM PDT 24 |
Peak memory | 216176 kb |
Host | smart-ab683fc6-ae3c-467b-8aca-384856b969d6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=900999863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.900999863 |
Directory | /workspace/22.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/22.spi_device_tpm_rw.654830183 |
Short name | T796 |
Test name | |
Test status | |
Simulation time | 206767869 ps |
CPU time | 3.1 seconds |
Started | Jul 15 06:47:54 PM PDT 24 |
Finished | Jul 15 06:47:57 PM PDT 24 |
Peak memory | 216096 kb |
Host | smart-1b8e690b-1284-4a24-8e7c-161df82d3fd6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=654830183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.654830183 |
Directory | /workspace/22.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/22.spi_device_tpm_sts_read.985582173 |
Short name | T696 |
Test name | |
Test status | |
Simulation time | 30074169 ps |
CPU time | 0.85 seconds |
Started | Jul 15 06:47:49 PM PDT 24 |
Finished | Jul 15 06:47:50 PM PDT 24 |
Peak memory | 205928 kb |
Host | smart-d3b1b4db-3790-4928-9e27-d00ab5d385c1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=985582173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.985582173 |
Directory | /workspace/22.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/22.spi_device_upload.3980210912 |
Short name | T970 |
Test name | |
Test status | |
Simulation time | 207421645 ps |
CPU time | 3.37 seconds |
Started | Jul 15 06:47:54 PM PDT 24 |
Finished | Jul 15 06:47:58 PM PDT 24 |
Peak memory | 224416 kb |
Host | smart-c247dfb9-483c-4106-90f4-46c062be40c3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3980210912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3980210912 |
Directory | /workspace/22.spi_device_upload/latest |
Test location | /workspace/coverage/default/23.spi_device_alert_test.2198420269 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 37265555 ps |
CPU time | 0.72 seconds |
Started | Jul 15 06:48:07 PM PDT 24 |
Finished | Jul 15 06:48:08 PM PDT 24 |
Peak memory | 204868 kb |
Host | smart-c0fe0806-4179-4dcd-83cd-8d1fc23a3f37 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198420269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test. 2198420269 |
Directory | /workspace/23.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/23.spi_device_cfg_cmd.1085961860 |
Short name | T665 |
Test name | |
Test status | |
Simulation time | 813375859 ps |
CPU time | 6.51 seconds |
Started | Jul 15 06:48:06 PM PDT 24 |
Finished | Jul 15 06:48:12 PM PDT 24 |
Peak memory | 224372 kb |
Host | smart-f59c82be-25c0-4775-9c19-3ce2e1521aa3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1085961860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1085961860 |
Directory | /workspace/23.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/23.spi_device_csb_read.1540299675 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 46434886 ps |
CPU time | 0.78 seconds |
Started | Jul 15 06:47:57 PM PDT 24 |
Finished | Jul 15 06:47:58 PM PDT 24 |
Peak memory | 206716 kb |
Host | smart-a6d3a82a-aa2a-4e15-80ba-df4fe1750000 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1540299675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1540299675 |
Directory | /workspace/23.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/23.spi_device_flash_all.240294367 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 26848259878 ps |
CPU time | 59.61 seconds |
Started | Jul 15 06:48:08 PM PDT 24 |
Finished | Jul 15 06:49:08 PM PDT 24 |
Peak memory | 249308 kb |
Host | smart-94e560b5-9abd-4303-a070-a61c5d1db561 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=240294367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.240294367 |
Directory | /workspace/23.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/23.spi_device_flash_and_tpm.3153141332 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 27585268921 ps |
CPU time | 46.32 seconds |
Started | Jul 15 06:48:05 PM PDT 24 |
Finished | Jul 15 06:48:52 PM PDT 24 |
Peak memory | 234268 kb |
Host | smart-de00cb46-87d0-486a-918e-e04650c2edf8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3153141332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3153141332 |
Directory | /workspace/23.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/23.spi_device_flash_mode.2773306025 |
Short name | T969 |
Test name | |
Test status | |
Simulation time | 164741113 ps |
CPU time | 4.42 seconds |
Started | Jul 15 06:48:07 PM PDT 24 |
Finished | Jul 15 06:48:12 PM PDT 24 |
Peak memory | 224392 kb |
Host | smart-060c6813-5286-4763-8909-c0c926f1cc5d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2773306025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2773306025 |
Directory | /workspace/23.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.4245520334 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 8868144973 ps |
CPU time | 60.06 seconds |
Started | Jul 15 06:48:10 PM PDT 24 |
Finished | Jul 15 06:49:11 PM PDT 24 |
Peak memory | 253012 kb |
Host | smart-b27cbae5-0243-4042-87f4-e2c1f4e56cdd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4245520334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd s.4245520334 |
Directory | /workspace/23.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/23.spi_device_intercept.336576777 |
Short name | T754 |
Test name | |
Test status | |
Simulation time | 975177651 ps |
CPU time | 5.27 seconds |
Started | Jul 15 06:47:58 PM PDT 24 |
Finished | Jul 15 06:48:04 PM PDT 24 |
Peak memory | 224396 kb |
Host | smart-e653823a-dee4-4bff-8639-f993132ca06b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=336576777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.336576777 |
Directory | /workspace/23.spi_device_intercept/latest |
Test location | /workspace/coverage/default/23.spi_device_mailbox.465852890 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 30909683224 ps |
CPU time | 40.64 seconds |
Started | Jul 15 06:48:06 PM PDT 24 |
Finished | Jul 15 06:48:47 PM PDT 24 |
Peak memory | 251632 kb |
Host | smart-b50b51c5-c79b-49d9-b948-9680713d482d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=465852890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.465852890 |
Directory | /workspace/23.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1758465234 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 855326095 ps |
CPU time | 3.59 seconds |
Started | Jul 15 06:48:00 PM PDT 24 |
Finished | Jul 15 06:48:04 PM PDT 24 |
Peak memory | 232600 kb |
Host | smart-fa1d3d04-096d-4d8c-8e7a-48cbe6a0d8f0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1758465234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa p.1758465234 |
Directory | /workspace/23.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/23.spi_device_pass_cmd_filtering.4016569197 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 719989321 ps |
CPU time | 6.42 seconds |
Started | Jul 15 06:47:59 PM PDT 24 |
Finished | Jul 15 06:48:05 PM PDT 24 |
Peak memory | 232668 kb |
Host | smart-bb9d6f83-20f6-4f98-a369-10dcefbb8d2e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4016569197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.4016569197 |
Directory | /workspace/23.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/23.spi_device_read_buffer_direct.1852842171 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 254747808 ps |
CPU time | 5.35 seconds |
Started | Jul 15 06:48:06 PM PDT 24 |
Finished | Jul 15 06:48:12 PM PDT 24 |
Peak memory | 220476 kb |
Host | smart-bdee3e9b-67c8-4ae7-8322-081c3f2b8d99 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1852842171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir ect.1852842171 |
Directory | /workspace/23.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/23.spi_device_stress_all.286242452 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 60450675925 ps |
CPU time | 425.53 seconds |
Started | Jul 15 06:48:05 PM PDT 24 |
Finished | Jul 15 06:55:11 PM PDT 24 |
Peak memory | 265600 kb |
Host | smart-0a6f8441-78fa-4836-8e6a-82e42741c5fc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286242452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres s_all.286242452 |
Directory | /workspace/23.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/23.spi_device_tpm_all.3394438431 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 7389924168 ps |
CPU time | 10.62 seconds |
Started | Jul 15 06:48:00 PM PDT 24 |
Finished | Jul 15 06:48:11 PM PDT 24 |
Peak memory | 216296 kb |
Host | smart-3fcdf76f-19cd-48f6-9435-8ad14ddc64d1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3394438431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3394438431 |
Directory | /workspace/23.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.811677292 |
Short name | T560 |
Test name | |
Test status | |
Simulation time | 2543195489 ps |
CPU time | 8 seconds |
Started | Jul 15 06:48:00 PM PDT 24 |
Finished | Jul 15 06:48:08 PM PDT 24 |
Peak memory | 216316 kb |
Host | smart-6df83c24-657d-4b7b-b649-509e7928da57 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=811677292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.811677292 |
Directory | /workspace/23.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/23.spi_device_tpm_rw.2483066270 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 128310194 ps |
CPU time | 1.49 seconds |
Started | Jul 15 06:48:00 PM PDT 24 |
Finished | Jul 15 06:48:02 PM PDT 24 |
Peak memory | 216168 kb |
Host | smart-b0b23ff7-c131-4795-a8a1-548f58debba9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2483066270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2483066270 |
Directory | /workspace/23.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/23.spi_device_tpm_sts_read.2139984105 |
Short name | T877 |
Test name | |
Test status | |
Simulation time | 76057356 ps |
CPU time | 0.9 seconds |
Started | Jul 15 06:47:57 PM PDT 24 |
Finished | Jul 15 06:47:58 PM PDT 24 |
Peak memory | 206924 kb |
Host | smart-fc618cb4-72e8-43d1-8771-55a2bf080151 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2139984105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2139984105 |
Directory | /workspace/23.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/23.spi_device_upload.3747893813 |
Short name | T928 |
Test name | |
Test status | |
Simulation time | 22584379412 ps |
CPU time | 21.58 seconds |
Started | Jul 15 06:48:12 PM PDT 24 |
Finished | Jul 15 06:48:34 PM PDT 24 |
Peak memory | 239116 kb |
Host | smart-ad144b82-b094-47b1-a040-de32f83019b5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3747893813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3747893813 |
Directory | /workspace/23.spi_device_upload/latest |
Test location | /workspace/coverage/default/24.spi_device_alert_test.3730300698 |
Short name | T808 |
Test name | |
Test status | |
Simulation time | 33872669 ps |
CPU time | 0.69 seconds |
Started | Jul 15 06:48:20 PM PDT 24 |
Finished | Jul 15 06:48:22 PM PDT 24 |
Peak memory | 205464 kb |
Host | smart-0a011088-6b7f-4a00-ba22-1240f5b923c5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730300698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test. 3730300698 |
Directory | /workspace/24.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/24.spi_device_cfg_cmd.3152024218 |
Short name | T824 |
Test name | |
Test status | |
Simulation time | 312704079 ps |
CPU time | 2.54 seconds |
Started | Jul 15 06:48:13 PM PDT 24 |
Finished | Jul 15 06:48:16 PM PDT 24 |
Peak memory | 232560 kb |
Host | smart-3c6f8dbd-df92-4e1f-b8b0-0b7642d5e8e7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3152024218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3152024218 |
Directory | /workspace/24.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/24.spi_device_csb_read.3367426579 |
Short name | T672 |
Test name | |
Test status | |
Simulation time | 58969017 ps |
CPU time | 0.79 seconds |
Started | Jul 15 06:48:07 PM PDT 24 |
Finished | Jul 15 06:48:08 PM PDT 24 |
Peak memory | 206508 kb |
Host | smart-88bbf6a6-b741-4550-b66f-da45ab537d61 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3367426579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3367426579 |
Directory | /workspace/24.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/24.spi_device_flash_all.1713284217 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 171966367186 ps |
CPU time | 164.33 seconds |
Started | Jul 15 06:48:13 PM PDT 24 |
Finished | Jul 15 06:50:58 PM PDT 24 |
Peak memory | 256564 kb |
Host | smart-da8712a9-410b-4aa7-a74f-c542fbfcecfc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1713284217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1713284217 |
Directory | /workspace/24.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/24.spi_device_flash_and_tpm.3397049714 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 19814462144 ps |
CPU time | 181.91 seconds |
Started | Jul 15 06:48:13 PM PDT 24 |
Finished | Jul 15 06:51:15 PM PDT 24 |
Peak memory | 252384 kb |
Host | smart-f8f18592-4ce0-4b4e-9823-12ee5847241b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3397049714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3397049714 |
Directory | /workspace/24.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3423486606 |
Short name | T914 |
Test name | |
Test status | |
Simulation time | 211282217 ps |
CPU time | 0.82 seconds |
Started | Jul 15 06:48:13 PM PDT 24 |
Finished | Jul 15 06:48:14 PM PDT 24 |
Peak memory | 217336 kb |
Host | smart-836fc201-689e-4f0f-9273-d075941cdb55 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3423486606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl e.3423486606 |
Directory | /workspace/24.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/24.spi_device_flash_mode.2099448242 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 794066623 ps |
CPU time | 15.37 seconds |
Started | Jul 15 06:48:14 PM PDT 24 |
Finished | Jul 15 06:48:30 PM PDT 24 |
Peak memory | 240404 kb |
Host | smart-e7afa796-e40c-440d-876c-84d863c135be |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2099448242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2099448242 |
Directory | /workspace/24.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.411816599 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 1813617871 ps |
CPU time | 34.14 seconds |
Started | Jul 15 06:48:13 PM PDT 24 |
Finished | Jul 15 06:48:48 PM PDT 24 |
Peak memory | 249056 kb |
Host | smart-fd5fc14b-a0ed-488b-8b68-c1d745a08d86 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=411816599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds .411816599 |
Directory | /workspace/24.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/24.spi_device_intercept.3805143856 |
Short name | T711 |
Test name | |
Test status | |
Simulation time | 4009441844 ps |
CPU time | 8.39 seconds |
Started | Jul 15 06:48:11 PM PDT 24 |
Finished | Jul 15 06:48:20 PM PDT 24 |
Peak memory | 232708 kb |
Host | smart-f00bd38f-421a-471c-adb2-76eba8493233 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3805143856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3805143856 |
Directory | /workspace/24.spi_device_intercept/latest |
Test location | /workspace/coverage/default/24.spi_device_mailbox.3034179414 |
Short name | T903 |
Test name | |
Test status | |
Simulation time | 1807859787 ps |
CPU time | 17.69 seconds |
Started | Jul 15 06:48:15 PM PDT 24 |
Finished | Jul 15 06:48:33 PM PDT 24 |
Peak memory | 232612 kb |
Host | smart-e6833d29-7231-4a8f-9c79-0d021c92b74d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3034179414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3034179414 |
Directory | /workspace/24.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1598739931 |
Short name | T681 |
Test name | |
Test status | |
Simulation time | 410875587 ps |
CPU time | 4.2 seconds |
Started | Jul 15 06:48:12 PM PDT 24 |
Finished | Jul 15 06:48:17 PM PDT 24 |
Peak memory | 224396 kb |
Host | smart-6c620974-9c87-451b-96d7-f637aa574815 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1598739931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa p.1598739931 |
Directory | /workspace/24.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3448426395 |
Short name | T783 |
Test name | |
Test status | |
Simulation time | 9004936717 ps |
CPU time | 25.28 seconds |
Started | Jul 15 06:48:13 PM PDT 24 |
Finished | Jul 15 06:48:39 PM PDT 24 |
Peak memory | 233740 kb |
Host | smart-09845786-4595-4854-8f17-e667f00128d4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3448426395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3448426395 |
Directory | /workspace/24.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/24.spi_device_read_buffer_direct.364894121 |
Short name | T492 |
Test name | |
Test status | |
Simulation time | 4057246002 ps |
CPU time | 15.16 seconds |
Started | Jul 15 06:48:12 PM PDT 24 |
Finished | Jul 15 06:48:27 PM PDT 24 |
Peak memory | 219404 kb |
Host | smart-7d0eba6b-74c9-4296-b0ea-695d79ddd268 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=364894121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire ct.364894121 |
Directory | /workspace/24.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/24.spi_device_stress_all.1450685940 |
Short name | T547 |
Test name | |
Test status | |
Simulation time | 34089424283 ps |
CPU time | 326.98 seconds |
Started | Jul 15 06:48:13 PM PDT 24 |
Finished | Jul 15 06:53:41 PM PDT 24 |
Peak memory | 250676 kb |
Host | smart-28fbb72c-a7cb-40a6-ab4a-ed489f8e82d1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450685940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre ss_all.1450685940 |
Directory | /workspace/24.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/24.spi_device_tpm_all.1575972037 |
Short name | T834 |
Test name | |
Test status | |
Simulation time | 916443831 ps |
CPU time | 6.28 seconds |
Started | Jul 15 06:48:13 PM PDT 24 |
Finished | Jul 15 06:48:20 PM PDT 24 |
Peak memory | 216396 kb |
Host | smart-98ad3693-a7c2-4406-a54d-78cfa25f9e18 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1575972037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1575972037 |
Directory | /workspace/24.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1538407402 |
Short name | T499 |
Test name | |
Test status | |
Simulation time | 3047469171 ps |
CPU time | 9.83 seconds |
Started | Jul 15 06:48:12 PM PDT 24 |
Finished | Jul 15 06:48:22 PM PDT 24 |
Peak memory | 216256 kb |
Host | smart-f6e0e002-adff-49e4-9655-d012d38cdd3a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1538407402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1538407402 |
Directory | /workspace/24.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/24.spi_device_tpm_rw.2650148998 |
Short name | T895 |
Test name | |
Test status | |
Simulation time | 46955508 ps |
CPU time | 0.79 seconds |
Started | Jul 15 06:48:14 PM PDT 24 |
Finished | Jul 15 06:48:15 PM PDT 24 |
Peak memory | 205952 kb |
Host | smart-d0e3fa41-ef25-4026-a8fa-d9ef168d6ba7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2650148998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2650148998 |
Directory | /workspace/24.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/24.spi_device_tpm_sts_read.4234764485 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 41262678 ps |
CPU time | 0.73 seconds |
Started | Jul 15 06:48:12 PM PDT 24 |
Finished | Jul 15 06:48:13 PM PDT 24 |
Peak memory | 205924 kb |
Host | smart-fcf85f1f-76d0-4def-9eeb-a31597bc465f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4234764485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.4234764485 |
Directory | /workspace/24.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/24.spi_device_upload.1988834403 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 16401978426 ps |
CPU time | 11.11 seconds |
Started | Jul 15 06:48:10 PM PDT 24 |
Finished | Jul 15 06:48:21 PM PDT 24 |
Peak memory | 235988 kb |
Host | smart-4c77b963-01ea-4361-938d-e0c0b4b86f07 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1988834403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1988834403 |
Directory | /workspace/24.spi_device_upload/latest |
Test location | /workspace/coverage/default/25.spi_device_alert_test.2024130758 |
Short name | T864 |
Test name | |
Test status | |
Simulation time | 17940558 ps |
CPU time | 0.74 seconds |
Started | Jul 15 06:48:26 PM PDT 24 |
Finished | Jul 15 06:48:27 PM PDT 24 |
Peak memory | 205472 kb |
Host | smart-6be9ac03-a8c3-4cde-8a81-3c2f7a2339c8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024130758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test. 2024130758 |
Directory | /workspace/25.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/25.spi_device_cfg_cmd.2355912470 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 196072433 ps |
CPU time | 4.04 seconds |
Started | Jul 15 06:48:19 PM PDT 24 |
Finished | Jul 15 06:48:23 PM PDT 24 |
Peak memory | 232580 kb |
Host | smart-ae2c64a1-16a0-4e90-b4da-47555ecc1527 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2355912470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2355912470 |
Directory | /workspace/25.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/25.spi_device_csb_read.2895908283 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 19471625 ps |
CPU time | 0.74 seconds |
Started | Jul 15 06:48:19 PM PDT 24 |
Finished | Jul 15 06:48:20 PM PDT 24 |
Peak memory | 206832 kb |
Host | smart-1f4bda09-13b8-452a-8bcc-d04206518e08 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2895908283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2895908283 |
Directory | /workspace/25.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/25.spi_device_flash_and_tpm.4151621840 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 77932871336 ps |
CPU time | 259.66 seconds |
Started | Jul 15 06:48:28 PM PDT 24 |
Finished | Jul 15 06:52:48 PM PDT 24 |
Peak memory | 251264 kb |
Host | smart-9d86887b-2f07-41f6-9b11-47f15d9215d2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4151621840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.4151621840 |
Directory | /workspace/25.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.766253221 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 27592390330 ps |
CPU time | 131.74 seconds |
Started | Jul 15 06:48:24 PM PDT 24 |
Finished | Jul 15 06:50:36 PM PDT 24 |
Peak memory | 264712 kb |
Host | smart-eeefbdf3-717e-49cc-a091-c86e229677d9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=766253221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle .766253221 |
Directory | /workspace/25.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/25.spi_device_flash_mode.2879679824 |
Short name | T847 |
Test name | |
Test status | |
Simulation time | 300658391 ps |
CPU time | 2.93 seconds |
Started | Jul 15 06:48:19 PM PDT 24 |
Finished | Jul 15 06:48:23 PM PDT 24 |
Peak memory | 224392 kb |
Host | smart-5e9a8300-3be9-4002-b0f4-7dbbf615fddb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2879679824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2879679824 |
Directory | /workspace/25.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.3014434976 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 2330193572 ps |
CPU time | 22.16 seconds |
Started | Jul 15 06:48:17 PM PDT 24 |
Finished | Jul 15 06:48:40 PM PDT 24 |
Peak memory | 240864 kb |
Host | smart-276d3605-069f-466f-a849-d86ec58dcf6a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3014434976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd s.3014434976 |
Directory | /workspace/25.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/25.spi_device_intercept.3796344874 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 3760398076 ps |
CPU time | 13.76 seconds |
Started | Jul 15 06:48:21 PM PDT 24 |
Finished | Jul 15 06:48:36 PM PDT 24 |
Peak memory | 229732 kb |
Host | smart-e3a777a1-1196-4895-9f9c-ec5d089ed1fe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3796344874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3796344874 |
Directory | /workspace/25.spi_device_intercept/latest |
Test location | /workspace/coverage/default/25.spi_device_mailbox.4036737041 |
Short name | T650 |
Test name | |
Test status | |
Simulation time | 107215885 ps |
CPU time | 2.19 seconds |
Started | Jul 15 06:48:20 PM PDT 24 |
Finished | Jul 15 06:48:23 PM PDT 24 |
Peak memory | 224068 kb |
Host | smart-4ea02530-22d4-4199-8e27-5a8716d62804 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4036737041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.4036737041 |
Directory | /workspace/25.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.356667585 |
Short name | T558 |
Test name | |
Test status | |
Simulation time | 361617268 ps |
CPU time | 4.95 seconds |
Started | Jul 15 06:48:19 PM PDT 24 |
Finished | Jul 15 06:48:25 PM PDT 24 |
Peak memory | 232656 kb |
Host | smart-a565163d-abba-4c3c-8587-514ae1973f4a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=356667585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap .356667585 |
Directory | /workspace/25.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2979666139 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 2840228473 ps |
CPU time | 10.56 seconds |
Started | Jul 15 06:48:19 PM PDT 24 |
Finished | Jul 15 06:48:30 PM PDT 24 |
Peak memory | 240548 kb |
Host | smart-01691c24-26d7-4f3b-971c-9faf035d12f7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2979666139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2979666139 |
Directory | /workspace/25.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/25.spi_device_read_buffer_direct.3402060585 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 16605678413 ps |
CPU time | 9.91 seconds |
Started | Jul 15 06:48:19 PM PDT 24 |
Finished | Jul 15 06:48:29 PM PDT 24 |
Peak memory | 223160 kb |
Host | smart-93ddbc65-68b2-41b1-8e6f-75adaab5fd3a |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3402060585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir ect.3402060585 |
Directory | /workspace/25.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/25.spi_device_tpm_all.2298067236 |
Short name | T661 |
Test name | |
Test status | |
Simulation time | 782449662 ps |
CPU time | 5.3 seconds |
Started | Jul 15 06:48:20 PM PDT 24 |
Finished | Jul 15 06:48:26 PM PDT 24 |
Peak memory | 216184 kb |
Host | smart-5ba1baab-8b5f-44f4-b071-7b83e55ea412 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2298067236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2298067236 |
Directory | /workspace/25.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3826110952 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 23923102445 ps |
CPU time | 10.59 seconds |
Started | Jul 15 06:48:17 PM PDT 24 |
Finished | Jul 15 06:48:28 PM PDT 24 |
Peak memory | 216308 kb |
Host | smart-04ada3e1-ab60-4384-bd8a-c99545dc45bc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3826110952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3826110952 |
Directory | /workspace/25.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/25.spi_device_tpm_rw.2461248453 |
Short name | T752 |
Test name | |
Test status | |
Simulation time | 151980269 ps |
CPU time | 1.89 seconds |
Started | Jul 15 06:48:21 PM PDT 24 |
Finished | Jul 15 06:48:23 PM PDT 24 |
Peak memory | 216124 kb |
Host | smart-2dcf58b1-a376-41c7-89e5-731d0b3a1efe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2461248453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2461248453 |
Directory | /workspace/25.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/25.spi_device_tpm_sts_read.2334310308 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 51701844 ps |
CPU time | 0.89 seconds |
Started | Jul 15 06:48:19 PM PDT 24 |
Finished | Jul 15 06:48:21 PM PDT 24 |
Peak memory | 205932 kb |
Host | smart-aabc65cb-145c-486f-8ea1-9db65941d808 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2334310308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2334310308 |
Directory | /workspace/25.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/25.spi_device_upload.200945863 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 456953822 ps |
CPU time | 4 seconds |
Started | Jul 15 06:48:19 PM PDT 24 |
Finished | Jul 15 06:48:24 PM PDT 24 |
Peak memory | 232684 kb |
Host | smart-61459e14-a36c-4b69-b2a2-3fc84fb64dd5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=200945863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.200945863 |
Directory | /workspace/25.spi_device_upload/latest |
Test location | /workspace/coverage/default/26.spi_device_alert_test.4196637343 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 24849835 ps |
CPU time | 0.73 seconds |
Started | Jul 15 06:48:32 PM PDT 24 |
Finished | Jul 15 06:48:33 PM PDT 24 |
Peak memory | 205492 kb |
Host | smart-5ade47b1-38ac-4dfe-82cd-b908d1c626e8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196637343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test. 4196637343 |
Directory | /workspace/26.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/26.spi_device_cfg_cmd.147395030 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 5027590108 ps |
CPU time | 21.29 seconds |
Started | Jul 15 06:48:26 PM PDT 24 |
Finished | Jul 15 06:48:47 PM PDT 24 |
Peak memory | 232752 kb |
Host | smart-6f4f8a16-d92e-4a2b-83c4-01b3cdb1e4fe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=147395030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.147395030 |
Directory | /workspace/26.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/26.spi_device_csb_read.3397781013 |
Short name | T807 |
Test name | |
Test status | |
Simulation time | 201637114 ps |
CPU time | 0.8 seconds |
Started | Jul 15 06:48:28 PM PDT 24 |
Finished | Jul 15 06:48:29 PM PDT 24 |
Peak memory | 206548 kb |
Host | smart-bf98e239-258b-44e9-9484-b2b1c2bf393a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3397781013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3397781013 |
Directory | /workspace/26.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/26.spi_device_flash_all.516373777 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 58061460807 ps |
CPU time | 405.91 seconds |
Started | Jul 15 06:48:34 PM PDT 24 |
Finished | Jul 15 06:55:21 PM PDT 24 |
Peak memory | 250132 kb |
Host | smart-2b8f3c13-95f6-44e0-a6e9-cb8e9e7d646c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=516373777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.516373777 |
Directory | /workspace/26.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/26.spi_device_flash_and_tpm.406742324 |
Short name | T468 |
Test name | |
Test status | |
Simulation time | 72734156548 ps |
CPU time | 190.38 seconds |
Started | Jul 15 06:48:34 PM PDT 24 |
Finished | Jul 15 06:51:45 PM PDT 24 |
Peak memory | 249188 kb |
Host | smart-eed52b61-f54f-409d-9213-c2ba9b7314e4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=406742324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.406742324 |
Directory | /workspace/26.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1957116323 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 4295674838 ps |
CPU time | 56.46 seconds |
Started | Jul 15 06:48:31 PM PDT 24 |
Finished | Jul 15 06:49:28 PM PDT 24 |
Peak memory | 250284 kb |
Host | smart-a1ffd810-38b6-4c7e-98e8-13e932ffe352 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1957116323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl e.1957116323 |
Directory | /workspace/26.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/26.spi_device_flash_mode.3015768839 |
Short name | T506 |
Test name | |
Test status | |
Simulation time | 266489005 ps |
CPU time | 6.32 seconds |
Started | Jul 15 06:48:31 PM PDT 24 |
Finished | Jul 15 06:48:37 PM PDT 24 |
Peak memory | 233696 kb |
Host | smart-d3036548-c56e-455e-9bbc-6dd2d7c21e09 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3015768839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3015768839 |
Directory | /workspace/26.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.2000238580 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 7851042966 ps |
CPU time | 84.59 seconds |
Started | Jul 15 06:48:32 PM PDT 24 |
Finished | Jul 15 06:49:58 PM PDT 24 |
Peak memory | 249156 kb |
Host | smart-0ce36b2e-9366-436b-83d7-9130e1250ba5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2000238580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd s.2000238580 |
Directory | /workspace/26.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/26.spi_device_intercept.1746948476 |
Short name | T961 |
Test name | |
Test status | |
Simulation time | 2628516514 ps |
CPU time | 12.26 seconds |
Started | Jul 15 06:48:26 PM PDT 24 |
Finished | Jul 15 06:48:39 PM PDT 24 |
Peak memory | 232796 kb |
Host | smart-83b1bdce-c845-432f-837c-5df45473e8a7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1746948476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1746948476 |
Directory | /workspace/26.spi_device_intercept/latest |
Test location | /workspace/coverage/default/26.spi_device_mailbox.1498722156 |
Short name | T716 |
Test name | |
Test status | |
Simulation time | 7887612860 ps |
CPU time | 32.37 seconds |
Started | Jul 15 06:48:27 PM PDT 24 |
Finished | Jul 15 06:49:00 PM PDT 24 |
Peak memory | 232784 kb |
Host | smart-4bcaf586-db49-4c0a-8b36-edd461c60850 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1498722156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1498722156 |
Directory | /workspace/26.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.338734095 |
Short name | T786 |
Test name | |
Test status | |
Simulation time | 9902220806 ps |
CPU time | 4.5 seconds |
Started | Jul 15 06:48:26 PM PDT 24 |
Finished | Jul 15 06:48:31 PM PDT 24 |
Peak memory | 232700 kb |
Host | smart-67aa4792-f433-4c07-be5b-33de02d2569e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=338734095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap .338734095 |
Directory | /workspace/26.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/26.spi_device_pass_cmd_filtering.175011891 |
Short name | T545 |
Test name | |
Test status | |
Simulation time | 3426724121 ps |
CPU time | 5.04 seconds |
Started | Jul 15 06:48:27 PM PDT 24 |
Finished | Jul 15 06:48:33 PM PDT 24 |
Peak memory | 232700 kb |
Host | smart-49d2beae-3d6d-461a-a800-26d1e37685ce |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=175011891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.175011891 |
Directory | /workspace/26.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/26.spi_device_read_buffer_direct.571651525 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 133183240 ps |
CPU time | 3.82 seconds |
Started | Jul 15 06:48:32 PM PDT 24 |
Finished | Jul 15 06:48:37 PM PDT 24 |
Peak memory | 224068 kb |
Host | smart-245bc2cd-d220-4cd9-88d4-1ff8302b9371 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=571651525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire ct.571651525 |
Directory | /workspace/26.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/26.spi_device_stress_all.1103239169 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 67606763052 ps |
CPU time | 213.1 seconds |
Started | Jul 15 06:48:32 PM PDT 24 |
Finished | Jul 15 06:52:06 PM PDT 24 |
Peak memory | 249172 kb |
Host | smart-a3a8c199-e13c-4423-af47-75de31c00f67 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103239169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre ss_all.1103239169 |
Directory | /workspace/26.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/26.spi_device_tpm_all.2466056473 |
Short name | T584 |
Test name | |
Test status | |
Simulation time | 2371399298 ps |
CPU time | 28.1 seconds |
Started | Jul 15 06:48:27 PM PDT 24 |
Finished | Jul 15 06:48:55 PM PDT 24 |
Peak memory | 216244 kb |
Host | smart-e97bf895-cc59-4626-a915-fa25cbaecf36 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2466056473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2466056473 |
Directory | /workspace/26.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3135561764 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 18194620462 ps |
CPU time | 10.77 seconds |
Started | Jul 15 06:48:30 PM PDT 24 |
Finished | Jul 15 06:48:41 PM PDT 24 |
Peak memory | 217656 kb |
Host | smart-79c40a6b-6b85-4a07-84a2-3f52f63c0561 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3135561764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3135561764 |
Directory | /workspace/26.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/26.spi_device_tpm_rw.2611148791 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 101414363 ps |
CPU time | 1.47 seconds |
Started | Jul 15 06:48:25 PM PDT 24 |
Finished | Jul 15 06:48:27 PM PDT 24 |
Peak memory | 216168 kb |
Host | smart-9980b07a-3747-4cd6-b2ad-ec31fdb5f5af |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2611148791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2611148791 |
Directory | /workspace/26.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/26.spi_device_tpm_sts_read.1381742285 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 81295156 ps |
CPU time | 0.76 seconds |
Started | Jul 15 06:48:24 PM PDT 24 |
Finished | Jul 15 06:48:26 PM PDT 24 |
Peak memory | 205944 kb |
Host | smart-59c1b6fa-7c16-4389-b97c-19766cdfe225 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1381742285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1381742285 |
Directory | /workspace/26.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/26.spi_device_upload.1784954173 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 4281284545 ps |
CPU time | 6.93 seconds |
Started | Jul 15 06:48:28 PM PDT 24 |
Finished | Jul 15 06:48:35 PM PDT 24 |
Peak memory | 236124 kb |
Host | smart-0bf763ad-22ec-41f7-a806-5d1ee2397b82 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1784954173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1784954173 |
Directory | /workspace/26.spi_device_upload/latest |
Test location | /workspace/coverage/default/27.spi_device_alert_test.3729211398 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 45767150 ps |
CPU time | 0.7 seconds |
Started | Jul 15 06:48:40 PM PDT 24 |
Finished | Jul 15 06:48:42 PM PDT 24 |
Peak memory | 205476 kb |
Host | smart-918ca25e-693c-4915-b1b2-413aab983890 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729211398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test. 3729211398 |
Directory | /workspace/27.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/27.spi_device_cfg_cmd.795466268 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 408826658 ps |
CPU time | 4.45 seconds |
Started | Jul 15 06:48:37 PM PDT 24 |
Finished | Jul 15 06:48:41 PM PDT 24 |
Peak memory | 232640 kb |
Host | smart-4900a85c-4ae0-4357-899e-908d8c7c6767 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=795466268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.795466268 |
Directory | /workspace/27.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/27.spi_device_csb_read.2894236719 |
Short name | T913 |
Test name | |
Test status | |
Simulation time | 15647705 ps |
CPU time | 0.79 seconds |
Started | Jul 15 06:48:32 PM PDT 24 |
Finished | Jul 15 06:48:33 PM PDT 24 |
Peak memory | 206844 kb |
Host | smart-d26bc3d1-9fea-4898-971d-519b353712cc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2894236719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2894236719 |
Directory | /workspace/27.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/27.spi_device_flash_all.21207056 |
Short name | T508 |
Test name | |
Test status | |
Simulation time | 22897786749 ps |
CPU time | 90.37 seconds |
Started | Jul 15 06:48:40 PM PDT 24 |
Finished | Jul 15 06:50:11 PM PDT 24 |
Peak memory | 239036 kb |
Host | smart-cb44cd09-1ebe-41ad-a934-7aee40672a4c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=21207056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.21207056 |
Directory | /workspace/27.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/27.spi_device_flash_and_tpm.4216819635 |
Short name | T693 |
Test name | |
Test status | |
Simulation time | 2817837504 ps |
CPU time | 15.57 seconds |
Started | Jul 15 06:48:40 PM PDT 24 |
Finished | Jul 15 06:48:56 PM PDT 24 |
Peak memory | 224648 kb |
Host | smart-483ce13a-6808-4620-b36f-2f3e49ae3959 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4216819635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.4216819635 |
Directory | /workspace/27.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.4092041990 |
Short name | T787 |
Test name | |
Test status | |
Simulation time | 12168030899 ps |
CPU time | 96.54 seconds |
Started | Jul 15 06:48:39 PM PDT 24 |
Finished | Jul 15 06:50:16 PM PDT 24 |
Peak memory | 249168 kb |
Host | smart-060cb97e-92b6-45d2-804a-7773403648be |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4092041990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl e.4092041990 |
Directory | /workspace/27.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/27.spi_device_flash_mode.3838090089 |
Short name | T599 |
Test name | |
Test status | |
Simulation time | 3132200155 ps |
CPU time | 8.41 seconds |
Started | Jul 15 06:48:41 PM PDT 24 |
Finished | Jul 15 06:48:50 PM PDT 24 |
Peak memory | 238216 kb |
Host | smart-b7886f75-d8e0-4d99-b227-e725f1fa279e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3838090089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3838090089 |
Directory | /workspace/27.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.1960598947 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 2915803942 ps |
CPU time | 50.75 seconds |
Started | Jul 15 06:48:42 PM PDT 24 |
Finished | Jul 15 06:49:33 PM PDT 24 |
Peak memory | 254016 kb |
Host | smart-1b9449d5-e913-4335-8b10-a14d84383f9f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1960598947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd s.1960598947 |
Directory | /workspace/27.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/27.spi_device_intercept.2790086276 |
Short name | T528 |
Test name | |
Test status | |
Simulation time | 277686414 ps |
CPU time | 3.81 seconds |
Started | Jul 15 06:48:43 PM PDT 24 |
Finished | Jul 15 06:48:47 PM PDT 24 |
Peak memory | 224348 kb |
Host | smart-62bdd58b-1011-454d-ad47-dfc767ca85da |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2790086276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2790086276 |
Directory | /workspace/27.spi_device_intercept/latest |
Test location | /workspace/coverage/default/27.spi_device_mailbox.219057290 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 34563856 ps |
CPU time | 2.51 seconds |
Started | Jul 15 06:48:40 PM PDT 24 |
Finished | Jul 15 06:48:43 PM PDT 24 |
Peak memory | 232328 kb |
Host | smart-719074b4-1354-440b-b737-94bd11586f14 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=219057290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.219057290 |
Directory | /workspace/27.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3469780263 |
Short name | T789 |
Test name | |
Test status | |
Simulation time | 967307187 ps |
CPU time | 5.19 seconds |
Started | Jul 15 06:48:37 PM PDT 24 |
Finished | Jul 15 06:48:43 PM PDT 24 |
Peak memory | 224400 kb |
Host | smart-5c980679-e85c-439e-90e0-a36755c3ca97 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3469780263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa p.3469780263 |
Directory | /workspace/27.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1026908722 |
Short name | T863 |
Test name | |
Test status | |
Simulation time | 41326730 ps |
CPU time | 2.61 seconds |
Started | Jul 15 06:48:32 PM PDT 24 |
Finished | Jul 15 06:48:36 PM PDT 24 |
Peak memory | 232624 kb |
Host | smart-19bef8b7-dfcc-4bd4-bf07-d2fe0eaea4d2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1026908722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1026908722 |
Directory | /workspace/27.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/27.spi_device_read_buffer_direct.2581252345 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 255787906 ps |
CPU time | 4.68 seconds |
Started | Jul 15 06:48:39 PM PDT 24 |
Finished | Jul 15 06:48:44 PM PDT 24 |
Peak memory | 218784 kb |
Host | smart-2dfaf14c-a551-4edc-8073-986cf16aad52 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2581252345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir ect.2581252345 |
Directory | /workspace/27.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/27.spi_device_stress_all.4200958314 |
Short name | T641 |
Test name | |
Test status | |
Simulation time | 256795233 ps |
CPU time | 0.93 seconds |
Started | Jul 15 06:48:39 PM PDT 24 |
Finished | Jul 15 06:48:40 PM PDT 24 |
Peak memory | 206588 kb |
Host | smart-7db825f4-a9a1-4086-8993-0d5c8ca78a9a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200958314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre ss_all.4200958314 |
Directory | /workspace/27.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/27.spi_device_tpm_all.3574568286 |
Short name | T883 |
Test name | |
Test status | |
Simulation time | 13499074 ps |
CPU time | 0.73 seconds |
Started | Jul 15 06:48:34 PM PDT 24 |
Finished | Jul 15 06:48:35 PM PDT 24 |
Peak memory | 206016 kb |
Host | smart-23ac1db1-d0a7-4900-a43e-1a524ea1a90d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3574568286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3574568286 |
Directory | /workspace/27.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1674168088 |
Short name | T516 |
Test name | |
Test status | |
Simulation time | 34506205677 ps |
CPU time | 21.19 seconds |
Started | Jul 15 06:48:31 PM PDT 24 |
Finished | Jul 15 06:48:53 PM PDT 24 |
Peak memory | 216356 kb |
Host | smart-5cfad035-d439-4f33-afac-05ae6a2a54af |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1674168088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1674168088 |
Directory | /workspace/27.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/27.spi_device_tpm_rw.1606314426 |
Short name | T934 |
Test name | |
Test status | |
Simulation time | 1331269240 ps |
CPU time | 6.15 seconds |
Started | Jul 15 06:48:33 PM PDT 24 |
Finished | Jul 15 06:48:39 PM PDT 24 |
Peak memory | 216160 kb |
Host | smart-a5c8b4e4-4c0c-4a05-b1d4-66db35d559e9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1606314426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1606314426 |
Directory | /workspace/27.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/27.spi_device_tpm_sts_read.2659880482 |
Short name | T517 |
Test name | |
Test status | |
Simulation time | 345496502 ps |
CPU time | 0.78 seconds |
Started | Jul 15 06:48:32 PM PDT 24 |
Finished | Jul 15 06:48:34 PM PDT 24 |
Peak memory | 205928 kb |
Host | smart-528e4d9a-615e-4a4f-92bd-476d5e5f2c62 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2659880482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2659880482 |
Directory | /workspace/27.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/27.spi_device_upload.536266064 |
Short name | T938 |
Test name | |
Test status | |
Simulation time | 30286057594 ps |
CPU time | 22.29 seconds |
Started | Jul 15 06:48:42 PM PDT 24 |
Finished | Jul 15 06:49:04 PM PDT 24 |
Peak memory | 224556 kb |
Host | smart-b074606b-c45e-4f9f-b7ba-2e15d9ea16ac |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=536266064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.536266064 |
Directory | /workspace/27.spi_device_upload/latest |
Test location | /workspace/coverage/default/28.spi_device_alert_test.4173839971 |
Short name | T989 |
Test name | |
Test status | |
Simulation time | 70405183 ps |
CPU time | 0.71 seconds |
Started | Jul 15 06:48:46 PM PDT 24 |
Finished | Jul 15 06:48:47 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-50c66095-fe0f-473a-81cf-0937b7f4ea86 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173839971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test. 4173839971 |
Directory | /workspace/28.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/28.spi_device_cfg_cmd.580863943 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 2764620782 ps |
CPU time | 8.59 seconds |
Started | Jul 15 06:48:46 PM PDT 24 |
Finished | Jul 15 06:48:56 PM PDT 24 |
Peak memory | 232680 kb |
Host | smart-fab0b32b-5e2e-4e86-b207-f739c54441f5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=580863943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.580863943 |
Directory | /workspace/28.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/28.spi_device_csb_read.1846835950 |
Short name | T524 |
Test name | |
Test status | |
Simulation time | 34606610 ps |
CPU time | 0.8 seconds |
Started | Jul 15 06:48:40 PM PDT 24 |
Finished | Jul 15 06:48:42 PM PDT 24 |
Peak memory | 206832 kb |
Host | smart-f4663074-5ad8-47f9-8238-e7c68012af11 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1846835950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1846835950 |
Directory | /workspace/28.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/28.spi_device_flash_all.1668550124 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 2248910686 ps |
CPU time | 30.88 seconds |
Started | Jul 15 06:48:48 PM PDT 24 |
Finished | Jul 15 06:49:20 PM PDT 24 |
Peak memory | 237280 kb |
Host | smart-6602ac27-2daf-4b80-b9e2-de8672533a0b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1668550124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1668550124 |
Directory | /workspace/28.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/28.spi_device_flash_and_tpm.1995005712 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 146217844693 ps |
CPU time | 353.42 seconds |
Started | Jul 15 06:48:46 PM PDT 24 |
Finished | Jul 15 06:54:40 PM PDT 24 |
Peak memory | 253332 kb |
Host | smart-42c53806-b3d3-47e3-be49-b2ded5728f55 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1995005712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1995005712 |
Directory | /workspace/28.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3081523755 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 17940034542 ps |
CPU time | 173.4 seconds |
Started | Jul 15 06:48:46 PM PDT 24 |
Finished | Jul 15 06:51:40 PM PDT 24 |
Peak memory | 249208 kb |
Host | smart-94625314-6598-4b5b-928f-aad494a5a3ca |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3081523755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl e.3081523755 |
Directory | /workspace/28.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/28.spi_device_flash_mode.1688743902 |
Short name | T979 |
Test name | |
Test status | |
Simulation time | 1154469819 ps |
CPU time | 20.11 seconds |
Started | Jul 15 06:48:47 PM PDT 24 |
Finished | Jul 15 06:49:07 PM PDT 24 |
Peak memory | 240296 kb |
Host | smart-8ab847f6-e839-4b96-b752-9e924d3eab22 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1688743902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1688743902 |
Directory | /workspace/28.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/28.spi_device_intercept.720114889 |
Short name | T948 |
Test name | |
Test status | |
Simulation time | 1884563086 ps |
CPU time | 16.88 seconds |
Started | Jul 15 06:48:43 PM PDT 24 |
Finished | Jul 15 06:49:01 PM PDT 24 |
Peak memory | 224408 kb |
Host | smart-a4c992c1-222d-47c7-b92d-52fd7c30de33 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=720114889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.720114889 |
Directory | /workspace/28.spi_device_intercept/latest |
Test location | /workspace/coverage/default/28.spi_device_mailbox.3090815684 |
Short name | T644 |
Test name | |
Test status | |
Simulation time | 4976865889 ps |
CPU time | 10.64 seconds |
Started | Jul 15 06:48:46 PM PDT 24 |
Finished | Jul 15 06:48:57 PM PDT 24 |
Peak memory | 224516 kb |
Host | smart-8cba80e3-3667-4868-a551-40c503bdffdb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3090815684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3090815684 |
Directory | /workspace/28.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1480014394 |
Short name | T602 |
Test name | |
Test status | |
Simulation time | 183529727 ps |
CPU time | 2.72 seconds |
Started | Jul 15 06:48:48 PM PDT 24 |
Finished | Jul 15 06:48:51 PM PDT 24 |
Peak memory | 232528 kb |
Host | smart-b5500da1-dbc5-40e5-bf16-cc13123a1665 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1480014394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa p.1480014394 |
Directory | /workspace/28.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2827619741 |
Short name | T782 |
Test name | |
Test status | |
Simulation time | 1167603526 ps |
CPU time | 6.17 seconds |
Started | Jul 15 06:48:36 PM PDT 24 |
Finished | Jul 15 06:48:43 PM PDT 24 |
Peak memory | 232656 kb |
Host | smart-94c4a680-0e24-4ef5-9dd7-375c1d3964c8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2827619741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2827619741 |
Directory | /workspace/28.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/28.spi_device_read_buffer_direct.3874038485 |
Short name | T471 |
Test name | |
Test status | |
Simulation time | 363092869 ps |
CPU time | 4.64 seconds |
Started | Jul 15 06:48:45 PM PDT 24 |
Finished | Jul 15 06:48:50 PM PDT 24 |
Peak memory | 223056 kb |
Host | smart-326ad7d0-a5c9-4887-8d75-f7676d573591 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3874038485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir ect.3874038485 |
Directory | /workspace/28.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/28.spi_device_stress_all.1272189234 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 17255549365 ps |
CPU time | 124.2 seconds |
Started | Jul 15 06:48:44 PM PDT 24 |
Finished | Jul 15 06:50:49 PM PDT 24 |
Peak memory | 273080 kb |
Host | smart-abbca7fe-b6de-4c83-9cfa-40e0f8afceca |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272189234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre ss_all.1272189234 |
Directory | /workspace/28.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/28.spi_device_tpm_all.3442357527 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 29051526995 ps |
CPU time | 40.25 seconds |
Started | Jul 15 06:48:40 PM PDT 24 |
Finished | Jul 15 06:49:21 PM PDT 24 |
Peak memory | 216420 kb |
Host | smart-ebf6c64e-16cd-4520-8a71-46e0765bf69e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3442357527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3442357527 |
Directory | /workspace/28.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3565794603 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 183596104 ps |
CPU time | 2.35 seconds |
Started | Jul 15 06:48:38 PM PDT 24 |
Finished | Jul 15 06:48:41 PM PDT 24 |
Peak memory | 216152 kb |
Host | smart-3a0d2221-6c94-4e93-8258-a85a181d1dfe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3565794603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3565794603 |
Directory | /workspace/28.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/28.spi_device_tpm_rw.768371826 |
Short name | T960 |
Test name | |
Test status | |
Simulation time | 234459459 ps |
CPU time | 2.17 seconds |
Started | Jul 15 06:48:43 PM PDT 24 |
Finished | Jul 15 06:48:46 PM PDT 24 |
Peak memory | 216140 kb |
Host | smart-83600d71-26ad-4677-90e3-d5f145cca54f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=768371826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.768371826 |
Directory | /workspace/28.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/28.spi_device_tpm_sts_read.1741167751 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 307998373 ps |
CPU time | 0.85 seconds |
Started | Jul 15 06:48:40 PM PDT 24 |
Finished | Jul 15 06:48:41 PM PDT 24 |
Peak memory | 205916 kb |
Host | smart-e576c997-a3fb-4963-bc40-0555465cdf3f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1741167751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1741167751 |
Directory | /workspace/28.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/28.spi_device_upload.1137800801 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 208433621 ps |
CPU time | 5.44 seconds |
Started | Jul 15 06:48:46 PM PDT 24 |
Finished | Jul 15 06:48:52 PM PDT 24 |
Peak memory | 232660 kb |
Host | smart-9fc2d1d8-d431-4098-b5fb-4c822e6bea18 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1137800801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1137800801 |
Directory | /workspace/28.spi_device_upload/latest |
Test location | /workspace/coverage/default/29.spi_device_alert_test.3088376155 |
Short name | T526 |
Test name | |
Test status | |
Simulation time | 17011344 ps |
CPU time | 0.72 seconds |
Started | Jul 15 06:49:00 PM PDT 24 |
Finished | Jul 15 06:49:01 PM PDT 24 |
Peak memory | 205464 kb |
Host | smart-3b76c21a-73da-424d-a100-c73a8098881b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088376155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test. 3088376155 |
Directory | /workspace/29.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/29.spi_device_cfg_cmd.2349762027 |
Short name | T588 |
Test name | |
Test status | |
Simulation time | 425792252 ps |
CPU time | 2.39 seconds |
Started | Jul 15 06:48:53 PM PDT 24 |
Finished | Jul 15 06:48:55 PM PDT 24 |
Peak memory | 223988 kb |
Host | smart-112e2381-a8ec-4eb2-92b1-c485eb25822c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2349762027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2349762027 |
Directory | /workspace/29.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/29.spi_device_csb_read.4079350090 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 17116275 ps |
CPU time | 0.79 seconds |
Started | Jul 15 06:48:46 PM PDT 24 |
Finished | Jul 15 06:48:48 PM PDT 24 |
Peak memory | 206516 kb |
Host | smart-4cdffc18-c9d3-43ef-a0e4-dc3181c8e7a8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4079350090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.4079350090 |
Directory | /workspace/29.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/29.spi_device_flash_all.3900545238 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 25425326000 ps |
CPU time | 44.94 seconds |
Started | Jul 15 06:48:51 PM PDT 24 |
Finished | Jul 15 06:49:36 PM PDT 24 |
Peak memory | 249184 kb |
Host | smart-ba3e6e90-8763-4e1b-96bf-515f8ecb8556 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3900545238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3900545238 |
Directory | /workspace/29.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/29.spi_device_flash_and_tpm.2696168574 |
Short name | T829 |
Test name | |
Test status | |
Simulation time | 114054242322 ps |
CPU time | 271.65 seconds |
Started | Jul 15 06:48:53 PM PDT 24 |
Finished | Jul 15 06:53:25 PM PDT 24 |
Peak memory | 256748 kb |
Host | smart-18c500b6-64b1-4889-884c-fe0cf06b2fd7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2696168574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2696168574 |
Directory | /workspace/29.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2955000676 |
Short name | T552 |
Test name | |
Test status | |
Simulation time | 6675918881 ps |
CPU time | 46.48 seconds |
Started | Jul 15 06:48:53 PM PDT 24 |
Finished | Jul 15 06:49:40 PM PDT 24 |
Peak memory | 248768 kb |
Host | smart-6d890e68-093a-467d-a07f-d7ccc9b18e3c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2955000676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl e.2955000676 |
Directory | /workspace/29.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/29.spi_device_flash_mode.3211255771 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 3747711792 ps |
CPU time | 21.61 seconds |
Started | Jul 15 06:48:54 PM PDT 24 |
Finished | Jul 15 06:49:16 PM PDT 24 |
Peak memory | 240616 kb |
Host | smart-fe01e347-06b7-460f-980b-9683d8007d7b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3211255771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3211255771 |
Directory | /workspace/29.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2963763451 |
Short name | T875 |
Test name | |
Test status | |
Simulation time | 747562413 ps |
CPU time | 4.09 seconds |
Started | Jul 15 06:48:53 PM PDT 24 |
Finished | Jul 15 06:48:58 PM PDT 24 |
Peak memory | 224412 kb |
Host | smart-06d703b6-7788-4fb8-9fa7-f11090370a71 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2963763451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd s.2963763451 |
Directory | /workspace/29.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/29.spi_device_intercept.790287132 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 601006741 ps |
CPU time | 6.96 seconds |
Started | Jul 15 06:48:53 PM PDT 24 |
Finished | Jul 15 06:49:01 PM PDT 24 |
Peak memory | 224388 kb |
Host | smart-74c0fc81-bf04-4403-a459-de2b5375a9f6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=790287132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.790287132 |
Directory | /workspace/29.spi_device_intercept/latest |
Test location | /workspace/coverage/default/29.spi_device_mailbox.1593115181 |
Short name | T487 |
Test name | |
Test status | |
Simulation time | 4558115261 ps |
CPU time | 30.42 seconds |
Started | Jul 15 06:48:52 PM PDT 24 |
Finished | Jul 15 06:49:23 PM PDT 24 |
Peak memory | 248268 kb |
Host | smart-b5d33549-3d77-408d-93fb-0a10ec02e697 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1593115181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1593115181 |
Directory | /workspace/29.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.292701867 |
Short name | T780 |
Test name | |
Test status | |
Simulation time | 852679358 ps |
CPU time | 8.33 seconds |
Started | Jul 15 06:48:52 PM PDT 24 |
Finished | Jul 15 06:49:01 PM PDT 24 |
Peak memory | 232520 kb |
Host | smart-d44b174d-1673-4ec5-a209-4dac2e7e4abe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=292701867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap .292701867 |
Directory | /workspace/29.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3153896255 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 776315207 ps |
CPU time | 4.78 seconds |
Started | Jul 15 06:48:46 PM PDT 24 |
Finished | Jul 15 06:48:52 PM PDT 24 |
Peak memory | 239944 kb |
Host | smart-d40aacd8-2941-4a7e-b50a-662e34fa4254 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3153896255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3153896255 |
Directory | /workspace/29.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/29.spi_device_read_buffer_direct.4189882902 |
Short name | T906 |
Test name | |
Test status | |
Simulation time | 162472292 ps |
CPU time | 4.81 seconds |
Started | Jul 15 06:48:52 PM PDT 24 |
Finished | Jul 15 06:48:58 PM PDT 24 |
Peak memory | 223096 kb |
Host | smart-55220448-14ba-464a-89c2-7a03bbfc4fa0 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4189882902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir ect.4189882902 |
Directory | /workspace/29.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/29.spi_device_stress_all.255102090 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 61029502 ps |
CPU time | 1.08 seconds |
Started | Jul 15 06:48:53 PM PDT 24 |
Finished | Jul 15 06:48:55 PM PDT 24 |
Peak memory | 206816 kb |
Host | smart-a90b8d21-3872-49b3-af1c-44d4e826af64 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255102090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres s_all.255102090 |
Directory | /workspace/29.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/29.spi_device_tpm_all.2488733807 |
Short name | T630 |
Test name | |
Test status | |
Simulation time | 2486243393 ps |
CPU time | 25.09 seconds |
Started | Jul 15 06:48:47 PM PDT 24 |
Finished | Jul 15 06:49:12 PM PDT 24 |
Peak memory | 216420 kb |
Host | smart-efb4e5ad-8670-4cc9-b920-0c262c608cfb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2488733807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2488733807 |
Directory | /workspace/29.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3533111969 |
Short name | T634 |
Test name | |
Test status | |
Simulation time | 7258535433 ps |
CPU time | 18.95 seconds |
Started | Jul 15 06:48:49 PM PDT 24 |
Finished | Jul 15 06:49:08 PM PDT 24 |
Peak memory | 216248 kb |
Host | smart-33d4816a-7481-4970-89e3-250e351bcecb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3533111969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3533111969 |
Directory | /workspace/29.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/29.spi_device_tpm_rw.3752093504 |
Short name | T479 |
Test name | |
Test status | |
Simulation time | 69237062 ps |
CPU time | 1.33 seconds |
Started | Jul 15 06:48:49 PM PDT 24 |
Finished | Jul 15 06:48:50 PM PDT 24 |
Peak memory | 216232 kb |
Host | smart-68c5c76d-14fa-49f2-aa8a-b7ad87fa783a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3752093504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3752093504 |
Directory | /workspace/29.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/29.spi_device_tpm_sts_read.3078418371 |
Short name | T894 |
Test name | |
Test status | |
Simulation time | 22881436 ps |
CPU time | 0.74 seconds |
Started | Jul 15 06:48:48 PM PDT 24 |
Finished | Jul 15 06:48:49 PM PDT 24 |
Peak memory | 205908 kb |
Host | smart-e09555df-80cc-43d3-b751-90cc5006eda0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3078418371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3078418371 |
Directory | /workspace/29.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/29.spi_device_upload.3982538734 |
Short name | T511 |
Test name | |
Test status | |
Simulation time | 476407625 ps |
CPU time | 2.39 seconds |
Started | Jul 15 06:48:51 PM PDT 24 |
Finished | Jul 15 06:48:54 PM PDT 24 |
Peak memory | 223580 kb |
Host | smart-84293241-b5fa-49cd-919d-ceb495029f4f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3982538734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3982538734 |
Directory | /workspace/29.spi_device_upload/latest |
Test location | /workspace/coverage/default/3.spi_device_alert_test.506507461 |
Short name | T520 |
Test name | |
Test status | |
Simulation time | 19003612 ps |
CPU time | 0.72 seconds |
Started | Jul 15 06:45:07 PM PDT 24 |
Finished | Jul 15 06:45:08 PM PDT 24 |
Peak memory | 204896 kb |
Host | smart-3bdaae84-bc55-4d93-8a1c-d0f81a55ca41 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506507461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.506507461 |
Directory | /workspace/3.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/3.spi_device_cfg_cmd.2386042814 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 77780426 ps |
CPU time | 2.45 seconds |
Started | Jul 15 06:45:07 PM PDT 24 |
Finished | Jul 15 06:45:10 PM PDT 24 |
Peak memory | 224376 kb |
Host | smart-17028262-c25c-4f11-8ca7-c998cb19aba1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2386042814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2386042814 |
Directory | /workspace/3.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/3.spi_device_csb_read.2342060105 |
Short name | T940 |
Test name | |
Test status | |
Simulation time | 18524889 ps |
CPU time | 0.79 seconds |
Started | Jul 15 06:45:03 PM PDT 24 |
Finished | Jul 15 06:45:04 PM PDT 24 |
Peak memory | 206872 kb |
Host | smart-0ce9cff7-fd5b-40fb-a539-c7816096ead7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2342060105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2342060105 |
Directory | /workspace/3.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/3.spi_device_flash_all.927595338 |
Short name | T561 |
Test name | |
Test status | |
Simulation time | 18190677801 ps |
CPU time | 160.74 seconds |
Started | Jul 15 06:45:04 PM PDT 24 |
Finished | Jul 15 06:47:46 PM PDT 24 |
Peak memory | 257328 kb |
Host | smart-92ec5da4-92ed-415e-b11f-f47e3f407cc4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=927595338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.927595338 |
Directory | /workspace/3.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2357861967 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 28909064393 ps |
CPU time | 299.2 seconds |
Started | Jul 15 06:45:08 PM PDT 24 |
Finished | Jul 15 06:50:08 PM PDT 24 |
Peak memory | 265620 kb |
Host | smart-cd0f2c21-315d-4207-a64d-6a7abbee1771 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2357861967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle .2357861967 |
Directory | /workspace/3.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/3.spi_device_flash_mode.1932261081 |
Short name | T750 |
Test name | |
Test status | |
Simulation time | 1612654216 ps |
CPU time | 10.62 seconds |
Started | Jul 15 06:45:06 PM PDT 24 |
Finished | Jul 15 06:45:18 PM PDT 24 |
Peak memory | 224396 kb |
Host | smart-36ac321d-637e-4e28-9a0a-6744df309ab6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1932261081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1932261081 |
Directory | /workspace/3.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.614651148 |
Short name | T809 |
Test name | |
Test status | |
Simulation time | 1810930072 ps |
CPU time | 14.91 seconds |
Started | Jul 15 06:45:07 PM PDT 24 |
Finished | Jul 15 06:45:22 PM PDT 24 |
Peak memory | 224436 kb |
Host | smart-5444bfdf-1780-4ca2-8043-26772d79d9c4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=614651148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds. 614651148 |
Directory | /workspace/3.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/3.spi_device_intercept.553441046 |
Short name | T697 |
Test name | |
Test status | |
Simulation time | 179736639 ps |
CPU time | 2.6 seconds |
Started | Jul 15 06:45:10 PM PDT 24 |
Finished | Jul 15 06:45:14 PM PDT 24 |
Peak memory | 232552 kb |
Host | smart-78100856-8a46-4f38-9787-f6d0cf941afc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=553441046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.553441046 |
Directory | /workspace/3.spi_device_intercept/latest |
Test location | /workspace/coverage/default/3.spi_device_mailbox.734240696 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 1530664611 ps |
CPU time | 8.26 seconds |
Started | Jul 15 06:45:07 PM PDT 24 |
Finished | Jul 15 06:45:16 PM PDT 24 |
Peak memory | 224360 kb |
Host | smart-0566a0f3-e617-4f5e-8d2d-049fca54b4db |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=734240696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.734240696 |
Directory | /workspace/3.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2198746686 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 699673426 ps |
CPU time | 6.48 seconds |
Started | Jul 15 06:45:03 PM PDT 24 |
Finished | Jul 15 06:45:11 PM PDT 24 |
Peak memory | 224456 kb |
Host | smart-4e017638-8d69-4826-b523-c47ef62b12fc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2198746686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap .2198746686 |
Directory | /workspace/3.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/3.spi_device_pass_cmd_filtering.592078266 |
Short name | T770 |
Test name | |
Test status | |
Simulation time | 834749248 ps |
CPU time | 5.47 seconds |
Started | Jul 15 06:45:03 PM PDT 24 |
Finished | Jul 15 06:45:09 PM PDT 24 |
Peak memory | 232632 kb |
Host | smart-90fdb240-a536-4085-995d-976c566d1813 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=592078266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.592078266 |
Directory | /workspace/3.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/3.spi_device_read_buffer_direct.2787307769 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 2811952619 ps |
CPU time | 9.35 seconds |
Started | Jul 15 06:45:06 PM PDT 24 |
Finished | Jul 15 06:45:15 PM PDT 24 |
Peak memory | 221684 kb |
Host | smart-c497503d-d5fa-4aa2-b9a4-9e93b6195af9 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2787307769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire ct.2787307769 |
Directory | /workspace/3.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/3.spi_device_sec_cm.3233617762 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 86686868 ps |
CPU time | 1.24 seconds |
Started | Jul 15 06:45:09 PM PDT 24 |
Finished | Jul 15 06:45:12 PM PDT 24 |
Peak memory | 237540 kb |
Host | smart-74952d33-0799-4a09-9fa7-3af72edb7424 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233617762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3233617762 |
Directory | /workspace/3.spi_device_sec_cm/latest |
Test location | /workspace/coverage/default/3.spi_device_stress_all.2216971848 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 130026785 ps |
CPU time | 1.15 seconds |
Started | Jul 15 06:45:08 PM PDT 24 |
Finished | Jul 15 06:45:10 PM PDT 24 |
Peak memory | 207008 kb |
Host | smart-fdb22e33-3a12-444b-befb-bffaee651815 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216971848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres s_all.2216971848 |
Directory | /workspace/3.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/3.spi_device_tpm_all.3717794412 |
Short name | T832 |
Test name | |
Test status | |
Simulation time | 3978732260 ps |
CPU time | 23.59 seconds |
Started | Jul 15 06:45:02 PM PDT 24 |
Finished | Jul 15 06:45:26 PM PDT 24 |
Peak memory | 216328 kb |
Host | smart-4e1a6f07-a406-4b0a-b31c-937cbf7f02dd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3717794412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3717794412 |
Directory | /workspace/3.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1913583813 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 175947207 ps |
CPU time | 1.06 seconds |
Started | Jul 15 06:45:02 PM PDT 24 |
Finished | Jul 15 06:45:04 PM PDT 24 |
Peak memory | 207152 kb |
Host | smart-8b539d77-8d4a-4a24-abce-4ac616412682 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1913583813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1913583813 |
Directory | /workspace/3.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/3.spi_device_tpm_rw.4268814417 |
Short name | T604 |
Test name | |
Test status | |
Simulation time | 154157364 ps |
CPU time | 8.91 seconds |
Started | Jul 15 06:45:04 PM PDT 24 |
Finished | Jul 15 06:45:13 PM PDT 24 |
Peak memory | 216196 kb |
Host | smart-bd3576e5-0f92-4bf0-968d-a523f789e740 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4268814417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.4268814417 |
Directory | /workspace/3.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/3.spi_device_tpm_sts_read.2523371138 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 93071271 ps |
CPU time | 0.78 seconds |
Started | Jul 15 06:45:01 PM PDT 24 |
Finished | Jul 15 06:45:03 PM PDT 24 |
Peak memory | 205932 kb |
Host | smart-2a0e6c1a-c3bc-496a-93b4-684c107e47a3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2523371138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2523371138 |
Directory | /workspace/3.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/3.spi_device_upload.1842636848 |
Short name | T1002 |
Test name | |
Test status | |
Simulation time | 3028144973 ps |
CPU time | 5.69 seconds |
Started | Jul 15 06:45:07 PM PDT 24 |
Finished | Jul 15 06:45:13 PM PDT 24 |
Peak memory | 224492 kb |
Host | smart-388bacd3-66f3-4097-9fab-9ae59b0cafe9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1842636848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1842636848 |
Directory | /workspace/3.spi_device_upload/latest |
Test location | /workspace/coverage/default/30.spi_device_alert_test.34706507 |
Short name | T831 |
Test name | |
Test status | |
Simulation time | 12845672 ps |
CPU time | 0.71 seconds |
Started | Jul 15 06:49:06 PM PDT 24 |
Finished | Jul 15 06:49:07 PM PDT 24 |
Peak memory | 205500 kb |
Host | smart-a098d7fb-134d-4698-9efd-9333181f0e82 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34706507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.34706507 |
Directory | /workspace/30.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/30.spi_device_cfg_cmd.4249284736 |
Short name | T930 |
Test name | |
Test status | |
Simulation time | 453246470 ps |
CPU time | 3.21 seconds |
Started | Jul 15 06:48:59 PM PDT 24 |
Finished | Jul 15 06:49:03 PM PDT 24 |
Peak memory | 224560 kb |
Host | smart-865638c2-b08f-4ce2-9f27-815708233f23 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4249284736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.4249284736 |
Directory | /workspace/30.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/30.spi_device_csb_read.2366668625 |
Short name | T730 |
Test name | |
Test status | |
Simulation time | 20160478 ps |
CPU time | 0.82 seconds |
Started | Jul 15 06:48:57 PM PDT 24 |
Finished | Jul 15 06:48:58 PM PDT 24 |
Peak memory | 206548 kb |
Host | smart-60c70d31-a5a1-4824-b4e6-d70a4427777b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2366668625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2366668625 |
Directory | /workspace/30.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/30.spi_device_flash_all.2357077666 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 33639226580 ps |
CPU time | 93.16 seconds |
Started | Jul 15 06:48:58 PM PDT 24 |
Finished | Jul 15 06:50:31 PM PDT 24 |
Peak memory | 263864 kb |
Host | smart-573f9d25-9b44-432a-958d-23f0d74e25d0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2357077666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2357077666 |
Directory | /workspace/30.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/30.spi_device_flash_and_tpm.4286804462 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 4560523006 ps |
CPU time | 101.79 seconds |
Started | Jul 15 06:48:56 PM PDT 24 |
Finished | Jul 15 06:50:38 PM PDT 24 |
Peak memory | 265584 kb |
Host | smart-4c3dbc4b-f2ba-4ebb-8cc2-8c2e40959f89 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4286804462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.4286804462 |
Directory | /workspace/30.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3053384670 |
Short name | T937 |
Test name | |
Test status | |
Simulation time | 173528872310 ps |
CPU time | 169.37 seconds |
Started | Jul 15 06:48:59 PM PDT 24 |
Finished | Jul 15 06:51:49 PM PDT 24 |
Peak memory | 249204 kb |
Host | smart-e3a7ce91-3480-4213-a4c0-3228ccb05d68 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3053384670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl e.3053384670 |
Directory | /workspace/30.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/30.spi_device_flash_mode.3708004014 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 875277282 ps |
CPU time | 7.19 seconds |
Started | Jul 15 06:48:59 PM PDT 24 |
Finished | Jul 15 06:49:07 PM PDT 24 |
Peak memory | 240800 kb |
Host | smart-8ec95689-29ad-4866-ae64-3b311f1c48cf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3708004014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3708004014 |
Directory | /workspace/30.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.4029915281 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 21089989136 ps |
CPU time | 161.54 seconds |
Started | Jul 15 06:49:01 PM PDT 24 |
Finished | Jul 15 06:51:43 PM PDT 24 |
Peak memory | 253956 kb |
Host | smart-dd702e92-8740-4900-9ae3-c8a4a84b7d03 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4029915281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd s.4029915281 |
Directory | /workspace/30.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/30.spi_device_intercept.2727975378 |
Short name | T916 |
Test name | |
Test status | |
Simulation time | 102656173 ps |
CPU time | 3.07 seconds |
Started | Jul 15 06:49:00 PM PDT 24 |
Finished | Jul 15 06:49:04 PM PDT 24 |
Peak memory | 232584 kb |
Host | smart-50097987-6edf-4367-ab75-bbae08375d22 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2727975378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2727975378 |
Directory | /workspace/30.spi_device_intercept/latest |
Test location | /workspace/coverage/default/30.spi_device_mailbox.795602719 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 2474822184 ps |
CPU time | 45.43 seconds |
Started | Jul 15 06:48:59 PM PDT 24 |
Finished | Jul 15 06:49:45 PM PDT 24 |
Peak memory | 238260 kb |
Host | smart-9a78fe66-b218-461c-b0e9-315643ff7cf1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=795602719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.795602719 |
Directory | /workspace/30.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.4111510625 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 7299630069 ps |
CPU time | 25.54 seconds |
Started | Jul 15 06:48:59 PM PDT 24 |
Finished | Jul 15 06:49:25 PM PDT 24 |
Peak memory | 240900 kb |
Host | smart-a2eab546-d283-4023-ba4a-9e6d8db05783 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4111510625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa p.4111510625 |
Directory | /workspace/30.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/30.spi_device_pass_cmd_filtering.557435522 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 28802145005 ps |
CPU time | 13.44 seconds |
Started | Jul 15 06:49:00 PM PDT 24 |
Finished | Jul 15 06:49:14 PM PDT 24 |
Peak memory | 224588 kb |
Host | smart-717e58f4-3678-4710-97ef-ceb53b62d3a2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=557435522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.557435522 |
Directory | /workspace/30.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/30.spi_device_read_buffer_direct.2178866942 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 511308659 ps |
CPU time | 3.58 seconds |
Started | Jul 15 06:49:03 PM PDT 24 |
Finished | Jul 15 06:49:07 PM PDT 24 |
Peak memory | 220548 kb |
Host | smart-cd334223-1170-45ca-8599-e513802d38c9 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2178866942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir ect.2178866942 |
Directory | /workspace/30.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/30.spi_device_stress_all.1640861766 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 224312497685 ps |
CPU time | 565.26 seconds |
Started | Jul 15 06:48:55 PM PDT 24 |
Finished | Jul 15 06:58:21 PM PDT 24 |
Peak memory | 273480 kb |
Host | smart-2220f94c-9ff1-4ad2-bff8-44b54355dc34 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640861766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre ss_all.1640861766 |
Directory | /workspace/30.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/30.spi_device_tpm_all.1530849005 |
Short name | T954 |
Test name | |
Test status | |
Simulation time | 104318871702 ps |
CPU time | 27.62 seconds |
Started | Jul 15 06:49:02 PM PDT 24 |
Finished | Jul 15 06:49:30 PM PDT 24 |
Peak memory | 216364 kb |
Host | smart-e2035c0c-9780-4ce8-8ae9-30e5dfaaa021 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1530849005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1530849005 |
Directory | /workspace/30.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2556208451 |
Short name | T497 |
Test name | |
Test status | |
Simulation time | 441432376 ps |
CPU time | 2.67 seconds |
Started | Jul 15 06:48:58 PM PDT 24 |
Finished | Jul 15 06:49:01 PM PDT 24 |
Peak memory | 216084 kb |
Host | smart-acedc62e-3437-4b4d-89db-f6fc7bbac826 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2556208451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2556208451 |
Directory | /workspace/30.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/30.spi_device_tpm_rw.2356537946 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 544087775 ps |
CPU time | 2.96 seconds |
Started | Jul 15 06:49:00 PM PDT 24 |
Finished | Jul 15 06:49:03 PM PDT 24 |
Peak memory | 216196 kb |
Host | smart-564054b3-2a4d-49ac-be8f-4bbfb12ca4df |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2356537946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2356537946 |
Directory | /workspace/30.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/30.spi_device_tpm_sts_read.1978173865 |
Short name | T692 |
Test name | |
Test status | |
Simulation time | 127796280 ps |
CPU time | 0.76 seconds |
Started | Jul 15 06:48:57 PM PDT 24 |
Finished | Jul 15 06:48:58 PM PDT 24 |
Peak memory | 206092 kb |
Host | smart-cbdbe1ef-f222-4e8f-9d90-ca9e1da18f85 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1978173865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1978173865 |
Directory | /workspace/30.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/30.spi_device_upload.576842076 |
Short name | T918 |
Test name | |
Test status | |
Simulation time | 12659289024 ps |
CPU time | 16.49 seconds |
Started | Jul 15 06:48:59 PM PDT 24 |
Finished | Jul 15 06:49:15 PM PDT 24 |
Peak memory | 224524 kb |
Host | smart-5663049b-45f3-4af0-bcb2-c7a18a09600d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=576842076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.576842076 |
Directory | /workspace/30.spi_device_upload/latest |
Test location | /workspace/coverage/default/31.spi_device_alert_test.2243208893 |
Short name | T593 |
Test name | |
Test status | |
Simulation time | 86746376 ps |
CPU time | 0.78 seconds |
Started | Jul 15 06:49:18 PM PDT 24 |
Finished | Jul 15 06:49:20 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-6f984797-2c55-4380-9d07-af7fd372283e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243208893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test. 2243208893 |
Directory | /workspace/31.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/31.spi_device_cfg_cmd.2521174442 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 97879014 ps |
CPU time | 3.76 seconds |
Started | Jul 15 06:49:03 PM PDT 24 |
Finished | Jul 15 06:49:07 PM PDT 24 |
Peak memory | 232628 kb |
Host | smart-ba4bbab0-1fd1-48ed-a3e9-855dff10b0be |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2521174442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2521174442 |
Directory | /workspace/31.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/31.spi_device_csb_read.3305143779 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 32624955 ps |
CPU time | 0.79 seconds |
Started | Jul 15 06:49:07 PM PDT 24 |
Finished | Jul 15 06:49:08 PM PDT 24 |
Peak memory | 206828 kb |
Host | smart-4b9e5752-832a-4afd-a3f0-aabcd9cfe13d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3305143779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3305143779 |
Directory | /workspace/31.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/31.spi_device_flash_all.2536674084 |
Short name | T747 |
Test name | |
Test status | |
Simulation time | 45595961946 ps |
CPU time | 340.85 seconds |
Started | Jul 15 06:49:06 PM PDT 24 |
Finished | Jul 15 06:54:47 PM PDT 24 |
Peak memory | 256720 kb |
Host | smart-240b4572-6557-41d1-9b07-3d62749472a0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2536674084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2536674084 |
Directory | /workspace/31.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/31.spi_device_flash_and_tpm.177183137 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 26729155366 ps |
CPU time | 146.49 seconds |
Started | Jul 15 06:49:10 PM PDT 24 |
Finished | Jul 15 06:51:37 PM PDT 24 |
Peak memory | 249220 kb |
Host | smart-08c74ab4-98ff-43a2-ae71-4c80904bc51c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=177183137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.177183137 |
Directory | /workspace/31.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2377483101 |
Short name | T988 |
Test name | |
Test status | |
Simulation time | 18632892062 ps |
CPU time | 99.15 seconds |
Started | Jul 15 06:49:12 PM PDT 24 |
Finished | Jul 15 06:50:52 PM PDT 24 |
Peak memory | 234016 kb |
Host | smart-69f8bf3d-b4b2-409b-bc84-6a68f64953cb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2377483101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl e.2377483101 |
Directory | /workspace/31.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/31.spi_device_flash_mode.578679725 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 2727215158 ps |
CPU time | 38.12 seconds |
Started | Jul 15 06:49:04 PM PDT 24 |
Finished | Jul 15 06:49:42 PM PDT 24 |
Peak memory | 240952 kb |
Host | smart-c5af2219-368a-4f03-a27b-9938ed0da582 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=578679725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.578679725 |
Directory | /workspace/31.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.65459906 |
Short name | T1006 |
Test name | |
Test status | |
Simulation time | 36702343475 ps |
CPU time | 133.31 seconds |
Started | Jul 15 06:49:09 PM PDT 24 |
Finished | Jul 15 06:51:23 PM PDT 24 |
Peak memory | 250964 kb |
Host | smart-27f21f75-ca60-4f8e-88ac-f228b3925528 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=65459906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds.65459906 |
Directory | /workspace/31.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/31.spi_device_intercept.3543114001 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 28023671 ps |
CPU time | 2.51 seconds |
Started | Jul 15 06:49:06 PM PDT 24 |
Finished | Jul 15 06:49:08 PM PDT 24 |
Peak memory | 232300 kb |
Host | smart-fe77dfee-c199-4d9a-8185-35ad64fd881a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3543114001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3543114001 |
Directory | /workspace/31.spi_device_intercept/latest |
Test location | /workspace/coverage/default/31.spi_device_mailbox.3258419810 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 683920879 ps |
CPU time | 5.88 seconds |
Started | Jul 15 06:49:03 PM PDT 24 |
Finished | Jul 15 06:49:10 PM PDT 24 |
Peak memory | 232672 kb |
Host | smart-cb89def3-2f59-43ad-a6a4-d0dea07def27 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3258419810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3258419810 |
Directory | /workspace/31.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2182571794 |
Short name | T771 |
Test name | |
Test status | |
Simulation time | 3222256945 ps |
CPU time | 6.02 seconds |
Started | Jul 15 06:49:05 PM PDT 24 |
Finished | Jul 15 06:49:11 PM PDT 24 |
Peak memory | 232636 kb |
Host | smart-609a190f-e022-429f-b2be-014f4ebaead8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2182571794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa p.2182571794 |
Directory | /workspace/31.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2897674978 |
Short name | T724 |
Test name | |
Test status | |
Simulation time | 156370442 ps |
CPU time | 3.51 seconds |
Started | Jul 15 06:49:05 PM PDT 24 |
Finished | Jul 15 06:49:09 PM PDT 24 |
Peak memory | 232636 kb |
Host | smart-68c34abf-7dfd-4ccf-89d2-f536a53e0c9f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2897674978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2897674978 |
Directory | /workspace/31.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/31.spi_device_read_buffer_direct.3950642142 |
Short name | T852 |
Test name | |
Test status | |
Simulation time | 296531210 ps |
CPU time | 6.7 seconds |
Started | Jul 15 06:49:06 PM PDT 24 |
Finished | Jul 15 06:49:13 PM PDT 24 |
Peak memory | 222536 kb |
Host | smart-7ec65389-0c72-49e1-82df-37b1a1cfee77 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3950642142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir ect.3950642142 |
Directory | /workspace/31.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/31.spi_device_stress_all.677612408 |
Short name | T859 |
Test name | |
Test status | |
Simulation time | 8856111131 ps |
CPU time | 98.18 seconds |
Started | Jul 15 06:49:18 PM PDT 24 |
Finished | Jul 15 06:50:57 PM PDT 24 |
Peak memory | 271120 kb |
Host | smart-10e94511-56e0-4322-93ab-499c6ee47d6c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677612408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres s_all.677612408 |
Directory | /workspace/31.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/31.spi_device_tpm_all.1901811117 |
Short name | T878 |
Test name | |
Test status | |
Simulation time | 21539296434 ps |
CPU time | 30.67 seconds |
Started | Jul 15 06:49:02 PM PDT 24 |
Finished | Jul 15 06:49:33 PM PDT 24 |
Peak memory | 216260 kb |
Host | smart-6ce518ba-0732-4a6e-915e-b6fff0c9adf7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1901811117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1901811117 |
Directory | /workspace/31.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2464671254 |
Short name | T871 |
Test name | |
Test status | |
Simulation time | 6250320448 ps |
CPU time | 5.38 seconds |
Started | Jul 15 06:49:08 PM PDT 24 |
Finished | Jul 15 06:49:14 PM PDT 24 |
Peak memory | 216492 kb |
Host | smart-6ec220aa-3039-4ec4-bfe3-a4bf7e5220f1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2464671254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2464671254 |
Directory | /workspace/31.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/31.spi_device_tpm_rw.1913270715 |
Short name | T946 |
Test name | |
Test status | |
Simulation time | 88317559 ps |
CPU time | 0.99 seconds |
Started | Jul 15 06:49:07 PM PDT 24 |
Finished | Jul 15 06:49:08 PM PDT 24 |
Peak memory | 207000 kb |
Host | smart-b1cbe9e5-0719-41ff-82d1-c314811aedda |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1913270715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1913270715 |
Directory | /workspace/31.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/31.spi_device_tpm_sts_read.4067637106 |
Short name | T574 |
Test name | |
Test status | |
Simulation time | 49198688 ps |
CPU time | 0.78 seconds |
Started | Jul 15 06:49:17 PM PDT 24 |
Finished | Jul 15 06:49:18 PM PDT 24 |
Peak memory | 205936 kb |
Host | smart-e55cdc05-4048-4d6f-b35e-9c86b71358d9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4067637106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.4067637106 |
Directory | /workspace/31.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/31.spi_device_upload.4166291103 |
Short name | T806 |
Test name | |
Test status | |
Simulation time | 841296435 ps |
CPU time | 7.94 seconds |
Started | Jul 15 06:49:05 PM PDT 24 |
Finished | Jul 15 06:49:13 PM PDT 24 |
Peak memory | 239512 kb |
Host | smart-4365c37f-cb7f-4bc8-adf9-8a6405dd8a1f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4166291103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.4166291103 |
Directory | /workspace/31.spi_device_upload/latest |
Test location | /workspace/coverage/default/32.spi_device_alert_test.3345732143 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 11859404 ps |
CPU time | 0.7 seconds |
Started | Jul 15 06:49:18 PM PDT 24 |
Finished | Jul 15 06:49:19 PM PDT 24 |
Peak memory | 205456 kb |
Host | smart-c860de67-a263-4956-af66-f748fda8a166 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345732143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test. 3345732143 |
Directory | /workspace/32.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/32.spi_device_cfg_cmd.1834833104 |
Short name | T889 |
Test name | |
Test status | |
Simulation time | 1004970233 ps |
CPU time | 4.29 seconds |
Started | Jul 15 06:49:11 PM PDT 24 |
Finished | Jul 15 06:49:16 PM PDT 24 |
Peak memory | 232520 kb |
Host | smart-4b4c3dbc-fc77-46dd-89ca-a54d72f27b4f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1834833104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1834833104 |
Directory | /workspace/32.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/32.spi_device_csb_read.1463349608 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 26187310 ps |
CPU time | 0.75 seconds |
Started | Jul 15 06:49:12 PM PDT 24 |
Finished | Jul 15 06:49:13 PM PDT 24 |
Peak memory | 205844 kb |
Host | smart-596db1f0-7f3e-4269-aab9-b54971a3e52c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1463349608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1463349608 |
Directory | /workspace/32.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/32.spi_device_flash_all.2979835915 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 6457480355 ps |
CPU time | 40.97 seconds |
Started | Jul 15 06:49:10 PM PDT 24 |
Finished | Jul 15 06:49:52 PM PDT 24 |
Peak memory | 254288 kb |
Host | smart-22f38891-405b-4afd-9a7d-2e4bc7b75765 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2979835915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2979835915 |
Directory | /workspace/32.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/32.spi_device_flash_and_tpm.1592045208 |
Short name | T603 |
Test name | |
Test status | |
Simulation time | 11013898841 ps |
CPU time | 43.95 seconds |
Started | Jul 15 06:49:15 PM PDT 24 |
Finished | Jul 15 06:50:00 PM PDT 24 |
Peak memory | 240968 kb |
Host | smart-887631c1-dd62-4bec-b08b-3ab145795af7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1592045208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1592045208 |
Directory | /workspace/32.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3516655950 |
Short name | T623 |
Test name | |
Test status | |
Simulation time | 11072894125 ps |
CPU time | 26.02 seconds |
Started | Jul 15 06:49:18 PM PDT 24 |
Finished | Jul 15 06:49:45 PM PDT 24 |
Peak memory | 240936 kb |
Host | smart-807dd79a-d8d8-4798-8d1f-999ceda9d089 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3516655950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl e.3516655950 |
Directory | /workspace/32.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/32.spi_device_flash_mode.903180875 |
Short name | T616 |
Test name | |
Test status | |
Simulation time | 1233206350 ps |
CPU time | 9.52 seconds |
Started | Jul 15 06:49:11 PM PDT 24 |
Finished | Jul 15 06:49:21 PM PDT 24 |
Peak memory | 235156 kb |
Host | smart-e942d2b6-fc58-4618-a351-815482d450dd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=903180875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.903180875 |
Directory | /workspace/32.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.1684834686 |
Short name | T816 |
Test name | |
Test status | |
Simulation time | 4143642785 ps |
CPU time | 13.01 seconds |
Started | Jul 15 06:49:18 PM PDT 24 |
Finished | Jul 15 06:49:32 PM PDT 24 |
Peak memory | 235116 kb |
Host | smart-452a2a7a-56e4-4898-b8cd-6aa9e695adf2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1684834686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd s.1684834686 |
Directory | /workspace/32.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/32.spi_device_intercept.125854459 |
Short name | T964 |
Test name | |
Test status | |
Simulation time | 188441401 ps |
CPU time | 4.22 seconds |
Started | Jul 15 06:49:13 PM PDT 24 |
Finished | Jul 15 06:49:18 PM PDT 24 |
Peak memory | 224460 kb |
Host | smart-e9aa3fd5-790c-4cb9-897b-8d28a7180a15 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=125854459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.125854459 |
Directory | /workspace/32.spi_device_intercept/latest |
Test location | /workspace/coverage/default/32.spi_device_mailbox.3370119198 |
Short name | T715 |
Test name | |
Test status | |
Simulation time | 36616820 ps |
CPU time | 2.4 seconds |
Started | Jul 15 06:49:10 PM PDT 24 |
Finished | Jul 15 06:49:13 PM PDT 24 |
Peak memory | 232288 kb |
Host | smart-662252ad-ddfc-46d1-bb9f-46eb0bb9e9c3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3370119198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3370119198 |
Directory | /workspace/32.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2859832944 |
Short name | T856 |
Test name | |
Test status | |
Simulation time | 44425931542 ps |
CPU time | 30.76 seconds |
Started | Jul 15 06:49:12 PM PDT 24 |
Finished | Jul 15 06:49:44 PM PDT 24 |
Peak memory | 240900 kb |
Host | smart-7e3bb8ca-d7fe-4fe9-a779-b9c481bea7a6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2859832944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa p.2859832944 |
Directory | /workspace/32.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1502206237 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 552614636 ps |
CPU time | 4.3 seconds |
Started | Jul 15 06:49:11 PM PDT 24 |
Finished | Jul 15 06:49:16 PM PDT 24 |
Peak memory | 232668 kb |
Host | smart-fff5a82d-a743-46e3-9a41-9cdac24a5c6f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1502206237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1502206237 |
Directory | /workspace/32.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/32.spi_device_read_buffer_direct.257110894 |
Short name | T683 |
Test name | |
Test status | |
Simulation time | 2928835229 ps |
CPU time | 13.74 seconds |
Started | Jul 15 06:49:18 PM PDT 24 |
Finished | Jul 15 06:49:33 PM PDT 24 |
Peak memory | 219332 kb |
Host | smart-38dca980-1655-4419-bc78-c454f1062a1c |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=257110894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire ct.257110894 |
Directory | /workspace/32.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/32.spi_device_tpm_all.2656970803 |
Short name | T555 |
Test name | |
Test status | |
Simulation time | 2433278537 ps |
CPU time | 17.43 seconds |
Started | Jul 15 06:49:11 PM PDT 24 |
Finished | Jul 15 06:49:29 PM PDT 24 |
Peak memory | 216332 kb |
Host | smart-6373e1e9-0623-482d-babf-7e889e1928b5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2656970803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2656970803 |
Directory | /workspace/32.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3427569637 |
Short name | T776 |
Test name | |
Test status | |
Simulation time | 727290137 ps |
CPU time | 2.35 seconds |
Started | Jul 15 06:49:18 PM PDT 24 |
Finished | Jul 15 06:49:21 PM PDT 24 |
Peak memory | 216192 kb |
Host | smart-ba4ff6e5-80b3-44b6-98f2-8a599122c7e4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3427569637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3427569637 |
Directory | /workspace/32.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/32.spi_device_tpm_rw.2507468926 |
Short name | T568 |
Test name | |
Test status | |
Simulation time | 143237640 ps |
CPU time | 1.32 seconds |
Started | Jul 15 06:49:11 PM PDT 24 |
Finished | Jul 15 06:49:13 PM PDT 24 |
Peak memory | 216124 kb |
Host | smart-e2642d7e-890d-411c-a9d2-e9734e5e103f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2507468926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2507468926 |
Directory | /workspace/32.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/32.spi_device_tpm_sts_read.4097602584 |
Short name | T833 |
Test name | |
Test status | |
Simulation time | 85000263 ps |
CPU time | 0.81 seconds |
Started | Jul 15 06:49:12 PM PDT 24 |
Finished | Jul 15 06:49:13 PM PDT 24 |
Peak memory | 205924 kb |
Host | smart-fd8998ea-2396-4f20-a1a9-2335dddf24d9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4097602584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.4097602584 |
Directory | /workspace/32.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/32.spi_device_upload.4034815757 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 1809197409 ps |
CPU time | 2.69 seconds |
Started | Jul 15 06:49:18 PM PDT 24 |
Finished | Jul 15 06:49:22 PM PDT 24 |
Peak memory | 224428 kb |
Host | smart-d848ebf1-c6b7-4e17-b5ab-b9ad2f526877 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4034815757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.4034815757 |
Directory | /workspace/32.spi_device_upload/latest |
Test location | /workspace/coverage/default/33.spi_device_alert_test.3598876246 |
Short name | T586 |
Test name | |
Test status | |
Simulation time | 147159110 ps |
CPU time | 0.71 seconds |
Started | Jul 15 06:49:24 PM PDT 24 |
Finished | Jul 15 06:49:25 PM PDT 24 |
Peak memory | 205472 kb |
Host | smart-cbfa262f-4d0e-4c4f-bdb3-6438b2ce4300 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598876246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test. 3598876246 |
Directory | /workspace/33.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/33.spi_device_cfg_cmd.2735098840 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 582949430 ps |
CPU time | 3.91 seconds |
Started | Jul 15 06:49:16 PM PDT 24 |
Finished | Jul 15 06:49:21 PM PDT 24 |
Peak memory | 232636 kb |
Host | smart-c8a57a3d-5162-4fae-b388-228145b7574c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2735098840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2735098840 |
Directory | /workspace/33.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/33.spi_device_csb_read.498691148 |
Short name | T658 |
Test name | |
Test status | |
Simulation time | 61314566 ps |
CPU time | 0.77 seconds |
Started | Jul 15 06:49:15 PM PDT 24 |
Finished | Jul 15 06:49:17 PM PDT 24 |
Peak memory | 206532 kb |
Host | smart-b8a7c6bd-b045-43d5-afad-78f1f51f1512 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=498691148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.498691148 |
Directory | /workspace/33.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/33.spi_device_flash_all.1306823003 |
Short name | T963 |
Test name | |
Test status | |
Simulation time | 5152756097 ps |
CPU time | 88.97 seconds |
Started | Jul 15 06:49:24 PM PDT 24 |
Finished | Jul 15 06:50:54 PM PDT 24 |
Peak memory | 257340 kb |
Host | smart-6fe62182-3ed2-498b-9648-140e910b0a7f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1306823003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1306823003 |
Directory | /workspace/33.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/33.spi_device_flash_and_tpm.3555793437 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 112833110676 ps |
CPU time | 331.2 seconds |
Started | Jul 15 06:49:22 PM PDT 24 |
Finished | Jul 15 06:54:53 PM PDT 24 |
Peak memory | 257328 kb |
Host | smart-dcdb6508-4b6d-4fde-8b90-d20bf10e9cb7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3555793437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3555793437 |
Directory | /workspace/33.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3270418222 |
Short name | T896 |
Test name | |
Test status | |
Simulation time | 20139401867 ps |
CPU time | 106.12 seconds |
Started | Jul 15 06:49:22 PM PDT 24 |
Finished | Jul 15 06:51:08 PM PDT 24 |
Peak memory | 256312 kb |
Host | smart-d5c4558c-2990-4335-8ee6-56884ee2533f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3270418222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl e.3270418222 |
Directory | /workspace/33.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/33.spi_device_flash_mode.255935608 |
Short name | T767 |
Test name | |
Test status | |
Simulation time | 354507357 ps |
CPU time | 5.08 seconds |
Started | Jul 15 06:49:17 PM PDT 24 |
Finished | Jul 15 06:49:23 PM PDT 24 |
Peak memory | 237472 kb |
Host | smart-5dca9b7c-b133-444d-8e72-17ca441cb8c6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=255935608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.255935608 |
Directory | /workspace/33.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.3057676952 |
Short name | T982 |
Test name | |
Test status | |
Simulation time | 643173016221 ps |
CPU time | 473.22 seconds |
Started | Jul 15 06:49:24 PM PDT 24 |
Finished | Jul 15 06:57:18 PM PDT 24 |
Peak memory | 266448 kb |
Host | smart-7ad8342d-e65c-4b37-a4c9-6cf1ec762275 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3057676952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd s.3057676952 |
Directory | /workspace/33.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/33.spi_device_intercept.2204444781 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 2973045659 ps |
CPU time | 3.47 seconds |
Started | Jul 15 06:49:15 PM PDT 24 |
Finished | Jul 15 06:49:19 PM PDT 24 |
Peak memory | 224504 kb |
Host | smart-a40d242a-6516-4875-bff8-51511cf90cea |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2204444781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2204444781 |
Directory | /workspace/33.spi_device_intercept/latest |
Test location | /workspace/coverage/default/33.spi_device_mailbox.2335120680 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 4083368635 ps |
CPU time | 36.55 seconds |
Started | Jul 15 06:49:17 PM PDT 24 |
Finished | Jul 15 06:49:54 PM PDT 24 |
Peak memory | 224452 kb |
Host | smart-83079619-454f-45e7-9d54-e11c424163ce |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2335120680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2335120680 |
Directory | /workspace/33.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.78769771 |
Short name | T646 |
Test name | |
Test status | |
Simulation time | 3768851918 ps |
CPU time | 7.55 seconds |
Started | Jul 15 06:49:18 PM PDT 24 |
Finished | Jul 15 06:49:26 PM PDT 24 |
Peak memory | 232756 kb |
Host | smart-d83bf311-04db-4000-8779-3be59f71591f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=78769771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap.78769771 |
Directory | /workspace/33.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1023313173 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 407214189 ps |
CPU time | 8.76 seconds |
Started | Jul 15 06:49:14 PM PDT 24 |
Finished | Jul 15 06:49:23 PM PDT 24 |
Peak memory | 240368 kb |
Host | smart-3f657b14-160f-476d-92bd-7534f9951ace |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1023313173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1023313173 |
Directory | /workspace/33.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/33.spi_device_read_buffer_direct.1488118063 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 756643306 ps |
CPU time | 4.64 seconds |
Started | Jul 15 06:49:21 PM PDT 24 |
Finished | Jul 15 06:49:27 PM PDT 24 |
Peak memory | 219844 kb |
Host | smart-ec96d411-efc5-4d7d-a50c-af3cbc433b4a |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1488118063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir ect.1488118063 |
Directory | /workspace/33.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/33.spi_device_stress_all.684436674 |
Short name | T820 |
Test name | |
Test status | |
Simulation time | 78250157129 ps |
CPU time | 206.3 seconds |
Started | Jul 15 06:49:21 PM PDT 24 |
Finished | Jul 15 06:52:48 PM PDT 24 |
Peak memory | 264288 kb |
Host | smart-819bb3e4-ce38-43e4-833f-37b2d8fb7bf6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684436674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres s_all.684436674 |
Directory | /workspace/33.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/33.spi_device_tpm_all.3010514737 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 5545800201 ps |
CPU time | 11.08 seconds |
Started | Jul 15 06:49:19 PM PDT 24 |
Finished | Jul 15 06:49:31 PM PDT 24 |
Peak memory | 216416 kb |
Host | smart-a9a08628-4471-48cf-9829-c9161e1c0cdc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3010514737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3010514737 |
Directory | /workspace/33.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3283177156 |
Short name | T469 |
Test name | |
Test status | |
Simulation time | 3192360635 ps |
CPU time | 5.54 seconds |
Started | Jul 15 06:49:19 PM PDT 24 |
Finished | Jul 15 06:49:25 PM PDT 24 |
Peak memory | 216256 kb |
Host | smart-766ed6b8-2aa8-4741-898f-95c586f39af5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3283177156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3283177156 |
Directory | /workspace/33.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/33.spi_device_tpm_rw.2156941540 |
Short name | T844 |
Test name | |
Test status | |
Simulation time | 74395282 ps |
CPU time | 1.11 seconds |
Started | Jul 15 06:49:17 PM PDT 24 |
Finished | Jul 15 06:49:19 PM PDT 24 |
Peak memory | 216064 kb |
Host | smart-ee272c66-ab02-4d2c-8790-e4757a9af162 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2156941540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2156941540 |
Directory | /workspace/33.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/33.spi_device_tpm_sts_read.2794760778 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 439069432 ps |
CPU time | 1.11 seconds |
Started | Jul 15 06:49:15 PM PDT 24 |
Finished | Jul 15 06:49:17 PM PDT 24 |
Peak memory | 206912 kb |
Host | smart-8bd8b456-be02-4ec6-96b6-3387a55931bb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2794760778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2794760778 |
Directory | /workspace/33.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/33.spi_device_upload.3718899886 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 3465670314 ps |
CPU time | 10.55 seconds |
Started | Jul 15 06:49:18 PM PDT 24 |
Finished | Jul 15 06:49:29 PM PDT 24 |
Peak memory | 224588 kb |
Host | smart-82cf823a-64af-4184-a7d5-dd53a64ba42b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3718899886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3718899886 |
Directory | /workspace/33.spi_device_upload/latest |
Test location | /workspace/coverage/default/34.spi_device_alert_test.2563836408 |
Short name | T708 |
Test name | |
Test status | |
Simulation time | 37758745 ps |
CPU time | 0.79 seconds |
Started | Jul 15 06:49:31 PM PDT 24 |
Finished | Jul 15 06:49:32 PM PDT 24 |
Peak memory | 205800 kb |
Host | smart-7d1ecd46-d464-47ed-a4f2-374188d6c88b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563836408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test. 2563836408 |
Directory | /workspace/34.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/34.spi_device_cfg_cmd.3806068816 |
Short name | T537 |
Test name | |
Test status | |
Simulation time | 55361906 ps |
CPU time | 2.71 seconds |
Started | Jul 15 06:49:30 PM PDT 24 |
Finished | Jul 15 06:49:34 PM PDT 24 |
Peak memory | 232600 kb |
Host | smart-949a8b8a-73b3-4a46-b560-519362f24ba6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3806068816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3806068816 |
Directory | /workspace/34.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/34.spi_device_csb_read.1524513494 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 23529221 ps |
CPU time | 0.76 seconds |
Started | Jul 15 06:49:22 PM PDT 24 |
Finished | Jul 15 06:49:24 PM PDT 24 |
Peak memory | 205864 kb |
Host | smart-b50510d1-bc96-4d43-9c9b-dfa428833734 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1524513494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1524513494 |
Directory | /workspace/34.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/34.spi_device_flash_all.3640674201 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 5465143640 ps |
CPU time | 24.86 seconds |
Started | Jul 15 06:49:31 PM PDT 24 |
Finished | Jul 15 06:49:57 PM PDT 24 |
Peak memory | 232676 kb |
Host | smart-950cb7a9-d609-4b2e-9701-1456198237d7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3640674201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3640674201 |
Directory | /workspace/34.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/34.spi_device_flash_mode.4173639004 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 91379074 ps |
CPU time | 2.68 seconds |
Started | Jul 15 06:49:30 PM PDT 24 |
Finished | Jul 15 06:49:33 PM PDT 24 |
Peak memory | 224436 kb |
Host | smart-488a01e8-3348-41ff-9a2d-1af4a89c5d50 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4173639004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.4173639004 |
Directory | /workspace/34.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.1511668032 |
Short name | T563 |
Test name | |
Test status | |
Simulation time | 32878319689 ps |
CPU time | 78.03 seconds |
Started | Jul 15 06:49:30 PM PDT 24 |
Finished | Jul 15 06:50:49 PM PDT 24 |
Peak memory | 240912 kb |
Host | smart-32119536-8403-4248-ad58-8ce1e52be1be |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1511668032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd s.1511668032 |
Directory | /workspace/34.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/34.spi_device_intercept.3708663264 |
Short name | T802 |
Test name | |
Test status | |
Simulation time | 86839725 ps |
CPU time | 2.5 seconds |
Started | Jul 15 06:49:21 PM PDT 24 |
Finished | Jul 15 06:49:23 PM PDT 24 |
Peak memory | 218684 kb |
Host | smart-9c7aa3cb-0517-4879-b009-c0596de8ce8a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3708663264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3708663264 |
Directory | /workspace/34.spi_device_intercept/latest |
Test location | /workspace/coverage/default/34.spi_device_mailbox.2204699613 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 4689606385 ps |
CPU time | 59.41 seconds |
Started | Jul 15 06:49:23 PM PDT 24 |
Finished | Jul 15 06:50:23 PM PDT 24 |
Peak memory | 232712 kb |
Host | smart-20f7b624-2ea5-4f79-bf7a-fec8276fd69d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2204699613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2204699613 |
Directory | /workspace/34.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1793800052 |
Short name | T484 |
Test name | |
Test status | |
Simulation time | 2295665618 ps |
CPU time | 3.53 seconds |
Started | Jul 15 06:49:20 PM PDT 24 |
Finished | Jul 15 06:49:24 PM PDT 24 |
Peak memory | 232696 kb |
Host | smart-fe729eb9-a9f0-45c8-a4f7-a022ef30cb0c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1793800052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa p.1793800052 |
Directory | /workspace/34.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3455369509 |
Short name | T544 |
Test name | |
Test status | |
Simulation time | 2915500515 ps |
CPU time | 11.21 seconds |
Started | Jul 15 06:49:22 PM PDT 24 |
Finished | Jul 15 06:49:34 PM PDT 24 |
Peak memory | 224548 kb |
Host | smart-94e52eac-e147-4b3f-be92-6414e2b0b6b4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3455369509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3455369509 |
Directory | /workspace/34.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/34.spi_device_read_buffer_direct.3480399764 |
Short name | T611 |
Test name | |
Test status | |
Simulation time | 4913196354 ps |
CPU time | 10.75 seconds |
Started | Jul 15 06:49:31 PM PDT 24 |
Finished | Jul 15 06:49:42 PM PDT 24 |
Peak memory | 222184 kb |
Host | smart-e20cd45d-52b1-471d-9c6c-4afb8d471af2 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3480399764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir ect.3480399764 |
Directory | /workspace/34.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/34.spi_device_tpm_all.2289638215 |
Short name | T842 |
Test name | |
Test status | |
Simulation time | 29356494540 ps |
CPU time | 38.59 seconds |
Started | Jul 15 06:49:19 PM PDT 24 |
Finished | Jul 15 06:49:58 PM PDT 24 |
Peak memory | 216280 kb |
Host | smart-65bc1bad-ad60-4f8c-ac11-889228fe44bb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2289638215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2289638215 |
Directory | /workspace/34.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1985235476 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 2038890784 ps |
CPU time | 4.6 seconds |
Started | Jul 15 06:49:24 PM PDT 24 |
Finished | Jul 15 06:49:29 PM PDT 24 |
Peak memory | 216208 kb |
Host | smart-c2f4591f-5953-403c-be13-2abe8aff07d7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1985235476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1985235476 |
Directory | /workspace/34.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/34.spi_device_tpm_rw.431967909 |
Short name | T962 |
Test name | |
Test status | |
Simulation time | 372337862 ps |
CPU time | 1.71 seconds |
Started | Jul 15 06:49:24 PM PDT 24 |
Finished | Jul 15 06:49:26 PM PDT 24 |
Peak memory | 216152 kb |
Host | smart-000f4673-d337-4a4d-af32-911a502aa2bf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=431967909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.431967909 |
Directory | /workspace/34.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/34.spi_device_tpm_sts_read.3411762031 |
Short name | T530 |
Test name | |
Test status | |
Simulation time | 178865595 ps |
CPU time | 0.83 seconds |
Started | Jul 15 06:49:23 PM PDT 24 |
Finished | Jul 15 06:49:24 PM PDT 24 |
Peak memory | 205872 kb |
Host | smart-939ada59-4930-44c5-b18d-1ac2032a9ff0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3411762031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3411762031 |
Directory | /workspace/34.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/34.spi_device_upload.4181705887 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 2863546456 ps |
CPU time | 10.79 seconds |
Started | Jul 15 06:49:31 PM PDT 24 |
Finished | Jul 15 06:49:42 PM PDT 24 |
Peak memory | 239352 kb |
Host | smart-fc3578c1-1a69-477d-9269-bf57b64d2a0d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4181705887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.4181705887 |
Directory | /workspace/34.spi_device_upload/latest |
Test location | /workspace/coverage/default/35.spi_device_alert_test.2115586073 |
Short name | T849 |
Test name | |
Test status | |
Simulation time | 82492344 ps |
CPU time | 0.73 seconds |
Started | Jul 15 06:49:37 PM PDT 24 |
Finished | Jul 15 06:49:40 PM PDT 24 |
Peak memory | 205516 kb |
Host | smart-ffa69484-15a1-487c-bf1e-c057ec4d0712 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115586073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test. 2115586073 |
Directory | /workspace/35.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/35.spi_device_cfg_cmd.3228481015 |
Short name | T624 |
Test name | |
Test status | |
Simulation time | 37465086 ps |
CPU time | 2.54 seconds |
Started | Jul 15 06:49:38 PM PDT 24 |
Finished | Jul 15 06:49:43 PM PDT 24 |
Peak memory | 232592 kb |
Host | smart-089d33b5-6595-4a73-8a65-b42d20c5294e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3228481015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3228481015 |
Directory | /workspace/35.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/35.spi_device_csb_read.1176396598 |
Short name | T972 |
Test name | |
Test status | |
Simulation time | 17442358 ps |
CPU time | 0.77 seconds |
Started | Jul 15 06:49:29 PM PDT 24 |
Finished | Jul 15 06:49:30 PM PDT 24 |
Peak memory | 205836 kb |
Host | smart-b3de13f7-6b1f-4b96-92bb-057401852dd7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1176396598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1176396598 |
Directory | /workspace/35.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/35.spi_device_flash_all.1132213412 |
Short name | T679 |
Test name | |
Test status | |
Simulation time | 63443389731 ps |
CPU time | 207.5 seconds |
Started | Jul 15 06:49:38 PM PDT 24 |
Finished | Jul 15 06:53:07 PM PDT 24 |
Peak memory | 249148 kb |
Host | smart-deb37be6-aed9-497c-aeaf-e313de04f6ff |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1132213412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1132213412 |
Directory | /workspace/35.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/35.spi_device_flash_and_tpm.3828258282 |
Short name | T887 |
Test name | |
Test status | |
Simulation time | 31336236971 ps |
CPU time | 82.78 seconds |
Started | Jul 15 06:49:38 PM PDT 24 |
Finished | Jul 15 06:51:03 PM PDT 24 |
Peak memory | 249160 kb |
Host | smart-f9c130bd-951f-4503-a8dc-8efdc24b275e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3828258282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3828258282 |
Directory | /workspace/35.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.4061502859 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 31916312337 ps |
CPU time | 132.72 seconds |
Started | Jul 15 06:49:38 PM PDT 24 |
Finished | Jul 15 06:51:53 PM PDT 24 |
Peak memory | 265360 kb |
Host | smart-1fc8c0da-60fb-445b-967b-c6b0dfdd5475 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4061502859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl e.4061502859 |
Directory | /workspace/35.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/35.spi_device_flash_mode.3123812443 |
Short name | T595 |
Test name | |
Test status | |
Simulation time | 175702853 ps |
CPU time | 7.23 seconds |
Started | Jul 15 06:49:38 PM PDT 24 |
Finished | Jul 15 06:49:48 PM PDT 24 |
Peak memory | 232692 kb |
Host | smart-d9475276-f82e-4bc4-a20b-495fe8084f70 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3123812443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3123812443 |
Directory | /workspace/35.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.1066822253 |
Short name | T944 |
Test name | |
Test status | |
Simulation time | 27852217 ps |
CPU time | 0.84 seconds |
Started | Jul 15 06:49:37 PM PDT 24 |
Finished | Jul 15 06:49:40 PM PDT 24 |
Peak memory | 215860 kb |
Host | smart-665a91fa-3e6c-4b09-a4c2-bbef657c3eeb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1066822253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd s.1066822253 |
Directory | /workspace/35.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/35.spi_device_intercept.3644058870 |
Short name | T572 |
Test name | |
Test status | |
Simulation time | 4080351404 ps |
CPU time | 20.94 seconds |
Started | Jul 15 06:49:31 PM PDT 24 |
Finished | Jul 15 06:49:53 PM PDT 24 |
Peak memory | 224520 kb |
Host | smart-8a8c1139-597b-44ec-b5f2-a4d98cfa9b86 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3644058870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3644058870 |
Directory | /workspace/35.spi_device_intercept/latest |
Test location | /workspace/coverage/default/35.spi_device_mailbox.4020657550 |
Short name | T618 |
Test name | |
Test status | |
Simulation time | 320399635 ps |
CPU time | 4.61 seconds |
Started | Jul 15 06:49:38 PM PDT 24 |
Finished | Jul 15 06:49:45 PM PDT 24 |
Peak memory | 232708 kb |
Host | smart-de349376-7181-4581-9356-70dbe46c207b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4020657550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.4020657550 |
Directory | /workspace/35.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1236668858 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 1515170548 ps |
CPU time | 3.3 seconds |
Started | Jul 15 06:49:28 PM PDT 24 |
Finished | Jul 15 06:49:31 PM PDT 24 |
Peak memory | 232612 kb |
Host | smart-222d55a1-847f-441f-b19f-170475626f6c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1236668858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa p.1236668858 |
Directory | /workspace/35.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3949062269 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 9148733053 ps |
CPU time | 6.37 seconds |
Started | Jul 15 06:49:31 PM PDT 24 |
Finished | Jul 15 06:49:38 PM PDT 24 |
Peak memory | 232776 kb |
Host | smart-31f31c09-be08-4e92-a8fb-3202de6259d8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3949062269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3949062269 |
Directory | /workspace/35.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/35.spi_device_read_buffer_direct.3099304077 |
Short name | T922 |
Test name | |
Test status | |
Simulation time | 74764131 ps |
CPU time | 3.42 seconds |
Started | Jul 15 06:49:37 PM PDT 24 |
Finished | Jul 15 06:49:41 PM PDT 24 |
Peak memory | 218796 kb |
Host | smart-04e84cf9-3ac3-441a-9702-844d21d7b56a |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3099304077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir ect.3099304077 |
Directory | /workspace/35.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/35.spi_device_tpm_all.1563437929 |
Short name | T765 |
Test name | |
Test status | |
Simulation time | 2663920403 ps |
CPU time | 12.06 seconds |
Started | Jul 15 06:49:31 PM PDT 24 |
Finished | Jul 15 06:49:43 PM PDT 24 |
Peak memory | 219348 kb |
Host | smart-8e789b15-c40d-4e00-9bca-18f227a7c30a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1563437929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1563437929 |
Directory | /workspace/35.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3102336514 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 916596793 ps |
CPU time | 6.74 seconds |
Started | Jul 15 06:49:27 PM PDT 24 |
Finished | Jul 15 06:49:34 PM PDT 24 |
Peak memory | 216148 kb |
Host | smart-f9652503-8fef-436c-8703-c92696c4fb6b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3102336514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3102336514 |
Directory | /workspace/35.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/35.spi_device_tpm_rw.675820039 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 126293876 ps |
CPU time | 1.4 seconds |
Started | Jul 15 06:49:30 PM PDT 24 |
Finished | Jul 15 06:49:32 PM PDT 24 |
Peak memory | 216184 kb |
Host | smart-fcaccba2-514a-4b29-8eca-88de58763e97 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=675820039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.675820039 |
Directory | /workspace/35.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/35.spi_device_tpm_sts_read.2484220006 |
Short name | T912 |
Test name | |
Test status | |
Simulation time | 30998224 ps |
CPU time | 0.73 seconds |
Started | Jul 15 06:49:32 PM PDT 24 |
Finished | Jul 15 06:49:33 PM PDT 24 |
Peak memory | 205920 kb |
Host | smart-5ca765fe-8198-4f82-a63d-48101d29bf74 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2484220006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2484220006 |
Directory | /workspace/35.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/35.spi_device_upload.2054012184 |
Short name | T837 |
Test name | |
Test status | |
Simulation time | 24511612704 ps |
CPU time | 19.92 seconds |
Started | Jul 15 06:49:37 PM PDT 24 |
Finished | Jul 15 06:49:59 PM PDT 24 |
Peak memory | 232800 kb |
Host | smart-6191cd6e-f350-4788-b9c0-650ce47bac66 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2054012184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2054012184 |
Directory | /workspace/35.spi_device_upload/latest |
Test location | /workspace/coverage/default/36.spi_device_alert_test.3752727517 |
Short name | T490 |
Test name | |
Test status | |
Simulation time | 34271216 ps |
CPU time | 0.7 seconds |
Started | Jul 15 06:49:42 PM PDT 24 |
Finished | Jul 15 06:49:43 PM PDT 24 |
Peak memory | 205480 kb |
Host | smart-ed2ac3f0-d94d-41d2-85ce-f1a9863848dd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752727517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test. 3752727517 |
Directory | /workspace/36.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/36.spi_device_cfg_cmd.4012883922 |
Short name | T534 |
Test name | |
Test status | |
Simulation time | 3841008430 ps |
CPU time | 13.87 seconds |
Started | Jul 15 06:49:46 PM PDT 24 |
Finished | Jul 15 06:50:01 PM PDT 24 |
Peak memory | 224564 kb |
Host | smart-6536f8e0-ff77-4f15-86e9-e1a7cd7acc46 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4012883922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.4012883922 |
Directory | /workspace/36.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/36.spi_device_csb_read.4013222019 |
Short name | T531 |
Test name | |
Test status | |
Simulation time | 43369843 ps |
CPU time | 0.79 seconds |
Started | Jul 15 06:49:39 PM PDT 24 |
Finished | Jul 15 06:49:42 PM PDT 24 |
Peak memory | 206532 kb |
Host | smart-c941b17c-af89-4972-837a-9c5d76140c43 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4013222019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.4013222019 |
Directory | /workspace/36.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/36.spi_device_flash_all.1285458937 |
Short name | T666 |
Test name | |
Test status | |
Simulation time | 3065186734 ps |
CPU time | 49.46 seconds |
Started | Jul 15 06:49:44 PM PDT 24 |
Finished | Jul 15 06:50:35 PM PDT 24 |
Peak memory | 249160 kb |
Host | smart-fffcf0e9-36ec-45b4-8f61-7f6d8e95fba9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1285458937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1285458937 |
Directory | /workspace/36.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/36.spi_device_flash_and_tpm.2190217854 |
Short name | T582 |
Test name | |
Test status | |
Simulation time | 11433689474 ps |
CPU time | 189.97 seconds |
Started | Jul 15 06:49:48 PM PDT 24 |
Finished | Jul 15 06:52:59 PM PDT 24 |
Peak memory | 265604 kb |
Host | smart-ba8005a6-effc-48ac-9e58-6b9507fe2d64 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2190217854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2190217854 |
Directory | /workspace/36.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.4240518379 |
Short name | T631 |
Test name | |
Test status | |
Simulation time | 2878343342 ps |
CPU time | 56.65 seconds |
Started | Jul 15 06:49:48 PM PDT 24 |
Finished | Jul 15 06:50:45 PM PDT 24 |
Peak memory | 252824 kb |
Host | smart-b5f56b94-9802-40e7-bbeb-332100df323e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4240518379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl e.4240518379 |
Directory | /workspace/36.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/36.spi_device_flash_mode.4063243678 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 1514599920 ps |
CPU time | 8.69 seconds |
Started | Jul 15 06:49:46 PM PDT 24 |
Finished | Jul 15 06:49:55 PM PDT 24 |
Peak memory | 224584 kb |
Host | smart-cce0791c-a40d-4387-b6b9-f619a9115382 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4063243678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.4063243678 |
Directory | /workspace/36.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.1733004959 |
Short name | T702 |
Test name | |
Test status | |
Simulation time | 12900347 ps |
CPU time | 0.78 seconds |
Started | Jul 15 06:49:45 PM PDT 24 |
Finished | Jul 15 06:49:47 PM PDT 24 |
Peak memory | 215740 kb |
Host | smart-6e145fd9-121c-4662-855a-58e085f25bbf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1733004959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd s.1733004959 |
Directory | /workspace/36.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/36.spi_device_intercept.2005969850 |
Short name | T614 |
Test name | |
Test status | |
Simulation time | 509656670 ps |
CPU time | 3.56 seconds |
Started | Jul 15 06:49:38 PM PDT 24 |
Finished | Jul 15 06:49:43 PM PDT 24 |
Peak memory | 224400 kb |
Host | smart-9a2d543f-1c3a-4048-b957-8f0f7c39e49d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2005969850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2005969850 |
Directory | /workspace/36.spi_device_intercept/latest |
Test location | /workspace/coverage/default/36.spi_device_mailbox.1123262636 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 765873526 ps |
CPU time | 10.93 seconds |
Started | Jul 15 06:49:37 PM PDT 24 |
Finished | Jul 15 06:49:50 PM PDT 24 |
Peak memory | 224612 kb |
Host | smart-3a75764f-582c-4753-9ff1-4cdf97771978 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1123262636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1123262636 |
Directory | /workspace/36.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.232709166 |
Short name | T694 |
Test name | |
Test status | |
Simulation time | 310407954 ps |
CPU time | 2.49 seconds |
Started | Jul 15 06:49:36 PM PDT 24 |
Finished | Jul 15 06:49:39 PM PDT 24 |
Peak memory | 224388 kb |
Host | smart-c4251818-0768-4620-8de1-85ca08978957 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=232709166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap .232709166 |
Directory | /workspace/36.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1856631090 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 15397333808 ps |
CPU time | 16.77 seconds |
Started | Jul 15 06:49:37 PM PDT 24 |
Finished | Jul 15 06:49:56 PM PDT 24 |
Peak memory | 232688 kb |
Host | smart-7721ce9e-fdb6-40c4-a1fa-dba74edab1a9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1856631090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1856631090 |
Directory | /workspace/36.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/36.spi_device_read_buffer_direct.3807604674 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 559181547 ps |
CPU time | 5.11 seconds |
Started | Jul 15 06:49:45 PM PDT 24 |
Finished | Jul 15 06:49:51 PM PDT 24 |
Peak memory | 218972 kb |
Host | smart-14e7d8ac-5009-4095-a6a5-77f33687b931 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3807604674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir ect.3807604674 |
Directory | /workspace/36.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/36.spi_device_stress_all.3137270295 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 25749681790 ps |
CPU time | 250.45 seconds |
Started | Jul 15 06:49:45 PM PDT 24 |
Finished | Jul 15 06:53:56 PM PDT 24 |
Peak memory | 251080 kb |
Host | smart-1335b19a-7c96-4ab2-8e4a-a01a5cd65947 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137270295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre ss_all.3137270295 |
Directory | /workspace/36.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/36.spi_device_tpm_all.627096538 |
Short name | T617 |
Test name | |
Test status | |
Simulation time | 14846980806 ps |
CPU time | 19.12 seconds |
Started | Jul 15 06:49:38 PM PDT 24 |
Finished | Jul 15 06:50:00 PM PDT 24 |
Peak memory | 216508 kb |
Host | smart-354dd20d-a7af-4707-aa81-fac84068181f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=627096538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.627096538 |
Directory | /workspace/36.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2728534308 |
Short name | T486 |
Test name | |
Test status | |
Simulation time | 10171728454 ps |
CPU time | 13.98 seconds |
Started | Jul 15 06:49:40 PM PDT 24 |
Finished | Jul 15 06:49:55 PM PDT 24 |
Peak memory | 216308 kb |
Host | smart-3f46a213-267c-40fe-aa8b-a2af2ea2beff |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2728534308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2728534308 |
Directory | /workspace/36.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/36.spi_device_tpm_rw.2047424996 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 57659896 ps |
CPU time | 3.39 seconds |
Started | Jul 15 06:49:38 PM PDT 24 |
Finished | Jul 15 06:49:43 PM PDT 24 |
Peak memory | 216136 kb |
Host | smart-93ad29f5-d8f2-418c-b35a-66fbec969d40 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2047424996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2047424996 |
Directory | /workspace/36.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/36.spi_device_tpm_sts_read.694839679 |
Short name | T846 |
Test name | |
Test status | |
Simulation time | 76125503 ps |
CPU time | 0.95 seconds |
Started | Jul 15 06:49:39 PM PDT 24 |
Finished | Jul 15 06:49:42 PM PDT 24 |
Peak memory | 206948 kb |
Host | smart-2c062f16-5dec-4f16-b7fb-d62f86e0dcda |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=694839679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.694839679 |
Directory | /workspace/36.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/36.spi_device_upload.4211455023 |
Short name | T927 |
Test name | |
Test status | |
Simulation time | 5790925350 ps |
CPU time | 9.46 seconds |
Started | Jul 15 06:49:39 PM PDT 24 |
Finished | Jul 15 06:49:50 PM PDT 24 |
Peak memory | 232772 kb |
Host | smart-5c63c848-0e7c-4feb-9d7e-b5f052240668 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4211455023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.4211455023 |
Directory | /workspace/36.spi_device_upload/latest |
Test location | /workspace/coverage/default/37.spi_device_alert_test.186713992 |
Short name | T622 |
Test name | |
Test status | |
Simulation time | 31081182 ps |
CPU time | 0.76 seconds |
Started | Jul 15 06:49:51 PM PDT 24 |
Finished | Jul 15 06:49:53 PM PDT 24 |
Peak memory | 205516 kb |
Host | smart-21fea302-5857-4c68-98a7-67a69c80f899 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186713992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.186713992 |
Directory | /workspace/37.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/37.spi_device_cfg_cmd.1919053849 |
Short name | T483 |
Test name | |
Test status | |
Simulation time | 10148602651 ps |
CPU time | 23.26 seconds |
Started | Jul 15 06:49:52 PM PDT 24 |
Finished | Jul 15 06:50:16 PM PDT 24 |
Peak memory | 224504 kb |
Host | smart-95ca355a-5122-497b-88ef-d169011eb8af |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1919053849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1919053849 |
Directory | /workspace/37.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/37.spi_device_csb_read.3072952591 |
Short name | T821 |
Test name | |
Test status | |
Simulation time | 19937966 ps |
CPU time | 0.76 seconds |
Started | Jul 15 06:49:43 PM PDT 24 |
Finished | Jul 15 06:49:44 PM PDT 24 |
Peak memory | 206528 kb |
Host | smart-a2216e5d-36fa-44c7-8f06-fb5d33c1ab6b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3072952591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3072952591 |
Directory | /workspace/37.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/37.spi_device_flash_all.4008883712 |
Short name | T643 |
Test name | |
Test status | |
Simulation time | 42442759503 ps |
CPU time | 115.19 seconds |
Started | Jul 15 06:49:51 PM PDT 24 |
Finished | Jul 15 06:51:47 PM PDT 24 |
Peak memory | 253272 kb |
Host | smart-556b0162-7583-4d4e-814c-4cfd03978b6f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4008883712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.4008883712 |
Directory | /workspace/37.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/37.spi_device_flash_and_tpm.1836722070 |
Short name | T721 |
Test name | |
Test status | |
Simulation time | 163988236008 ps |
CPU time | 366.07 seconds |
Started | Jul 15 06:49:52 PM PDT 24 |
Finished | Jul 15 06:55:59 PM PDT 24 |
Peak memory | 251476 kb |
Host | smart-b5e0877e-880c-4663-a88e-6197dd612828 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1836722070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1836722070 |
Directory | /workspace/37.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.208554267 |
Short name | T577 |
Test name | |
Test status | |
Simulation time | 4576452544 ps |
CPU time | 64.26 seconds |
Started | Jul 15 06:49:53 PM PDT 24 |
Finished | Jul 15 06:50:58 PM PDT 24 |
Peak memory | 248824 kb |
Host | smart-eb982fa0-d402-488c-a539-2dcb10c018f0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=208554267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle .208554267 |
Directory | /workspace/37.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/37.spi_device_flash_mode.872644755 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 118524843 ps |
CPU time | 2.6 seconds |
Started | Jul 15 06:49:50 PM PDT 24 |
Finished | Jul 15 06:49:54 PM PDT 24 |
Peak memory | 224380 kb |
Host | smart-cd26b075-e48a-4c77-9502-a51980ffcd03 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=872644755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.872644755 |
Directory | /workspace/37.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.1686255177 |
Short name | T510 |
Test name | |
Test status | |
Simulation time | 19649615930 ps |
CPU time | 142.85 seconds |
Started | Jul 15 06:49:51 PM PDT 24 |
Finished | Jul 15 06:52:15 PM PDT 24 |
Peak memory | 251220 kb |
Host | smart-d57c6eee-fcc3-43ea-8bbc-04f772911db5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1686255177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd s.1686255177 |
Directory | /workspace/37.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/37.spi_device_intercept.1737675341 |
Short name | T710 |
Test name | |
Test status | |
Simulation time | 483647983 ps |
CPU time | 2.18 seconds |
Started | Jul 15 06:49:45 PM PDT 24 |
Finished | Jul 15 06:49:48 PM PDT 24 |
Peak memory | 224024 kb |
Host | smart-1c6e718f-7f4a-43a1-bacc-e3e46342cc6a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1737675341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1737675341 |
Directory | /workspace/37.spi_device_intercept/latest |
Test location | /workspace/coverage/default/37.spi_device_mailbox.362065864 |
Short name | T647 |
Test name | |
Test status | |
Simulation time | 7988599463 ps |
CPU time | 24.57 seconds |
Started | Jul 15 06:49:45 PM PDT 24 |
Finished | Jul 15 06:50:11 PM PDT 24 |
Peak memory | 239784 kb |
Host | smart-efae51ec-786c-4ef5-9df4-348ee7244c08 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=362065864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.362065864 |
Directory | /workspace/37.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1584577819 |
Short name | T472 |
Test name | |
Test status | |
Simulation time | 702874822 ps |
CPU time | 3.42 seconds |
Started | Jul 15 06:49:44 PM PDT 24 |
Finished | Jul 15 06:49:48 PM PDT 24 |
Peak memory | 232604 kb |
Host | smart-6ea61f8a-9fc4-448d-8554-764267e11e63 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1584577819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa p.1584577819 |
Directory | /workspace/37.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/37.spi_device_pass_cmd_filtering.729261472 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 13702004164 ps |
CPU time | 22.73 seconds |
Started | Jul 15 06:49:44 PM PDT 24 |
Finished | Jul 15 06:50:08 PM PDT 24 |
Peak memory | 240672 kb |
Host | smart-219992d5-1af3-4c67-9fe3-fadc9c6326c3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=729261472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.729261472 |
Directory | /workspace/37.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/37.spi_device_read_buffer_direct.4041949747 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 963473408 ps |
CPU time | 13.05 seconds |
Started | Jul 15 06:49:49 PM PDT 24 |
Finished | Jul 15 06:50:03 PM PDT 24 |
Peak memory | 222128 kb |
Host | smart-7af1af51-981e-44e3-88af-ad6ac96aa8d0 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4041949747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir ect.4041949747 |
Directory | /workspace/37.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/37.spi_device_stress_all.2407677984 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 69257016 ps |
CPU time | 1.28 seconds |
Started | Jul 15 06:49:53 PM PDT 24 |
Finished | Jul 15 06:49:55 PM PDT 24 |
Peak memory | 207772 kb |
Host | smart-b17c4c22-40cf-4c69-8d36-3e1db4ec9c07 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407677984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre ss_all.2407677984 |
Directory | /workspace/37.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/37.spi_device_tpm_all.2393834249 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 4366008111 ps |
CPU time | 9.34 seconds |
Started | Jul 15 06:49:48 PM PDT 24 |
Finished | Jul 15 06:49:59 PM PDT 24 |
Peak memory | 220348 kb |
Host | smart-360f6e0d-b8b5-4c8b-9daf-3bb36cf9ea72 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2393834249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2393834249 |
Directory | /workspace/37.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2519502416 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 8827932721 ps |
CPU time | 25.31 seconds |
Started | Jul 15 06:49:45 PM PDT 24 |
Finished | Jul 15 06:50:11 PM PDT 24 |
Peak memory | 216224 kb |
Host | smart-8ccd0dd4-2a67-41f5-9a4c-05a81981b1d2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2519502416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2519502416 |
Directory | /workspace/37.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/37.spi_device_tpm_rw.1774018691 |
Short name | T936 |
Test name | |
Test status | |
Simulation time | 36730000 ps |
CPU time | 2.01 seconds |
Started | Jul 15 06:49:42 PM PDT 24 |
Finished | Jul 15 06:49:45 PM PDT 24 |
Peak memory | 216144 kb |
Host | smart-87690926-d9f7-4279-aa3e-21124b053ec1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1774018691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1774018691 |
Directory | /workspace/37.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/37.spi_device_tpm_sts_read.647822287 |
Short name | T723 |
Test name | |
Test status | |
Simulation time | 47454725 ps |
CPU time | 0.81 seconds |
Started | Jul 15 06:49:45 PM PDT 24 |
Finished | Jul 15 06:49:47 PM PDT 24 |
Peak memory | 205940 kb |
Host | smart-ee22f6bf-980d-40da-ab4c-aa01dc67ab43 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=647822287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.647822287 |
Directory | /workspace/37.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/37.spi_device_upload.1994840372 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 41295066287 ps |
CPU time | 31.63 seconds |
Started | Jul 15 06:49:44 PM PDT 24 |
Finished | Jul 15 06:50:17 PM PDT 24 |
Peak memory | 249152 kb |
Host | smart-7e2e60d6-84b7-4e1d-a3f8-c9504369c6a6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1994840372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1994840372 |
Directory | /workspace/37.spi_device_upload/latest |
Test location | /workspace/coverage/default/38.spi_device_alert_test.2204305389 |
Short name | T857 |
Test name | |
Test status | |
Simulation time | 11059682 ps |
CPU time | 0.71 seconds |
Started | Jul 15 06:49:59 PM PDT 24 |
Finished | Jul 15 06:50:01 PM PDT 24 |
Peak memory | 204908 kb |
Host | smart-897a1c23-6770-46c7-967a-924f1b572736 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204305389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test. 2204305389 |
Directory | /workspace/38.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/38.spi_device_cfg_cmd.3366122242 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 2926202671 ps |
CPU time | 9.4 seconds |
Started | Jul 15 06:49:54 PM PDT 24 |
Finished | Jul 15 06:50:04 PM PDT 24 |
Peak memory | 232668 kb |
Host | smart-8ae0e456-6b08-4639-a8c9-9e9e22313476 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3366122242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3366122242 |
Directory | /workspace/38.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/38.spi_device_csb_read.2140333216 |
Short name | T635 |
Test name | |
Test status | |
Simulation time | 32169988 ps |
CPU time | 0.77 seconds |
Started | Jul 15 06:49:53 PM PDT 24 |
Finished | Jul 15 06:49:55 PM PDT 24 |
Peak memory | 206868 kb |
Host | smart-be4c827d-e4ec-4f10-ac76-f7437c77d978 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2140333216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2140333216 |
Directory | /workspace/38.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/38.spi_device_flash_all.2723087373 |
Short name | T501 |
Test name | |
Test status | |
Simulation time | 155459840571 ps |
CPU time | 274.34 seconds |
Started | Jul 15 06:49:57 PM PDT 24 |
Finished | Jul 15 06:54:31 PM PDT 24 |
Peak memory | 254860 kb |
Host | smart-eb832cb3-082c-48a1-9154-2740ed6025b5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2723087373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2723087373 |
Directory | /workspace/38.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/38.spi_device_flash_and_tpm.842919957 |
Short name | T764 |
Test name | |
Test status | |
Simulation time | 178468782825 ps |
CPU time | 183.17 seconds |
Started | Jul 15 06:49:55 PM PDT 24 |
Finished | Jul 15 06:52:59 PM PDT 24 |
Peak memory | 257356 kb |
Host | smart-5642032a-0934-4bd0-ad76-3d30e988b419 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=842919957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.842919957 |
Directory | /workspace/38.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3219359402 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 11289129163 ps |
CPU time | 64.89 seconds |
Started | Jul 15 06:49:56 PM PDT 24 |
Finished | Jul 15 06:51:02 PM PDT 24 |
Peak memory | 251940 kb |
Host | smart-f73a785d-8020-43cc-8fb1-a7c0f95d3c0b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3219359402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl e.3219359402 |
Directory | /workspace/38.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/38.spi_device_flash_mode.3841087144 |
Short name | T620 |
Test name | |
Test status | |
Simulation time | 248046835 ps |
CPU time | 6.76 seconds |
Started | Jul 15 06:49:53 PM PDT 24 |
Finished | Jul 15 06:50:01 PM PDT 24 |
Peak memory | 224340 kb |
Host | smart-e21232e5-2a4b-4167-b2c8-6adcce3cf21b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3841087144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3841087144 |
Directory | /workspace/38.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2843594053 |
Short name | T717 |
Test name | |
Test status | |
Simulation time | 36187596281 ps |
CPU time | 92.56 seconds |
Started | Jul 15 06:49:51 PM PDT 24 |
Finished | Jul 15 06:51:25 PM PDT 24 |
Peak memory | 249116 kb |
Host | smart-9e65855d-4785-4d82-9ed9-ea182105e58c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2843594053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd s.2843594053 |
Directory | /workspace/38.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/38.spi_device_intercept.3418624122 |
Short name | T714 |
Test name | |
Test status | |
Simulation time | 4103318690 ps |
CPU time | 18.21 seconds |
Started | Jul 15 06:49:51 PM PDT 24 |
Finished | Jul 15 06:50:10 PM PDT 24 |
Peak memory | 232708 kb |
Host | smart-d69e5577-147d-4fb2-82d4-23d4b8a48f5b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3418624122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3418624122 |
Directory | /workspace/38.spi_device_intercept/latest |
Test location | /workspace/coverage/default/38.spi_device_mailbox.1235960914 |
Short name | T1005 |
Test name | |
Test status | |
Simulation time | 365578474 ps |
CPU time | 6.8 seconds |
Started | Jul 15 06:49:51 PM PDT 24 |
Finished | Jul 15 06:49:59 PM PDT 24 |
Peak memory | 232572 kb |
Host | smart-4d93008e-2837-4f5b-90c8-80421cc683c5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1235960914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1235960914 |
Directory | /workspace/38.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.4222640717 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 1686640921 ps |
CPU time | 5.78 seconds |
Started | Jul 15 06:49:52 PM PDT 24 |
Finished | Jul 15 06:49:59 PM PDT 24 |
Peak memory | 232584 kb |
Host | smart-928eb57f-acf1-49c5-83e7-47fdc519da2a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4222640717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa p.4222640717 |
Directory | /workspace/38.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3426761719 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 4360139959 ps |
CPU time | 4.33 seconds |
Started | Jul 15 06:49:52 PM PDT 24 |
Finished | Jul 15 06:49:57 PM PDT 24 |
Peak memory | 232676 kb |
Host | smart-eca806ce-5d38-4c98-a2c8-330a532e49f6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3426761719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3426761719 |
Directory | /workspace/38.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/38.spi_device_read_buffer_direct.2989588174 |
Short name | T981 |
Test name | |
Test status | |
Simulation time | 5232880534 ps |
CPU time | 7.74 seconds |
Started | Jul 15 06:49:51 PM PDT 24 |
Finished | Jul 15 06:50:00 PM PDT 24 |
Peak memory | 220060 kb |
Host | smart-7cb9c59a-e8f4-44cf-aabf-f0de19ff8be6 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2989588174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir ect.2989588174 |
Directory | /workspace/38.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/38.spi_device_stress_all.669976696 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 9366891696 ps |
CPU time | 115.31 seconds |
Started | Jul 15 06:49:59 PM PDT 24 |
Finished | Jul 15 06:51:55 PM PDT 24 |
Peak memory | 251312 kb |
Host | smart-431e882d-654f-4c61-b1ce-4ae53c2f44ba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669976696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres s_all.669976696 |
Directory | /workspace/38.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/38.spi_device_tpm_all.2947562744 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 1667238982 ps |
CPU time | 4.95 seconds |
Started | Jul 15 06:49:52 PM PDT 24 |
Finished | Jul 15 06:49:58 PM PDT 24 |
Peak memory | 216128 kb |
Host | smart-737348ef-cbea-4afc-b818-cb13b51874bc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2947562744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2947562744 |
Directory | /workspace/38.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1862705840 |
Short name | T504 |
Test name | |
Test status | |
Simulation time | 8496632886 ps |
CPU time | 8.49 seconds |
Started | Jul 15 06:49:50 PM PDT 24 |
Finished | Jul 15 06:49:59 PM PDT 24 |
Peak memory | 216340 kb |
Host | smart-ffbce3f8-c70c-48a4-9800-9051c9caf860 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1862705840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1862705840 |
Directory | /workspace/38.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/38.spi_device_tpm_rw.1078505611 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 165636007 ps |
CPU time | 1.88 seconds |
Started | Jul 15 06:49:52 PM PDT 24 |
Finished | Jul 15 06:49:55 PM PDT 24 |
Peak memory | 216180 kb |
Host | smart-00759e18-da77-4b97-8190-43536b8b6b51 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1078505611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1078505611 |
Directory | /workspace/38.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/38.spi_device_tpm_sts_read.2675560026 |
Short name | T812 |
Test name | |
Test status | |
Simulation time | 47086246 ps |
CPU time | 0.91 seconds |
Started | Jul 15 06:49:54 PM PDT 24 |
Finished | Jul 15 06:49:56 PM PDT 24 |
Peak memory | 206228 kb |
Host | smart-0b006764-a881-4e0d-be43-52aa4d4ca09b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2675560026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2675560026 |
Directory | /workspace/38.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/38.spi_device_upload.3196123456 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 769264793 ps |
CPU time | 5.75 seconds |
Started | Jul 15 06:49:52 PM PDT 24 |
Finished | Jul 15 06:49:59 PM PDT 24 |
Peak memory | 240580 kb |
Host | smart-11f036db-535c-4fd6-9962-18d637283abc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3196123456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3196123456 |
Directory | /workspace/38.spi_device_upload/latest |
Test location | /workspace/coverage/default/39.spi_device_alert_test.3808644669 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 46516889 ps |
CPU time | 0.82 seconds |
Started | Jul 15 06:50:05 PM PDT 24 |
Finished | Jul 15 06:50:06 PM PDT 24 |
Peak memory | 205756 kb |
Host | smart-d0c96b20-32e9-41a5-a6b1-780f2ace1318 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808644669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test. 3808644669 |
Directory | /workspace/39.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/39.spi_device_cfg_cmd.286608975 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 1462867103 ps |
CPU time | 7.13 seconds |
Started | Jul 15 06:50:06 PM PDT 24 |
Finished | Jul 15 06:50:14 PM PDT 24 |
Peak memory | 224396 kb |
Host | smart-e560f9e4-434b-4880-a462-daa69dd8289c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=286608975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.286608975 |
Directory | /workspace/39.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/39.spi_device_csb_read.2648661415 |
Short name | T904 |
Test name | |
Test status | |
Simulation time | 40035850 ps |
CPU time | 0.76 seconds |
Started | Jul 15 06:50:03 PM PDT 24 |
Finished | Jul 15 06:50:04 PM PDT 24 |
Peak memory | 205536 kb |
Host | smart-ba2e0cee-7d53-41ad-b057-dac46f220d8d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2648661415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2648661415 |
Directory | /workspace/39.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/39.spi_device_flash_all.385805086 |
Short name | T653 |
Test name | |
Test status | |
Simulation time | 11876307694 ps |
CPU time | 83.86 seconds |
Started | Jul 15 06:49:59 PM PDT 24 |
Finished | Jul 15 06:51:23 PM PDT 24 |
Peak memory | 256740 kb |
Host | smart-abdf3c77-d592-4482-af4c-a40f791ba939 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=385805086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.385805086 |
Directory | /workspace/39.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/39.spi_device_flash_and_tpm.4151371019 |
Short name | T879 |
Test name | |
Test status | |
Simulation time | 19048460938 ps |
CPU time | 72.27 seconds |
Started | Jul 15 06:50:00 PM PDT 24 |
Finished | Jul 15 06:51:13 PM PDT 24 |
Peak memory | 250612 kb |
Host | smart-74a054a1-150b-4647-a98d-5adc7eb03b93 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4151371019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.4151371019 |
Directory | /workspace/39.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3629793241 |
Short name | T942 |
Test name | |
Test status | |
Simulation time | 108620690566 ps |
CPU time | 365.41 seconds |
Started | Jul 15 06:50:08 PM PDT 24 |
Finished | Jul 15 06:56:13 PM PDT 24 |
Peak memory | 257400 kb |
Host | smart-b93a6526-5c9c-4bb5-9a1a-b0c1010d21df |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3629793241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl e.3629793241 |
Directory | /workspace/39.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/39.spi_device_flash_mode.2899844161 |
Short name | T638 |
Test name | |
Test status | |
Simulation time | 100475397 ps |
CPU time | 2.76 seconds |
Started | Jul 15 06:50:03 PM PDT 24 |
Finished | Jul 15 06:50:06 PM PDT 24 |
Peak memory | 224412 kb |
Host | smart-29d5f32f-e1a0-4065-9cbd-f3695a10a72b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2899844161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2899844161 |
Directory | /workspace/39.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.1549716512 |
Short name | T676 |
Test name | |
Test status | |
Simulation time | 5728175056 ps |
CPU time | 15.51 seconds |
Started | Jul 15 06:49:59 PM PDT 24 |
Finished | Jul 15 06:50:15 PM PDT 24 |
Peak memory | 233188 kb |
Host | smart-b625d9ef-c6a4-4e19-892b-a75d691515a5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1549716512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd s.1549716512 |
Directory | /workspace/39.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/39.spi_device_intercept.1404682976 |
Short name | T888 |
Test name | |
Test status | |
Simulation time | 722625478 ps |
CPU time | 5.19 seconds |
Started | Jul 15 06:49:57 PM PDT 24 |
Finished | Jul 15 06:50:02 PM PDT 24 |
Peak memory | 224432 kb |
Host | smart-ead0ceef-aedb-4740-b0f0-e156d616ae8d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1404682976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1404682976 |
Directory | /workspace/39.spi_device_intercept/latest |
Test location | /workspace/coverage/default/39.spi_device_mailbox.2123078648 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 28417152951 ps |
CPU time | 46.18 seconds |
Started | Jul 15 06:50:03 PM PDT 24 |
Finished | Jul 15 06:50:49 PM PDT 24 |
Peak memory | 232800 kb |
Host | smart-ce554275-4749-4db2-99b5-cc3b86246592 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2123078648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2123078648 |
Directory | /workspace/39.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.648616867 |
Short name | T872 |
Test name | |
Test status | |
Simulation time | 2051622582 ps |
CPU time | 7 seconds |
Started | Jul 15 06:49:57 PM PDT 24 |
Finished | Jul 15 06:50:05 PM PDT 24 |
Peak memory | 234920 kb |
Host | smart-d6ae4b31-097a-4b09-b079-10a4f5486885 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=648616867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap .648616867 |
Directory | /workspace/39.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1633439241 |
Short name | T636 |
Test name | |
Test status | |
Simulation time | 6932052919 ps |
CPU time | 20.27 seconds |
Started | Jul 15 06:49:58 PM PDT 24 |
Finished | Jul 15 06:50:18 PM PDT 24 |
Peak memory | 232732 kb |
Host | smart-f9e2a542-34ee-44b9-87ae-f743c7e52470 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1633439241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1633439241 |
Directory | /workspace/39.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/39.spi_device_read_buffer_direct.3824484660 |
Short name | T985 |
Test name | |
Test status | |
Simulation time | 492153555 ps |
CPU time | 4.91 seconds |
Started | Jul 15 06:50:05 PM PDT 24 |
Finished | Jul 15 06:50:11 PM PDT 24 |
Peak memory | 223072 kb |
Host | smart-a15d4882-3a02-4055-bcea-58798738b13e |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3824484660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir ect.3824484660 |
Directory | /workspace/39.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/39.spi_device_tpm_all.1936837975 |
Short name | T535 |
Test name | |
Test status | |
Simulation time | 419651838 ps |
CPU time | 5.3 seconds |
Started | Jul 15 06:50:00 PM PDT 24 |
Finished | Jul 15 06:50:06 PM PDT 24 |
Peak memory | 216444 kb |
Host | smart-37631bee-ed52-4b6b-97e0-5456940d2935 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1936837975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1936837975 |
Directory | /workspace/39.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2104225740 |
Short name | T965 |
Test name | |
Test status | |
Simulation time | 12572367090 ps |
CPU time | 15.55 seconds |
Started | Jul 15 06:49:59 PM PDT 24 |
Finished | Jul 15 06:50:15 PM PDT 24 |
Peak memory | 216268 kb |
Host | smart-03b792ee-0322-4d64-9147-5de0f5e7c259 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2104225740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2104225740 |
Directory | /workspace/39.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/39.spi_device_tpm_rw.726980470 |
Short name | T485 |
Test name | |
Test status | |
Simulation time | 26450085 ps |
CPU time | 0.68 seconds |
Started | Jul 15 06:49:59 PM PDT 24 |
Finished | Jul 15 06:50:00 PM PDT 24 |
Peak memory | 205588 kb |
Host | smart-b849295f-1259-4685-be4a-4c41ab6312c8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=726980470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.726980470 |
Directory | /workspace/39.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/39.spi_device_tpm_sts_read.960693395 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 48091473 ps |
CPU time | 0.81 seconds |
Started | Jul 15 06:50:00 PM PDT 24 |
Finished | Jul 15 06:50:01 PM PDT 24 |
Peak memory | 205928 kb |
Host | smart-32f1f179-33c2-4209-bb84-f075292fbe8b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=960693395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.960693395 |
Directory | /workspace/39.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/39.spi_device_upload.1307175343 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 15275106786 ps |
CPU time | 39.56 seconds |
Started | Jul 15 06:50:05 PM PDT 24 |
Finished | Jul 15 06:50:46 PM PDT 24 |
Peak memory | 232716 kb |
Host | smart-6f80a910-05d1-48c0-8db1-faf24b867e4a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1307175343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1307175343 |
Directory | /workspace/39.spi_device_upload/latest |
Test location | /workspace/coverage/default/4.spi_device_alert_test.1395642608 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 12610034 ps |
CPU time | 0.69 seconds |
Started | Jul 15 06:45:16 PM PDT 24 |
Finished | Jul 15 06:45:17 PM PDT 24 |
Peak memory | 204912 kb |
Host | smart-b89864de-afaf-478d-9577-061a009a9b63 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395642608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1 395642608 |
Directory | /workspace/4.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/4.spi_device_cfg_cmd.3998743194 |
Short name | T759 |
Test name | |
Test status | |
Simulation time | 1080549766 ps |
CPU time | 4.11 seconds |
Started | Jul 15 06:45:09 PM PDT 24 |
Finished | Jul 15 06:45:15 PM PDT 24 |
Peak memory | 224468 kb |
Host | smart-f7703345-aaa9-418d-8626-08eca7b26f15 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3998743194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3998743194 |
Directory | /workspace/4.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/4.spi_device_csb_read.386411250 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 16449915 ps |
CPU time | 0.8 seconds |
Started | Jul 15 06:45:08 PM PDT 24 |
Finished | Jul 15 06:45:09 PM PDT 24 |
Peak memory | 206580 kb |
Host | smart-2dd5241b-9571-4e17-9048-76daccc7a6fc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=386411250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.386411250 |
Directory | /workspace/4.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/4.spi_device_flash_all.2533321991 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 28046303109 ps |
CPU time | 209.33 seconds |
Started | Jul 15 06:45:14 PM PDT 24 |
Finished | Jul 15 06:48:44 PM PDT 24 |
Peak memory | 254964 kb |
Host | smart-0741ed5e-a3b0-4794-853d-8eb3c3fef4a7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2533321991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2533321991 |
Directory | /workspace/4.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/4.spi_device_flash_and_tpm.889111730 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 116565722033 ps |
CPU time | 76.19 seconds |
Started | Jul 15 06:45:14 PM PDT 24 |
Finished | Jul 15 06:46:31 PM PDT 24 |
Peak memory | 253284 kb |
Host | smart-e21994d6-f3b3-4dd2-9cb6-806bf5d89bf5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=889111730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.889111730 |
Directory | /workspace/4.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/4.spi_device_flash_mode.3416003611 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 27675975682 ps |
CPU time | 35.72 seconds |
Started | Jul 15 06:45:07 PM PDT 24 |
Finished | Jul 15 06:45:44 PM PDT 24 |
Peak memory | 240588 kb |
Host | smart-86879492-18bc-4509-a901-c1ad677333d2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3416003611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3416003611 |
Directory | /workspace/4.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.1505072073 |
Short name | T669 |
Test name | |
Test status | |
Simulation time | 29321240420 ps |
CPU time | 71.61 seconds |
Started | Jul 15 06:45:09 PM PDT 24 |
Finished | Jul 15 06:46:22 PM PDT 24 |
Peak memory | 249136 kb |
Host | smart-c2585014-081b-4c69-8907-59ac07cfe3d9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1505072073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds .1505072073 |
Directory | /workspace/4.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/4.spi_device_intercept.444927343 |
Short name | T860 |
Test name | |
Test status | |
Simulation time | 3619571229 ps |
CPU time | 8.69 seconds |
Started | Jul 15 06:45:09 PM PDT 24 |
Finished | Jul 15 06:45:18 PM PDT 24 |
Peak memory | 224500 kb |
Host | smart-204c80a2-4e81-40b8-80df-195da76d4ce4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=444927343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.444927343 |
Directory | /workspace/4.spi_device_intercept/latest |
Test location | /workspace/coverage/default/4.spi_device_mailbox.476048109 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 2200358189 ps |
CPU time | 30.72 seconds |
Started | Jul 15 06:45:09 PM PDT 24 |
Finished | Jul 15 06:45:41 PM PDT 24 |
Peak memory | 240664 kb |
Host | smart-8f23d974-3c60-4fc2-95db-2b19fc991b2d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=476048109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.476048109 |
Directory | /workspace/4.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1552618927 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 1920938548 ps |
CPU time | 5.89 seconds |
Started | Jul 15 06:45:08 PM PDT 24 |
Finished | Jul 15 06:45:15 PM PDT 24 |
Peak memory | 232616 kb |
Host | smart-e05e8451-1cf1-487f-90d6-c31702edf93b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1552618927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap .1552618927 |
Directory | /workspace/4.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/4.spi_device_pass_cmd_filtering.4262373749 |
Short name | T728 |
Test name | |
Test status | |
Simulation time | 50891437553 ps |
CPU time | 38.64 seconds |
Started | Jul 15 06:45:09 PM PDT 24 |
Finished | Jul 15 06:45:49 PM PDT 24 |
Peak memory | 240408 kb |
Host | smart-f7177ea2-6bea-4498-b523-d93aa0d56234 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4262373749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.4262373749 |
Directory | /workspace/4.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/4.spi_device_read_buffer_direct.1135311125 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 602583071 ps |
CPU time | 6.44 seconds |
Started | Jul 15 06:45:06 PM PDT 24 |
Finished | Jul 15 06:45:13 PM PDT 24 |
Peak memory | 220720 kb |
Host | smart-91702c2a-f77e-4c02-b9d8-853d1a00457e |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1135311125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire ct.1135311125 |
Directory | /workspace/4.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/4.spi_device_sec_cm.2876789325 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 104077106 ps |
CPU time | 0.96 seconds |
Started | Jul 15 06:45:15 PM PDT 24 |
Finished | Jul 15 06:45:16 PM PDT 24 |
Peak memory | 236484 kb |
Host | smart-513998ca-2fca-4dae-b6d9-ed12517c6133 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876789325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2876789325 |
Directory | /workspace/4.spi_device_sec_cm/latest |
Test location | /workspace/coverage/default/4.spi_device_stress_all.3758808916 |
Short name | T677 |
Test name | |
Test status | |
Simulation time | 13180440340 ps |
CPU time | 48.03 seconds |
Started | Jul 15 06:45:16 PM PDT 24 |
Finished | Jul 15 06:46:04 PM PDT 24 |
Peak memory | 249132 kb |
Host | smart-0d7c352d-2cd0-48ff-a64a-318bcd676520 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758808916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres s_all.3758808916 |
Directory | /workspace/4.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/4.spi_device_tpm_all.3220286285 |
Short name | T649 |
Test name | |
Test status | |
Simulation time | 3235791208 ps |
CPU time | 26.17 seconds |
Started | Jul 15 06:45:09 PM PDT 24 |
Finished | Jul 15 06:45:36 PM PDT 24 |
Peak memory | 216456 kb |
Host | smart-02893b97-5f0d-4ed9-a186-45e3b2f9c0b5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3220286285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3220286285 |
Directory | /workspace/4.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2522711546 |
Short name | T977 |
Test name | |
Test status | |
Simulation time | 8202342770 ps |
CPU time | 11.95 seconds |
Started | Jul 15 06:45:10 PM PDT 24 |
Finished | Jul 15 06:45:23 PM PDT 24 |
Peak memory | 216276 kb |
Host | smart-c9e2bd8b-e203-4fca-8d3c-04cf30c58f38 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2522711546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2522711546 |
Directory | /workspace/4.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/4.spi_device_tpm_rw.1846111908 |
Short name | T746 |
Test name | |
Test status | |
Simulation time | 427650609 ps |
CPU time | 1.28 seconds |
Started | Jul 15 06:45:07 PM PDT 24 |
Finished | Jul 15 06:45:09 PM PDT 24 |
Peak memory | 216136 kb |
Host | smart-eda8624e-a1cc-4c84-9015-d6bc4303ba82 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1846111908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1846111908 |
Directory | /workspace/4.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/4.spi_device_tpm_sts_read.3930459756 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 16332927 ps |
CPU time | 0.73 seconds |
Started | Jul 15 06:45:07 PM PDT 24 |
Finished | Jul 15 06:45:08 PM PDT 24 |
Peak memory | 205936 kb |
Host | smart-bf77d7fd-62cf-4e0f-ad99-982b48998cd8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3930459756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3930459756 |
Directory | /workspace/4.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/4.spi_device_upload.2575489650 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 12372986992 ps |
CPU time | 10.35 seconds |
Started | Jul 15 06:45:09 PM PDT 24 |
Finished | Jul 15 06:45:21 PM PDT 24 |
Peak memory | 224544 kb |
Host | smart-260753ae-0595-4437-b6df-026cd3fecc76 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2575489650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2575489650 |
Directory | /workspace/4.spi_device_upload/latest |
Test location | /workspace/coverage/default/40.spi_device_alert_test.3068988244 |
Short name | T550 |
Test name | |
Test status | |
Simulation time | 15501197 ps |
CPU time | 0.73 seconds |
Started | Jul 15 06:50:12 PM PDT 24 |
Finished | Jul 15 06:50:13 PM PDT 24 |
Peak memory | 205468 kb |
Host | smart-38646611-402b-4f58-9326-a2a04db31305 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068988244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test. 3068988244 |
Directory | /workspace/40.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/40.spi_device_cfg_cmd.1926285354 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 122376715 ps |
CPU time | 2.53 seconds |
Started | Jul 15 06:50:06 PM PDT 24 |
Finished | Jul 15 06:50:09 PM PDT 24 |
Peak memory | 232568 kb |
Host | smart-2384309f-08a0-4788-b983-2de518a765d9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1926285354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1926285354 |
Directory | /workspace/40.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/40.spi_device_csb_read.85983193 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 36298986 ps |
CPU time | 0.77 seconds |
Started | Jul 15 06:50:04 PM PDT 24 |
Finished | Jul 15 06:50:05 PM PDT 24 |
Peak memory | 206556 kb |
Host | smart-fb6cfa97-9aa4-4bb2-a826-185a28ac31b4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=85983193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.85983193 |
Directory | /workspace/40.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/40.spi_device_flash_all.3511218468 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 37543287343 ps |
CPU time | 77.69 seconds |
Started | Jul 15 06:50:05 PM PDT 24 |
Finished | Jul 15 06:51:23 PM PDT 24 |
Peak memory | 240264 kb |
Host | smart-aec478ba-9f73-46ff-bcac-f2f290b806cb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3511218468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3511218468 |
Directory | /workspace/40.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2890478874 |
Short name | T736 |
Test name | |
Test status | |
Simulation time | 2911466752 ps |
CPU time | 33.85 seconds |
Started | Jul 15 06:50:05 PM PDT 24 |
Finished | Jul 15 06:50:40 PM PDT 24 |
Peak memory | 237388 kb |
Host | smart-9f2091fa-917b-4c67-ae50-fe32488318a6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2890478874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl e.2890478874 |
Directory | /workspace/40.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/40.spi_device_flash_mode.640671011 |
Short name | T489 |
Test name | |
Test status | |
Simulation time | 1304709961 ps |
CPU time | 23.36 seconds |
Started | Jul 15 06:50:05 PM PDT 24 |
Finished | Jul 15 06:50:29 PM PDT 24 |
Peak memory | 232684 kb |
Host | smart-8141a772-b614-421f-8b44-00aa3ec475fb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=640671011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.640671011 |
Directory | /workspace/40.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.2513072936 |
Short name | T594 |
Test name | |
Test status | |
Simulation time | 79107623094 ps |
CPU time | 136.72 seconds |
Started | Jul 15 06:50:05 PM PDT 24 |
Finished | Jul 15 06:52:23 PM PDT 24 |
Peak memory | 250452 kb |
Host | smart-c64b0d14-5239-4eca-b24f-97365a0be1cc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2513072936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd s.2513072936 |
Directory | /workspace/40.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/40.spi_device_intercept.1912155112 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 681558544 ps |
CPU time | 7.53 seconds |
Started | Jul 15 06:50:05 PM PDT 24 |
Finished | Jul 15 06:50:13 PM PDT 24 |
Peak memory | 232660 kb |
Host | smart-04032fc8-8b7e-4fbe-9f06-bc553e1f5f60 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1912155112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1912155112 |
Directory | /workspace/40.spi_device_intercept/latest |
Test location | /workspace/coverage/default/40.spi_device_mailbox.1619763145 |
Short name | T773 |
Test name | |
Test status | |
Simulation time | 19001390445 ps |
CPU time | 82.08 seconds |
Started | Jul 15 06:50:03 PM PDT 24 |
Finished | Jul 15 06:51:26 PM PDT 24 |
Peak memory | 235592 kb |
Host | smart-059c75ad-ace2-4c5c-bca5-77405cd7dfe2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1619763145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1619763145 |
Directory | /workspace/40.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.692300123 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 9179292372 ps |
CPU time | 27.18 seconds |
Started | Jul 15 06:50:05 PM PDT 24 |
Finished | Jul 15 06:50:33 PM PDT 24 |
Peak memory | 238316 kb |
Host | smart-63c01c79-a2bf-44ed-81ea-61b31a6dada3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=692300123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap .692300123 |
Directory | /workspace/40.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/40.spi_device_pass_cmd_filtering.547719184 |
Short name | T885 |
Test name | |
Test status | |
Simulation time | 1368092159 ps |
CPU time | 4.93 seconds |
Started | Jul 15 06:50:05 PM PDT 24 |
Finished | Jul 15 06:50:11 PM PDT 24 |
Peak memory | 224480 kb |
Host | smart-4c67cdab-c332-44b9-98f1-e42b4fbd7fc7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=547719184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.547719184 |
Directory | /workspace/40.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/40.spi_device_read_buffer_direct.325874428 |
Short name | T706 |
Test name | |
Test status | |
Simulation time | 1180646527 ps |
CPU time | 11.73 seconds |
Started | Jul 15 06:50:03 PM PDT 24 |
Finished | Jul 15 06:50:15 PM PDT 24 |
Peak memory | 221964 kb |
Host | smart-4d8fc343-2d2e-40fb-89d6-ad6eae9be659 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=325874428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire ct.325874428 |
Directory | /workspace/40.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/40.spi_device_stress_all.3857228918 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 58116780 ps |
CPU time | 1.13 seconds |
Started | Jul 15 06:50:12 PM PDT 24 |
Finished | Jul 15 06:50:13 PM PDT 24 |
Peak memory | 215104 kb |
Host | smart-3e7ebf73-09f2-46ab-aa9b-d9df044dbac0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857228918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre ss_all.3857228918 |
Directory | /workspace/40.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/40.spi_device_tpm_all.1063149540 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 2270805993 ps |
CPU time | 20.98 seconds |
Started | Jul 15 06:50:05 PM PDT 24 |
Finished | Jul 15 06:50:26 PM PDT 24 |
Peak memory | 216244 kb |
Host | smart-e8ddfa81-2c87-4725-a5e3-342016dcf446 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1063149540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1063149540 |
Directory | /workspace/40.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.4020636787 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 7189995503 ps |
CPU time | 6.74 seconds |
Started | Jul 15 06:50:03 PM PDT 24 |
Finished | Jul 15 06:50:10 PM PDT 24 |
Peak memory | 216312 kb |
Host | smart-16165988-1cdc-4a05-a1d5-c1a145c0d397 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4020636787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.4020636787 |
Directory | /workspace/40.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/40.spi_device_tpm_rw.2682016978 |
Short name | T507 |
Test name | |
Test status | |
Simulation time | 72653286 ps |
CPU time | 0.94 seconds |
Started | Jul 15 06:50:04 PM PDT 24 |
Finished | Jul 15 06:50:05 PM PDT 24 |
Peak memory | 206512 kb |
Host | smart-144fc7bd-91d3-406c-99da-18b4e4a2dd3f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2682016978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2682016978 |
Directory | /workspace/40.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/40.spi_device_tpm_sts_read.2175427038 |
Short name | T1009 |
Test name | |
Test status | |
Simulation time | 118146593 ps |
CPU time | 0.87 seconds |
Started | Jul 15 06:50:07 PM PDT 24 |
Finished | Jul 15 06:50:08 PM PDT 24 |
Peak memory | 205936 kb |
Host | smart-b3479761-e12f-48d7-9138-2edf8735c0d4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2175427038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2175427038 |
Directory | /workspace/40.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/40.spi_device_upload.610845529 |
Short name | T522 |
Test name | |
Test status | |
Simulation time | 264784428 ps |
CPU time | 2.72 seconds |
Started | Jul 15 06:50:05 PM PDT 24 |
Finished | Jul 15 06:50:09 PM PDT 24 |
Peak memory | 224212 kb |
Host | smart-9d4c6fd8-be7e-4fee-a102-021b999685e8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=610845529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.610845529 |
Directory | /workspace/40.spi_device_upload/latest |
Test location | /workspace/coverage/default/41.spi_device_alert_test.2125255048 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 41614103 ps |
CPU time | 0.69 seconds |
Started | Jul 15 06:50:19 PM PDT 24 |
Finished | Jul 15 06:50:20 PM PDT 24 |
Peak memory | 205440 kb |
Host | smart-47781c9c-ab10-47dd-b86f-e329944c7806 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125255048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test. 2125255048 |
Directory | /workspace/41.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/41.spi_device_cfg_cmd.2190121113 |
Short name | T473 |
Test name | |
Test status | |
Simulation time | 258862925 ps |
CPU time | 2.85 seconds |
Started | Jul 15 06:50:11 PM PDT 24 |
Finished | Jul 15 06:50:14 PM PDT 24 |
Peak memory | 224420 kb |
Host | smart-c300487b-a23c-4662-853a-df83c9d51a4e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2190121113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2190121113 |
Directory | /workspace/41.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/41.spi_device_csb_read.358738292 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 17513020 ps |
CPU time | 0.79 seconds |
Started | Jul 15 06:50:10 PM PDT 24 |
Finished | Jul 15 06:50:11 PM PDT 24 |
Peak memory | 206584 kb |
Host | smart-5d8d7787-f2e8-4bc5-af38-e7bd138539a9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=358738292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.358738292 |
Directory | /workspace/41.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/41.spi_device_flash_all.663012055 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 65821634950 ps |
CPU time | 127.16 seconds |
Started | Jul 15 06:50:13 PM PDT 24 |
Finished | Jul 15 06:52:20 PM PDT 24 |
Peak memory | 257360 kb |
Host | smart-9eb25208-7615-438c-8132-66b01258576e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=663012055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.663012055 |
Directory | /workspace/41.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/41.spi_device_flash_and_tpm.586325916 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 1657614065 ps |
CPU time | 26.63 seconds |
Started | Jul 15 06:50:22 PM PDT 24 |
Finished | Jul 15 06:50:49 PM PDT 24 |
Peak memory | 233732 kb |
Host | smart-acc211af-f38b-4c85-acd9-d343c58ded33 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=586325916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.586325916 |
Directory | /workspace/41.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.867282352 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 40845791162 ps |
CPU time | 374.8 seconds |
Started | Jul 15 06:50:20 PM PDT 24 |
Finished | Jul 15 06:56:35 PM PDT 24 |
Peak memory | 266596 kb |
Host | smart-ab790f1a-e894-4d80-ad84-7775ff2bd75a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=867282352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle .867282352 |
Directory | /workspace/41.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/41.spi_device_flash_mode.3391186627 |
Short name | T853 |
Test name | |
Test status | |
Simulation time | 5281022091 ps |
CPU time | 37.18 seconds |
Started | Jul 15 06:50:15 PM PDT 24 |
Finished | Jul 15 06:50:52 PM PDT 24 |
Peak memory | 240960 kb |
Host | smart-4cc4885d-9157-4103-b2eb-97c8faa28a55 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3391186627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3391186627 |
Directory | /workspace/41.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.2011025920 |
Short name | T951 |
Test name | |
Test status | |
Simulation time | 3602003287 ps |
CPU time | 49.37 seconds |
Started | Jul 15 06:50:13 PM PDT 24 |
Finished | Jul 15 06:51:03 PM PDT 24 |
Peak memory | 249544 kb |
Host | smart-4cd14bba-c65c-4cde-945a-d0102c8fb083 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2011025920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd s.2011025920 |
Directory | /workspace/41.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/41.spi_device_intercept.2055883191 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 1849845116 ps |
CPU time | 16.78 seconds |
Started | Jul 15 06:50:13 PM PDT 24 |
Finished | Jul 15 06:50:30 PM PDT 24 |
Peak memory | 224396 kb |
Host | smart-fb1b744f-1467-4f05-bc18-351aa4e01e5a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2055883191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2055883191 |
Directory | /workspace/41.spi_device_intercept/latest |
Test location | /workspace/coverage/default/41.spi_device_mailbox.4271889748 |
Short name | T575 |
Test name | |
Test status | |
Simulation time | 7442958316 ps |
CPU time | 26.05 seconds |
Started | Jul 15 06:50:12 PM PDT 24 |
Finished | Jul 15 06:50:39 PM PDT 24 |
Peak memory | 232732 kb |
Host | smart-65b8d8a7-ae06-4d8d-b78a-ad34ef299668 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4271889748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.4271889748 |
Directory | /workspace/41.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2713425317 |
Short name | T920 |
Test name | |
Test status | |
Simulation time | 356322280 ps |
CPU time | 2.24 seconds |
Started | Jul 15 06:50:10 PM PDT 24 |
Finished | Jul 15 06:50:13 PM PDT 24 |
Peak memory | 223988 kb |
Host | smart-15c1e577-63db-475e-a659-6ab6d951f4d0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2713425317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa p.2713425317 |
Directory | /workspace/41.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3872678403 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 4044863428 ps |
CPU time | 11.15 seconds |
Started | Jul 15 06:50:11 PM PDT 24 |
Finished | Jul 15 06:50:22 PM PDT 24 |
Peak memory | 232672 kb |
Host | smart-65fd1f64-bcec-437f-8180-0578c67a6db3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3872678403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3872678403 |
Directory | /workspace/41.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/41.spi_device_read_buffer_direct.67794390 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 156921879 ps |
CPU time | 4.7 seconds |
Started | Jul 15 06:50:12 PM PDT 24 |
Finished | Jul 15 06:50:17 PM PDT 24 |
Peak memory | 223080 kb |
Host | smart-3d4b5e89-99e6-46e7-83f0-2ec11741c5ed |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=67794390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direc t.67794390 |
Directory | /workspace/41.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/41.spi_device_stress_all.3001403050 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 22180166889 ps |
CPU time | 141.16 seconds |
Started | Jul 15 06:50:23 PM PDT 24 |
Finished | Jul 15 06:52:44 PM PDT 24 |
Peak memory | 281384 kb |
Host | smart-1a01858d-b6e4-4497-8c0e-8eeda26090a4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001403050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre ss_all.3001403050 |
Directory | /workspace/41.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/41.spi_device_tpm_all.1411383877 |
Short name | T662 |
Test name | |
Test status | |
Simulation time | 379054267 ps |
CPU time | 6.15 seconds |
Started | Jul 15 06:50:09 PM PDT 24 |
Finished | Jul 15 06:50:16 PM PDT 24 |
Peak memory | 216468 kb |
Host | smart-43a1986a-6cc4-4cb4-acb2-2ff8aef8621e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1411383877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1411383877 |
Directory | /workspace/41.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.623232922 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 1784858470 ps |
CPU time | 5.08 seconds |
Started | Jul 15 06:50:10 PM PDT 24 |
Finished | Jul 15 06:50:16 PM PDT 24 |
Peak memory | 216268 kb |
Host | smart-9e32d88b-4875-42c7-87cf-5f255972ec4b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=623232922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.623232922 |
Directory | /workspace/41.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/41.spi_device_tpm_rw.3380741666 |
Short name | T763 |
Test name | |
Test status | |
Simulation time | 53249471 ps |
CPU time | 0.79 seconds |
Started | Jul 15 06:50:15 PM PDT 24 |
Finished | Jul 15 06:50:16 PM PDT 24 |
Peak memory | 205928 kb |
Host | smart-778a8fd0-5489-4299-91a9-54b2076adf9c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3380741666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3380741666 |
Directory | /workspace/41.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/41.spi_device_tpm_sts_read.3889880686 |
Short name | T1010 |
Test name | |
Test status | |
Simulation time | 455602747 ps |
CPU time | 1.03 seconds |
Started | Jul 15 06:50:11 PM PDT 24 |
Finished | Jul 15 06:50:12 PM PDT 24 |
Peak memory | 206948 kb |
Host | smart-1046fc31-a5cd-45ca-b9ee-5ae4e3795408 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3889880686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3889880686 |
Directory | /workspace/41.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/41.spi_device_upload.1021108137 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 1092602759 ps |
CPU time | 3.94 seconds |
Started | Jul 15 06:50:10 PM PDT 24 |
Finished | Jul 15 06:50:14 PM PDT 24 |
Peak memory | 224372 kb |
Host | smart-0cc91874-a485-4a19-a3b6-674c1e1786e4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1021108137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1021108137 |
Directory | /workspace/41.spi_device_upload/latest |
Test location | /workspace/coverage/default/42.spi_device_alert_test.393870120 |
Short name | T998 |
Test name | |
Test status | |
Simulation time | 42018789 ps |
CPU time | 0.7 seconds |
Started | Jul 15 06:50:26 PM PDT 24 |
Finished | Jul 15 06:50:27 PM PDT 24 |
Peak memory | 204952 kb |
Host | smart-980c45b7-db64-4e87-993a-6a1dd9ca1aef |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393870120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.393870120 |
Directory | /workspace/42.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/42.spi_device_cfg_cmd.539827304 |
Short name | T632 |
Test name | |
Test status | |
Simulation time | 2520271002 ps |
CPU time | 14.32 seconds |
Started | Jul 15 06:50:21 PM PDT 24 |
Finished | Jul 15 06:50:35 PM PDT 24 |
Peak memory | 232784 kb |
Host | smart-a94b39c0-1ea1-4ed6-bb35-e26ff6677e9f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=539827304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.539827304 |
Directory | /workspace/42.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/42.spi_device_csb_read.800192633 |
Short name | T605 |
Test name | |
Test status | |
Simulation time | 46504865 ps |
CPU time | 0.8 seconds |
Started | Jul 15 06:50:21 PM PDT 24 |
Finished | Jul 15 06:50:22 PM PDT 24 |
Peak memory | 206556 kb |
Host | smart-b8220d65-4215-49af-bba3-87cf45907933 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=800192633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.800192633 |
Directory | /workspace/42.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/42.spi_device_flash_all.2882569098 |
Short name | T601 |
Test name | |
Test status | |
Simulation time | 10149320980 ps |
CPU time | 75.78 seconds |
Started | Jul 15 06:50:19 PM PDT 24 |
Finished | Jul 15 06:51:35 PM PDT 24 |
Peak memory | 240956 kb |
Host | smart-39eb8e21-a4d2-42b5-81a3-3f59a22b380b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2882569098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2882569098 |
Directory | /workspace/42.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/42.spi_device_flash_and_tpm.1368623348 |
Short name | T855 |
Test name | |
Test status | |
Simulation time | 1774205848 ps |
CPU time | 26.95 seconds |
Started | Jul 15 06:50:23 PM PDT 24 |
Finished | Jul 15 06:50:50 PM PDT 24 |
Peak memory | 240892 kb |
Host | smart-cb41cc02-1cfc-4dd5-b705-2f8311c97528 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1368623348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1368623348 |
Directory | /workspace/42.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1558451224 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 71723420662 ps |
CPU time | 91.57 seconds |
Started | Jul 15 06:50:25 PM PDT 24 |
Finished | Jul 15 06:51:57 PM PDT 24 |
Peak memory | 250592 kb |
Host | smart-b8e020fb-6af9-4167-b22a-f3e0053ba5c3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1558451224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl e.1558451224 |
Directory | /workspace/42.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/42.spi_device_flash_mode.3622155397 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 3520571421 ps |
CPU time | 16.57 seconds |
Started | Jul 15 06:50:22 PM PDT 24 |
Finished | Jul 15 06:50:40 PM PDT 24 |
Peak memory | 224584 kb |
Host | smart-37364f12-4de0-4771-9515-19876f5dbc64 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3622155397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3622155397 |
Directory | /workspace/42.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.2368870397 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 1679091209 ps |
CPU time | 17.08 seconds |
Started | Jul 15 06:50:20 PM PDT 24 |
Finished | Jul 15 06:50:37 PM PDT 24 |
Peak memory | 236260 kb |
Host | smart-fedc3f73-9e17-4f11-950d-9ddd06f25d82 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2368870397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd s.2368870397 |
Directory | /workspace/42.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/42.spi_device_intercept.2698037455 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 1029960056 ps |
CPU time | 11.89 seconds |
Started | Jul 15 06:50:18 PM PDT 24 |
Finished | Jul 15 06:50:30 PM PDT 24 |
Peak memory | 224404 kb |
Host | smart-16dc2f0b-9eee-4fd3-8f4d-08e04546a254 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2698037455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2698037455 |
Directory | /workspace/42.spi_device_intercept/latest |
Test location | /workspace/coverage/default/42.spi_device_mailbox.1287953846 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 213132111 ps |
CPU time | 2.43 seconds |
Started | Jul 15 06:50:22 PM PDT 24 |
Finished | Jul 15 06:50:25 PM PDT 24 |
Peak memory | 232364 kb |
Host | smart-e93aea26-2dbb-4551-be51-2579baabedbe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1287953846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1287953846 |
Directory | /workspace/42.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.4116209448 |
Short name | T478 |
Test name | |
Test status | |
Simulation time | 516512614 ps |
CPU time | 5.72 seconds |
Started | Jul 15 06:50:22 PM PDT 24 |
Finished | Jul 15 06:50:28 PM PDT 24 |
Peak memory | 232588 kb |
Host | smart-f1592647-2d7e-47f8-9cf2-78cfaf3108d3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4116209448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa p.4116209448 |
Directory | /workspace/42.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/42.spi_device_pass_cmd_filtering.312947525 |
Short name | T941 |
Test name | |
Test status | |
Simulation time | 27738916857 ps |
CPU time | 11.06 seconds |
Started | Jul 15 06:50:19 PM PDT 24 |
Finished | Jul 15 06:50:31 PM PDT 24 |
Peak memory | 224548 kb |
Host | smart-a33c8584-9bfd-4846-805e-811a9fe3c50b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=312947525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.312947525 |
Directory | /workspace/42.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/42.spi_device_read_buffer_direct.1553337541 |
Short name | T713 |
Test name | |
Test status | |
Simulation time | 1320335866 ps |
CPU time | 5.41 seconds |
Started | Jul 15 06:50:17 PM PDT 24 |
Finished | Jul 15 06:50:22 PM PDT 24 |
Peak memory | 218772 kb |
Host | smart-7d7a4591-cece-4873-872e-712376f12b99 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1553337541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir ect.1553337541 |
Directory | /workspace/42.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/42.spi_device_stress_all.2721382346 |
Short name | T495 |
Test name | |
Test status | |
Simulation time | 370606853281 ps |
CPU time | 407.75 seconds |
Started | Jul 15 06:50:23 PM PDT 24 |
Finished | Jul 15 06:57:11 PM PDT 24 |
Peak memory | 256172 kb |
Host | smart-30f25f6c-ba46-4466-a255-40b3c6f52aef |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721382346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre ss_all.2721382346 |
Directory | /workspace/42.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/42.spi_device_tpm_all.132675569 |
Short name | T525 |
Test name | |
Test status | |
Simulation time | 2385358152 ps |
CPU time | 24.19 seconds |
Started | Jul 15 06:50:18 PM PDT 24 |
Finished | Jul 15 06:50:43 PM PDT 24 |
Peak memory | 216420 kb |
Host | smart-e5c11a19-253d-41e6-84ff-7b0cecd8d866 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=132675569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.132675569 |
Directory | /workspace/42.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1452974684 |
Short name | T929 |
Test name | |
Test status | |
Simulation time | 2155534161 ps |
CPU time | 7.2 seconds |
Started | Jul 15 06:50:20 PM PDT 24 |
Finished | Jul 15 06:50:28 PM PDT 24 |
Peak memory | 216176 kb |
Host | smart-666b640f-42c2-4a90-b94b-eb993364e010 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1452974684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1452974684 |
Directory | /workspace/42.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/42.spi_device_tpm_rw.1754582016 |
Short name | T947 |
Test name | |
Test status | |
Simulation time | 87840509 ps |
CPU time | 3.11 seconds |
Started | Jul 15 06:50:22 PM PDT 24 |
Finished | Jul 15 06:50:26 PM PDT 24 |
Peak memory | 216152 kb |
Host | smart-32967a35-b9cd-432c-a330-e5ea40d6af3e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1754582016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1754582016 |
Directory | /workspace/42.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/42.spi_device_tpm_sts_read.3272944922 |
Short name | T521 |
Test name | |
Test status | |
Simulation time | 79434425 ps |
CPU time | 0.82 seconds |
Started | Jul 15 06:50:18 PM PDT 24 |
Finished | Jul 15 06:50:19 PM PDT 24 |
Peak memory | 205928 kb |
Host | smart-96fe61e6-93fd-4b50-bc1f-2f87158cbd07 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3272944922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3272944922 |
Directory | /workspace/42.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/42.spi_device_upload.2215578927 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 856907373 ps |
CPU time | 3.91 seconds |
Started | Jul 15 06:50:20 PM PDT 24 |
Finished | Jul 15 06:50:24 PM PDT 24 |
Peak memory | 232548 kb |
Host | smart-ec9316fc-a214-4337-b9a6-3cd3e409cdab |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2215578927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2215578927 |
Directory | /workspace/42.spi_device_upload/latest |
Test location | /workspace/coverage/default/43.spi_device_alert_test.450474302 |
Short name | T523 |
Test name | |
Test status | |
Simulation time | 119415180 ps |
CPU time | 0.73 seconds |
Started | Jul 15 06:50:30 PM PDT 24 |
Finished | Jul 15 06:50:31 PM PDT 24 |
Peak memory | 205740 kb |
Host | smart-343b9d60-d821-4b27-a259-0b548b422911 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450474302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.450474302 |
Directory | /workspace/43.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/43.spi_device_cfg_cmd.2598667968 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 214343716 ps |
CPU time | 2.89 seconds |
Started | Jul 15 06:50:26 PM PDT 24 |
Finished | Jul 15 06:50:29 PM PDT 24 |
Peak memory | 232648 kb |
Host | smart-c10ada86-5f2f-444d-852f-676750b45325 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2598667968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2598667968 |
Directory | /workspace/43.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/43.spi_device_csb_read.4118940291 |
Short name | T939 |
Test name | |
Test status | |
Simulation time | 59936160 ps |
CPU time | 0.78 seconds |
Started | Jul 15 06:50:22 PM PDT 24 |
Finished | Jul 15 06:50:23 PM PDT 24 |
Peak memory | 206516 kb |
Host | smart-c5d8ee00-0305-4c92-b347-6278ba91caa5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4118940291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.4118940291 |
Directory | /workspace/43.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/43.spi_device_flash_all.564895375 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 47508930179 ps |
CPU time | 164.21 seconds |
Started | Jul 15 06:50:30 PM PDT 24 |
Finished | Jul 15 06:53:15 PM PDT 24 |
Peak memory | 249508 kb |
Host | smart-572bd344-3d65-4dc4-98b8-f677e2a69b03 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=564895375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.564895375 |
Directory | /workspace/43.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/43.spi_device_flash_and_tpm.855731315 |
Short name | T705 |
Test name | |
Test status | |
Simulation time | 249157508592 ps |
CPU time | 578.79 seconds |
Started | Jul 15 06:50:29 PM PDT 24 |
Finished | Jul 15 07:00:09 PM PDT 24 |
Peak memory | 269484 kb |
Host | smart-a4731257-b12a-4f3b-923d-f6ea25b2d9c6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=855731315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.855731315 |
Directory | /workspace/43.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.629058207 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 37915204077 ps |
CPU time | 383.42 seconds |
Started | Jul 15 06:50:33 PM PDT 24 |
Finished | Jul 15 06:56:57 PM PDT 24 |
Peak memory | 249236 kb |
Host | smart-3dfb6994-ddf0-4ae8-9729-e8689c577590 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=629058207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle .629058207 |
Directory | /workspace/43.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/43.spi_device_flash_mode.312207474 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 3837296679 ps |
CPU time | 35.89 seconds |
Started | Jul 15 06:50:42 PM PDT 24 |
Finished | Jul 15 06:51:19 PM PDT 24 |
Peak memory | 224504 kb |
Host | smart-cc654ecc-1892-45f1-90e7-21b663cb075a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=312207474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.312207474 |
Directory | /workspace/43.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.4158817846 |
Short name | T1013 |
Test name | |
Test status | |
Simulation time | 34680437729 ps |
CPU time | 70.76 seconds |
Started | Jul 15 06:50:33 PM PDT 24 |
Finished | Jul 15 06:51:44 PM PDT 24 |
Peak memory | 249124 kb |
Host | smart-4fd22492-4773-4f80-bbe7-67517b58d2c3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4158817846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd s.4158817846 |
Directory | /workspace/43.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/43.spi_device_intercept.4285758852 |
Short name | T729 |
Test name | |
Test status | |
Simulation time | 34111788 ps |
CPU time | 2.68 seconds |
Started | Jul 15 06:50:27 PM PDT 24 |
Finished | Jul 15 06:50:30 PM PDT 24 |
Peak memory | 232604 kb |
Host | smart-fe3e9b8f-de4e-48fc-a9ee-1d7e1e128e28 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4285758852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.4285758852 |
Directory | /workspace/43.spi_device_intercept/latest |
Test location | /workspace/coverage/default/43.spi_device_mailbox.123958833 |
Short name | T858 |
Test name | |
Test status | |
Simulation time | 9908678110 ps |
CPU time | 27.02 seconds |
Started | Jul 15 06:50:22 PM PDT 24 |
Finished | Jul 15 06:50:49 PM PDT 24 |
Peak memory | 224460 kb |
Host | smart-bf4936d2-63fd-40cc-adcd-556beec66490 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=123958833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.123958833 |
Directory | /workspace/43.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2429787428 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 482859225 ps |
CPU time | 5.37 seconds |
Started | Jul 15 06:50:26 PM PDT 24 |
Finished | Jul 15 06:50:32 PM PDT 24 |
Peak memory | 240608 kb |
Host | smart-0b682f87-a5d5-4b22-9f7d-035ceecc39ae |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2429787428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa p.2429787428 |
Directory | /workspace/43.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2094655321 |
Short name | T648 |
Test name | |
Test status | |
Simulation time | 677110226 ps |
CPU time | 2.75 seconds |
Started | Jul 15 06:50:25 PM PDT 24 |
Finished | Jul 15 06:50:28 PM PDT 24 |
Peak memory | 232568 kb |
Host | smart-0794743b-e436-4730-acf8-c7b83d28047a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2094655321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2094655321 |
Directory | /workspace/43.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/43.spi_device_read_buffer_direct.1847748510 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 617865747 ps |
CPU time | 7.9 seconds |
Started | Jul 15 06:50:30 PM PDT 24 |
Finished | Jul 15 06:50:38 PM PDT 24 |
Peak memory | 219240 kb |
Host | smart-2e970d24-2600-4d8f-84b1-be109d9e0f5e |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1847748510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir ect.1847748510 |
Directory | /workspace/43.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/43.spi_device_stress_all.2300020302 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 2577283315 ps |
CPU time | 38.35 seconds |
Started | Jul 15 06:50:42 PM PDT 24 |
Finished | Jul 15 06:51:21 PM PDT 24 |
Peak memory | 224616 kb |
Host | smart-b7a0ed38-cf1d-485b-b372-47229c366bc7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300020302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre ss_all.2300020302 |
Directory | /workspace/43.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/43.spi_device_tpm_all.1070556951 |
Short name | T907 |
Test name | |
Test status | |
Simulation time | 1557294919 ps |
CPU time | 5.96 seconds |
Started | Jul 15 06:50:25 PM PDT 24 |
Finished | Jul 15 06:50:31 PM PDT 24 |
Peak memory | 216548 kb |
Host | smart-71d2a116-5dfa-4f11-a2df-793fcfc0e42c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1070556951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1070556951 |
Directory | /workspace/43.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.56773263 |
Short name | T908 |
Test name | |
Test status | |
Simulation time | 355985017 ps |
CPU time | 1.6 seconds |
Started | Jul 15 06:50:25 PM PDT 24 |
Finished | Jul 15 06:50:26 PM PDT 24 |
Peak memory | 207832 kb |
Host | smart-765fe8ee-1b2c-4e3a-8075-cfe0dba94e1c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=56773263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.56773263 |
Directory | /workspace/43.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/43.spi_device_tpm_rw.2573258952 |
Short name | T790 |
Test name | |
Test status | |
Simulation time | 115324015 ps |
CPU time | 2.55 seconds |
Started | Jul 15 06:50:25 PM PDT 24 |
Finished | Jul 15 06:50:28 PM PDT 24 |
Peak memory | 216148 kb |
Host | smart-73f90934-dd33-429c-afe9-5b04b492bc6d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2573258952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2573258952 |
Directory | /workspace/43.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/43.spi_device_tpm_sts_read.2389429524 |
Short name | T756 |
Test name | |
Test status | |
Simulation time | 68480927 ps |
CPU time | 0.9 seconds |
Started | Jul 15 06:50:26 PM PDT 24 |
Finished | Jul 15 06:50:28 PM PDT 24 |
Peak memory | 205944 kb |
Host | smart-059f25d7-474e-4d35-ac12-7193378e6ea6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2389429524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2389429524 |
Directory | /workspace/43.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/43.spi_device_upload.3521701181 |
Short name | T748 |
Test name | |
Test status | |
Simulation time | 6898354037 ps |
CPU time | 12.21 seconds |
Started | Jul 15 06:50:26 PM PDT 24 |
Finished | Jul 15 06:50:39 PM PDT 24 |
Peak memory | 232704 kb |
Host | smart-75d41482-3567-466b-a82b-4a4c1d236c0a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3521701181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3521701181 |
Directory | /workspace/43.spi_device_upload/latest |
Test location | /workspace/coverage/default/44.spi_device_alert_test.2472715286 |
Short name | T536 |
Test name | |
Test status | |
Simulation time | 35074947 ps |
CPU time | 0.72 seconds |
Started | Jul 15 06:50:38 PM PDT 24 |
Finished | Jul 15 06:50:39 PM PDT 24 |
Peak memory | 204904 kb |
Host | smart-b2497b52-a98e-49dc-868a-9d67b0b1ffe1 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472715286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test. 2472715286 |
Directory | /workspace/44.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/44.spi_device_cfg_cmd.3546311523 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 637586602 ps |
CPU time | 4.26 seconds |
Started | Jul 15 06:50:30 PM PDT 24 |
Finished | Jul 15 06:50:35 PM PDT 24 |
Peak memory | 232576 kb |
Host | smart-9529834b-90f1-46cd-b41a-290edecb6a79 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3546311523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3546311523 |
Directory | /workspace/44.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/44.spi_device_csb_read.1649807984 |
Short name | T718 |
Test name | |
Test status | |
Simulation time | 21662799 ps |
CPU time | 0.77 seconds |
Started | Jul 15 06:50:32 PM PDT 24 |
Finished | Jul 15 06:50:33 PM PDT 24 |
Peak memory | 205548 kb |
Host | smart-eb8138cf-0e25-4abf-8a58-37bbd4fdb2d9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1649807984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1649807984 |
Directory | /workspace/44.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/44.spi_device_flash_all.1935513118 |
Short name | T932 |
Test name | |
Test status | |
Simulation time | 16617469 ps |
CPU time | 0.76 seconds |
Started | Jul 15 06:50:35 PM PDT 24 |
Finished | Jul 15 06:50:36 PM PDT 24 |
Peak memory | 215748 kb |
Host | smart-9a1baf13-73c9-49df-9db0-6c01846b4bb8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1935513118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1935513118 |
Directory | /workspace/44.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/44.spi_device_flash_and_tpm.2106884629 |
Short name | T818 |
Test name | |
Test status | |
Simulation time | 410839168595 ps |
CPU time | 271.95 seconds |
Started | Jul 15 06:50:37 PM PDT 24 |
Finished | Jul 15 06:55:09 PM PDT 24 |
Peak memory | 272300 kb |
Host | smart-8b11c0cc-33e3-4fdf-936d-729b54868105 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2106884629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2106884629 |
Directory | /workspace/44.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/44.spi_device_flash_mode.3361538103 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 962121412 ps |
CPU time | 12.84 seconds |
Started | Jul 15 06:50:37 PM PDT 24 |
Finished | Jul 15 06:50:51 PM PDT 24 |
Peak memory | 232972 kb |
Host | smart-79a515f3-02c8-49ca-a6dc-437e4926c88f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3361538103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3361538103 |
Directory | /workspace/44.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/44.spi_device_intercept.2587115406 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 4697706536 ps |
CPU time | 12.68 seconds |
Started | Jul 15 06:50:30 PM PDT 24 |
Finished | Jul 15 06:50:43 PM PDT 24 |
Peak memory | 224484 kb |
Host | smart-707cc47b-58f1-42c0-a1e4-f9f9e02bc856 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2587115406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2587115406 |
Directory | /workspace/44.spi_device_intercept/latest |
Test location | /workspace/coverage/default/44.spi_device_mailbox.3589085021 |
Short name | T509 |
Test name | |
Test status | |
Simulation time | 600896641 ps |
CPU time | 8.6 seconds |
Started | Jul 15 06:50:32 PM PDT 24 |
Finished | Jul 15 06:50:41 PM PDT 24 |
Peak memory | 234420 kb |
Host | smart-442b9954-fda3-4652-b761-377925ade076 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3589085021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3589085021 |
Directory | /workspace/44.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2593920456 |
Short name | T926 |
Test name | |
Test status | |
Simulation time | 690367593 ps |
CPU time | 4.47 seconds |
Started | Jul 15 06:50:32 PM PDT 24 |
Finished | Jul 15 06:50:37 PM PDT 24 |
Peak memory | 232572 kb |
Host | smart-8ececa49-9931-42d3-aee2-66c2b3bc2275 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2593920456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa p.2593920456 |
Directory | /workspace/44.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1038763537 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 439353565 ps |
CPU time | 7.78 seconds |
Started | Jul 15 06:50:30 PM PDT 24 |
Finished | Jul 15 06:50:38 PM PDT 24 |
Peak memory | 248412 kb |
Host | smart-c79a45ac-232a-4cbe-b710-7fb63c2abc05 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1038763537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1038763537 |
Directory | /workspace/44.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/44.spi_device_read_buffer_direct.897097069 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 121552558 ps |
CPU time | 4.29 seconds |
Started | Jul 15 06:50:37 PM PDT 24 |
Finished | Jul 15 06:50:42 PM PDT 24 |
Peak memory | 222996 kb |
Host | smart-17e98748-d15e-4377-ac06-b40720e20155 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=897097069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire ct.897097069 |
Directory | /workspace/44.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/44.spi_device_stress_all.3008619637 |
Short name | T481 |
Test name | |
Test status | |
Simulation time | 48900652 ps |
CPU time | 1.11 seconds |
Started | Jul 15 06:50:37 PM PDT 24 |
Finished | Jul 15 06:50:38 PM PDT 24 |
Peak memory | 207680 kb |
Host | smart-635f5c0a-4d19-4407-9a91-213c4bba52d2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008619637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre ss_all.3008619637 |
Directory | /workspace/44.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/44.spi_device_tpm_all.110143387 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 3568605347 ps |
CPU time | 19.71 seconds |
Started | Jul 15 06:50:31 PM PDT 24 |
Finished | Jul 15 06:50:51 PM PDT 24 |
Peak memory | 216332 kb |
Host | smart-36b35c80-a580-4d2e-9a8b-f8b43f2ac85f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=110143387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.110143387 |
Directory | /workspace/44.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1793296958 |
Short name | T798 |
Test name | |
Test status | |
Simulation time | 6730910739 ps |
CPU time | 6.58 seconds |
Started | Jul 15 06:50:42 PM PDT 24 |
Finished | Jul 15 06:50:49 PM PDT 24 |
Peak memory | 216224 kb |
Host | smart-3570ed59-40b5-4548-9ce6-c7d53e33bf90 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1793296958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1793296958 |
Directory | /workspace/44.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/44.spi_device_tpm_rw.2303966489 |
Short name | T921 |
Test name | |
Test status | |
Simulation time | 287077566 ps |
CPU time | 2.66 seconds |
Started | Jul 15 06:50:41 PM PDT 24 |
Finished | Jul 15 06:50:44 PM PDT 24 |
Peak memory | 216184 kb |
Host | smart-5c185703-69da-420a-a269-e829f0b5d606 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2303966489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2303966489 |
Directory | /workspace/44.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/44.spi_device_tpm_sts_read.579826748 |
Short name | T799 |
Test name | |
Test status | |
Simulation time | 22919210 ps |
CPU time | 0.72 seconds |
Started | Jul 15 06:50:32 PM PDT 24 |
Finished | Jul 15 06:50:33 PM PDT 24 |
Peak memory | 205936 kb |
Host | smart-e477529a-56c1-4b05-9fdb-15c4655baa4d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=579826748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.579826748 |
Directory | /workspace/44.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/44.spi_device_upload.884679299 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 315299412 ps |
CPU time | 6 seconds |
Started | Jul 15 06:50:42 PM PDT 24 |
Finished | Jul 15 06:50:48 PM PDT 24 |
Peak memory | 222524 kb |
Host | smart-35a9136f-2fa1-430b-b2fe-9daffb527977 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=884679299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.884679299 |
Directory | /workspace/44.spi_device_upload/latest |
Test location | /workspace/coverage/default/45.spi_device_alert_test.4219288919 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 40700761 ps |
CPU time | 0.7 seconds |
Started | Jul 15 06:50:42 PM PDT 24 |
Finished | Jul 15 06:50:44 PM PDT 24 |
Peak memory | 204888 kb |
Host | smart-1c8fbcbd-435c-40e5-ad18-f510ffba774c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219288919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test. 4219288919 |
Directory | /workspace/45.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/45.spi_device_cfg_cmd.869827667 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 64074334 ps |
CPU time | 2.65 seconds |
Started | Jul 15 06:50:38 PM PDT 24 |
Finished | Jul 15 06:50:41 PM PDT 24 |
Peak memory | 232648 kb |
Host | smart-a497c873-79d6-4e6a-b115-a614b89d8adb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=869827667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.869827667 |
Directory | /workspace/45.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/45.spi_device_csb_read.2082999924 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 17676640 ps |
CPU time | 0.76 seconds |
Started | Jul 15 06:50:39 PM PDT 24 |
Finished | Jul 15 06:50:40 PM PDT 24 |
Peak memory | 205516 kb |
Host | smart-1cdc812a-883b-4212-a7be-de0f4e663f68 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2082999924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2082999924 |
Directory | /workspace/45.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/45.spi_device_flash_all.3309866755 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 11679421214 ps |
CPU time | 21.42 seconds |
Started | Jul 15 06:50:46 PM PDT 24 |
Finished | Jul 15 06:51:07 PM PDT 24 |
Peak memory | 238876 kb |
Host | smart-512b94ac-2c64-4260-8362-381c8a2832b4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3309866755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3309866755 |
Directory | /workspace/45.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/45.spi_device_flash_and_tpm.356025585 |
Short name | T758 |
Test name | |
Test status | |
Simulation time | 10455851055 ps |
CPU time | 50.67 seconds |
Started | Jul 15 06:50:42 PM PDT 24 |
Finished | Jul 15 06:51:33 PM PDT 24 |
Peak memory | 224640 kb |
Host | smart-a7d0cf3d-06f5-40bf-ba23-838c73e91e27 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=356025585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.356025585 |
Directory | /workspace/45.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/45.spi_device_flash_mode.409328211 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 817927972 ps |
CPU time | 9.24 seconds |
Started | Jul 15 06:50:38 PM PDT 24 |
Finished | Jul 15 06:50:48 PM PDT 24 |
Peak memory | 235096 kb |
Host | smart-3e9079d4-fff0-4a8e-9714-7eb7a64a503e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=409328211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.409328211 |
Directory | /workspace/45.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.553910423 |
Short name | T1000 |
Test name | |
Test status | |
Simulation time | 14207542 ps |
CPU time | 0.77 seconds |
Started | Jul 15 06:50:38 PM PDT 24 |
Finished | Jul 15 06:50:40 PM PDT 24 |
Peak memory | 215736 kb |
Host | smart-31be7f0d-1046-4216-ac2f-90dc01534ec5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=553910423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds .553910423 |
Directory | /workspace/45.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/45.spi_device_intercept.3970055968 |
Short name | T898 |
Test name | |
Test status | |
Simulation time | 34093377 ps |
CPU time | 2.48 seconds |
Started | Jul 15 06:50:36 PM PDT 24 |
Finished | Jul 15 06:50:40 PM PDT 24 |
Peak memory | 232220 kb |
Host | smart-138973fb-f6d3-428f-9cf1-4640f7e25bf3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3970055968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3970055968 |
Directory | /workspace/45.spi_device_intercept/latest |
Test location | /workspace/coverage/default/45.spi_device_mailbox.2799414341 |
Short name | T541 |
Test name | |
Test status | |
Simulation time | 22054103899 ps |
CPU time | 85 seconds |
Started | Jul 15 06:50:38 PM PDT 24 |
Finished | Jul 15 06:52:03 PM PDT 24 |
Peak memory | 232768 kb |
Host | smart-6ce5eb24-fe9e-4254-a4f4-94f0267edda8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2799414341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2799414341 |
Directory | /workspace/45.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1862525602 |
Short name | T861 |
Test name | |
Test status | |
Simulation time | 5982294080 ps |
CPU time | 5.99 seconds |
Started | Jul 15 06:50:37 PM PDT 24 |
Finished | Jul 15 06:50:43 PM PDT 24 |
Peak memory | 232704 kb |
Host | smart-6c7a1f7c-5dac-4fe3-8e55-e11738bbf8cb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1862525602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa p.1862525602 |
Directory | /workspace/45.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3074686991 |
Short name | T865 |
Test name | |
Test status | |
Simulation time | 4804490876 ps |
CPU time | 14.58 seconds |
Started | Jul 15 06:50:39 PM PDT 24 |
Finished | Jul 15 06:50:54 PM PDT 24 |
Peak memory | 224596 kb |
Host | smart-b79f63df-c67c-424f-a5dd-54787be7a71f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3074686991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3074686991 |
Directory | /workspace/45.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/45.spi_device_read_buffer_direct.947884103 |
Short name | T542 |
Test name | |
Test status | |
Simulation time | 326572292 ps |
CPU time | 5.37 seconds |
Started | Jul 15 06:50:43 PM PDT 24 |
Finished | Jul 15 06:50:49 PM PDT 24 |
Peak memory | 219276 kb |
Host | smart-e894d2c2-fd32-481b-9092-790509df5cf4 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=947884103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire ct.947884103 |
Directory | /workspace/45.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/45.spi_device_stress_all.3370486678 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 343250031467 ps |
CPU time | 784.09 seconds |
Started | Jul 15 06:50:44 PM PDT 24 |
Finished | Jul 15 07:03:48 PM PDT 24 |
Peak memory | 272932 kb |
Host | smart-9acc7d5f-d40e-422d-b03d-563106e06c72 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370486678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre ss_all.3370486678 |
Directory | /workspace/45.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/45.spi_device_tpm_all.1050804820 |
Short name | T619 |
Test name | |
Test status | |
Simulation time | 17409672 ps |
CPU time | 0.74 seconds |
Started | Jul 15 06:50:37 PM PDT 24 |
Finished | Jul 15 06:50:38 PM PDT 24 |
Peak memory | 205668 kb |
Host | smart-851dd56b-6f18-498d-a7b1-8b8e9b35b77e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1050804820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1050804820 |
Directory | /workspace/45.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.6031144 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 2749960257 ps |
CPU time | 9.27 seconds |
Started | Jul 15 06:50:42 PM PDT 24 |
Finished | Jul 15 06:50:52 PM PDT 24 |
Peak memory | 216308 kb |
Host | smart-f3a516f3-9edd-48d6-ae7e-058dfd0d7e6f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=6031144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.6031144 |
Directory | /workspace/45.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/45.spi_device_tpm_rw.2615594577 |
Short name | T823 |
Test name | |
Test status | |
Simulation time | 22569526 ps |
CPU time | 0.9 seconds |
Started | Jul 15 06:50:35 PM PDT 24 |
Finished | Jul 15 06:50:36 PM PDT 24 |
Peak memory | 206392 kb |
Host | smart-055fadcf-e356-4033-996b-83979c6d28a1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2615594577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2615594577 |
Directory | /workspace/45.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/45.spi_device_tpm_sts_read.919506031 |
Short name | T901 |
Test name | |
Test status | |
Simulation time | 197816167 ps |
CPU time | 0.85 seconds |
Started | Jul 15 06:50:37 PM PDT 24 |
Finished | Jul 15 06:50:38 PM PDT 24 |
Peak memory | 206932 kb |
Host | smart-36feebe9-4d48-4fdd-bc1d-3bb05c609228 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=919506031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.919506031 |
Directory | /workspace/45.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/45.spi_device_upload.1926438248 |
Short name | T755 |
Test name | |
Test status | |
Simulation time | 4673577443 ps |
CPU time | 14.33 seconds |
Started | Jul 15 06:50:36 PM PDT 24 |
Finished | Jul 15 06:50:50 PM PDT 24 |
Peak memory | 232712 kb |
Host | smart-5ee99336-6e1e-4e0e-9b04-c0c5c5f70649 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1926438248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1926438248 |
Directory | /workspace/45.spi_device_upload/latest |
Test location | /workspace/coverage/default/46.spi_device_alert_test.2035609263 |
Short name | T503 |
Test name | |
Test status | |
Simulation time | 14960501 ps |
CPU time | 0.82 seconds |
Started | Jul 15 06:50:46 PM PDT 24 |
Finished | Jul 15 06:50:48 PM PDT 24 |
Peak memory | 204848 kb |
Host | smart-c71c2ed9-586c-4ea8-b6af-8a415cf8b084 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035609263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test. 2035609263 |
Directory | /workspace/46.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/46.spi_device_cfg_cmd.3107000425 |
Short name | T843 |
Test name | |
Test status | |
Simulation time | 506709229 ps |
CPU time | 4.02 seconds |
Started | Jul 15 06:50:50 PM PDT 24 |
Finished | Jul 15 06:50:55 PM PDT 24 |
Peak memory | 224460 kb |
Host | smart-2e267e3f-ec0e-4d51-935d-14427818aebb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3107000425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3107000425 |
Directory | /workspace/46.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/46.spi_device_csb_read.2380100155 |
Short name | T804 |
Test name | |
Test status | |
Simulation time | 15664713 ps |
CPU time | 0.81 seconds |
Started | Jul 15 06:50:41 PM PDT 24 |
Finished | Jul 15 06:50:42 PM PDT 24 |
Peak memory | 206528 kb |
Host | smart-818ae00f-7768-4626-86c4-85625afed6f7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2380100155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2380100155 |
Directory | /workspace/46.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/46.spi_device_flash_all.2169610083 |
Short name | T606 |
Test name | |
Test status | |
Simulation time | 13713406 ps |
CPU time | 0.76 seconds |
Started | Jul 15 06:50:49 PM PDT 24 |
Finished | Jul 15 06:50:51 PM PDT 24 |
Peak memory | 215728 kb |
Host | smart-971b9c82-abf8-4463-b94d-b9f9c842ab71 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2169610083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2169610083 |
Directory | /workspace/46.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/46.spi_device_flash_and_tpm.1901032973 |
Short name | T1012 |
Test name | |
Test status | |
Simulation time | 8754760386 ps |
CPU time | 120.31 seconds |
Started | Jul 15 06:50:49 PM PDT 24 |
Finished | Jul 15 06:52:50 PM PDT 24 |
Peak memory | 265596 kb |
Host | smart-22af1dc1-a0e0-46bb-9cb6-41b64fcd72d5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1901032973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1901032973 |
Directory | /workspace/46.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2916290842 |
Short name | T633 |
Test name | |
Test status | |
Simulation time | 277491742241 ps |
CPU time | 239.52 seconds |
Started | Jul 15 06:50:47 PM PDT 24 |
Finished | Jul 15 06:54:47 PM PDT 24 |
Peak memory | 256464 kb |
Host | smart-ba632ac6-9b95-4c9b-bd2e-ce7fbefad418 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2916290842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl e.2916290842 |
Directory | /workspace/46.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/46.spi_device_flash_mode.4272369399 |
Short name | T952 |
Test name | |
Test status | |
Simulation time | 1274907330 ps |
CPU time | 5.28 seconds |
Started | Jul 15 06:50:50 PM PDT 24 |
Finished | Jul 15 06:50:56 PM PDT 24 |
Peak memory | 224440 kb |
Host | smart-b00ebf40-774b-4136-bda7-b9f7f223072a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4272369399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.4272369399 |
Directory | /workspace/46.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2324008685 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 38506504299 ps |
CPU time | 158.73 seconds |
Started | Jul 15 06:50:49 PM PDT 24 |
Finished | Jul 15 06:53:29 PM PDT 24 |
Peak memory | 250360 kb |
Host | smart-958092ac-a0ad-4ee3-a190-07844f3eb3fa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2324008685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd s.2324008685 |
Directory | /workspace/46.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/46.spi_device_intercept.2320431502 |
Short name | T931 |
Test name | |
Test status | |
Simulation time | 2872976931 ps |
CPU time | 7.6 seconds |
Started | Jul 15 06:50:44 PM PDT 24 |
Finished | Jul 15 06:50:52 PM PDT 24 |
Peak memory | 224552 kb |
Host | smart-e14603be-feeb-4dfc-9517-31b7996fe5ea |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2320431502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2320431502 |
Directory | /workspace/46.spi_device_intercept/latest |
Test location | /workspace/coverage/default/46.spi_device_mailbox.537713122 |
Short name | T991 |
Test name | |
Test status | |
Simulation time | 764294413 ps |
CPU time | 5.98 seconds |
Started | Jul 15 06:50:43 PM PDT 24 |
Finished | Jul 15 06:50:50 PM PDT 24 |
Peak memory | 232656 kb |
Host | smart-5e0f1719-4499-4f95-bf69-da83aa396487 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=537713122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.537713122 |
Directory | /workspace/46.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3494692367 |
Short name | T984 |
Test name | |
Test status | |
Simulation time | 2751818163 ps |
CPU time | 5.6 seconds |
Started | Jul 15 06:50:43 PM PDT 24 |
Finished | Jul 15 06:50:49 PM PDT 24 |
Peak memory | 232616 kb |
Host | smart-b7b8dff7-f8b0-4e8a-bbd9-15386baa8024 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3494692367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa p.3494692367 |
Directory | /workspace/46.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1830810514 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 407821414 ps |
CPU time | 6.83 seconds |
Started | Jul 15 06:50:44 PM PDT 24 |
Finished | Jul 15 06:50:52 PM PDT 24 |
Peak memory | 232592 kb |
Host | smart-28491922-0a20-42ed-a573-ea1ab3eae211 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1830810514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1830810514 |
Directory | /workspace/46.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/46.spi_device_read_buffer_direct.838478716 |
Short name | T925 |
Test name | |
Test status | |
Simulation time | 808678833 ps |
CPU time | 13.06 seconds |
Started | Jul 15 06:50:47 PM PDT 24 |
Finished | Jul 15 06:51:01 PM PDT 24 |
Peak memory | 220240 kb |
Host | smart-507e543d-e82b-491d-84f1-21cfb0fd54d7 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=838478716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire ct.838478716 |
Directory | /workspace/46.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/46.spi_device_stress_all.1740104089 |
Short name | T978 |
Test name | |
Test status | |
Simulation time | 149626784635 ps |
CPU time | 1393.03 seconds |
Started | Jul 15 06:50:49 PM PDT 24 |
Finished | Jul 15 07:14:03 PM PDT 24 |
Peak memory | 299440 kb |
Host | smart-f10393d9-7218-433e-8b99-f707082d9743 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740104089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre ss_all.1740104089 |
Directory | /workspace/46.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/46.spi_device_tpm_all.1405995976 |
Short name | T660 |
Test name | |
Test status | |
Simulation time | 2198443400 ps |
CPU time | 21.55 seconds |
Started | Jul 15 06:50:43 PM PDT 24 |
Finished | Jul 15 06:51:05 PM PDT 24 |
Peak memory | 216212 kb |
Host | smart-3cb514c6-fa2d-48f9-a966-157807e7d953 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1405995976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1405995976 |
Directory | /workspace/46.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2364498952 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 630203417 ps |
CPU time | 2.99 seconds |
Started | Jul 15 06:50:44 PM PDT 24 |
Finished | Jul 15 06:50:47 PM PDT 24 |
Peak memory | 216196 kb |
Host | smart-a6190e0f-b0ee-4036-8e7e-be136a87368a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2364498952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2364498952 |
Directory | /workspace/46.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/46.spi_device_tpm_rw.1918596267 |
Short name | T688 |
Test name | |
Test status | |
Simulation time | 55309439 ps |
CPU time | 1.21 seconds |
Started | Jul 15 06:50:43 PM PDT 24 |
Finished | Jul 15 06:50:44 PM PDT 24 |
Peak memory | 207812 kb |
Host | smart-5535d138-f288-4d21-b92d-2c6819b51095 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1918596267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1918596267 |
Directory | /workspace/46.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/46.spi_device_tpm_sts_read.1039449180 |
Short name | T822 |
Test name | |
Test status | |
Simulation time | 526159367 ps |
CPU time | 0.9 seconds |
Started | Jul 15 06:50:43 PM PDT 24 |
Finished | Jul 15 06:50:44 PM PDT 24 |
Peak memory | 206916 kb |
Host | smart-a1bd1b33-dab0-4819-896b-dbe785fa93fe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1039449180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1039449180 |
Directory | /workspace/46.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/46.spi_device_upload.2271644117 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 3076147964 ps |
CPU time | 10.77 seconds |
Started | Jul 15 06:50:50 PM PDT 24 |
Finished | Jul 15 06:51:02 PM PDT 24 |
Peak memory | 233696 kb |
Host | smart-9a943d2a-8756-4b52-8071-87629f1f110a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2271644117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2271644117 |
Directory | /workspace/46.spi_device_upload/latest |
Test location | /workspace/coverage/default/47.spi_device_alert_test.1306971614 |
Short name | T557 |
Test name | |
Test status | |
Simulation time | 57918060 ps |
CPU time | 0.76 seconds |
Started | Jul 15 06:50:54 PM PDT 24 |
Finished | Jul 15 06:50:56 PM PDT 24 |
Peak memory | 205412 kb |
Host | smart-b76f1998-14fb-47ac-8ad5-17bc76b34dcc |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306971614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test. 1306971614 |
Directory | /workspace/47.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/47.spi_device_cfg_cmd.65097303 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 213684021 ps |
CPU time | 2.61 seconds |
Started | Jul 15 06:50:51 PM PDT 24 |
Finished | Jul 15 06:50:54 PM PDT 24 |
Peak memory | 224388 kb |
Host | smart-0316b6e1-0af8-47bd-8ff6-12ebcd1d5639 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=65097303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.65097303 |
Directory | /workspace/47.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/47.spi_device_csb_read.3689221785 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 21105040 ps |
CPU time | 0.78 seconds |
Started | Jul 15 06:50:51 PM PDT 24 |
Finished | Jul 15 06:50:52 PM PDT 24 |
Peak memory | 206896 kb |
Host | smart-1ec30464-dd56-4d09-96fa-3200082569e8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3689221785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3689221785 |
Directory | /workspace/47.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/47.spi_device_flash_all.532928420 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 141568269193 ps |
CPU time | 60.94 seconds |
Started | Jul 15 06:50:54 PM PDT 24 |
Finished | Jul 15 06:51:56 PM PDT 24 |
Peak memory | 240960 kb |
Host | smart-a24f5bc3-d8b2-4cee-8ee6-69581b61dfcb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=532928420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.532928420 |
Directory | /workspace/47.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/47.spi_device_flash_and_tpm.2027459683 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 77573300134 ps |
CPU time | 196.52 seconds |
Started | Jul 15 06:50:56 PM PDT 24 |
Finished | Jul 15 06:54:12 PM PDT 24 |
Peak memory | 232832 kb |
Host | smart-65f4bff6-484e-49e1-b92f-7d70b46edf45 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2027459683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2027459683 |
Directory | /workspace/47.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1842912964 |
Short name | T744 |
Test name | |
Test status | |
Simulation time | 88394755636 ps |
CPU time | 373.79 seconds |
Started | Jul 15 06:50:54 PM PDT 24 |
Finished | Jul 15 06:57:09 PM PDT 24 |
Peak memory | 265684 kb |
Host | smart-d92cdbbc-03fb-4648-bf81-26c2cc0fb095 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1842912964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl e.1842912964 |
Directory | /workspace/47.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/47.spi_device_flash_mode.2235077965 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 778771742 ps |
CPU time | 14.49 seconds |
Started | Jul 15 06:50:54 PM PDT 24 |
Finished | Jul 15 06:51:09 PM PDT 24 |
Peak memory | 240648 kb |
Host | smart-72c5d5ec-770d-4c40-ac7f-ccea14816673 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2235077965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2235077965 |
Directory | /workspace/47.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.2681793392 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 14359766934 ps |
CPU time | 142.01 seconds |
Started | Jul 15 06:50:55 PM PDT 24 |
Finished | Jul 15 06:53:17 PM PDT 24 |
Peak memory | 251960 kb |
Host | smart-bae663d1-9593-422a-8b6c-56dcdc4553d0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2681793392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd s.2681793392 |
Directory | /workspace/47.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/47.spi_device_intercept.2107077005 |
Short name | T854 |
Test name | |
Test status | |
Simulation time | 309883754 ps |
CPU time | 4.83 seconds |
Started | Jul 15 06:50:48 PM PDT 24 |
Finished | Jul 15 06:50:54 PM PDT 24 |
Peak memory | 232596 kb |
Host | smart-f12db3f6-1d0f-40fb-b7bb-298b5c7c9d6e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2107077005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2107077005 |
Directory | /workspace/47.spi_device_intercept/latest |
Test location | /workspace/coverage/default/47.spi_device_mailbox.669800361 |
Short name | T580 |
Test name | |
Test status | |
Simulation time | 38275237905 ps |
CPU time | 83.44 seconds |
Started | Jul 15 06:50:50 PM PDT 24 |
Finished | Jul 15 06:52:13 PM PDT 24 |
Peak memory | 232716 kb |
Host | smart-13eccc63-50e2-480a-9376-7cd6cddc0cf4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=669800361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.669800361 |
Directory | /workspace/47.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.862692755 |
Short name | T671 |
Test name | |
Test status | |
Simulation time | 975750014 ps |
CPU time | 3.15 seconds |
Started | Jul 15 06:50:51 PM PDT 24 |
Finished | Jul 15 06:50:55 PM PDT 24 |
Peak memory | 232604 kb |
Host | smart-18c96c5f-bed1-4944-9abf-7306bd528cba |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=862692755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap .862692755 |
Directory | /workspace/47.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/47.spi_device_pass_cmd_filtering.997032135 |
Short name | T958 |
Test name | |
Test status | |
Simulation time | 473373177 ps |
CPU time | 6.61 seconds |
Started | Jul 15 06:50:47 PM PDT 24 |
Finished | Jul 15 06:50:54 PM PDT 24 |
Peak memory | 224464 kb |
Host | smart-207d9d7d-e8f1-4e9e-8dda-69d87793360c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=997032135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.997032135 |
Directory | /workspace/47.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/47.spi_device_read_buffer_direct.805518975 |
Short name | T893 |
Test name | |
Test status | |
Simulation time | 7617027571 ps |
CPU time | 12.71 seconds |
Started | Jul 15 06:50:59 PM PDT 24 |
Finished | Jul 15 06:51:12 PM PDT 24 |
Peak memory | 220388 kb |
Host | smart-baba6edb-b863-479a-9443-541b549e6105 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=805518975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire ct.805518975 |
Directory | /workspace/47.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/47.spi_device_stress_all.275460751 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 24098882824 ps |
CPU time | 111.2 seconds |
Started | Jul 15 06:50:58 PM PDT 24 |
Finished | Jul 15 06:52:49 PM PDT 24 |
Peak memory | 266652 kb |
Host | smart-7d1e836f-108f-4b96-98be-e8b48cd808ed |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275460751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres s_all.275460751 |
Directory | /workspace/47.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/47.spi_device_tpm_all.319439749 |
Short name | T645 |
Test name | |
Test status | |
Simulation time | 1403754463 ps |
CPU time | 2.92 seconds |
Started | Jul 15 06:50:50 PM PDT 24 |
Finished | Jul 15 06:50:54 PM PDT 24 |
Peak memory | 216168 kb |
Host | smart-6ad511e1-a66f-45e0-a2f6-ddc5a220e240 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=319439749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.319439749 |
Directory | /workspace/47.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2281394635 |
Short name | T680 |
Test name | |
Test status | |
Simulation time | 936107717 ps |
CPU time | 3.65 seconds |
Started | Jul 15 06:50:49 PM PDT 24 |
Finished | Jul 15 06:50:53 PM PDT 24 |
Peak memory | 216136 kb |
Host | smart-4ced783b-ac7a-4e73-b520-afaeb5899148 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2281394635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2281394635 |
Directory | /workspace/47.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/47.spi_device_tpm_rw.1910597380 |
Short name | T753 |
Test name | |
Test status | |
Simulation time | 12490800 ps |
CPU time | 0.78 seconds |
Started | Jul 15 06:50:49 PM PDT 24 |
Finished | Jul 15 06:50:50 PM PDT 24 |
Peak memory | 205880 kb |
Host | smart-a3a8db83-2ecc-48ef-9059-48dcbb99d64d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1910597380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1910597380 |
Directory | /workspace/47.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/47.spi_device_tpm_sts_read.2415424895 |
Short name | T791 |
Test name | |
Test status | |
Simulation time | 26937267 ps |
CPU time | 0.78 seconds |
Started | Jul 15 06:50:50 PM PDT 24 |
Finished | Jul 15 06:50:52 PM PDT 24 |
Peak memory | 205884 kb |
Host | smart-2c4ec565-4743-40a1-a7c2-2fd756f13a6b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2415424895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2415424895 |
Directory | /workspace/47.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/47.spi_device_upload.2205229999 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 1427343117 ps |
CPU time | 5.57 seconds |
Started | Jul 15 06:50:50 PM PDT 24 |
Finished | Jul 15 06:50:56 PM PDT 24 |
Peak memory | 232636 kb |
Host | smart-554b4c2c-8da9-40b9-981b-f13ffe27c6b0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2205229999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2205229999 |
Directory | /workspace/47.spi_device_upload/latest |
Test location | /workspace/coverage/default/48.spi_device_alert_test.1020502621 |
Short name | T817 |
Test name | |
Test status | |
Simulation time | 58220279 ps |
CPU time | 0.73 seconds |
Started | Jul 15 06:51:01 PM PDT 24 |
Finished | Jul 15 06:51:02 PM PDT 24 |
Peak memory | 205480 kb |
Host | smart-9c0f7762-1c2c-4abe-b1af-0176359cdf8e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020502621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test. 1020502621 |
Directory | /workspace/48.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/48.spi_device_cfg_cmd.3809584723 |
Short name | T740 |
Test name | |
Test status | |
Simulation time | 1268982327 ps |
CPU time | 5.35 seconds |
Started | Jul 15 06:51:00 PM PDT 24 |
Finished | Jul 15 06:51:06 PM PDT 24 |
Peak memory | 232672 kb |
Host | smart-641daad6-48c9-4a29-a73f-431aaa242c59 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3809584723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3809584723 |
Directory | /workspace/48.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/48.spi_device_csb_read.923454527 |
Short name | T915 |
Test name | |
Test status | |
Simulation time | 39174045 ps |
CPU time | 0.79 seconds |
Started | Jul 15 06:50:58 PM PDT 24 |
Finished | Jul 15 06:50:59 PM PDT 24 |
Peak memory | 206700 kb |
Host | smart-a87f7e73-263e-464a-a0c0-cc37493f80de |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=923454527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.923454527 |
Directory | /workspace/48.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/48.spi_device_flash_and_tpm.2502795517 |
Short name | T795 |
Test name | |
Test status | |
Simulation time | 3375864861 ps |
CPU time | 28.19 seconds |
Started | Jul 15 06:51:02 PM PDT 24 |
Finished | Jul 15 06:51:31 PM PDT 24 |
Peak memory | 222876 kb |
Host | smart-a389e7a8-3317-42f3-95ce-971e12001c4e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2502795517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2502795517 |
Directory | /workspace/48.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1502884560 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 61503675059 ps |
CPU time | 281.41 seconds |
Started | Jul 15 06:50:59 PM PDT 24 |
Finished | Jul 15 06:55:41 PM PDT 24 |
Peak memory | 256796 kb |
Host | smart-33684695-d25c-4167-9991-cdd006b7dd4d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1502884560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl e.1502884560 |
Directory | /workspace/48.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/48.spi_device_flash_mode.2552906935 |
Short name | T629 |
Test name | |
Test status | |
Simulation time | 3318929170 ps |
CPU time | 11.82 seconds |
Started | Jul 15 06:50:59 PM PDT 24 |
Finished | Jul 15 06:51:12 PM PDT 24 |
Peak memory | 240868 kb |
Host | smart-19b51477-ccb2-409d-8eb3-07779a497e39 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2552906935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2552906935 |
Directory | /workspace/48.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.1141743079 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 35242604703 ps |
CPU time | 193.66 seconds |
Started | Jul 15 06:51:02 PM PDT 24 |
Finished | Jul 15 06:54:16 PM PDT 24 |
Peak memory | 264952 kb |
Host | smart-c36a88cf-0a8c-46c5-8f2d-cb667765b91d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1141743079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd s.1141743079 |
Directory | /workspace/48.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/48.spi_device_intercept.1696316040 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 2606774211 ps |
CPU time | 7.48 seconds |
Started | Jul 15 06:51:00 PM PDT 24 |
Finished | Jul 15 06:51:08 PM PDT 24 |
Peak memory | 232720 kb |
Host | smart-ee2c54f2-a260-4a8f-9785-80a29cd651fd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1696316040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1696316040 |
Directory | /workspace/48.spi_device_intercept/latest |
Test location | /workspace/coverage/default/48.spi_device_mailbox.1152708384 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 11592130684 ps |
CPU time | 107.06 seconds |
Started | Jul 15 06:50:59 PM PDT 24 |
Finished | Jul 15 06:52:46 PM PDT 24 |
Peak memory | 240924 kb |
Host | smart-e4a2ca34-d2d4-4545-9fb2-1dc6d011c136 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1152708384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1152708384 |
Directory | /workspace/48.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.81258808 |
Short name | T689 |
Test name | |
Test status | |
Simulation time | 8698652569 ps |
CPU time | 26.05 seconds |
Started | Jul 15 06:50:56 PM PDT 24 |
Finished | Jul 15 06:51:22 PM PDT 24 |
Peak memory | 232760 kb |
Host | smart-1036f667-05aa-4e33-b73b-f23336cb51b8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=81258808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap.81258808 |
Directory | /workspace/48.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3021103312 |
Short name | T686 |
Test name | |
Test status | |
Simulation time | 124978770 ps |
CPU time | 2.56 seconds |
Started | Jul 15 06:50:53 PM PDT 24 |
Finished | Jul 15 06:50:56 PM PDT 24 |
Peak memory | 224432 kb |
Host | smart-120614d9-0789-4bdf-a826-ea7fe7c9ec1b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3021103312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3021103312 |
Directory | /workspace/48.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/48.spi_device_read_buffer_direct.880889506 |
Short name | T1003 |
Test name | |
Test status | |
Simulation time | 919848302 ps |
CPU time | 11.7 seconds |
Started | Jul 15 06:51:02 PM PDT 24 |
Finished | Jul 15 06:51:14 PM PDT 24 |
Peak memory | 222572 kb |
Host | smart-09afe384-f3d4-4c6e-8a19-b022ec7a2ebd |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=880889506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire ct.880889506 |
Directory | /workspace/48.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/48.spi_device_stress_all.3610883767 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 79816240 ps |
CPU time | 1.09 seconds |
Started | Jul 15 06:51:02 PM PDT 24 |
Finished | Jul 15 06:51:04 PM PDT 24 |
Peak memory | 206944 kb |
Host | smart-855c24cc-54bc-42da-995d-b16894bbe103 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610883767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre ss_all.3610883767 |
Directory | /workspace/48.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/48.spi_device_tpm_all.199526800 |
Short name | T835 |
Test name | |
Test status | |
Simulation time | 491774080 ps |
CPU time | 2.34 seconds |
Started | Jul 15 06:50:55 PM PDT 24 |
Finished | Jul 15 06:50:58 PM PDT 24 |
Peak memory | 216128 kb |
Host | smart-fcda8193-464b-4590-a0a1-cb22674cfcee |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=199526800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.199526800 |
Directory | /workspace/48.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.784770083 |
Short name | T467 |
Test name | |
Test status | |
Simulation time | 4521991897 ps |
CPU time | 13.2 seconds |
Started | Jul 15 06:50:56 PM PDT 24 |
Finished | Jul 15 06:51:10 PM PDT 24 |
Peak memory | 216212 kb |
Host | smart-c4e2d58a-de7c-41e3-b428-6464333b236c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=784770083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.784770083 |
Directory | /workspace/48.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/48.spi_device_tpm_rw.3263039183 |
Short name | T924 |
Test name | |
Test status | |
Simulation time | 362428363 ps |
CPU time | 1.6 seconds |
Started | Jul 15 06:50:57 PM PDT 24 |
Finished | Jul 15 06:50:58 PM PDT 24 |
Peak memory | 216200 kb |
Host | smart-d749603f-4fb9-4739-80c4-b036e2c74177 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3263039183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3263039183 |
Directory | /workspace/48.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/48.spi_device_tpm_sts_read.2502068705 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 62315062 ps |
CPU time | 0.9 seconds |
Started | Jul 15 06:50:56 PM PDT 24 |
Finished | Jul 15 06:50:57 PM PDT 24 |
Peak memory | 205936 kb |
Host | smart-2d1dd76d-40e5-409e-ab9d-16c930d87231 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2502068705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2502068705 |
Directory | /workspace/48.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/48.spi_device_upload.1967337777 |
Short name | T957 |
Test name | |
Test status | |
Simulation time | 7488170402 ps |
CPU time | 16.5 seconds |
Started | Jul 15 06:51:01 PM PDT 24 |
Finished | Jul 15 06:51:18 PM PDT 24 |
Peak memory | 248556 kb |
Host | smart-94e34c27-da0c-4fbd-8866-561ec6029a39 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1967337777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1967337777 |
Directory | /workspace/48.spi_device_upload/latest |
Test location | /workspace/coverage/default/49.spi_device_alert_test.2954244423 |
Short name | T656 |
Test name | |
Test status | |
Simulation time | 18281300 ps |
CPU time | 0.74 seconds |
Started | Jul 15 06:51:15 PM PDT 24 |
Finished | Jul 15 06:51:16 PM PDT 24 |
Peak memory | 204884 kb |
Host | smart-a4e73651-e342-4bb0-ab3a-98799432b08e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954244423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test. 2954244423 |
Directory | /workspace/49.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/49.spi_device_cfg_cmd.3306123633 |
Short name | T703 |
Test name | |
Test status | |
Simulation time | 7871967572 ps |
CPU time | 15.62 seconds |
Started | Jul 15 06:51:07 PM PDT 24 |
Finished | Jul 15 06:51:23 PM PDT 24 |
Peak memory | 224580 kb |
Host | smart-8f3fad58-08d0-4aad-be33-b81bc72e5d80 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3306123633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3306123633 |
Directory | /workspace/49.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/49.spi_device_csb_read.3037629807 |
Short name | T973 |
Test name | |
Test status | |
Simulation time | 112906081 ps |
CPU time | 0.76 seconds |
Started | Jul 15 06:51:06 PM PDT 24 |
Finished | Jul 15 06:51:08 PM PDT 24 |
Peak memory | 205844 kb |
Host | smart-63d9cb80-b6ed-41b8-9325-9a20534f4ee0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3037629807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3037629807 |
Directory | /workspace/49.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/49.spi_device_flash_all.3586951573 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 43030820 ps |
CPU time | 0.77 seconds |
Started | Jul 15 06:51:05 PM PDT 24 |
Finished | Jul 15 06:51:06 PM PDT 24 |
Peak memory | 215720 kb |
Host | smart-cdf0cc95-e60c-4cf8-8413-76d15a24e3c5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3586951573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3586951573 |
Directory | /workspace/49.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/49.spi_device_flash_and_tpm.1149463634 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 43684352833 ps |
CPU time | 219.03 seconds |
Started | Jul 15 06:51:07 PM PDT 24 |
Finished | Jul 15 06:54:46 PM PDT 24 |
Peak memory | 252324 kb |
Host | smart-872a38f7-6bbd-4d96-b3cb-3a81e5153b75 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1149463634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1149463634 |
Directory | /workspace/49.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3323122715 |
Short name | T549 |
Test name | |
Test status | |
Simulation time | 14791197023 ps |
CPU time | 119.35 seconds |
Started | Jul 15 06:51:05 PM PDT 24 |
Finished | Jul 15 06:53:04 PM PDT 24 |
Peak memory | 240664 kb |
Host | smart-7399c32a-c352-40c6-81af-47c179d0bab5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3323122715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl e.3323122715 |
Directory | /workspace/49.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/49.spi_device_flash_mode.1902585198 |
Short name | T993 |
Test name | |
Test status | |
Simulation time | 1422457630 ps |
CPU time | 4.06 seconds |
Started | Jul 15 06:51:09 PM PDT 24 |
Finished | Jul 15 06:51:13 PM PDT 24 |
Peak memory | 224412 kb |
Host | smart-b12c1c31-5700-49d1-99ec-03a4086334b8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1902585198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1902585198 |
Directory | /workspace/49.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.2986222741 |
Short name | T1004 |
Test name | |
Test status | |
Simulation time | 11008654685 ps |
CPU time | 116.36 seconds |
Started | Jul 15 06:51:08 PM PDT 24 |
Finished | Jul 15 06:53:05 PM PDT 24 |
Peak memory | 251812 kb |
Host | smart-bfa9afd3-fc34-4f32-a1fe-5f7420813397 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2986222741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd s.2986222741 |
Directory | /workspace/49.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/49.spi_device_intercept.961876615 |
Short name | T628 |
Test name | |
Test status | |
Simulation time | 9610354927 ps |
CPU time | 20.94 seconds |
Started | Jul 15 06:51:07 PM PDT 24 |
Finished | Jul 15 06:51:29 PM PDT 24 |
Peak memory | 224528 kb |
Host | smart-0aba1e7a-8e71-413b-b834-9ee8c1088fc0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=961876615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.961876615 |
Directory | /workspace/49.spi_device_intercept/latest |
Test location | /workspace/coverage/default/49.spi_device_mailbox.2935343195 |
Short name | T698 |
Test name | |
Test status | |
Simulation time | 36527626 ps |
CPU time | 2.26 seconds |
Started | Jul 15 06:51:10 PM PDT 24 |
Finished | Jul 15 06:51:13 PM PDT 24 |
Peak memory | 232324 kb |
Host | smart-59cb9812-5130-4c0c-b43a-a341393d8adc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2935343195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2935343195 |
Directory | /workspace/49.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1931764048 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 794995375 ps |
CPU time | 9 seconds |
Started | Jul 15 06:51:11 PM PDT 24 |
Finished | Jul 15 06:51:20 PM PDT 24 |
Peak memory | 231584 kb |
Host | smart-daa754e9-6f4b-4ec3-978b-5d179c55062d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1931764048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa p.1931764048 |
Directory | /workspace/49.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1051754314 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 48154360684 ps |
CPU time | 33.7 seconds |
Started | Jul 15 06:51:07 PM PDT 24 |
Finished | Jul 15 06:51:41 PM PDT 24 |
Peak memory | 240520 kb |
Host | smart-681be72b-f858-453f-a25a-7249d1367abe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1051754314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1051754314 |
Directory | /workspace/49.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/49.spi_device_read_buffer_direct.3426662382 |
Short name | T945 |
Test name | |
Test status | |
Simulation time | 127877339 ps |
CPU time | 3.64 seconds |
Started | Jul 15 06:51:06 PM PDT 24 |
Finished | Jul 15 06:51:10 PM PDT 24 |
Peak memory | 219596 kb |
Host | smart-23f0d3b2-b84b-41d8-8435-bd9ab7e3409f |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3426662382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir ect.3426662382 |
Directory | /workspace/49.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/49.spi_device_stress_all.3638596732 |
Short name | T639 |
Test name | |
Test status | |
Simulation time | 153860223 ps |
CPU time | 0.99 seconds |
Started | Jul 15 06:51:07 PM PDT 24 |
Finished | Jul 15 06:51:09 PM PDT 24 |
Peak memory | 207688 kb |
Host | smart-aba71861-2ad9-482a-b54d-71d71a5a58c0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638596732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre ss_all.3638596732 |
Directory | /workspace/49.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/49.spi_device_tpm_all.1643049449 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 2602869490 ps |
CPU time | 8.21 seconds |
Started | Jul 15 06:51:09 PM PDT 24 |
Finished | Jul 15 06:51:17 PM PDT 24 |
Peak memory | 216308 kb |
Host | smart-b361839f-b49b-48c1-9627-bd872f58790b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1643049449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1643049449 |
Directory | /workspace/49.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2974503627 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 2182154690 ps |
CPU time | 6.27 seconds |
Started | Jul 15 06:51:07 PM PDT 24 |
Finished | Jul 15 06:51:13 PM PDT 24 |
Peak memory | 216192 kb |
Host | smart-78292796-515d-46dd-a447-551bc4a82411 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2974503627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2974503627 |
Directory | /workspace/49.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/49.spi_device_tpm_rw.1451536948 |
Short name | T500 |
Test name | |
Test status | |
Simulation time | 162149731 ps |
CPU time | 3.05 seconds |
Started | Jul 15 06:51:09 PM PDT 24 |
Finished | Jul 15 06:51:13 PM PDT 24 |
Peak memory | 216184 kb |
Host | smart-385cd5da-e2e8-4437-96be-03add4cd75e5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1451536948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1451536948 |
Directory | /workspace/49.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/49.spi_device_tpm_sts_read.1059584942 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 47378072 ps |
CPU time | 0.87 seconds |
Started | Jul 15 06:51:07 PM PDT 24 |
Finished | Jul 15 06:51:08 PM PDT 24 |
Peak memory | 205880 kb |
Host | smart-209ee30f-06fa-499d-87dc-61da839315ad |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1059584942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1059584942 |
Directory | /workspace/49.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/49.spi_device_upload.1394107890 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 39643050810 ps |
CPU time | 17.47 seconds |
Started | Jul 15 06:51:08 PM PDT 24 |
Finished | Jul 15 06:51:26 PM PDT 24 |
Peak memory | 232740 kb |
Host | smart-dd3f281e-7500-41a8-a599-41cfc5e1f540 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1394107890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1394107890 |
Directory | /workspace/49.spi_device_upload/latest |
Test location | /workspace/coverage/default/5.spi_device_alert_test.829686759 |
Short name | T607 |
Test name | |
Test status | |
Simulation time | 11235334 ps |
CPU time | 0.76 seconds |
Started | Jul 15 06:45:21 PM PDT 24 |
Finished | Jul 15 06:45:23 PM PDT 24 |
Peak memory | 204916 kb |
Host | smart-b0edaf9c-3944-4a27-95e2-bbccb7297f09 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829686759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.829686759 |
Directory | /workspace/5.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/5.spi_device_cfg_cmd.1621549536 |
Short name | T990 |
Test name | |
Test status | |
Simulation time | 663890744 ps |
CPU time | 3.63 seconds |
Started | Jul 15 06:45:13 PM PDT 24 |
Finished | Jul 15 06:45:17 PM PDT 24 |
Peak memory | 232596 kb |
Host | smart-7e763409-4503-45f6-98fc-50668900a0e8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1621549536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1621549536 |
Directory | /workspace/5.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/5.spi_device_csb_read.2542607013 |
Short name | T999 |
Test name | |
Test status | |
Simulation time | 21852949 ps |
CPU time | 0.78 seconds |
Started | Jul 15 06:45:16 PM PDT 24 |
Finished | Jul 15 06:45:17 PM PDT 24 |
Peak memory | 206888 kb |
Host | smart-a56734c7-c2b3-49bb-8c7b-69602729ceb4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2542607013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2542607013 |
Directory | /workspace/5.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/5.spi_device_flash_all.106105412 |
Short name | T956 |
Test name | |
Test status | |
Simulation time | 2875030846 ps |
CPU time | 56.9 seconds |
Started | Jul 15 06:45:21 PM PDT 24 |
Finished | Jul 15 06:46:18 PM PDT 24 |
Peak memory | 254024 kb |
Host | smart-297393cb-deee-4356-bf1e-96a6f49263e8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=106105412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.106105412 |
Directory | /workspace/5.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/5.spi_device_flash_and_tpm.3616333732 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 12902323130 ps |
CPU time | 155.62 seconds |
Started | Jul 15 06:45:22 PM PDT 24 |
Finished | Jul 15 06:47:58 PM PDT 24 |
Peak memory | 252716 kb |
Host | smart-46331421-30ed-4276-8fd9-fffdec85b81c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3616333732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3616333732 |
Directory | /workspace/5.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2806670815 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 7713316846 ps |
CPU time | 112.36 seconds |
Started | Jul 15 06:45:24 PM PDT 24 |
Finished | Jul 15 06:47:17 PM PDT 24 |
Peak memory | 255736 kb |
Host | smart-2ad11fc3-3329-4446-950e-98157f50a586 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2806670815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle .2806670815 |
Directory | /workspace/5.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/5.spi_device_flash_mode.1468897273 |
Short name | T884 |
Test name | |
Test status | |
Simulation time | 974764785 ps |
CPU time | 9.77 seconds |
Started | Jul 15 06:45:14 PM PDT 24 |
Finished | Jul 15 06:45:24 PM PDT 24 |
Peak memory | 240780 kb |
Host | smart-13ac731e-e80f-49a6-9052-4d3e1f8d7a82 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1468897273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1468897273 |
Directory | /workspace/5.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.2620117050 |
Short name | T513 |
Test name | |
Test status | |
Simulation time | 14670096434 ps |
CPU time | 72.73 seconds |
Started | Jul 15 06:45:13 PM PDT 24 |
Finished | Jul 15 06:46:26 PM PDT 24 |
Peak memory | 250784 kb |
Host | smart-e2a150fe-aa88-4460-b28a-ad1dd9a32d94 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2620117050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds .2620117050 |
Directory | /workspace/5.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/5.spi_device_intercept.1664867476 |
Short name | T810 |
Test name | |
Test status | |
Simulation time | 5453764133 ps |
CPU time | 4.65 seconds |
Started | Jul 15 06:45:15 PM PDT 24 |
Finished | Jul 15 06:45:20 PM PDT 24 |
Peak memory | 224492 kb |
Host | smart-7ed63c6f-7ac8-4eda-8022-ca4773a9effc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1664867476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1664867476 |
Directory | /workspace/5.spi_device_intercept/latest |
Test location | /workspace/coverage/default/5.spi_device_mailbox.645638816 |
Short name | T532 |
Test name | |
Test status | |
Simulation time | 1447992222 ps |
CPU time | 15.72 seconds |
Started | Jul 15 06:45:17 PM PDT 24 |
Finished | Jul 15 06:45:33 PM PDT 24 |
Peak memory | 239300 kb |
Host | smart-bd53d5e1-74d2-4389-a5e1-dc06583a9b42 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=645638816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.645638816 |
Directory | /workspace/5.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1997322583 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 3282572367 ps |
CPU time | 10.19 seconds |
Started | Jul 15 06:45:17 PM PDT 24 |
Finished | Jul 15 06:45:28 PM PDT 24 |
Peak memory | 224356 kb |
Host | smart-a65e28e2-9b3d-41fd-b9f5-ec2af2abbd76 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1997322583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap .1997322583 |
Directory | /workspace/5.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/5.spi_device_pass_cmd_filtering.696321736 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 151035971 ps |
CPU time | 2.95 seconds |
Started | Jul 15 06:45:14 PM PDT 24 |
Finished | Jul 15 06:45:17 PM PDT 24 |
Peak memory | 232560 kb |
Host | smart-78d7437d-33c4-4521-bef8-f90ecc518498 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=696321736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.696321736 |
Directory | /workspace/5.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/5.spi_device_read_buffer_direct.3699370657 |
Short name | T480 |
Test name | |
Test status | |
Simulation time | 1069160761 ps |
CPU time | 11.29 seconds |
Started | Jul 15 06:45:20 PM PDT 24 |
Finished | Jul 15 06:45:31 PM PDT 24 |
Peak memory | 220248 kb |
Host | smart-ce9a1817-646a-4016-8134-43302c533f7d |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3699370657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire ct.3699370657 |
Directory | /workspace/5.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/5.spi_device_stress_all.107860118 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 39319870039 ps |
CPU time | 161.55 seconds |
Started | Jul 15 06:45:21 PM PDT 24 |
Finished | Jul 15 06:48:03 PM PDT 24 |
Peak memory | 272892 kb |
Host | smart-b829cc03-5dcd-4345-8856-062e47637e31 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107860118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress _all.107860118 |
Directory | /workspace/5.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/5.spi_device_tpm_all.3261813057 |
Short name | T668 |
Test name | |
Test status | |
Simulation time | 12415561 ps |
CPU time | 0.71 seconds |
Started | Jul 15 06:45:16 PM PDT 24 |
Finished | Jul 15 06:45:18 PM PDT 24 |
Peak memory | 205668 kb |
Host | smart-9efe083c-8a67-4c05-b5ef-7590d7346938 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3261813057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3261813057 |
Directory | /workspace/5.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1240620191 |
Short name | T700 |
Test name | |
Test status | |
Simulation time | 3910204656 ps |
CPU time | 11.75 seconds |
Started | Jul 15 06:45:16 PM PDT 24 |
Finished | Jul 15 06:45:28 PM PDT 24 |
Peak memory | 216300 kb |
Host | smart-05e97c04-0899-4d8a-83d8-e17dff39e0c3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1240620191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1240620191 |
Directory | /workspace/5.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/5.spi_device_tpm_rw.855439326 |
Short name | T848 |
Test name | |
Test status | |
Simulation time | 70882583 ps |
CPU time | 0.74 seconds |
Started | Jul 15 06:45:17 PM PDT 24 |
Finished | Jul 15 06:45:18 PM PDT 24 |
Peak memory | 205616 kb |
Host | smart-476cccd6-4c10-49c4-9c83-82b361e4185d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=855439326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.855439326 |
Directory | /workspace/5.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/5.spi_device_tpm_sts_read.104932863 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 157198117 ps |
CPU time | 0.83 seconds |
Started | Jul 15 06:45:17 PM PDT 24 |
Finished | Jul 15 06:45:18 PM PDT 24 |
Peak memory | 205904 kb |
Host | smart-823f26e1-3569-4d76-ae1e-2f16c630326b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=104932863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.104932863 |
Directory | /workspace/5.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/5.spi_device_upload.4257865018 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 19906422115 ps |
CPU time | 17.91 seconds |
Started | Jul 15 06:45:16 PM PDT 24 |
Finished | Jul 15 06:45:35 PM PDT 24 |
Peak memory | 232768 kb |
Host | smart-275499b5-821b-45c2-8d62-0bb24a4d077c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4257865018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.4257865018 |
Directory | /workspace/5.spi_device_upload/latest |
Test location | /workspace/coverage/default/6.spi_device_alert_test.1338666646 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 24084780 ps |
CPU time | 0.73 seconds |
Started | Jul 15 06:45:28 PM PDT 24 |
Finished | Jul 15 06:45:30 PM PDT 24 |
Peak memory | 205512 kb |
Host | smart-200b55fe-2c8f-4e09-8de0-f9a5fddc144c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338666646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1 338666646 |
Directory | /workspace/6.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/6.spi_device_cfg_cmd.2276133595 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 63207678 ps |
CPU time | 2.42 seconds |
Started | Jul 15 06:45:27 PM PDT 24 |
Finished | Jul 15 06:45:29 PM PDT 24 |
Peak memory | 224336 kb |
Host | smart-a3d9a96c-7804-4299-9a36-89318fd034b7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2276133595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2276133595 |
Directory | /workspace/6.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/6.spi_device_csb_read.3500677625 |
Short name | T699 |
Test name | |
Test status | |
Simulation time | 31654299 ps |
CPU time | 0.83 seconds |
Started | Jul 15 06:45:21 PM PDT 24 |
Finished | Jul 15 06:45:22 PM PDT 24 |
Peak memory | 206536 kb |
Host | smart-fb924416-9973-4d1f-bd06-bac15b8f15b3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3500677625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3500677625 |
Directory | /workspace/6.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/6.spi_device_flash_all.671343436 |
Short name | T959 |
Test name | |
Test status | |
Simulation time | 8151560941 ps |
CPU time | 41.29 seconds |
Started | Jul 15 06:45:30 PM PDT 24 |
Finished | Jul 15 06:46:12 PM PDT 24 |
Peak memory | 224388 kb |
Host | smart-e377a319-2b1e-4b20-87f0-d7cf67b2656b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=671343436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.671343436 |
Directory | /workspace/6.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/6.spi_device_flash_and_tpm.4075655541 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 5802191770 ps |
CPU time | 59.2 seconds |
Started | Jul 15 06:45:28 PM PDT 24 |
Finished | Jul 15 06:46:28 PM PDT 24 |
Peak memory | 264728 kb |
Host | smart-63f0d936-5173-40de-acf9-d27dcd0350b3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4075655541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.4075655541 |
Directory | /workspace/6.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.479030564 |
Short name | T874 |
Test name | |
Test status | |
Simulation time | 5835124220 ps |
CPU time | 81.8 seconds |
Started | Jul 15 06:45:28 PM PDT 24 |
Finished | Jul 15 06:46:50 PM PDT 24 |
Peak memory | 251584 kb |
Host | smart-d9eff208-e8db-4ef3-b2d5-64773fa72f1b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=479030564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle. 479030564 |
Directory | /workspace/6.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/6.spi_device_flash_mode.294977500 |
Short name | T1001 |
Test name | |
Test status | |
Simulation time | 2010675846 ps |
CPU time | 13.52 seconds |
Started | Jul 15 06:45:24 PM PDT 24 |
Finished | Jul 15 06:45:38 PM PDT 24 |
Peak memory | 224420 kb |
Host | smart-fe411e03-9e1d-4199-9457-61a4a92066aa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=294977500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.294977500 |
Directory | /workspace/6.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.1873339172 |
Short name | T772 |
Test name | |
Test status | |
Simulation time | 109375888087 ps |
CPU time | 180.33 seconds |
Started | Jul 15 06:45:28 PM PDT 24 |
Finished | Jul 15 06:48:29 PM PDT 24 |
Peak memory | 241132 kb |
Host | smart-5b9bede8-cc6b-4250-8625-820d291ecfd3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1873339172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds .1873339172 |
Directory | /workspace/6.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/6.spi_device_intercept.4204047070 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 38124193883 ps |
CPU time | 35.13 seconds |
Started | Jul 15 06:45:23 PM PDT 24 |
Finished | Jul 15 06:45:59 PM PDT 24 |
Peak memory | 232740 kb |
Host | smart-9e8396b2-1fa5-4c8f-b690-8cda019e0911 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4204047070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.4204047070 |
Directory | /workspace/6.spi_device_intercept/latest |
Test location | /workspace/coverage/default/6.spi_device_mailbox.2582308044 |
Short name | T738 |
Test name | |
Test status | |
Simulation time | 45819695583 ps |
CPU time | 35.1 seconds |
Started | Jul 15 06:45:22 PM PDT 24 |
Finished | Jul 15 06:45:58 PM PDT 24 |
Peak memory | 240992 kb |
Host | smart-5d5a2954-1038-4bbc-8e17-300522f4771f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2582308044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2582308044 |
Directory | /workspace/6.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1240442005 |
Short name | T828 |
Test name | |
Test status | |
Simulation time | 44081627166 ps |
CPU time | 19.52 seconds |
Started | Jul 15 06:45:20 PM PDT 24 |
Finished | Jul 15 06:45:40 PM PDT 24 |
Peak memory | 236688 kb |
Host | smart-3fb605aa-3ffe-49cb-a573-799699ad1cce |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1240442005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap .1240442005 |
Directory | /workspace/6.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2298377787 |
Short name | T892 |
Test name | |
Test status | |
Simulation time | 2646372224 ps |
CPU time | 7.81 seconds |
Started | Jul 15 06:45:24 PM PDT 24 |
Finished | Jul 15 06:45:32 PM PDT 24 |
Peak memory | 232772 kb |
Host | smart-8557a93f-2c08-4a7a-9600-29be2eb41b04 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2298377787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2298377787 |
Directory | /workspace/6.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/6.spi_device_read_buffer_direct.56290719 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 226153027 ps |
CPU time | 4.47 seconds |
Started | Jul 15 06:45:28 PM PDT 24 |
Finished | Jul 15 06:45:33 PM PDT 24 |
Peak memory | 222952 kb |
Host | smart-0b930e24-fa2a-4b4d-bb7f-78b05267f4fc |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=56290719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direct .56290719 |
Directory | /workspace/6.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/6.spi_device_tpm_all.281819166 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 20521107 ps |
CPU time | 0.7 seconds |
Started | Jul 15 06:45:22 PM PDT 24 |
Finished | Jul 15 06:45:23 PM PDT 24 |
Peak memory | 205640 kb |
Host | smart-05d154b0-bb99-46c7-976f-d97d13f8b94f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=281819166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.281819166 |
Directory | /workspace/6.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.407267014 |
Short name | T587 |
Test name | |
Test status | |
Simulation time | 1532543279 ps |
CPU time | 6.49 seconds |
Started | Jul 15 06:45:21 PM PDT 24 |
Finished | Jul 15 06:45:28 PM PDT 24 |
Peak memory | 216156 kb |
Host | smart-c587473b-01bc-4d2b-bdaf-01179a976051 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=407267014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.407267014 |
Directory | /workspace/6.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/6.spi_device_tpm_rw.371993015 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 51686276 ps |
CPU time | 0.79 seconds |
Started | Jul 15 06:45:20 PM PDT 24 |
Finished | Jul 15 06:45:21 PM PDT 24 |
Peak memory | 205948 kb |
Host | smart-67e9b486-e555-4bf5-a105-41a3c29cbdeb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=371993015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.371993015 |
Directory | /workspace/6.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/6.spi_device_tpm_sts_read.3474703909 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 30465412 ps |
CPU time | 0.87 seconds |
Started | Jul 15 06:45:21 PM PDT 24 |
Finished | Jul 15 06:45:22 PM PDT 24 |
Peak memory | 205916 kb |
Host | smart-5dff3e74-6317-42d6-bf3d-703aeca68140 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3474703909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3474703909 |
Directory | /workspace/6.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/6.spi_device_upload.2761721666 |
Short name | T675 |
Test name | |
Test status | |
Simulation time | 1439236079 ps |
CPU time | 4.28 seconds |
Started | Jul 15 06:45:28 PM PDT 24 |
Finished | Jul 15 06:45:33 PM PDT 24 |
Peak memory | 240804 kb |
Host | smart-f1b70b28-2044-402e-aa41-5fed5e5fa9f4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2761721666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2761721666 |
Directory | /workspace/6.spi_device_upload/latest |
Test location | /workspace/coverage/default/7.spi_device_alert_test.2699219574 |
Short name | T735 |
Test name | |
Test status | |
Simulation time | 66217546 ps |
CPU time | 0.76 seconds |
Started | Jul 15 06:45:43 PM PDT 24 |
Finished | Jul 15 06:45:44 PM PDT 24 |
Peak memory | 205816 kb |
Host | smart-d28c5900-69b3-47ca-b346-123add89f116 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699219574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2 699219574 |
Directory | /workspace/7.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/7.spi_device_cfg_cmd.3280559088 |
Short name | T600 |
Test name | |
Test status | |
Simulation time | 175887453 ps |
CPU time | 4.2 seconds |
Started | Jul 15 06:45:45 PM PDT 24 |
Finished | Jul 15 06:45:49 PM PDT 24 |
Peak memory | 232600 kb |
Host | smart-4e4f9625-b3e1-40bd-8510-e3b5ab80751c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3280559088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3280559088 |
Directory | /workspace/7.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/7.spi_device_csb_read.3666525832 |
Short name | T701 |
Test name | |
Test status | |
Simulation time | 93202176 ps |
CPU time | 0.78 seconds |
Started | Jul 15 06:45:29 PM PDT 24 |
Finished | Jul 15 06:45:30 PM PDT 24 |
Peak memory | 206864 kb |
Host | smart-24376123-f45e-4a6d-b506-e99253d15b35 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3666525832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3666525832 |
Directory | /workspace/7.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/7.spi_device_flash_all.3123673446 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 9875915475 ps |
CPU time | 86.06 seconds |
Started | Jul 15 06:45:43 PM PDT 24 |
Finished | Jul 15 06:47:09 PM PDT 24 |
Peak memory | 240948 kb |
Host | smart-9e78591a-e602-4842-b1d7-7f33ec1d4ca5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3123673446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3123673446 |
Directory | /workspace/7.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/7.spi_device_flash_and_tpm.608346058 |
Short name | T900 |
Test name | |
Test status | |
Simulation time | 98194750298 ps |
CPU time | 210.49 seconds |
Started | Jul 15 06:45:42 PM PDT 24 |
Finished | Jul 15 06:49:13 PM PDT 24 |
Peak memory | 254696 kb |
Host | smart-7fc5d417-20c5-4c36-8418-d045d44f2b52 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=608346058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.608346058 |
Directory | /workspace/7.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1103334685 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 89520325414 ps |
CPU time | 249.55 seconds |
Started | Jul 15 06:45:44 PM PDT 24 |
Finished | Jul 15 06:49:54 PM PDT 24 |
Peak memory | 252984 kb |
Host | smart-486bf1bb-c3f5-4111-bc57-662a3e9ba1a5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1103334685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle .1103334685 |
Directory | /workspace/7.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/7.spi_device_flash_mode.3984033488 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 999200994 ps |
CPU time | 9.39 seconds |
Started | Jul 15 06:45:43 PM PDT 24 |
Finished | Jul 15 06:45:53 PM PDT 24 |
Peak memory | 224400 kb |
Host | smart-2f930076-8178-48b2-9449-bcad5da06d3f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3984033488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3984033488 |
Directory | /workspace/7.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.1555093594 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 1888288353 ps |
CPU time | 41.52 seconds |
Started | Jul 15 06:45:42 PM PDT 24 |
Finished | Jul 15 06:46:24 PM PDT 24 |
Peak memory | 249036 kb |
Host | smart-89c9d6dc-14bb-472b-923b-92d64370e1ff |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1555093594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds .1555093594 |
Directory | /workspace/7.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/7.spi_device_intercept.3547128426 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 16502563927 ps |
CPU time | 30.55 seconds |
Started | Jul 15 06:45:36 PM PDT 24 |
Finished | Jul 15 06:46:08 PM PDT 24 |
Peak memory | 224516 kb |
Host | smart-6ceee0fd-4f3c-4af7-914d-7311247433fc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3547128426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3547128426 |
Directory | /workspace/7.spi_device_intercept/latest |
Test location | /workspace/coverage/default/7.spi_device_mailbox.3074309266 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 55377823574 ps |
CPU time | 137.24 seconds |
Started | Jul 15 06:45:35 PM PDT 24 |
Finished | Jul 15 06:47:53 PM PDT 24 |
Peak memory | 251604 kb |
Host | smart-87ba778a-3a5e-463c-9469-db016b23314c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3074309266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3074309266 |
Directory | /workspace/7.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3885820898 |
Short name | T784 |
Test name | |
Test status | |
Simulation time | 36246105 ps |
CPU time | 2.58 seconds |
Started | Jul 15 06:45:37 PM PDT 24 |
Finished | Jul 15 06:45:40 PM PDT 24 |
Peak memory | 232248 kb |
Host | smart-81d4eb3d-416d-4e55-a39c-b76feb84f2dd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3885820898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap .3885820898 |
Directory | /workspace/7.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/7.spi_device_pass_cmd_filtering.283636453 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 31632575033 ps |
CPU time | 6.03 seconds |
Started | Jul 15 06:45:37 PM PDT 24 |
Finished | Jul 15 06:45:44 PM PDT 24 |
Peak memory | 232756 kb |
Host | smart-728fcf1c-d2c3-4dee-8513-81c2e67f0712 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=283636453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.283636453 |
Directory | /workspace/7.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/7.spi_device_read_buffer_direct.3280331628 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 2156395934 ps |
CPU time | 17.37 seconds |
Started | Jul 15 06:45:40 PM PDT 24 |
Finished | Jul 15 06:45:58 PM PDT 24 |
Peak memory | 221604 kb |
Host | smart-f9140ec7-6d55-4f4a-9908-f38adab0e6b6 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3280331628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire ct.3280331628 |
Directory | /workspace/7.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/7.spi_device_stress_all.2432603092 |
Short name | T975 |
Test name | |
Test status | |
Simulation time | 44060512520 ps |
CPU time | 111.05 seconds |
Started | Jul 15 06:45:44 PM PDT 24 |
Finished | Jul 15 06:47:35 PM PDT 24 |
Peak memory | 250216 kb |
Host | smart-0985338e-5200-4c1c-a123-0c16e1d117eb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432603092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres s_all.2432603092 |
Directory | /workspace/7.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/7.spi_device_tpm_all.2173022573 |
Short name | T785 |
Test name | |
Test status | |
Simulation time | 13396880748 ps |
CPU time | 15.76 seconds |
Started | Jul 15 06:45:36 PM PDT 24 |
Finished | Jul 15 06:45:52 PM PDT 24 |
Peak memory | 216308 kb |
Host | smart-a42e1a6c-4ac1-42d0-b23a-87ba19c02842 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2173022573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2173022573 |
Directory | /workspace/7.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.399599617 |
Short name | T498 |
Test name | |
Test status | |
Simulation time | 2957133893 ps |
CPU time | 6.3 seconds |
Started | Jul 15 06:45:35 PM PDT 24 |
Finished | Jul 15 06:45:42 PM PDT 24 |
Peak memory | 216344 kb |
Host | smart-de88076d-380c-4edb-bf13-73e2145d3cc1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=399599617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.399599617 |
Directory | /workspace/7.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/7.spi_device_tpm_rw.2627620726 |
Short name | T779 |
Test name | |
Test status | |
Simulation time | 323151604 ps |
CPU time | 6.67 seconds |
Started | Jul 15 06:45:36 PM PDT 24 |
Finished | Jul 15 06:45:44 PM PDT 24 |
Peak memory | 216132 kb |
Host | smart-4bc870dc-9510-4239-bf5b-71aac196c128 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2627620726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2627620726 |
Directory | /workspace/7.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/7.spi_device_tpm_sts_read.37989736 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 70928964 ps |
CPU time | 0.73 seconds |
Started | Jul 15 06:45:36 PM PDT 24 |
Finished | Jul 15 06:45:37 PM PDT 24 |
Peak memory | 205888 kb |
Host | smart-950ab2f8-6133-46a6-9111-c04b584ef50d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=37989736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.37989736 |
Directory | /workspace/7.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/7.spi_device_upload.3499497164 |
Short name | T868 |
Test name | |
Test status | |
Simulation time | 666384277 ps |
CPU time | 4.22 seconds |
Started | Jul 15 06:45:36 PM PDT 24 |
Finished | Jul 15 06:45:41 PM PDT 24 |
Peak memory | 224460 kb |
Host | smart-4e0087db-52ed-4863-8a54-f1015e0fa70a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3499497164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3499497164 |
Directory | /workspace/7.spi_device_upload/latest |
Test location | /workspace/coverage/default/8.spi_device_alert_test.3280286540 |
Short name | T935 |
Test name | |
Test status | |
Simulation time | 13651238 ps |
CPU time | 0.74 seconds |
Started | Jul 15 06:45:56 PM PDT 24 |
Finished | Jul 15 06:45:58 PM PDT 24 |
Peak memory | 204864 kb |
Host | smart-2190ec3b-03f3-4d5b-8a38-1f0eaf241830 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280286540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3 280286540 |
Directory | /workspace/8.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/8.spi_device_cfg_cmd.312802988 |
Short name | T953 |
Test name | |
Test status | |
Simulation time | 1633992161 ps |
CPU time | 3.5 seconds |
Started | Jul 15 06:45:52 PM PDT 24 |
Finished | Jul 15 06:45:56 PM PDT 24 |
Peak memory | 224388 kb |
Host | smart-4925b0db-8726-4364-85e3-12d03dc2eef1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=312802988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.312802988 |
Directory | /workspace/8.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/8.spi_device_csb_read.3017727828 |
Short name | T987 |
Test name | |
Test status | |
Simulation time | 29852599 ps |
CPU time | 0.73 seconds |
Started | Jul 15 06:45:42 PM PDT 24 |
Finished | Jul 15 06:45:43 PM PDT 24 |
Peak memory | 205560 kb |
Host | smart-459cb5ab-5e01-4487-ad6f-577b8e9877b6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3017727828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3017727828 |
Directory | /workspace/8.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/8.spi_device_flash_all.1377169443 |
Short name | T482 |
Test name | |
Test status | |
Simulation time | 70040505204 ps |
CPU time | 147.02 seconds |
Started | Jul 15 06:45:49 PM PDT 24 |
Finished | Jul 15 06:48:17 PM PDT 24 |
Peak memory | 251968 kb |
Host | smart-5d116b65-0654-44a3-84fc-a95d0a673f12 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1377169443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1377169443 |
Directory | /workspace/8.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/8.spi_device_flash_and_tpm.4019535792 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 1586892283 ps |
CPU time | 35.94 seconds |
Started | Jul 15 06:45:50 PM PDT 24 |
Finished | Jul 15 06:46:26 PM PDT 24 |
Peak memory | 249148 kb |
Host | smart-8a7bab6b-9392-429f-b140-755960daddf4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4019535792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.4019535792 |
Directory | /workspace/8.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3795287293 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 1857817979 ps |
CPU time | 42.52 seconds |
Started | Jul 15 06:45:50 PM PDT 24 |
Finished | Jul 15 06:46:34 PM PDT 24 |
Peak memory | 251236 kb |
Host | smart-3b808b65-0f81-4139-81f0-b197a9174d23 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3795287293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle .3795287293 |
Directory | /workspace/8.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/8.spi_device_flash_mode.158782577 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 4400904853 ps |
CPU time | 59.24 seconds |
Started | Jul 15 06:45:50 PM PDT 24 |
Finished | Jul 15 06:46:50 PM PDT 24 |
Peak memory | 224500 kb |
Host | smart-419df01f-c85e-4206-85c5-7e8557f36c36 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=158782577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.158782577 |
Directory | /workspace/8.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.3876315181 |
Short name | T652 |
Test name | |
Test status | |
Simulation time | 8536005428 ps |
CPU time | 90.04 seconds |
Started | Jul 15 06:45:48 PM PDT 24 |
Finished | Jul 15 06:47:19 PM PDT 24 |
Peak memory | 249148 kb |
Host | smart-a2af1512-76e8-4d44-86eb-0f4856a113b8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3876315181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds .3876315181 |
Directory | /workspace/8.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/8.spi_device_intercept.1254281056 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 813436644 ps |
CPU time | 6.08 seconds |
Started | Jul 15 06:45:51 PM PDT 24 |
Finished | Jul 15 06:45:58 PM PDT 24 |
Peak memory | 232624 kb |
Host | smart-e4e82c10-df67-482f-8ef9-52d884a55749 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1254281056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1254281056 |
Directory | /workspace/8.spi_device_intercept/latest |
Test location | /workspace/coverage/default/8.spi_device_mailbox.155632696 |
Short name | T642 |
Test name | |
Test status | |
Simulation time | 3313699742 ps |
CPU time | 10.16 seconds |
Started | Jul 15 06:45:49 PM PDT 24 |
Finished | Jul 15 06:46:00 PM PDT 24 |
Peak memory | 232688 kb |
Host | smart-28652a9e-caf9-448f-8c13-7b27b202a451 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=155632696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.155632696 |
Directory | /workspace/8.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.4078475526 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 1750060528 ps |
CPU time | 4.82 seconds |
Started | Jul 15 06:45:50 PM PDT 24 |
Finished | Jul 15 06:45:55 PM PDT 24 |
Peak memory | 224396 kb |
Host | smart-37e5b182-4289-4f86-ae25-c166475dd9b0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4078475526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap .4078475526 |
Directory | /workspace/8.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1075901895 |
Short name | T596 |
Test name | |
Test status | |
Simulation time | 10030051373 ps |
CPU time | 9.68 seconds |
Started | Jul 15 06:45:48 PM PDT 24 |
Finished | Jul 15 06:45:58 PM PDT 24 |
Peak memory | 224536 kb |
Host | smart-b59fc8fc-f5cb-46ca-ac2f-30790bdd9a1b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1075901895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1075901895 |
Directory | /workspace/8.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/8.spi_device_read_buffer_direct.1078559370 |
Short name | T709 |
Test name | |
Test status | |
Simulation time | 2618021672 ps |
CPU time | 17.5 seconds |
Started | Jul 15 06:45:50 PM PDT 24 |
Finished | Jul 15 06:46:08 PM PDT 24 |
Peak memory | 219404 kb |
Host | smart-6bf9d3e2-7fe6-405c-bd76-b90b1010fe83 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1078559370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire ct.1078559370 |
Directory | /workspace/8.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/8.spi_device_tpm_all.2075345377 |
Short name | T556 |
Test name | |
Test status | |
Simulation time | 2851076319 ps |
CPU time | 12.43 seconds |
Started | Jul 15 06:45:47 PM PDT 24 |
Finished | Jul 15 06:46:00 PM PDT 24 |
Peak memory | 219972 kb |
Host | smart-e101001d-f2b3-43c4-8c01-910f78f148e7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2075345377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2075345377 |
Directory | /workspace/8.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2037405223 |
Short name | T955 |
Test name | |
Test status | |
Simulation time | 12278944780 ps |
CPU time | 12.17 seconds |
Started | Jul 15 06:45:44 PM PDT 24 |
Finished | Jul 15 06:45:56 PM PDT 24 |
Peak memory | 216428 kb |
Host | smart-939027aa-25ef-4706-940a-6b78f3d5d02c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2037405223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2037405223 |
Directory | /workspace/8.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/8.spi_device_tpm_rw.4028103035 |
Short name | T562 |
Test name | |
Test status | |
Simulation time | 222385241 ps |
CPU time | 4.34 seconds |
Started | Jul 15 06:45:50 PM PDT 24 |
Finished | Jul 15 06:45:54 PM PDT 24 |
Peak memory | 216172 kb |
Host | smart-969691a5-a3f1-470f-b98b-5006932b95c3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4028103035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.4028103035 |
Directory | /workspace/8.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/8.spi_device_tpm_sts_read.1401784896 |
Short name | T777 |
Test name | |
Test status | |
Simulation time | 50484793 ps |
CPU time | 0.89 seconds |
Started | Jul 15 06:45:50 PM PDT 24 |
Finished | Jul 15 06:45:51 PM PDT 24 |
Peak memory | 205892 kb |
Host | smart-0aa05a80-e81b-4056-9ae6-4979d2db79df |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1401784896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1401784896 |
Directory | /workspace/8.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/8.spi_device_upload.4066123344 |
Short name | T840 |
Test name | |
Test status | |
Simulation time | 192022589 ps |
CPU time | 2.75 seconds |
Started | Jul 15 06:45:51 PM PDT 24 |
Finished | Jul 15 06:45:54 PM PDT 24 |
Peak memory | 224392 kb |
Host | smart-d0740745-48ce-42dc-b601-da54c294d377 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4066123344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.4066123344 |
Directory | /workspace/8.spi_device_upload/latest |
Test location | /workspace/coverage/default/9.spi_device_alert_test.1745494097 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 11654990 ps |
CPU time | 0.69 seconds |
Started | Jul 15 06:46:02 PM PDT 24 |
Finished | Jul 15 06:46:05 PM PDT 24 |
Peak memory | 205448 kb |
Host | smart-f82c41c5-232b-4c90-bda3-34542cf5c684 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745494097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1 745494097 |
Directory | /workspace/9.spi_device_alert_test/latest |
Test location | /workspace/coverage/default/9.spi_device_cfg_cmd.2178150357 |
Short name | T971 |
Test name | |
Test status | |
Simulation time | 2511455126 ps |
CPU time | 14 seconds |
Started | Jul 15 06:45:59 PM PDT 24 |
Finished | Jul 15 06:46:16 PM PDT 24 |
Peak memory | 224592 kb |
Host | smart-18ab3b62-228c-4985-81e9-03d2e2e32779 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2178150357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2178150357 |
Directory | /workspace/9.spi_device_cfg_cmd/latest |
Test location | /workspace/coverage/default/9.spi_device_csb_read.837200289 |
Short name | T502 |
Test name | |
Test status | |
Simulation time | 62195427 ps |
CPU time | 0.78 seconds |
Started | Jul 15 06:46:00 PM PDT 24 |
Finished | Jul 15 06:46:03 PM PDT 24 |
Peak memory | 206872 kb |
Host | smart-885bf3b7-7a50-417e-95f7-e14d010ea2dc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=837200289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.837200289 |
Directory | /workspace/9.spi_device_csb_read/latest |
Test location | /workspace/coverage/default/9.spi_device_flash_all.1239322966 |
Short name | T538 |
Test name | |
Test status | |
Simulation time | 5610498259 ps |
CPU time | 29.85 seconds |
Started | Jul 15 06:45:59 PM PDT 24 |
Finished | Jul 15 06:46:31 PM PDT 24 |
Peak memory | 255596 kb |
Host | smart-4f257faa-b16c-4245-8639-41734e85b6cb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1239322966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1239322966 |
Directory | /workspace/9.spi_device_flash_all/latest |
Test location | /workspace/coverage/default/9.spi_device_flash_and_tpm.1796369883 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 52992902961 ps |
CPU time | 126.61 seconds |
Started | Jul 15 06:46:01 PM PDT 24 |
Finished | Jul 15 06:48:10 PM PDT 24 |
Peak memory | 265980 kb |
Host | smart-08122c6e-809e-4874-9b13-b5f2c5f71604 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1796369883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1796369883 |
Directory | /workspace/9.spi_device_flash_and_tpm/latest |
Test location | /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.468378513 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 65333909489 ps |
CPU time | 609.5 seconds |
Started | Jul 15 06:45:59 PM PDT 24 |
Finished | Jul 15 06:56:11 PM PDT 24 |
Peak memory | 257208 kb |
Host | smart-eb488b71-96cc-4461-a63e-f1623285df26 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=468378513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle. 468378513 |
Directory | /workspace/9.spi_device_flash_and_tpm_min_idle/latest |
Test location | /workspace/coverage/default/9.spi_device_flash_mode.677186144 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 26033298599 ps |
CPU time | 53.87 seconds |
Started | Jul 15 06:45:58 PM PDT 24 |
Finished | Jul 15 06:46:55 PM PDT 24 |
Peak memory | 250472 kb |
Host | smart-a1284a9d-8927-498c-931c-ce536306df74 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=677186144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.677186144 |
Directory | /workspace/9.spi_device_flash_mode/latest |
Test location | /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.2162229421 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 13171817253 ps |
CPU time | 173.12 seconds |
Started | Jul 15 06:45:59 PM PDT 24 |
Finished | Jul 15 06:48:55 PM PDT 24 |
Peak memory | 266516 kb |
Host | smart-cbe8aee2-d2c7-4e7a-919e-d115b6e075cd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2162229421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds .2162229421 |
Directory | /workspace/9.spi_device_flash_mode_ignore_cmds/latest |
Test location | /workspace/coverage/default/9.spi_device_intercept.696911405 |
Short name | T664 |
Test name | |
Test status | |
Simulation time | 917602636 ps |
CPU time | 7.77 seconds |
Started | Jul 15 06:45:59 PM PDT 24 |
Finished | Jul 15 06:46:09 PM PDT 24 |
Peak memory | 224384 kb |
Host | smart-0b914052-91d9-446d-b022-37610d03678a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=696911405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.696911405 |
Directory | /workspace/9.spi_device_intercept/latest |
Test location | /workspace/coverage/default/9.spi_device_mailbox.1550914844 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 15663011569 ps |
CPU time | 39.17 seconds |
Started | Jul 15 06:45:59 PM PDT 24 |
Finished | Jul 15 06:46:41 PM PDT 24 |
Peak memory | 232676 kb |
Host | smart-49a5a3a3-a050-487a-b347-fe5d225c448f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1550914844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1550914844 |
Directory | /workspace/9.spi_device_mailbox/latest |
Test location | /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3004594750 |
Short name | T825 |
Test name | |
Test status | |
Simulation time | 13815581441 ps |
CPU time | 36.88 seconds |
Started | Jul 15 06:46:00 PM PDT 24 |
Finished | Jul 15 06:46:40 PM PDT 24 |
Peak memory | 240640 kb |
Host | smart-a7ce651c-45b9-4f2a-bd8d-323b59cc33a7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3004594750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap .3004594750 |
Directory | /workspace/9.spi_device_pass_addr_payload_swap/latest |
Test location | /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3829646382 |
Short name | T551 |
Test name | |
Test status | |
Simulation time | 412295813 ps |
CPU time | 2.59 seconds |
Started | Jul 15 06:45:57 PM PDT 24 |
Finished | Jul 15 06:46:00 PM PDT 24 |
Peak memory | 222988 kb |
Host | smart-6abe2796-9aa8-4f46-971e-cd61b5cc75cf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3829646382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3829646382 |
Directory | /workspace/9.spi_device_pass_cmd_filtering/latest |
Test location | /workspace/coverage/default/9.spi_device_read_buffer_direct.2328798258 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 1665423195 ps |
CPU time | 17.12 seconds |
Started | Jul 15 06:45:59 PM PDT 24 |
Finished | Jul 15 06:46:19 PM PDT 24 |
Peak memory | 222060 kb |
Host | smart-482af1e2-6580-4fbe-a935-a3146813ef14 |
User | root |
Command | /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2328798258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire ct.2328798258 |
Directory | /workspace/9.spi_device_read_buffer_direct/latest |
Test location | /workspace/coverage/default/9.spi_device_stress_all.4163086506 |
Short name | T684 |
Test name | |
Test status | |
Simulation time | 394294928183 ps |
CPU time | 279.79 seconds |
Started | Jul 15 06:46:02 PM PDT 24 |
Finished | Jul 15 06:50:44 PM PDT 24 |
Peak memory | 256304 kb |
Host | smart-eda57210-3757-4485-a832-baca4f033b1e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163086506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres s_all.4163086506 |
Directory | /workspace/9.spi_device_stress_all/latest |
Test location | /workspace/coverage/default/9.spi_device_tpm_all.1678414789 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 4657117616 ps |
CPU time | 19.95 seconds |
Started | Jul 15 06:45:58 PM PDT 24 |
Finished | Jul 15 06:46:20 PM PDT 24 |
Peak memory | 220192 kb |
Host | smart-fab0c7f0-e74d-48b8-9d7f-fd799e934720 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1678414789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1678414789 |
Directory | /workspace/9.spi_device_tpm_all/latest |
Test location | /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2317001615 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 1787259008 ps |
CPU time | 6.72 seconds |
Started | Jul 15 06:46:00 PM PDT 24 |
Finished | Jul 15 06:46:10 PM PDT 24 |
Peak memory | 216180 kb |
Host | smart-130e124a-f3df-4bf2-ad77-69ce697bfa77 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2317001615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2317001615 |
Directory | /workspace/9.spi_device_tpm_read_hw_reg/latest |
Test location | /workspace/coverage/default/9.spi_device_tpm_rw.1107238817 |
Short name | T540 |
Test name | |
Test status | |
Simulation time | 161220994 ps |
CPU time | 1.7 seconds |
Started | Jul 15 06:45:57 PM PDT 24 |
Finished | Jul 15 06:46:00 PM PDT 24 |
Peak memory | 216156 kb |
Host | smart-66a50de0-9e30-437f-a83a-56e07b0fe7b6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1107238817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1107238817 |
Directory | /workspace/9.spi_device_tpm_rw/latest |
Test location | /workspace/coverage/default/9.spi_device_tpm_sts_read.1099872306 |
Short name | T827 |
Test name | |
Test status | |
Simulation time | 175164312 ps |
CPU time | 1.03 seconds |
Started | Jul 15 06:45:57 PM PDT 24 |
Finished | Jul 15 06:45:59 PM PDT 24 |
Peak memory | 206964 kb |
Host | smart-cbd24b81-c2ae-4f77-b3ea-719853e9c473 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1099872306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1099872306 |
Directory | /workspace/9.spi_device_tpm_sts_read/latest |
Test location | /workspace/coverage/default/9.spi_device_upload.1429203885 |
Short name | T625 |
Test name | |
Test status | |
Simulation time | 3811539902 ps |
CPU time | 6 seconds |
Started | Jul 15 06:45:58 PM PDT 24 |
Finished | Jul 15 06:46:07 PM PDT 24 |
Peak memory | 232784 kb |
Host | smart-a9c4b16b-b09a-4fcb-a72c-983a2e1189e5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1429203885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1429203885 |
Directory | /workspace/9.spi_device_upload/latest |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |