Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3147383	1			T2	1		T3	1		T4	1119
all_values[1]	3147383	1			T2	1		T3	1		T4	1119
all_values[2]	3147383	1			T2	1		T3	1		T4	1119
all_values[3]	3147383	1			T2	1		T3	1		T4	1119
all_values[4]	3147383	1			T2	1		T3	1		T4	1119
all_values[5]	3147383	1			T2	1		T3	1		T4	1119
all_values[6]	3147383	1			T2	1		T3	1		T4	1119
all_values[7]	3147383	1			T2	1		T3	1		T4	1119

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24470883

1

T2

8

T3

8

T4

8952

auto[1]

708181

1

T21

51

T26

60

T27

73

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25150931

1

T2

8

T3

8

T4

8952

auto[1]

28133

1

T10

189

T37

392

T21

39

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	3078022	1			T2	1		T3	1		T4	1119
all_values[0]	auto[0]	auto[1]	13287	1			T10	97		T37	239		T21	3
all_values[0]	auto[1]	auto[0]	55478	1			T21	2		T26	1		T27	5
all_values[0]	auto[1]	auto[1]	596	1			T21	4		T26	3		T27	4
all_values[1]	auto[0]	auto[0]	3012365	1			T2	1		T3	1		T4	1119
all_values[1]	auto[0]	auto[1]	8275	1			T10	88		T37	114		T21	1
all_values[1]	auto[1]	auto[0]	126260	1			T21	2		T26	3		T27	4
all_values[1]	auto[1]	auto[1]	483	1			T21	2		T26	1		T27	6
all_values[2]	auto[0]	auto[0]	3053057	1			T2	1		T3	1		T4	1119
all_values[2]	auto[0]	auto[1]	3108	1			T10	4		T37	39		T21	3
all_values[2]	auto[1]	auto[0]	90917	1			T21	4		T26	7		T27	7
all_values[2]	auto[1]	auto[1]	301	1			T21	3		T26	6		T27	1
all_values[3]	auto[0]	auto[0]	3020291	1			T2	1		T3	1		T4	1119
all_values[3]	auto[0]	auto[1]	225	1			T21	2		T26	7		T27	2
all_values[3]	auto[1]	auto[0]	126660	1			T21	5		T26	3		T27	9
all_values[3]	auto[1]	auto[1]	207	1			T21	5		T26	3		T27	2
all_values[4]	auto[0]	auto[0]	3097132	1			T2	1		T3	1		T4	1119
all_values[4]	auto[0]	auto[1]	245	1			T21	1		T26	5		T27	1
all_values[4]	auto[1]	auto[0]	49811	1			T21	6		T26	5		T27	2
all_values[4]	auto[1]	auto[1]	195	1			T21	3		T26	3		T27	1
all_values[5]	auto[0]	auto[0]	3054821	1			T2	1		T3	1		T4	1119
all_values[5]	auto[0]	auto[1]	184	1			T21	2		T26	4		T28	3
all_values[5]	auto[1]	auto[0]	92212	1			T21	5		T26	3		T27	7
all_values[5]	auto[1]	auto[1]	166	1			T21	1		T26	2		T27	4
all_values[6]	auto[0]	auto[0]	3044499	1			T2	1		T3	1		T4	1119
all_values[6]	auto[0]	auto[1]	220	1			T21	1		T26	4		T27	3
all_values[6]	auto[1]	auto[0]	102458	1			T21	3		T26	6		T27	9
all_values[6]	auto[1]	auto[1]	206	1			T21	1		T26	5		T27	2
all_values[7]	auto[0]	auto[0]	3084954	1			T2	1		T3	1		T4	1119
all_values[7]	auto[0]	auto[1]	198	1			T21	5		T26	1		T27	1
all_values[7]	auto[1]	auto[0]	61994	1			T21	3		T26	3		T27	7
all_values[7]	auto[1]	auto[1]	237	1			T21	2		T26	6		T27	3