Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	36008	1			T5	210		T8	193		T10	87
auto[SpiFlashAddrCfg]	7861	1			T5	11		T8	34		T10	28
auto[SpiFlashAddr3b]	9917	1			T5	22		T8	52		T10	28
auto[SpiFlashAddr4b]	8315	1			T5	20		T8	48		T10	36

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35397

1

T5

195

T8

186

T10

92

auto[1]

26704

1

T5

68

T8

141

T10

87

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32691

1

T5

134

T8

108

T10

104

auto[1]

29410

1

T5

129

T8

219

T10

75

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	41013	1			T5	223		T8	219		T10	118
values[1]	1222	1			T5	3		T8	3		T10	2
values[2]	1585	1			T5	4		T8	6		T10	1
values[3]	1544	1			T5	2		T8	9		T10	8
values[4]	1554	1			T5	8		T8	6		T37	9
values[5]	1615	1			T5	4		T8	7		T10	3
values[6]	1582	1			T8	17		T10	9		T37	15
values[7]	1527	1			T5	1		T8	11		T10	8
values[8]	10459	1			T5	18		T8	49		T10	30

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30071

1

T5

263

T8

327

T13

8

auto[1]

32030

1

T10

179

T35

100

T40

190

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

58621

1

T5

259

T8

314

T10

166

write

3480

1

T5

4

T8

13

T10

13

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20897

1

T5

46

T8

109

T10

76

valids[0x1]

41204

1

T5

217

T8

218

T10

103

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1754	1			T5	2		T8	7		T10	10
internal_process_ops[0x5a]	1628	1			T5	2		T8	4		T10	6
internal_process_ops[0x05]	20770	1			T5	186		T8	129		T10	26
internal_process_ops[0x35]	1685	1			T8	8		T10	6		T37	9
internal_process_ops[0x15]	1747	1			T5	4		T8	12		T10	9
internal_process_ops[0x03]	1091	1			T5	4		T8	7		T10	1
internal_process_ops[0x0b]	1100	1			T5	1		T8	7		T10	2
internal_process_ops[0x3b]	1159	1			T5	3		T8	7		T10	1
internal_process_ops[0x6b]	1012	1			T5	2		T8	3		T10	4
internal_process_ops[0xbb]	1093	1			T5	4		T8	9		T41	4
internal_process_ops[0xeb]	1130	1			T5	5		T8	6		T19	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60395

1

T5

260

T8

318

T10

173

auto[1]

1706

1

T5

3

T8

9

T10

6

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59649

1

T5

257

T8

319

T10

168

auto[1]

2452

1

T5

6

T8

8

T10

11

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10255

1

T5

164

T8

113

T13

8

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5507

1

T5

43

T8

76

T16

10

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1995

1

T5

4

T8

17

T19

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1873

1

T5

7

T8

13

T16

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2568

1

T5

10

T8

31

T20

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2248

1

T5

11

T8

17

T16

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2060

1

T5

13

T8

17

T19

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2016

1

T5

7

T8

30

T16

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

134

1

T8

2

T37

2

T42

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

96

1

T5

3

T8

1

T37

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

72

1

T44

2

T45

1

T29

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

76

1

T8

1

T37

1

T45

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

108

1

T20

2

T45

1

T46

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

102

1

T8

2

T37

3

T43

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

78

1

T8

1

T37

2

T46

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

118

1

T8

1

T37

2

T42

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

116

1

T5

1

T8

1

T42

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

97

1

T8

2

T37

1

T43

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

59

1

T46

1

T47

2

T28

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

98

1

T8

1

T45

1

T28

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

118

1

T37

3

T43

1

T44

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

94

1

T46

2

T47

1

T28

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

85

1

T37

1

T42

1

T43

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

98

1

T8

1

T37

1

T43

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11296

1

T10

52

T35

21

T40

70

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8102

1

T10

35

T35

17

T40

33

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1548

1

T10

6

T35

5

T40

11

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1550

1

T10

17

T35

5

T40

6

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2133

1

T10

9

T35

9

T40

14

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2108

1

T10

18

T35

15

T40

23

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1668

1

T10

17

T35

6

T40

8

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1694

1

T10

12

T35

13

T40

9

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

137

1

T38

1

T27

5

T50

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

108

1

T40

2

T27

4

T50

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

117

1

T36

1

T26

2

T38

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

108

1

T40

1

T26

3

T38

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

117

1

T10

2

T40

1

T36

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

132

1

T35

1

T40

4

T27

6

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

108

1

T38

1

T27

4

T141

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

132

1

T10

3

T35

2

T40

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

132

1

T38

1

T27

10

T140

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

118

1

T10

1

T35

2

T38

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

124

1

T40

3

T38

1

T27

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

116

1

T35

1

T40

1

T38

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

151

1

T10

3

T35

3

T36

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

114

1

T10

2

T40

1

T26

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

118

1

T10

2

T40

1

T38

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

99

1

T26

1

T38

6

T27

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4151	1			T5	23		T8	37		T16	8
auto[0]	values[0]	valids[0x1]	14557	1			T5	200		T8	182		T13	8
auto[0]	values[1]	valids[0x1]	581	1			T5	3		T8	3		T37	8
auto[0]	values[2]	valids[0x0]	559	1			T5	4		T8	5		T20	2
auto[0]	values[2]	valids[0x1]	312	1			T8	1		T37	5		T42	3
auto[0]	values[3]	valids[0x0]	538	1			T8	5		T37	8		T42	2
auto[0]	values[3]	valids[0x1]	326	1			T5	2		T8	4		T37	4
auto[0]	values[4]	valids[0x0]	541	1			T5	4		T8	3		T37	8
auto[0]	values[4]	valids[0x1]	308	1			T5	4		T8	3		T37	1
auto[0]	values[5]	valids[0x0]	619	1			T5	4		T8	6		T41	10
auto[0]	values[5]	valids[0x1]	286	1			T8	1		T41	2		T37	4
auto[0]	values[6]	valids[0x0]	517	1			T8	14		T37	7		T42	1
auto[0]	values[6]	valids[0x1]	321	1			T8	3		T37	8		T42	1
auto[0]	values[7]	valids[0x0]	499	1			T5	1		T8	4		T16	2
auto[0]	values[7]	valids[0x1]	306	1			T8	7		T37	1		T42	3
auto[0]	values[8]	valids[0x0]	3621	1			T5	10		T8	35		T16	2
auto[0]	values[8]	valids[0x1]	2029	1			T5	8		T8	14		T20	8
auto[1]	values[0]	valids[0x0]	4439	1			T10	40		T35	18		T40	27
auto[1]	values[0]	valids[0x1]	17866	1			T10	78		T35	38		T40	100
auto[1]	values[1]	valids[0x1]	641	1			T10	2		T35	5		T40	3
auto[1]	values[2]	valids[0x0]	441	1			T35	2		T40	3		T36	2
auto[1]	values[2]	valids[0x1]	273	1			T10	1		T35	1		T40	5
auto[1]	values[3]	valids[0x0]	420	1			T10	6		T40	5		T36	1
auto[1]	values[3]	valids[0x1]	260	1			T10	2		T35	1		T40	1
auto[1]	values[4]	valids[0x0]	442	1			T35	3		T36	1		T26	3
auto[1]	values[4]	valids[0x1]	263	1			T40	3		T36	2		T26	3
auto[1]	values[5]	valids[0x0]	411	1			T10	2		T40	2		T36	2
auto[1]	values[5]	valids[0x1]	299	1			T10	1		T35	3		T36	2
auto[1]	values[6]	valids[0x0]	462	1			T10	4		T35	1		T40	5
auto[1]	values[6]	valids[0x1]	282	1			T10	5		T35	1		T26	3
auto[1]	values[7]	valids[0x0]	411	1			T10	6		T35	3		T36	1
auto[1]	values[7]	valids[0x1]	311	1			T10	2		T35	2		T40	6
auto[1]	values[8]	valids[0x0]	2826	1			T10	18		T35	16		T40	24
auto[1]	values[8]	valids[0x1]	1983	1			T10	12		T35	6		T40	6