Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3333684

1

T5

5678

T6

1

T8

15797

auto[1]

38483

1

T5

183

T8

127

T10

19

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

804358

1

T5

29

T6

1

T8

42

auto[1]

2567809

1

T5

5832

T8

15882

T10

7690

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	600934	1			T5	52		T6	1		T8	1544
auto[524288:1048575]	406848	1			T5	5713		T8	2		T10	4313
auto[1048576:1572863]	426820	1			T5	5		T8	1621		T10	8
auto[1572864:2097151]	384629	1			T5	1		T8	2652		T10	1
auto[2097152:2621439]	382381	1			T5	1		T8	7		T10	18
auto[2621440:3145727]	378368	1			T8	9828		T10	2282		T13	1843
auto[3145728:3670015]	423020	1			T5	48		T10	146		T13	106
auto[3670016:4194303]	369167	1			T5	41		T8	270		T10	10

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2605181

1

T5

5859

T6

1

T8

15918

auto[1]

766986

1

T5

2

T8

6

T10

2

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2896899

1

T5

3339

T6

1

T8

14912

auto[1]

475268

1

T5

2522

T8

1012

T10

1496

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	185203	1			T5	1		T6	1		T8	2
auto[0]	auto[0]	auto[0:524287]	auto[1]	329432	1			T8	517		T10	261		T20	2
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	70096	1			T5	1		T8	2		T10	12
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	262491	1			T5	3245		T10	4294		T37	649
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	95836	1			T5	2		T8	8		T10	3
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	268857	1			T5	1		T8	1545		T10	5
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	98643	1			T5	1		T8	2		T10	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	237573	1			T8	2648		T37	256		T40	517
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	98023	1			T8	2		T10	4		T13	97
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	232566	1			T8	5		T10	5		T37	264
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	60757	1			T8	12		T10	6		T13	1843
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	247389	1			T8	9780		T10	1505		T37	136
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	92224	1			T5	5		T10	10		T13	106
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	266921	1			T5	1		T10	133		T37	8
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	90493	1			T5	2		T8	5		T10	5
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	226072	1			T5	1		T8	257		T37	3073
auto[0]	auto[1]	auto[0:524287]	auto[0]	810	1			T5	1		T8	1		T10	3
auto[0]	auto[1]	auto[0:524287]	auto[1]	79412	1			T5	1		T8	1008		T10	708
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1158	1			T5	6		T10	1		T37	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	69486	1			T5	2406		T37	1		T40	769
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	945	1			T5	1		T37	5		T42	12
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	54915	1			T37	130		T45	1		T47	256
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	930	1			T42	5		T26	2		T45	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	43054	1			T37	256		T26	1		T45	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	877	1			T5	1		T10	3		T42	35
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	47575	1			T10	2		T36	53		T27	1107
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	2482	1			T10	1		T37	5		T74	82
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	61932	1			T10	768		T37	2980		T36	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	670	1			T5	2		T37	3		T74	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	58504	1			T37	5		T38	642		T46	260
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	802	1			T10	1		T37	2		T74	96
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	47556	1			T8	3		T10	1		T37	256
auto[1]	auto[0]	auto[0:524287]	auto[0]	522	1			T8	1		T20	2		T40	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	5171	1			T8	15		T20	35		T40	2
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	443	1			T10	3		T37	4		T43	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2509	1			T10	3		T37	15		T43	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	500	1			T5	1		T8	3		T37	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	5305	1			T8	65		T40	2		T43	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	428	1			T8	1		T40	3		T26	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3394	1			T8	1		T40	5		T26	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	439	1			T37	3		T42	14		T26	4
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2354	1			T37	27		T26	20		T45	12
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	504	1			T8	2		T10	1		T37	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	4906	1			T8	34		T10	1		T37	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	437	1			T5	1		T10	3		T37	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	3639	1			T5	39		T37	4		T40	7
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	432	1			T5	1		T8	1		T37	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	3340	1			T5	37		T8	4		T37	32
auto[1]	auto[1]	auto[0:524287]	auto[0]	103	1			T5	1		T10	1		T37	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	281	1			T5	48		T37	1		T36	4
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	96	1			T5	2		T37	1		T42	6
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	569	1			T5	53		T37	2		T40	4
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	95	1			T37	2		T42	4		T45	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	367	1			T37	12		T45	5		T33	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	100	1			T42	3		T26	1		T45	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	507	1			T45	4		T38	17		T27	13
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	75	1			T10	2		T27	2		T28	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	472	1			T10	2		T27	76		T200	7
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	85	1			T37	2		T36	1		T27	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	313	1			T37	3		T36	4		T27	19
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	80	1			T42	2		T38	2		T167	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	545	1			T38	15		T167	45		T163	49
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	70	1			T10	1		T42	2		T38	4
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	402	1			T10	2		T38	25		T141	2

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2099520	1			T5	3259		T6	1		T8	14782
auto[0]	auto[0]	auto[1]	763056	1			T5	1		T8	3		T13	5732
auto[0]	auto[1]	auto[0]	467857	1			T5	2417		T8	1012		T10	1487
auto[0]	auto[1]	auto[1]	3251	1			T5	1		T10	1		T74	170
auto[1]	auto[0]	auto[0]	33766	1			T5	79		T8	124		T10	10
auto[1]	auto[0]	auto[1]	557	1			T8	3		T10	1		T37	3
auto[1]	auto[1]	auto[0]	4038	1			T5	104		T10	8		T37	23
auto[1]	auto[1]	auto[1]	122	1			T37	2		T42	2		T40	1