Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3147383	1			T2	1		T3	1		T4	1119
all_pins[1]	3147383	1			T2	1		T3	1		T4	1119
all_pins[2]	3147383	1			T2	1		T3	1		T4	1119
all_pins[3]	3147383	1			T2	1		T3	1		T4	1119
all_pins[4]	3147383	1			T2	1		T3	1		T4	1119
all_pins[5]	3147383	1			T2	1		T3	1		T4	1119
all_pins[6]	3147383	1			T2	1		T3	1		T4	1119
all_pins[7]	3147383	1			T2	1		T3	1		T4	1119

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	25074460	1			T2	8		T3	8		T4	8952
values[0x1]	104604	1			T21	21		T26	29		T27	23
transitions[0x0=>0x1]	103002	1			T21	16		T26	22		T27	19
transitions[0x1=>0x0]	103019	1			T21	16		T26	22		T27	19

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3146738	1			T2	1		T3	1		T4	1119
all_pins[0]	values[0x1]	645	1			T21	4		T26	3		T27	4
all_pins[0]	transitions[0x0=>0x1]	486	1			T21	4		T26	3		T27	3
all_pins[0]	transitions[0x1=>0x0]	356	1			T21	2		T26	1		T27	5
all_pins[1]	values[0x0]	3146868	1			T2	1		T3	1		T4	1119
all_pins[1]	values[0x1]	515	1			T21	2		T26	1		T27	6
all_pins[1]	transitions[0x0=>0x1]	365	1			T21	1		T26	1		T27	6
all_pins[1]	transitions[0x1=>0x0]	167	1			T21	2		T26	6		T27	1
all_pins[2]	values[0x0]	3147066	1			T2	1		T3	1		T4	1119
all_pins[2]	values[0x1]	317	1			T21	3		T26	6		T27	1
all_pins[2]	transitions[0x0=>0x1]	263	1			T21	1		T26	6		T27	1
all_pins[2]	transitions[0x1=>0x0]	153	1			T21	3		T26	3		T27	2
all_pins[3]	values[0x0]	3147176	1			T2	1		T3	1		T4	1119
all_pins[3]	values[0x1]	207	1			T21	5		T26	3		T27	2
all_pins[3]	transitions[0x0=>0x1]	154	1			T21	4		T26	1		T27	1
all_pins[3]	transitions[0x1=>0x0]	142	1			T21	2		T26	1		T28	1
all_pins[4]	values[0x0]	3147188	1			T2	1		T3	1		T4	1119
all_pins[4]	values[0x1]	195	1			T21	3		T26	3		T27	1
all_pins[4]	transitions[0x0=>0x1]	157	1			T21	2		T26	2		T27	1
all_pins[4]	transitions[0x1=>0x0]	2091	1			T26	1		T27	4		T28	337
all_pins[5]	values[0x0]	3145254	1			T2	1		T3	1		T4	1119
all_pins[5]	values[0x1]	2129	1			T21	1		T26	2		T27	4
all_pins[5]	transitions[0x0=>0x1]	1114	1			T21	1		T26	2		T27	3
all_pins[5]	transitions[0x1=>0x0]	99344	1			T21	1		T26	5		T27	1
all_pins[6]	values[0x0]	3047024	1			T2	1		T3	1		T4	1119
all_pins[6]	values[0x1]	100359	1			T21	1		T26	5		T27	2
all_pins[6]	transitions[0x0=>0x1]	100290	1			T21	1		T26	2		T27	1
all_pins[6]	transitions[0x1=>0x0]	168	1			T21	2		T26	3		T27	2
all_pins[7]	values[0x0]	3147146	1			T2	1		T3	1		T4	1119
all_pins[7]	values[0x1]	237	1			T21	2		T26	6		T27	3
all_pins[7]	transitions[0x0=>0x1]	173	1			T21	2		T26	5		T27	3
all_pins[7]	transitions[0x1=>0x0]	598	1			T21	4		T26	2		T27	4