Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17743

1

T5

195

T8

186

T13

8

auto[1]

12328

1

T5

68

T8

141

T16

16

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3869	1			T5	115		T8	20		T17	4
values[1]	3310	1			T8	63		T20	53		T37	57
values[2]	3751	1			T16	16		T37	60		T42	20
values[3]	4189	1			T8	164		T37	44		T46	20
values[4]	3808	1			T37	21		T42	40		T43	21
values[5]	3785	1			T5	58		T8	20		T19	4
values[6]	3535	1			T5	70		T8	40		T41	20
values[7]	3824	1			T5	20		T8	20		T13	8

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3469	1			T5	115		T16	16		T161	4
values[1]	4707	1			T8	40		T75	6		T26	46
values[2]	3278	1			T8	60		T13	8		T19	4
values[3]	3421	1			T8	88		T17	4		T37	58
values[4]	3880	1			T5	128		T37	66		T42	20
values[5]	3748	1			T5	20		T41	20		T37	60
values[6]	3451	1			T8	20		T37	20		T42	20
values[7]	4117	1			T8	119		T20	53		T37	74

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	337	1			T5	106		T168	14		T160	30
auto[0]	values[0]	values[1]	378	1			T8	12		T75	6		T33	34
auto[0]	values[0]	values[2]	290	1			T42	16		T44	7		T33	10
auto[0]	values[0]	values[3]	303	1			T17	4		T46	10		T182	8
auto[0]	values[0]	values[4]	313	1			T28	16		T153	33		T201	16
auto[0]	values[0]	values[5]	330	1			T29	14		T202	2		T167	29
auto[0]	values[0]	values[6]	163	1			T44	9		T188	11		T203	9
auto[0]	values[0]	values[7]	198	1			T47	13		T29	28		T157	25
auto[0]	values[1]	values[0]	205	1			T26	10		T45	41		T28	17
auto[0]	values[1]	values[1]	251	1			T47	12		T167	10		T168	9
auto[0]	values[1]	values[2]	227	1			T8	10		T37	15		T47	14
auto[0]	values[1]	values[3]	149	1			T37	15		T153	12		T191	10
auto[0]	values[1]	values[4]	173	1			T43	30		T29	12		T204	8
auto[0]	values[1]	values[5]	326	1			T131	17		T162	13		T188	6
auto[0]	values[1]	values[6]	177	1			T74	14		T166	78		T186	10
auto[0]	values[1]	values[7]	381	1			T8	9		T20	53		T43	28
auto[0]	values[2]	values[0]	175	1			T46	10		T186	13		T205	20
auto[0]	values[2]	values[1]	369	1			T26	9		T46	10		T206	18
auto[0]	values[2]	values[2]	234	1			T26	14		T44	5		T52	6
auto[0]	values[2]	values[3]	377	1			T43	13		T46	23		T47	14
auto[0]	values[2]	values[4]	290	1			T26	10		T131	14		T186	14
auto[0]	values[2]	values[5]	247	1			T37	29		T42	8		T47	12
auto[0]	values[2]	values[6]	292	1			T37	9		T185	6		T207	12
auto[0]	values[2]	values[7]	161	1			T29	15		T208	6		T188	18
auto[0]	values[3]	values[0]	178	1			T29	12		T153	13		T167	10
auto[0]	values[3]	values[1]	359	1			T8	13		T47	10		T167	21
auto[0]	values[3]	values[2]	326	1			T37	14		T46	7		T28	16
auto[0]	values[3]	values[3]	278	1			T8	82		T209	18		T210	12
auto[0]	values[3]	values[4]	302	1			T55	20		T168	9		T162	13
auto[0]	values[3]	values[5]	313	1			T33	27		T178	10		T211	2
auto[0]	values[3]	values[6]	259	1			T28	23		T189	12		T167	12
auto[0]	values[3]	values[7]	379	1			T8	6		T37	12		T153	19
auto[0]	values[4]	values[0]	228	1			T182	5		T186	11		T191	13
auto[0]	values[4]	values[1]	477	1			T28	9		T168	17		T179	101
auto[0]	values[4]	values[2]	144	1			T47	9		T168	11		T188	11
auto[0]	values[4]	values[3]	261	1			T47	9		T29	24		T153	12
auto[0]	values[4]	values[4]	376	1			T37	11		T42	11		T182	14
auto[0]	values[4]	values[5]	284	1			T45	14		T186	20		T194	13
auto[0]	values[4]	values[6]	253	1			T42	14		T43	9		T153	16
auto[0]	values[4]	values[7]	418	1			T97	6		T45	32		T28	12
auto[0]	values[5]	values[0]	388	1			T188	10		T157	17		T212	20
auto[0]	values[5]	values[1]	290	1			T26	11		T29	7		T33	16
auto[0]	values[5]	values[2]	231	1			T19	4		T37	47		T166	68
auto[0]	values[5]	values[3]	234	1			T213	10		T192	10		T158	13
auto[0]	values[5]	values[4]	331	1			T5	10		T43	12		T44	13
auto[0]	values[5]	values[5]	221	1			T43	15		T28	11		T187	8
auto[0]	values[5]	values[6]	417	1			T8	13		T28	14		T188	19
auto[0]	values[5]	values[7]	190	1			T214	16		T166	39		T203	10
auto[0]	values[6]	values[0]	212	1			T161	4		T215	2		T47	8
auto[0]	values[6]	values[1]	177	1			T153	12		T168	13		T176	10
auto[0]	values[6]	values[2]	223	1			T8	29		T168	10		T188	13
auto[0]	values[6]	values[3]	354	1			T42	10		T43	10		T45	111
auto[0]	values[6]	values[4]	271	1			T5	62		T26	7		T29	11
auto[0]	values[6]	values[5]	183	1			T41	20		T37	12		T157	13
auto[0]	values[6]	values[6]	334	1			T179	8		T166	20		T186	13
auto[0]	values[6]	values[7]	278	1			T46	7		T47	19		T29	10
auto[0]	values[7]	values[0]	187	1			T43	15		T44	10		T29	15
auto[0]	values[7]	values[1]	431	1			T193	10		T131	9		T166	98
auto[0]	values[7]	values[2]	283	1			T13	8		T37	10		T47	9
auto[0]	values[7]	values[3]	181	1			T37	18		T169	2		T46	7
auto[0]	values[7]	values[4]	227	1			T37	35		T45	7		T29	14
auto[0]	values[7]	values[5]	197	1			T5	17		T95	4		T216	6
auto[0]	values[7]	values[6]	259	1			T167	13		T179	26		T162	28
auto[0]	values[7]	values[7]	463	1			T8	12		T37	39		T29	11
auto[1]	values[0]	values[0]	134	1			T5	9		T168	6		T160	10
auto[1]	values[0]	values[1]	296	1			T8	8		T33	9		T182	13
auto[1]	values[0]	values[2]	251	1			T42	4		T44	13		T33	10
auto[1]	values[0]	values[3]	176	1			T46	10		T182	12		T131	10
auto[1]	values[0]	values[4]	155	1			T28	4		T153	19		T34	5
auto[1]	values[0]	values[5]	223	1			T29	9		T167	8		T179	12
auto[1]	values[0]	values[6]	113	1			T44	11		T188	9		T203	11
auto[1]	values[0]	values[7]	209	1			T47	10		T29	12		T157	15
auto[1]	values[1]	values[0]	143	1			T26	10		T45	26		T28	3
auto[1]	values[1]	values[1]	349	1			T47	14		T167	10		T168	11
auto[1]	values[1]	values[2]	219	1			T8	10		T37	8		T80	8
auto[1]	values[1]	values[3]	128	1			T37	19		T153	8		T191	10
auto[1]	values[1]	values[4]	85	1			T43	14		T29	8		T168	11
auto[1]	values[1]	values[5]	172	1			T131	9		T162	7		T188	14
auto[1]	values[1]	values[6]	58	1			T166	3		T186	16		T184	5
auto[1]	values[1]	values[7]	267	1			T8	34		T43	12		T29	8
auto[1]	values[2]	values[0]	230	1			T16	16		T46	10		T186	8
auto[1]	values[2]	values[1]	286	1			T26	14		T46	10		T217	8
auto[1]	values[2]	values[2]	145	1			T26	7		T44	17		T173	11
auto[1]	values[2]	values[3]	182	1			T43	10		T46	17		T47	6
auto[1]	values[2]	values[4]	213	1			T26	10		T131	6		T186	8
auto[1]	values[2]	values[5]	247	1			T37	11		T42	12		T47	8
auto[1]	values[2]	values[6]	179	1			T37	11		T172	10		T218	7
auto[1]	values[2]	values[7]	124	1			T29	5		T188	4		T199	29
auto[1]	values[3]	values[0]	289	1			T29	8		T153	27		T167	60
auto[1]	values[3]	values[1]	178	1			T8	7		T47	10		T167	19
auto[1]	values[3]	values[2]	215	1			T37	10		T46	13		T28	4
auto[1]	values[3]	values[3]	160	1			T8	6		T210	8		T219	13
auto[1]	values[3]	values[4]	332	1			T168	11		T162	7		T160	20
auto[1]	values[3]	values[5]	236	1			T33	7		T162	15		T203	8
auto[1]	values[3]	values[6]	151	1			T28	17		T167	8		T166	47
auto[1]	values[3]	values[7]	234	1			T8	50		T37	8		T153	37
auto[1]	values[4]	values[0]	212	1			T182	15		T186	9		T191	7
auto[1]	values[4]	values[1]	226	1			T28	20		T168	3		T179	10
auto[1]	values[4]	values[2]	173	1			T47	11		T168	9		T188	9
auto[1]	values[4]	values[3]	128	1			T47	11		T29	12		T153	9
auto[1]	values[4]	values[4]	130	1			T37	10		T42	9		T182	6
auto[1]	values[4]	values[5]	228	1			T45	12		T186	10		T194	7
auto[1]	values[4]	values[6]	99	1			T42	6		T43	12		T153	7
auto[1]	values[4]	values[7]	171	1			T45	7		T28	11		T213	8
auto[1]	values[5]	values[0]	246	1			T188	12		T157	3		T160	13
auto[1]	values[5]	values[1]	185	1			T26	12		T29	13		T33	6
auto[1]	values[5]	values[2]	85	1			T37	7		T166	16		T210	12
auto[1]	values[5]	values[3]	197	1			T213	14		T192	10		T158	40
auto[1]	values[5]	values[4]	397	1			T5	48		T43	9		T44	18
auto[1]	values[5]	values[5]	108	1			T43	8		T28	12		T157	12
auto[1]	values[5]	values[6]	172	1			T8	7		T28	6		T188	6
auto[1]	values[5]	values[7]	93	1			T166	3		T203	11		T172	10
auto[1]	values[6]	values[0]	180	1			T47	24		T179	35		T188	10
auto[1]	values[6]	values[1]	118	1			T153	24		T168	7		T176	10
auto[1]	values[6]	values[2]	122	1			T8	11		T168	10		T188	8
auto[1]	values[6]	values[3]	160	1			T42	10		T43	14		T45	11
auto[1]	values[6]	values[4]	151	1			T5	8		T26	13		T29	9
auto[1]	values[6]	values[5]	250	1			T37	8		T157	7		T186	14
auto[1]	values[6]	values[6]	268	1			T179	12		T159	8		T166	20
auto[1]	values[6]	values[7]	254	1			T46	13		T47	4		T29	11
auto[1]	values[7]	values[0]	125	1			T43	5		T44	12		T29	5
auto[1]	values[7]	values[1]	337	1			T131	11		T166	6		T157	12
auto[1]	values[7]	values[2]	110	1			T37	10		T47	11		T153	8
auto[1]	values[7]	values[3]	153	1			T37	6		T46	13		T186	4
auto[1]	values[7]	values[4]	134	1			T37	10		T45	14		T29	15
auto[1]	values[7]	values[5]	183	1			T5	3		T168	6		T195	5
auto[1]	values[7]	values[6]	257	1			T220	12		T167	77		T221	6
auto[1]	values[7]	values[7]	297	1			T8	8		T37	15		T29	48