Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	427	1			T8	1		T19	2		T37	9
auto[ReadAddrCrossIntoMailbox]	266	1			T8	3		T37	3		T42	2
auto[ReadAddrCrossOutOfMailbox]	354	1			T8	1		T37	5		T42	2
auto[ReadAddrCrossAllMailbox]	236	1			T8	2		T19	2		T42	2
auto[ReadAddrOutsideMailbox]	3570	1			T5	19		T8	32		T16	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2356

1

T5

14

T8

18

T16

1

auto[1]

2497

1

T5

5

T8

21

T16

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	800	1			T5	4		T8	7		T20	4
read_ops[0x0b]	824	1			T5	1		T8	7		T41	2
read_ops[0x3b]	838	1			T5	3		T8	7		T37	14
read_ops[0x6b]	751	1			T5	2		T8	3		T16	2
read_ops[0xbb]	796	1			T5	4		T8	9		T41	4
read_ops[0xeb]	844	1			T5	5		T8	6		T19	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T42	1		T167	1		T223	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T37	1		T46	1		T47	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T37	1		T46	1		T28	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	14	1			T45	1		T158	1		T224	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	36	1			T37	1		T26	1		T182	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	38	1			T42	1		T29	1		T200	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T182	1		T157	1		T34	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T44	2		T28	1		T29	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	284	1			T5	4		T8	4		T20	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	318	1			T8	3		T20	2		T37	5
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T37	2		T26	1		T43	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T37	2		T29	1		T185	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T8	1		T186	3		T191	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T42	1		T43	1		T44	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T26	1		T46	1		T28	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T45	1		T29	1		T167	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T26	2		T43	1		T157	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T168	1		T179	1		T166	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	297	1			T5	1		T8	1		T41	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	329	1			T8	5		T41	1		T37	6
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T26	1		T46	2		T28	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T8	1		T37	1		T26	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T46	1		T29	2		T189	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T37	1		T153	1		T33	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T44	1		T157	1		T186	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T8	1		T37	1		T182	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T153	1		T189	3		T194	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	26	1			T44	2		T189	3		T188	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	307	1			T5	1		T8	4		T37	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	312	1			T5	2		T8	1		T37	9
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T26	1		T182	1		T223	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T37	1		T43	1		T153	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T42	1		T213	1		T157	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T29	1		T157	1		T160	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T42	1		T168	1		T179	3
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T37	1		T44	1		T33	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	10	1			T19	1		T29	1		T131	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T19	1		T153	1		T168	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	280	1			T5	2		T16	1		T41	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	281	1			T8	3		T16	1		T41	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T43	1		T55	1		T47	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T55	1		T29	1		T185	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T47	2		T153	1		T189	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T8	1		T29	1		T153	4
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	36	1			T37	1		T47	1		T153	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T46	1		T28	2		T29	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T153	1		T179	2		T166	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T8	1		T42	1		T44	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	271	1			T5	3		T8	4		T41	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	279	1			T5	1		T8	3		T41	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T19	1		T37	2		T26	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	50	1			T19	1		T26	1		T55	3
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T8	1		T44	1		T153	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T37	1		T167	1		T157	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T37	1		T47	2		T200	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T26	1		T168	1		T186	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	26	1			T44	1		T28	1		T200	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T8	1		T42	1		T131	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	287	1			T5	3		T8	3		T41	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	325	1			T5	2		T8	1		T41	3