Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3797	1			T8	108		T16	16		T19	4
values[1]	4195	1			T8	56		T42	40		T161	4
values[2]	3346	1			T5	20		T8	80		T37	98
values[3]	3240	1			T5	70		T41	20		T37	45
values[4]	3904	1			T37	44		T215	2		T43	20
values[5]	3890	1			T5	115		T8	20		T13	8
values[6]	3804	1			T8	20		T37	57		T42	20
values[7]	3895	1			T5	58		T8	43		T17	4

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3395	1			T8	88		T41	20		T37	88
values[1]	3519	1			T16	16		T43	21		T44	42
values[2]	4481	1			T5	128		T8	43		T17	4
values[3]	4243	1			T37	84		T42	40		T161	4
values[4]	3088	1			T8	80		T19	4		T37	21
values[5]	3866	1			T5	135		T8	20		T13	8
values[6]	3680	1			T8	40		T37	34		T42	20
values[7]	3799	1			T8	56		T20	53		T37	65

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29292

1

T5

260

T8

318

T13

8

auto[1]

779

1

T5

3

T8

9

T37

9

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	446	1			T8	86		T45	21		T182	18
auto[0]	values[0]	values[1]	375	1			T16	16		T45	52		T225	16
auto[0]	values[0]	values[2]	441	1			T47	20		T29	28		T33	20
auto[0]	values[0]	values[3]	566	1			T37	20		T226	10		T168	37
auto[0]	values[0]	values[4]	545	1			T8	20		T19	4		T37	20
auto[0]	values[0]	values[5]	318	1			T29	20		T182	20		T192	19
auto[0]	values[0]	values[6]	303	1			T43	20		T223	6		T168	18
auto[0]	values[0]	values[7]	702	1			T47	20		T29	23		T162	19
auto[0]	values[1]	values[0]	412	1			T28	23		T181	6		T179	110
auto[0]	values[1]	values[1]	484	1			T45	44		T28	18		T153	36
auto[0]	values[1]	values[2]	658	1			T45	47		T167	190		T192	40
auto[0]	values[1]	values[3]	810	1			T42	19		T161	4		T202	2
auto[0]	values[1]	values[4]	281	1			T42	20		T46	20		T227	15
auto[0]	values[1]	values[5]	450	1			T80	8		T168	20		T166	64
auto[0]	values[1]	values[6]	517	1			T43	20		T46	17		T188	19
auto[0]	values[1]	values[7]	485	1			T8	56		T182	20		T228	12
auto[0]	values[2]	values[0]	404	1			T37	53		T46	16		T153	29
auto[0]	values[2]	values[1]	552	1			T153	20		T171	46		T168	20
auto[0]	values[2]	values[2]	473	1			T37	19		T26	20		T43	22
auto[0]	values[2]	values[3]	254	1			T37	23		T216	6		T157	20
auto[0]	values[2]	values[4]	388	1			T8	18		T167	20		T180	22
auto[0]	values[2]	values[5]	308	1			T5	20		T8	19		T187	8
auto[0]	values[2]	values[6]	389	1			T8	39		T75	6		T44	31
auto[0]	values[2]	values[7]	474	1			T43	20		T47	17		T168	18
auto[0]	values[3]	values[0]	219	1			T41	20		T213	19		T199	27
auto[0]	values[3]	values[1]	539	1			T43	19		T157	18		T160	21
auto[0]	values[3]	values[2]	511	1			T5	70		T47	31		T153	35
auto[0]	values[3]	values[3]	541	1			T95	4		T26	21		T28	28
auto[0]	values[3]	values[4]	410	1			T229	46		T230	20		T231	6
auto[0]	values[3]	values[5]	322	1			T29	20		T222	10		T191	20
auto[0]	values[3]	values[6]	377	1			T28	19		T153	21		T186	22
auto[0]	values[3]	values[7]	242	1			T37	43		T47	21		T196	22
auto[0]	values[4]	values[0]	354	1			T46	17		T47	20		T168	19
auto[0]	values[4]	values[1]	498	1			T200	71		T179	42		T232	20
auto[0]	values[4]	values[2]	716	1			T37	24		T215	2		T47	19
auto[0]	values[4]	values[3]	331	1			T43	20		T46	20		T29	20
auto[0]	values[4]	values[4]	457	1			T52	6		T47	20		T160	18
auto[0]	values[4]	values[5]	487	1			T47	20		T29	19		T207	12
auto[0]	values[4]	values[6]	394	1			T153	23		T233	16		T157	18
auto[0]	values[4]	values[7]	576	1			T37	20		T47	23		T200	20
auto[0]	values[5]	values[0]	478	1			T46	20		T29	101		T167	20
auto[0]	values[5]	values[1]	242	1			T44	20		T206	18		T168	20
auto[0]	values[5]	values[2]	572	1			T47	26		T29	20		T179	44
auto[0]	values[5]	values[3]	621	1			T46	20		T211	2		T188	25
auto[0]	values[5]	values[4]	232	1			T8	19		T55	20		T34	19
auto[0]	values[5]	values[5]	718	1			T5	112		T13	8		T37	19
auto[0]	values[5]	values[6]	509	1			T153	18		T168	20		T172	19
auto[0]	values[5]	values[7]	403	1			T28	18		T153	56		T33	40
auto[0]	values[6]	values[0]	377	1			T26	20		T33	22		T179	20
auto[0]	values[6]	values[1]	378	1			T162	60		T157	20		T203	25
auto[0]	values[6]	values[2]	501	1			T26	20		T167	48		T208	6
auto[0]	values[6]	values[3]	357	1			T42	20		T97	6		T153	20
auto[0]	values[6]	values[4]	334	1			T8	20		T188	21		T194	20
auto[0]	values[6]	values[5]	789	1			T37	22		T26	23		T28	20
auto[0]	values[6]	values[6]	511	1			T37	34		T45	38		T153	23
auto[0]	values[6]	values[7]	462	1			T74	14		T43	24		T191	20
auto[0]	values[7]	values[0]	613	1			T37	33		T26	23		T43	20
auto[0]	values[7]	values[1]	359	1			T44	19		T28	20		T29	20
auto[0]	values[7]	values[2]	502	1			T5	58		T8	41		T17	4
auto[0]	values[7]	values[3]	656	1			T37	40		T28	21		T167	36
auto[0]	values[7]	values[4]	359	1			T43	45		T44	20		T46	18
auto[0]	values[7]	values[5]	377	1			T47	20		T200	28		T33	22
auto[0]	values[7]	values[6]	578	1			T42	18		T169	2		T29	36
auto[0]	values[7]	values[7]	355	1			T20	53		T186	26		T158	23
auto[1]	values[0]	values[0]	13	1			T8	2		T182	2		T157	2
auto[1]	values[0]	values[1]	11	1			T45	5		T234	2		T170	1
auto[1]	values[0]	values[2]	12	1			T29	1		T186	5		T192	2
auto[1]	values[0]	values[3]	14	1			T168	3		T179	1		T166	2
auto[1]	values[0]	values[4]	12	1			T37	1		T167	3		T179	1
auto[1]	values[0]	values[5]	7	1			T192	1		T219	1		T235	2
auto[1]	values[0]	values[6]	8	1			T168	2		T192	3		T236	1
auto[1]	values[0]	values[7]	24	1			T29	1		T162	1		T157	1
auto[1]	values[1]	values[0]	8	1			T179	1		T158	2		T237	2
auto[1]	values[1]	values[1]	10	1			T45	2		T28	2		T238	4
auto[1]	values[1]	values[2]	10	1			T167	2		T172	2		T237	2
auto[1]	values[1]	values[3]	17	1			T42	1		T166	2		T158	2
auto[1]	values[1]	values[4]	14	1			T177	2		T205	2		T170	3
auto[1]	values[1]	values[5]	7	1			T157	1		T239	2		T240	1
auto[1]	values[1]	values[6]	18	1			T43	1		T46	3		T188	1
auto[1]	values[1]	values[7]	14	1			T162	1		T34	1		T241	1
auto[1]	values[2]	values[0]	17	1			T37	1		T46	4		T213	1
auto[1]	values[2]	values[1]	9	1			T166	1		T241	1		T242	5
auto[1]	values[2]	values[2]	12	1			T37	1		T43	1		T158	2
auto[1]	values[2]	values[3]	13	1			T37	1		T192	2		T243	4
auto[1]	values[2]	values[4]	15	1			T8	2		T244	1		T245	1
auto[1]	values[2]	values[5]	9	1			T8	1		T131	1		T229	2
auto[1]	values[2]	values[6]	16	1			T8	1		T45	6		T28	1
auto[1]	values[2]	values[7]	13	1			T47	3		T168	2		T166	3
auto[1]	values[3]	values[0]	5	1			T213	3		T219	2		-	-
auto[1]	values[3]	values[1]	12	1			T43	2		T157	2		T160	1
auto[1]	values[3]	values[2]	14	1			T47	1		T153	1		T213	1
auto[1]	values[3]	values[3]	18	1			T28	1		T167	1		T179	1
auto[1]	values[3]	values[4]	6	1			T229	1		T246	1		T247	1
auto[1]	values[3]	values[5]	6	1			T203	3		T170	1		T248	2
auto[1]	values[3]	values[6]	8	1			T28	1		T186	1		T160	2
auto[1]	values[3]	values[7]	10	1			T37	2		T47	2		T192	1
auto[1]	values[4]	values[0]	12	1			T46	3		T168	1		T131	1
auto[1]	values[4]	values[1]	18	1			T179	4		T172	3		T249	2
auto[1]	values[4]	values[2]	14	1			T47	1		T203	2		T158	2
auto[1]	values[4]	values[3]	3	1			T237	2		T250	1		-	-
auto[1]	values[4]	values[4]	13	1			T160	4		T158	1		T199	1
auto[1]	values[4]	values[5]	16	1			T29	1		T158	2		T218	3
auto[1]	values[4]	values[6]	9	1			T157	2		T251	2		T252	2
auto[1]	values[4]	values[7]	6	1			T253	1		T254	2		T255	3
auto[1]	values[5]	values[0]	14	1			T29	2		T177	1		T237	2
auto[1]	values[5]	values[1]	8	1			T194	1		T203	2		T245	3
auto[1]	values[5]	values[2]	14	1			T179	2		T158	1		T249	1
auto[1]	values[5]	values[3]	16	1			T194	2		T219	1		T256	2
auto[1]	values[5]	values[4]	6	1			T8	1		T34	1		T195	1
auto[1]	values[5]	values[5]	19	1			T5	3		T37	1		T42	2
auto[1]	values[5]	values[6]	19	1			T153	2		T172	1		T224	2
auto[1]	values[5]	values[7]	19	1			T28	2		T33	3		T186	1
auto[1]	values[6]	values[0]	7	1			T131	2		T158	1		T257	2
auto[1]	values[6]	values[1]	16	1			T162	2		T203	1		T172	2
auto[1]	values[6]	values[2]	13	1			T34	2		T241	1		T135	3
auto[1]	values[6]	values[3]	14	1			T179	1		T235	1		T258	1
auto[1]	values[6]	values[4]	6	1			T188	1		T172	1		T240	3
auto[1]	values[6]	values[5]	20	1			T37	1		T213	1		T158	3
auto[1]	values[6]	values[6]	11	1			T45	1		T33	1		T186	3
auto[1]	values[6]	values[7]	8	1			T199	1		T259	1		T260	1
auto[1]	values[7]	values[0]	16	1			T37	1		T167	2		T186	4
auto[1]	values[7]	values[1]	8	1			T44	3		T235	1		T242	2
auto[1]	values[7]	values[2]	18	1			T8	2		T44	2		T168	2
auto[1]	values[7]	values[3]	12	1			T28	2		T167	1		T218	1
auto[1]	values[7]	values[4]	10	1			T43	2		T46	2		T174	1
auto[1]	values[7]	values[5]	13	1			T33	1		T166	4		T199	5
auto[1]	values[7]	values[6]	13	1			T42	2		T33	1		T135	2
auto[1]	values[7]	values[7]	6	1			T158	1		T260	2		T154	1