| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 8 | 0 | 8 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_flip_position | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
| cp_opcode | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| auto[0] | 69 | 1 | T119 | 2 | T261 | 1 | T262 | 2 | ||||
| auto[1] | 24 | 1 | T119 | 1 | T262 | 1 | T263 | 1 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 6 | 0 | 6 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| read_ops[0x03] | 34 | 1 | T262 | 3 | T264 | 4 | T265 | 2 | ||||
| read_ops[0x0b] | 13 | 1 | T266 | 1 | T267 | 2 | T268 | 10 | ||||
| read_ops[0x3b] | 8 | 1 | T263 | 1 | T267 | 4 | T269 | 2 | ||||
| read_ops[0x6b] | 8 | 1 | T270 | 2 | T268 | 2 | T271 | 4 | ||||
| read_ops[0xbb] | 21 | 1 | T264 | 2 | T272 | 2 | T273 | 1 | ||||
| read_ops[0xeb] | 9 | 1 | T119 | 3 | T261 | 1 | T263 | 1 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |