Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	868	1			T21	11		T26	14		T27	14
all_values[1]	868	1			T21	11		T26	14		T27	14
all_values[2]	868	1			T21	11		T26	14		T27	14
all_values[3]	868	1			T21	11		T26	14		T27	14
all_values[4]	868	1			T21	11		T26	14		T27	14
all_values[5]	868	1			T21	11		T26	14		T27	14
all_values[6]	868	1			T21	11		T26	14		T27	14
all_values[7]	868	1			T21	11		T26	14		T27	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3733

1

T21

52

T26

67

T27

55

auto[1]

3211

1

T21

36

T26

45

T27

57

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2769

1

T21

40

T26

35

T27

57

auto[1]

4175

1

T21

48

T26

77

T27

55

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3958

1

T21

56

T26

61

T27

65

auto[1]

2986

1

T21

32

T26

51

T27

47

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	167	1			T21	2		T26	1		T27	1
all_values[0]	auto[0]	auto[0]	auto[1]	94	1			T21	2		T26	5		T27	1
all_values[0]	auto[0]	auto[1]	auto[0]	162	1			T21	1		T27	3		T28	2
all_values[0]	auto[0]	auto[1]	auto[1]	75	1			T21	1		T26	1		T27	1
all_values[0]	auto[1]	auto[0]	auto[1]	206	1			T21	3		T26	5		T27	3
all_values[0]	auto[1]	auto[1]	auto[1]	164	1			T21	2		T26	2		T27	5
all_values[1]	auto[0]	auto[0]	auto[0]	197	1			T21	5		T26	5		T27	3
all_values[1]	auto[0]	auto[0]	auto[1]	80	1			T21	2		T26	2		T28	3
all_values[1]	auto[0]	auto[1]	auto[0]	157	1			T21	1		T26	4		T27	2
all_values[1]	auto[0]	auto[1]	auto[1]	76	1			T27	1		T29	2		T31	1
all_values[1]	auto[1]	auto[0]	auto[1]	187	1			T21	1		T26	3		T27	3
all_values[1]	auto[1]	auto[1]	auto[1]	171	1			T21	2		T27	5		T28	2
all_values[2]	auto[0]	auto[0]	auto[0]	162	1			T21	2		T26	1		T27	4
all_values[2]	auto[0]	auto[0]	auto[1]	90	1			T21	1		T26	1		T27	1
all_values[2]	auto[0]	auto[1]	auto[0]	141	1			T21	2		T26	2		T27	2
all_values[2]	auto[0]	auto[1]	auto[1]	91	1			T21	1		T26	4		T28	2
all_values[2]	auto[1]	auto[0]	auto[1]	217	1			T21	3		T26	2		T27	4
all_values[2]	auto[1]	auto[1]	auto[1]	167	1			T21	2		T26	4		T27	3
all_values[3]	auto[0]	auto[0]	auto[0]	172	1			T26	2		T27	3		T28	4
all_values[3]	auto[0]	auto[0]	auto[1]	93	1			T26	3		T28	3		T29	2
all_values[3]	auto[0]	auto[1]	auto[0]	141	1			T21	2		T26	1		T27	5
all_values[3]	auto[0]	auto[1]	auto[1]	77	1			T21	3		T27	1		T29	2
all_values[3]	auto[1]	auto[0]	auto[1]	215	1			T21	4		T26	4		T27	3
all_values[3]	auto[1]	auto[1]	auto[1]	170	1			T21	2		T26	4		T27	2
all_values[4]	auto[0]	auto[0]	auto[0]	194	1			T21	2		T26	2		T27	8
all_values[4]	auto[0]	auto[0]	auto[1]	91	1			T26	2		T28	1		T29	1
all_values[4]	auto[0]	auto[1]	auto[0]	135	1			T21	4		T26	3		T27	2
all_values[4]	auto[0]	auto[1]	auto[1]	75	1			T21	1		T28	1		T29	1
all_values[4]	auto[1]	auto[0]	auto[1]	219	1			T21	2		T26	5		T27	3
all_values[4]	auto[1]	auto[1]	auto[1]	154	1			T21	2		T26	2		T27	1
all_values[5]	auto[0]	auto[0]	auto[0]	263	1			T21	4		T26	6		T27	5
all_values[5]	auto[0]	auto[1]	auto[0]	255	1			T21	4		T26	2		T27	5
all_values[5]	auto[1]	auto[0]	auto[1]	196	1			T21	3		T26	5		T28	3
all_values[5]	auto[1]	auto[1]	auto[1]	154	1			T26	1		T27	4		T28	4
all_values[6]	auto[0]	auto[0]	auto[0]	153	1			T21	5		T26	1		T27	2
all_values[6]	auto[0]	auto[0]	auto[1]	85	1			T21	1		T27	2		T28	2
all_values[6]	auto[0]	auto[1]	auto[0]	157	1			T21	3		T26	2		T27	3
all_values[6]	auto[0]	auto[1]	auto[1]	84	1			T26	2		T28	2		T29	2
all_values[6]	auto[1]	auto[0]	auto[1]	216	1			T21	1		T26	5		T27	1
all_values[6]	auto[1]	auto[1]	auto[1]	173	1			T21	1		T26	4		T27	6
all_values[7]	auto[0]	auto[0]	auto[0]	165	1			T21	3		T26	2		T27	6
all_values[7]	auto[0]	auto[0]	auto[1]	80	1			T21	3		T26	4		T29	2
all_values[7]	auto[0]	auto[1]	auto[0]	148	1			T26	1		T27	3		T28	2
all_values[7]	auto[0]	auto[1]	auto[1]	98	1			T21	1		T26	2		T27	1
all_values[7]	auto[1]	auto[0]	auto[1]	191	1			T21	3		T26	1		T27	2
all_values[7]	auto[1]	auto[1]	auto[1]	186	1			T21	1		T26	4		T27	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal