Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1752

1

T3

5

T4

9

T7

7

auto[1]

1733

1

T3

11

T4

8

T7

1

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1935

1

T4

13

T9

1

T10

11

auto[1]

1550

1

T3

16

T4

4

T7

8

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2749

1

T3

16

T4

16

T7

8

auto[1]

736

1

T4

1

T10

5

T24

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	693	1			T3	1		T4	3		T7	1
valid[1]	711	1			T3	6		T4	5		T10	1
valid[2]	706	1			T3	1		T4	3		T7	3
valid[3]	679	1			T3	5		T4	4		T7	2
valid[4]	696	1			T3	3		T4	2		T7	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	142	1			T4	1		T10	1		T40	1
auto[0]	auto[0]	valid[0]	auto[1]	128	1			T3	1		T7	1		T14	3
auto[0]	auto[0]	valid[1]	auto[0]	96	1			T4	1		T40	1		T44	1
auto[0]	auto[0]	valid[1]	auto[1]	170	1			T3	2		T4	1		T14	4
auto[0]	auto[0]	valid[2]	auto[0]	133	1			T4	3		T10	1		T37	1
auto[0]	auto[0]	valid[2]	auto[1]	148	1			T7	3		T10	3		T14	4
auto[0]	auto[0]	valid[3]	auto[0]	120	1			T4	1		T9	1		T26	1
auto[0]	auto[0]	valid[3]	auto[1]	156	1			T3	2		T7	2		T10	1
auto[0]	auto[0]	valid[4]	auto[0]	124	1			T4	1		T37	1		T40	2
auto[0]	auto[0]	valid[4]	auto[1]	165	1			T4	1		T7	1		T10	1
auto[0]	auto[1]	valid[0]	auto[0]	131	1			T4	2		T44	1		T138	4
auto[0]	auto[1]	valid[0]	auto[1]	151	1			T14	5		T35	1		T26	1
auto[0]	auto[1]	valid[1]	auto[0]	112	1			T4	1		T24	1		T37	1
auto[0]	auto[1]	valid[1]	auto[1]	177	1			T3	4		T4	2		T35	1
auto[0]	auto[1]	valid[2]	auto[0]	117	1			T10	3		T24	1		T36	1
auto[0]	auto[1]	valid[2]	auto[1]	150	1			T3	1		T14	8		T73	1
auto[0]	auto[1]	valid[3]	auto[0]	124	1			T4	2		T10	1		T35	1
auto[0]	auto[1]	valid[3]	auto[1]	152	1			T3	3		T10	1		T14	5
auto[0]	auto[1]	valid[4]	auto[0]	100	1			T37	1		T26	1		T43	1
auto[0]	auto[1]	valid[4]	auto[1]	153	1			T3	3		T7	1		T10	1
auto[1]	auto[0]	valid[0]	auto[0]	80	1			T10	1		T37	1		T36	1
auto[1]	auto[0]	valid[1]	auto[0]	78	1			T35	1		T36	2		T26	3
auto[1]	auto[0]	valid[2]	auto[0]	71	1			T24	1		T35	1		T44	1
auto[1]	auto[0]	valid[3]	auto[0]	57	1			T10	1		T33	1		T275	2
auto[1]	auto[0]	valid[4]	auto[0]	84	1			T37	1		T36	1		T96	1
auto[1]	auto[1]	valid[0]	auto[0]	61	1			T27	1		T47	1		T280	1
auto[1]	auto[1]	valid[1]	auto[0]	78	1			T10	1		T24	1		T36	1
auto[1]	auto[1]	valid[2]	auto[0]	87	1			T10	1		T37	2		T35	1
auto[1]	auto[1]	valid[3]	auto[0]	70	1			T4	1		T10	1		T24	2
auto[1]	auto[1]	valid[4]	auto[0]	70	1			T35	1		T44	2		T38	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal