Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49335

1

T4

349

T9

10

T10

394

auto[1]

17065

1

T3

240

T4

50

T7

8

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48323

1

T3

240

T4

276

T7

8

auto[1]

18077

1

T4

123

T9

3

T10

165

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34063	1			T3	141		T4	192		T7	8
others[1]	5533	1			T3	17		T4	34		T10	58
others[2]	5571	1			T3	16		T4	36		T10	32
others[3]	6497	1			T3	12		T4	40		T9	1
interest[1]	3690	1			T3	17		T4	27		T9	2
interest[4]	22453	1			T3	90		T4	120		T7	8
interest[64]	11046	1			T3	37		T4	70		T9	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15942	1			T4	105		T9	5		T10	116
auto[0]	auto[0]	others[1]	2536	1			T4	16		T10	23		T24	6
auto[0]	auto[0]	others[2]	2584	1			T4	20		T10	15		T23	1
auto[0]	auto[0]	others[3]	3117	1			T4	30		T10	25		T23	1
auto[0]	auto[0]	interest[1]	1803	1			T4	16		T9	2		T10	11
auto[0]	auto[0]	interest[4]	10518	1			T4	67		T9	1		T10	86
auto[0]	auto[0]	interest[64]	5276	1			T4	39		T10	39		T24	12
auto[0]	auto[1]	others[0]	8914	1			T3	141		T4	24		T7	8
auto[0]	auto[1]	others[1]	1401	1			T3	17		T4	7		T10	10
auto[0]	auto[1]	others[2]	1438	1			T3	16		T4	3		T10	10
auto[0]	auto[1]	others[3]	1600	1			T3	12		T4	3		T10	11
auto[0]	auto[1]	interest[1]	908	1			T3	17		T4	2		T10	7
auto[0]	auto[1]	interest[4]	5949	1			T3	90		T4	17		T7	8
auto[0]	auto[1]	interest[64]	2804	1			T3	37		T4	11		T10	16
auto[1]	auto[0]	others[0]	9207	1			T4	63		T9	1		T10	79
auto[1]	auto[0]	others[1]	1596	1			T4	11		T10	25		T24	9
auto[1]	auto[0]	others[2]	1549	1			T4	13		T10	7		T24	5
auto[1]	auto[0]	others[3]	1780	1			T4	7		T9	1		T10	20
auto[1]	auto[0]	interest[1]	979	1			T4	9		T10	4		T24	3
auto[1]	auto[0]	interest[4]	5986	1			T4	36		T10	52		T12	2
auto[1]	auto[0]	interest[64]	2966	1			T4	20		T9	1		T10	30

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal