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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1130
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T130 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1319328115 Jul 16 07:46:20 PM PDT 24 Jul 16 07:46:28 PM PDT 24 425183435 ps
T107 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2239563888 Jul 16 07:46:47 PM PDT 24 Jul 16 07:47:21 PM PDT 24 3680561703 ps
T1021 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3899274286 Jul 16 07:46:40 PM PDT 24 Jul 16 07:46:42 PM PDT 24 17609765 ps
T142 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1171498553 Jul 16 07:47:20 PM PDT 24 Jul 16 07:47:39 PM PDT 24 2170841169 ps
T1022 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2150614620 Jul 16 07:47:18 PM PDT 24 Jul 16 07:47:22 PM PDT 24 14080781 ps
T86 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1214251476 Jul 16 07:46:46 PM PDT 24 Jul 16 07:46:58 PM PDT 24 786610127 ps
T145 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.324805335 Jul 16 07:46:20 PM PDT 24 Jul 16 07:46:43 PM PDT 24 1604029392 ps
T143 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1716458159 Jul 16 07:46:50 PM PDT 24 Jul 16 07:47:04 PM PDT 24 214257009 ps
T149 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2722894665 Jul 16 07:46:51 PM PDT 24 Jul 16 07:47:15 PM PDT 24 5800951870 ps
T1023 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1314082654 Jul 16 07:47:16 PM PDT 24 Jul 16 07:47:19 PM PDT 24 14206738 ps
T1024 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1460343164 Jul 16 07:47:15 PM PDT 24 Jul 16 07:47:18 PM PDT 24 51268305 ps
T1025 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3143785070 Jul 16 07:47:16 PM PDT 24 Jul 16 07:47:19 PM PDT 24 48989852 ps
T90 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.84264045 Jul 16 07:47:02 PM PDT 24 Jul 16 07:47:08 PM PDT 24 255765768 ps
T1026 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2732924918 Jul 16 07:46:22 PM PDT 24 Jul 16 07:46:29 PM PDT 24 78894381 ps
T108 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.661672509 Jul 16 07:46:23 PM PDT 24 Jul 16 07:46:30 PM PDT 24 278649971 ps
T1027 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.4085285046 Jul 16 07:47:18 PM PDT 24 Jul 16 07:47:22 PM PDT 24 15998286 ps
T1028 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2818459337 Jul 16 07:46:43 PM PDT 24 Jul 16 07:46:48 PM PDT 24 77990427 ps
T1029 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4065975995 Jul 16 07:46:40 PM PDT 24 Jul 16 07:46:44 PM PDT 24 515259158 ps
T1030 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3857955661 Jul 16 07:46:46 PM PDT 24 Jul 16 07:46:53 PM PDT 24 15524209 ps
T1031 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1239676968 Jul 16 07:46:51 PM PDT 24 Jul 16 07:46:59 PM PDT 24 58920979 ps
T1032 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3891118631 Jul 16 07:46:47 PM PDT 24 Jul 16 07:46:54 PM PDT 24 11084366 ps
T1033 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3554331324 Jul 16 07:46:21 PM PDT 24 Jul 16 07:46:25 PM PDT 24 18748339 ps
T1034 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3044087773 Jul 16 07:46:45 PM PDT 24 Jul 16 07:46:52 PM PDT 24 115512957 ps
T1035 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1591702872 Jul 16 07:47:15 PM PDT 24 Jul 16 07:47:17 PM PDT 24 46293112 ps
T1036 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2382086163 Jul 16 07:46:40 PM PDT 24 Jul 16 07:46:46 PM PDT 24 398865353 ps
T146 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.714758930 Jul 16 07:46:42 PM PDT 24 Jul 16 07:47:02 PM PDT 24 737881947 ps
T1037 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1682195792 Jul 16 07:46:45 PM PDT 24 Jul 16 07:46:53 PM PDT 24 51745696 ps
T1038 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3010416358 Jul 16 07:46:45 PM PDT 24 Jul 16 07:46:53 PM PDT 24 496722566 ps
T1039 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2843745354 Jul 16 07:46:48 PM PDT 24 Jul 16 07:46:55 PM PDT 24 12961102 ps
T1040 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1345199513 Jul 16 07:46:20 PM PDT 24 Jul 16 07:46:31 PM PDT 24 1135963018 ps
T1041 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1990605293 Jul 16 07:47:15 PM PDT 24 Jul 16 07:47:18 PM PDT 24 14193557 ps
T1042 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2376284791 Jul 16 07:46:46 PM PDT 24 Jul 16 07:46:53 PM PDT 24 21539039 ps
T1043 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3230390532 Jul 16 07:46:22 PM PDT 24 Jul 16 07:46:27 PM PDT 24 11603329 ps
T1044 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.254929458 Jul 16 07:47:19 PM PDT 24 Jul 16 07:47:23 PM PDT 24 47828962 ps
T151 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.75406817 Jul 16 07:46:58 PM PDT 24 Jul 16 07:47:25 PM PDT 24 4679994071 ps
T150 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.296190048 Jul 16 07:46:48 PM PDT 24 Jul 16 07:47:02 PM PDT 24 455504854 ps
T109 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.986089877 Jul 16 07:46:52 PM PDT 24 Jul 16 07:46:59 PM PDT 24 127493079 ps
T1045 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.405139222 Jul 16 07:47:00 PM PDT 24 Jul 16 07:47:06 PM PDT 24 674811351 ps
T110 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3357528170 Jul 16 07:46:41 PM PDT 24 Jul 16 07:46:57 PM PDT 24 1228319037 ps
T1046 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3366852053 Jul 16 07:47:18 PM PDT 24 Jul 16 07:47:22 PM PDT 24 20734279 ps
T1047 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.616297356 Jul 16 07:47:19 PM PDT 24 Jul 16 07:47:24 PM PDT 24 25782106 ps
T1048 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3364791758 Jul 16 07:46:47 PM PDT 24 Jul 16 07:46:57 PM PDT 24 163189342 ps
T1049 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3739957223 Jul 16 07:46:47 PM PDT 24 Jul 16 07:47:06 PM PDT 24 3156281978 ps
T1050 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1925899512 Jul 16 07:47:20 PM PDT 24 Jul 16 07:47:24 PM PDT 24 51502182 ps
T1051 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.582545315 Jul 16 07:47:02 PM PDT 24 Jul 16 07:47:06 PM PDT 24 32659591 ps
T1052 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3220901221 Jul 16 07:46:46 PM PDT 24 Jul 16 07:46:54 PM PDT 24 105488135 ps
T1053 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.643352169 Jul 16 07:47:16 PM PDT 24 Jul 16 07:47:19 PM PDT 24 19459826 ps
T1054 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1101091127 Jul 16 07:46:40 PM PDT 24 Jul 16 07:46:44 PM PDT 24 193533034 ps
T1055 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1833292121 Jul 16 07:46:46 PM PDT 24 Jul 16 07:46:57 PM PDT 24 143344701 ps
T111 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2786759402 Jul 16 07:46:19 PM PDT 24 Jul 16 07:46:36 PM PDT 24 420334841 ps
T1056 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2858317168 Jul 16 07:46:49 PM PDT 24 Jul 16 07:47:02 PM PDT 24 3743988504 ps
T1057 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1108069472 Jul 16 07:47:15 PM PDT 24 Jul 16 07:47:18 PM PDT 24 11195956 ps
T1058 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.20644703 Jul 16 07:46:41 PM PDT 24 Jul 16 07:46:45 PM PDT 24 388477898 ps
T1059 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1905894704 Jul 16 07:46:41 PM PDT 24 Jul 16 07:46:46 PM PDT 24 159611745 ps
T1060 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1964587051 Jul 16 07:47:19 PM PDT 24 Jul 16 07:47:23 PM PDT 24 30588299 ps
T1061 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1206817025 Jul 16 07:46:39 PM PDT 24 Jul 16 07:46:43 PM PDT 24 144760404 ps
T1062 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.343402903 Jul 16 07:46:20 PM PDT 24 Jul 16 07:47:03 PM PDT 24 5523520295 ps
T144 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1611753076 Jul 16 07:46:45 PM PDT 24 Jul 16 07:46:57 PM PDT 24 359127319 ps
T1063 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2748816166 Jul 16 07:46:57 PM PDT 24 Jul 16 07:47:04 PM PDT 24 103658303 ps
T1064 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3400537457 Jul 16 07:47:20 PM PDT 24 Jul 16 07:47:24 PM PDT 24 26024930 ps
T1065 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2901558229 Jul 16 07:47:02 PM PDT 24 Jul 16 07:47:17 PM PDT 24 1327360102 ps
T1066 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1796546600 Jul 16 07:46:20 PM PDT 24 Jul 16 07:46:24 PM PDT 24 67742110 ps
T1067 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3928903029 Jul 16 07:46:47 PM PDT 24 Jul 16 07:46:58 PM PDT 24 264393354 ps
T147 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1012811633 Jul 16 07:46:49 PM PDT 24 Jul 16 07:47:02 PM PDT 24 363037823 ps
T1068 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1047242800 Jul 16 07:46:42 PM PDT 24 Jul 16 07:46:45 PM PDT 24 121921201 ps
T1069 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1912848959 Jul 16 07:46:41 PM PDT 24 Jul 16 07:46:47 PM PDT 24 51808216 ps
T1070 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1322056220 Jul 16 07:46:57 PM PDT 24 Jul 16 07:47:02 PM PDT 24 98185932 ps
T1071 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.399219313 Jul 16 07:46:58 PM PDT 24 Jul 16 07:47:05 PM PDT 24 80323614 ps
T1072 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.549487218 Jul 16 07:46:48 PM PDT 24 Jul 16 07:46:57 PM PDT 24 36862496 ps
T1073 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3630592844 Jul 16 07:46:42 PM PDT 24 Jul 16 07:46:46 PM PDT 24 197886811 ps
T1074 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.845884154 Jul 16 07:46:45 PM PDT 24 Jul 16 07:46:54 PM PDT 24 99373516 ps
T1075 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2258063814 Jul 16 07:46:22 PM PDT 24 Jul 16 07:46:27 PM PDT 24 210190640 ps
T1076 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.703899022 Jul 16 07:46:47 PM PDT 24 Jul 16 07:46:58 PM PDT 24 609440552 ps
T1077 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.946866284 Jul 16 07:47:16 PM PDT 24 Jul 16 07:47:19 PM PDT 24 50719796 ps
T1078 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3283953150 Jul 16 07:46:47 PM PDT 24 Jul 16 07:47:01 PM PDT 24 1184630946 ps
T1079 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.785031446 Jul 16 07:47:17 PM PDT 24 Jul 16 07:47:23 PM PDT 24 202436906 ps
T1080 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.738468315 Jul 16 07:46:19 PM PDT 24 Jul 16 07:46:22 PM PDT 24 15651900 ps
T1081 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3098790533 Jul 16 07:47:17 PM PDT 24 Jul 16 07:47:21 PM PDT 24 50784084 ps
T1082 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2391675670 Jul 16 07:46:57 PM PDT 24 Jul 16 07:47:04 PM PDT 24 203705858 ps
T1083 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1522564581 Jul 16 07:46:48 PM PDT 24 Jul 16 07:46:57 PM PDT 24 163492051 ps
T1084 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3327713796 Jul 16 07:46:41 PM PDT 24 Jul 16 07:46:43 PM PDT 24 11303469 ps
T1085 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3476143269 Jul 16 07:47:15 PM PDT 24 Jul 16 07:47:18 PM PDT 24 77452868 ps
T1086 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.339118918 Jul 16 07:46:42 PM PDT 24 Jul 16 07:46:47 PM PDT 24 75155694 ps
T1087 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1508544321 Jul 16 07:47:19 PM PDT 24 Jul 16 07:47:23 PM PDT 24 21199720 ps
T1088 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3197229407 Jul 16 07:46:45 PM PDT 24 Jul 16 07:46:55 PM PDT 24 2453255505 ps
T1089 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1640003183 Jul 16 07:46:45 PM PDT 24 Jul 16 07:46:51 PM PDT 24 52832314 ps
T1090 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3330836543 Jul 16 07:46:40 PM PDT 24 Jul 16 07:46:43 PM PDT 24 38726401 ps
T1091 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.633572775 Jul 16 07:47:16 PM PDT 24 Jul 16 07:47:18 PM PDT 24 24652542 ps
T1092 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2894598095 Jul 16 07:46:21 PM PDT 24 Jul 16 07:46:25 PM PDT 24 12893179 ps
T1093 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.667956969 Jul 16 07:47:19 PM PDT 24 Jul 16 07:47:29 PM PDT 24 213354497 ps
T1094 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3798817520 Jul 16 07:47:20 PM PDT 24 Jul 16 07:47:26 PM PDT 24 40961755 ps
T1095 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.4099054078 Jul 16 07:46:49 PM PDT 24 Jul 16 07:47:04 PM PDT 24 362551298 ps
T71 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1851906806 Jul 16 07:46:22 PM PDT 24 Jul 16 07:46:28 PM PDT 24 40200270 ps
T1096 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3294981319 Jul 16 07:47:18 PM PDT 24 Jul 16 07:47:23 PM PDT 24 25899054 ps
T1097 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2927408734 Jul 16 07:46:41 PM PDT 24 Jul 16 07:46:44 PM PDT 24 181117875 ps
T1098 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2574753114 Jul 16 07:46:47 PM PDT 24 Jul 16 07:46:56 PM PDT 24 85420471 ps
T1099 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4057007080 Jul 16 07:46:21 PM PDT 24 Jul 16 07:46:27 PM PDT 24 101663389 ps
T1100 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3026210484 Jul 16 07:47:18 PM PDT 24 Jul 16 07:47:25 PM PDT 24 262508353 ps
T1101 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2479112492 Jul 16 07:46:41 PM PDT 24 Jul 16 07:46:44 PM PDT 24 45574489 ps
T1102 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.799906981 Jul 16 07:46:21 PM PDT 24 Jul 16 07:46:29 PM PDT 24 391824878 ps
T1103 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2934559089 Jul 16 07:47:18 PM PDT 24 Jul 16 07:47:22 PM PDT 24 58770279 ps
T1104 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3324983258 Jul 16 07:46:21 PM PDT 24 Jul 16 07:46:26 PM PDT 24 100092365 ps
T1105 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1753279903 Jul 16 07:47:16 PM PDT 24 Jul 16 07:47:19 PM PDT 24 15770787 ps
T1106 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2020663809 Jul 16 07:46:45 PM PDT 24 Jul 16 07:46:53 PM PDT 24 86303900 ps
T1107 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1272645606 Jul 16 07:46:21 PM PDT 24 Jul 16 07:46:43 PM PDT 24 289582289 ps
T1108 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3287436500 Jul 16 07:46:51 PM PDT 24 Jul 16 07:47:00 PM PDT 24 80660835 ps
T72 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1512176226 Jul 16 07:46:45 PM PDT 24 Jul 16 07:46:51 PM PDT 24 158023538 ps
T1109 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1193763926 Jul 16 07:47:03 PM PDT 24 Jul 16 07:47:06 PM PDT 24 50588566 ps
T1110 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.4104224385 Jul 16 07:46:56 PM PDT 24 Jul 16 07:47:03 PM PDT 24 386214018 ps
T1111 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2258957923 Jul 16 07:46:47 PM PDT 24 Jul 16 07:46:54 PM PDT 24 39422663 ps
T1112 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3726737319 Jul 16 07:47:16 PM PDT 24 Jul 16 07:47:20 PM PDT 24 14431639 ps
T1113 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.4048049704 Jul 16 07:47:18 PM PDT 24 Jul 16 07:47:23 PM PDT 24 18697463 ps
T1114 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1148327721 Jul 16 07:46:22 PM PDT 24 Jul 16 07:46:28 PM PDT 24 750873081 ps
T1115 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2473859452 Jul 16 07:47:19 PM PDT 24 Jul 16 07:47:26 PM PDT 24 220145679 ps
T148 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2375500632 Jul 16 07:46:51 PM PDT 24 Jul 16 07:47:05 PM PDT 24 368014738 ps
T1116 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1844003555 Jul 16 07:46:46 PM PDT 24 Jul 16 07:46:53 PM PDT 24 82815325 ps
T1117 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3874025008 Jul 16 07:47:03 PM PDT 24 Jul 16 07:47:07 PM PDT 24 456326715 ps
T1118 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.407411830 Jul 16 07:47:17 PM PDT 24 Jul 16 07:47:20 PM PDT 24 20795261 ps
T1119 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3296118686 Jul 16 07:46:20 PM PDT 24 Jul 16 07:46:23 PM PDT 24 72432579 ps
T1120 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.525094335 Jul 16 07:47:19 PM PDT 24 Jul 16 07:47:23 PM PDT 24 16956233 ps
T1121 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.845582246 Jul 16 07:47:16 PM PDT 24 Jul 16 07:47:21 PM PDT 24 142029262 ps
T1122 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3597020971 Jul 16 07:46:31 PM PDT 24 Jul 16 07:46:33 PM PDT 24 23463114 ps
T1123 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.790698983 Jul 16 07:46:21 PM PDT 24 Jul 16 07:46:26 PM PDT 24 33246793 ps
T1124 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1730912792 Jul 16 07:47:14 PM PDT 24 Jul 16 07:47:15 PM PDT 24 25038507 ps
T1125 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3977967000 Jul 16 07:47:14 PM PDT 24 Jul 16 07:47:16 PM PDT 24 15895160 ps
T1126 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1187165133 Jul 16 07:47:17 PM PDT 24 Jul 16 07:47:21 PM PDT 24 49181786 ps
T1127 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3296661003 Jul 16 07:46:59 PM PDT 24 Jul 16 07:47:04 PM PDT 24 134378109 ps
T1128 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3561283048 Jul 16 07:46:47 PM PDT 24 Jul 16 07:46:54 PM PDT 24 603748377 ps
T1129 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3887418798 Jul 16 07:46:22 PM PDT 24 Jul 16 07:46:27 PM PDT 24 14050708 ps
T1130 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3991213139 Jul 16 07:46:43 PM PDT 24 Jul 16 07:46:50 PM PDT 24 1523836176 ps

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3058941067
Short name T10
Test name
Test status
Simulation time 76374191113 ps
CPU time 189.62 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:05:49 PM PDT 24
Peak memory 249288 kb
Host smart-8d540472-cec5-4013-b73c-3ca4eb6bfdaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058941067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.3058941067
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1453295532
Short name T8
Test name
Test status
Simulation time 140196874890 ps
CPU time 178.28 seconds
Started Jul 16 07:59:45 PM PDT 24
Finished Jul 16 08:02:46 PM PDT 24
Peak memory 257056 kb
Host smart-e28314e1-28a4-4145-bfb1-f78e29a83996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453295532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1453295532
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3196361338
Short name T29
Test name
Test status
Simulation time 21736931255 ps
CPU time 141.29 seconds
Started Jul 16 08:00:17 PM PDT 24
Finished Jul 16 08:02:41 PM PDT 24
Peak memory 269296 kb
Host smart-b158438c-e9b4-4fcf-8147-95971886f20e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196361338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3196361338
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1304677282
Short name T64
Test name
Test status
Simulation time 1079550055 ps
CPU time 22.14 seconds
Started Jul 16 07:46:47 PM PDT 24
Finished Jul 16 07:47:16 PM PDT 24
Peak memory 215964 kb
Host smart-5385bc1a-f9de-4849-84cc-dbaaafd3d660
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304677282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1304677282
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3031059035
Short name T28
Test name
Test status
Simulation time 186345522919 ps
CPU time 421.07 seconds
Started Jul 16 08:02:46 PM PDT 24
Finished Jul 16 08:09:56 PM PDT 24
Peak memory 265684 kb
Host smart-837e6a9a-7dc8-4b57-90fb-44fb12a88a71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031059035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3031059035
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.142880452
Short name T65
Test name
Test status
Simulation time 21406667 ps
CPU time 0.72 seconds
Started Jul 16 07:59:46 PM PDT 24
Finished Jul 16 07:59:50 PM PDT 24
Peak memory 216104 kb
Host smart-6926939e-ac9d-4617-8998-18d4a06ec449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142880452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.142880452
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1319484414
Short name T160
Test name
Test status
Simulation time 87288166679 ps
CPU time 829.18 seconds
Started Jul 16 08:02:28 PM PDT 24
Finished Jul 16 08:16:25 PM PDT 24
Peak memory 265660 kb
Host smart-6609138d-394c-4b9e-b9b0-290979565acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319484414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1319484414
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1045838628
Short name T37
Test name
Test status
Simulation time 483982150413 ps
CPU time 516.75 seconds
Started Jul 16 07:59:32 PM PDT 24
Finished Jul 16 08:08:10 PM PDT 24
Peak memory 263188 kb
Host smart-e172ace7-e655-43ec-9548-1071883c1b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045838628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1045838628
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1222647138
Short name T26
Test name
Test status
Simulation time 36526880306 ps
CPU time 356.45 seconds
Started Jul 16 08:02:40 PM PDT 24
Finished Jul 16 08:08:48 PM PDT 24
Peak memory 264876 kb
Host smart-5503f149-a843-4779-b4f6-0f5ce1931664
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222647138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1222647138
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2961998882
Short name T81
Test name
Test status
Simulation time 213557902 ps
CPU time 5.75 seconds
Started Jul 16 07:47:15 PM PDT 24
Finished Jul 16 07:47:22 PM PDT 24
Peak memory 216024 kb
Host smart-d86e4c32-6777-49eb-a034-8384079faff7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961998882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2961998882
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1015288194
Short name T186
Test name
Test status
Simulation time 86409005076 ps
CPU time 813.15 seconds
Started Jul 16 08:02:18 PM PDT 24
Finished Jul 16 08:15:57 PM PDT 24
Peak memory 269388 kb
Host smart-5f825480-984a-45ba-ac60-7645667c07ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015288194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1015288194
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3764007449
Short name T47
Test name
Test status
Simulation time 240540035823 ps
CPU time 473.92 seconds
Started Jul 16 08:00:34 PM PDT 24
Finished Jul 16 08:08:29 PM PDT 24
Peak memory 266192 kb
Host smart-24c51614-4540-4de5-a133-6a3429b775a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764007449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3764007449
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1098098241
Short name T1
Test name
Test status
Simulation time 126312102 ps
CPU time 0.96 seconds
Started Jul 16 07:59:34 PM PDT 24
Finished Jul 16 07:59:36 PM PDT 24
Peak memory 235900 kb
Host smart-87b041ce-243d-4f66-ac53-71e89663ca1c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098098241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1098098241
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.509332030
Short name T119
Test name
Test status
Simulation time 9662142769 ps
CPU time 13.11 seconds
Started Jul 16 08:00:01 PM PDT 24
Finished Jul 16 08:00:18 PM PDT 24
Peak memory 235036 kb
Host smart-02ac7f37-27e7-468e-8a80-457cbd769359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509332030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.509332030
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.693600537
Short name T34
Test name
Test status
Simulation time 128621683662 ps
CPU time 593.07 seconds
Started Jul 16 07:59:41 PM PDT 24
Finished Jul 16 08:09:35 PM PDT 24
Peak memory 257324 kb
Host smart-cb87420a-7018-4fd3-9358-17bc2c96560b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693600537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.693600537
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2135451203
Short name T172
Test name
Test status
Simulation time 122398111701 ps
CPU time 458.26 seconds
Started Jul 16 08:01:10 PM PDT 24
Finished Jul 16 08:08:51 PM PDT 24
Peak memory 265632 kb
Host smart-43eb2c76-3ded-468a-88db-76716fa0dd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135451203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2135451203
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1793992555
Short name T69
Test name
Test status
Simulation time 44119282 ps
CPU time 1.37 seconds
Started Jul 16 07:46:49 PM PDT 24
Finished Jul 16 07:46:57 PM PDT 24
Peak memory 216768 kb
Host smart-e02099e7-8750-4803-88af-6fb941a31ff8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793992555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1793992555
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.4288362363
Short name T158
Test name
Test status
Simulation time 93684459607 ps
CPU time 332.7 seconds
Started Jul 16 07:59:41 PM PDT 24
Finished Jul 16 08:05:15 PM PDT 24
Peak memory 289560 kb
Host smart-7fdb1d5e-6308-40d5-a554-94088379a678
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288362363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.4288362363
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1675019718
Short name T27
Test name
Test status
Simulation time 161033568893 ps
CPU time 361.99 seconds
Started Jul 16 08:00:02 PM PDT 24
Finished Jul 16 08:06:09 PM PDT 24
Peak memory 283004 kb
Host smart-c2798be8-bc80-4064-97a9-d38718b071ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675019718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1675019718
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.2263572850
Short name T157
Test name
Test status
Simulation time 20820582977 ps
CPU time 207.32 seconds
Started Jul 16 08:00:39 PM PDT 24
Finished Jul 16 08:04:09 PM PDT 24
Peak memory 249760 kb
Host smart-dd6d8f64-dd49-45c8-87be-5a79c38efdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263572850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.2263572850
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1699442371
Short name T203
Test name
Test status
Simulation time 336386646053 ps
CPU time 833.54 seconds
Started Jul 16 08:00:24 PM PDT 24
Finished Jul 16 08:14:20 PM PDT 24
Peak memory 287368 kb
Host smart-646521c9-cf59-4b2b-8466-042a11d29099
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699442371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1699442371
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.1375406709
Short name T154
Test name
Test status
Simulation time 8928216965 ps
CPU time 72.72 seconds
Started Jul 16 08:01:57 PM PDT 24
Finished Jul 16 08:03:10 PM PDT 24
Peak memory 265420 kb
Host smart-26db8117-581b-4ca2-bc90-cbb7d174bc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375406709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.1375406709
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2573543815
Short name T43
Test name
Test status
Simulation time 63626453568 ps
CPU time 591.63 seconds
Started Jul 16 08:02:16 PM PDT 24
Finished Jul 16 08:12:13 PM PDT 24
Peak memory 255720 kb
Host smart-9f708edd-f4ee-4904-ba6a-4a307cc6ff15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573543815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2573543815
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.1900674955
Short name T219
Test name
Test status
Simulation time 84677802330 ps
CPU time 326 seconds
Started Jul 16 07:59:44 PM PDT 24
Finished Jul 16 08:05:12 PM PDT 24
Peak memory 262916 kb
Host smart-16118327-1da2-4a14-8aad-560dc5d324de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900674955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.1900674955
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1952884012
Short name T59
Test name
Test status
Simulation time 17864764 ps
CPU time 0.75 seconds
Started Jul 16 08:00:27 PM PDT 24
Finished Jul 16 08:00:30 PM PDT 24
Peak memory 204996 kb
Host smart-197ac3f9-2b6e-4591-bc7f-9b6fa769a29b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952884012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1952884012
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1704117478
Short name T177
Test name
Test status
Simulation time 4893283668 ps
CPU time 74.32 seconds
Started Jul 16 08:00:01 PM PDT 24
Finished Jul 16 08:01:20 PM PDT 24
Peak memory 249216 kb
Host smart-6546d3c9-2153-4598-84bb-cd907e1b5551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704117478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1704117478
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.2240505479
Short name T192
Test name
Test status
Simulation time 51893082645 ps
CPU time 71.81 seconds
Started Jul 16 08:00:20 PM PDT 24
Finished Jul 16 08:01:35 PM PDT 24
Peak memory 252960 kb
Host smart-9b4f27b0-f0d6-4e6b-accc-b0102b4101e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240505479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.2240505479
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.590156421
Short name T247
Test name
Test status
Simulation time 99509168176 ps
CPU time 129.62 seconds
Started Jul 16 07:59:41 PM PDT 24
Finished Jul 16 08:01:51 PM PDT 24
Peak memory 254496 kb
Host smart-e8030488-c335-45cd-bb9f-b8d8c62d7d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590156421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.
590156421
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.885037243
Short name T267
Test name
Test status
Simulation time 5396678754 ps
CPU time 36.85 seconds
Started Jul 16 08:01:10 PM PDT 24
Finished Jul 16 08:01:49 PM PDT 24
Peak memory 240988 kb
Host smart-6441d6df-ae29-4c71-97a4-09c20cb1b1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885037243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.885037243
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2970271303
Short name T166
Test name
Test status
Simulation time 11768171788 ps
CPU time 153.66 seconds
Started Jul 16 07:59:42 PM PDT 24
Finished Jul 16 08:02:16 PM PDT 24
Peak memory 273492 kb
Host smart-004b2316-34ac-4664-a7a6-ee8fac7f0003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970271303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2970271303
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1195886321
Short name T62
Test name
Test status
Simulation time 761222586 ps
CPU time 13.6 seconds
Started Jul 16 07:46:58 PM PDT 24
Finished Jul 16 07:47:15 PM PDT 24
Peak memory 216160 kb
Host smart-00d5e01f-ccb3-45d0-87da-5b23aaf0534f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195886321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1195886321
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2282228289
Short name T235
Test name
Test status
Simulation time 143197945064 ps
CPU time 470.96 seconds
Started Jul 16 08:00:12 PM PDT 24
Finished Jul 16 08:08:05 PM PDT 24
Peak memory 287872 kb
Host smart-05c1be10-5b28-47bb-bc48-43556ff8f755
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282228289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2282228289
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.84264045
Short name T90
Test name
Test status
Simulation time 255765768 ps
CPU time 4.38 seconds
Started Jul 16 07:47:02 PM PDT 24
Finished Jul 16 07:47:08 PM PDT 24
Peak memory 215960 kb
Host smart-6c7693cc-c2e1-400d-b095-e86ba0cda168
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84264045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.84264045
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.4280416948
Short name T83
Test name
Test status
Simulation time 317555257 ps
CPU time 19.17 seconds
Started Jul 16 07:46:46 PM PDT 24
Finished Jul 16 07:47:11 PM PDT 24
Peak memory 215804 kb
Host smart-8f991796-08f4-4622-8098-e45f5ba5b45b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280416948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.4280416948
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1611753076
Short name T144
Test name
Test status
Simulation time 359127319 ps
CPU time 7.84 seconds
Started Jul 16 07:46:45 PM PDT 24
Finished Jul 16 07:46:57 PM PDT 24
Peak memory 215756 kb
Host smart-9e7ac3dd-08a2-41a7-834b-33e003d062a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611753076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1611753076
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2692059635
Short name T164
Test name
Test status
Simulation time 47304918357 ps
CPU time 441.74 seconds
Started Jul 16 07:59:27 PM PDT 24
Finished Jul 16 08:06:52 PM PDT 24
Peak memory 250292 kb
Host smart-cc1421b1-ed2f-4e40-8e31-25237ecd137a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692059635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2692059635
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.3689744616
Short name T698
Test name
Test status
Simulation time 36924703152 ps
CPU time 89.44 seconds
Started Jul 16 08:00:02 PM PDT 24
Finished Jul 16 08:01:36 PM PDT 24
Peak memory 251108 kb
Host smart-1774924e-e269-42c7-bde2-3caa77a43f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689744616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.3689744616
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.3354749979
Short name T260
Test name
Test status
Simulation time 159601224694 ps
CPU time 314.8 seconds
Started Jul 16 08:00:19 PM PDT 24
Finished Jul 16 08:05:36 PM PDT 24
Peak memory 252856 kb
Host smart-8a022c89-3d22-487c-bba6-990e1aa08816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354749979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.3354749979
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3432364485
Short name T255
Test name
Test status
Simulation time 58036713221 ps
CPU time 434.93 seconds
Started Jul 16 08:00:20 PM PDT 24
Finished Jul 16 08:07:39 PM PDT 24
Peak memory 268500 kb
Host smart-5290e675-96b0-4257-9c75-1dae877674de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432364485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3432364485
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.270910537
Short name T920
Test name
Test status
Simulation time 9182806541 ps
CPU time 134.34 seconds
Started Jul 16 08:00:33 PM PDT 24
Finished Jul 16 08:02:49 PM PDT 24
Peak memory 265896 kb
Host smart-dd711b5b-e5f8-43b7-8c14-51655257339f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270910537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.270910537
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1471431573
Short name T250
Test name
Test status
Simulation time 168739441639 ps
CPU time 126.8 seconds
Started Jul 16 08:00:36 PM PDT 24
Finished Jul 16 08:02:45 PM PDT 24
Peak memory 249796 kb
Host smart-07bb32ef-fbe1-409b-98af-f5353c9d744e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471431573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1471431573
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.4156655936
Short name T273
Test name
Test status
Simulation time 2077833721 ps
CPU time 32.51 seconds
Started Jul 16 08:00:56 PM PDT 24
Finished Jul 16 08:01:30 PM PDT 24
Peak memory 224432 kb
Host smart-b9276204-dac7-4bce-87cc-3604c5f0df67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156655936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.4156655936
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.4184928200
Short name T270
Test name
Test status
Simulation time 2845057707 ps
CPU time 10.86 seconds
Started Jul 16 08:02:15 PM PDT 24
Finished Jul 16 08:02:30 PM PDT 24
Peak memory 224600 kb
Host smart-9339a78e-95cd-4d0f-b449-4626ef257c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184928200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.4184928200
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3990894932
Short name T18
Test name
Test status
Simulation time 1613962763 ps
CPU time 6.26 seconds
Started Jul 16 07:59:51 PM PDT 24
Finished Jul 16 07:59:59 PM PDT 24
Peak memory 223068 kb
Host smart-e95b0f78-ac5c-4fb1-b8e5-e1c41c18a6da
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3990894932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3990894932
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3909914097
Short name T430
Test name
Test status
Simulation time 499825044 ps
CPU time 3 seconds
Started Jul 16 08:00:20 PM PDT 24
Finished Jul 16 08:00:27 PM PDT 24
Peak memory 224520 kb
Host smart-ccb3f613-99bc-47e5-a96f-e59c8f850876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909914097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3909914097
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3272835706
Short name T84
Test name
Test status
Simulation time 2156816888 ps
CPU time 4.98 seconds
Started Jul 16 07:46:51 PM PDT 24
Finished Jul 16 07:47:02 PM PDT 24
Peak memory 215956 kb
Host smart-769866be-9d6e-4135-b7fc-9b53fc8b2ea4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272835706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3272835706
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2192145348
Short name T204
Test name
Test status
Simulation time 185124214 ps
CPU time 5.61 seconds
Started Jul 16 07:59:33 PM PDT 24
Finished Jul 16 07:59:39 PM PDT 24
Peak memory 224356 kb
Host smart-d831ffaf-b45e-4074-a04a-a04f74092143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192145348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2192145348
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3867301088
Short name T70
Test name
Test status
Simulation time 18943683 ps
CPU time 1.13 seconds
Started Jul 16 07:46:21 PM PDT 24
Finished Jul 16 07:46:25 PM PDT 24
Peak memory 207516 kb
Host smart-f3aef378-6dd6-4f64-8848-aa32981c6482
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867301088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3867301088
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.896501594
Short name T104
Test name
Test status
Simulation time 2000988101 ps
CPU time 19.54 seconds
Started Jul 16 07:46:20 PM PDT 24
Finished Jul 16 07:46:42 PM PDT 24
Peak memory 215596 kb
Host smart-95af4194-3d55-4593-bfa3-023e21cf3c1b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896501594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.896501594
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1522343995
Short name T100
Test name
Test status
Simulation time 916009384 ps
CPU time 13.83 seconds
Started Jul 16 07:46:19 PM PDT 24
Finished Jul 16 07:46:35 PM PDT 24
Peak memory 207480 kb
Host smart-9932f60c-b6ad-4251-9fb3-1102adcef80a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522343995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1522343995
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3943495118
Short name T92
Test name
Test status
Simulation time 183949031 ps
CPU time 2.7 seconds
Started Jul 16 07:46:20 PM PDT 24
Finished Jul 16 07:46:26 PM PDT 24
Peak memory 218340 kb
Host smart-b890db54-d2b2-4746-8a1d-76f37ab351a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943495118 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3943495118
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1148327721
Short name T1114
Test name
Test status
Simulation time 750873081 ps
CPU time 2.77 seconds
Started Jul 16 07:46:22 PM PDT 24
Finished Jul 16 07:46:28 PM PDT 24
Peak memory 215732 kb
Host smart-29356bc7-2254-43fe-a4ca-f9d318de5698
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148327721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
148327721
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.738468315
Short name T1080
Test name
Test status
Simulation time 15651900 ps
CPU time 0.72 seconds
Started Jul 16 07:46:19 PM PDT 24
Finished Jul 16 07:46:22 PM PDT 24
Peak memory 204292 kb
Host smart-dd6ad50e-3a4e-4b44-a5d9-a00d609ee6e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738468315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.738468315
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.790698983
Short name T1123
Test name
Test status
Simulation time 33246793 ps
CPU time 1.27 seconds
Started Jul 16 07:46:21 PM PDT 24
Finished Jul 16 07:46:26 PM PDT 24
Peak memory 215796 kb
Host smart-f4562723-5689-4fb1-98f1-a6d42c87430f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790698983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.790698983
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2894598095
Short name T1092
Test name
Test status
Simulation time 12893179 ps
CPU time 0.66 seconds
Started Jul 16 07:46:21 PM PDT 24
Finished Jul 16 07:46:25 PM PDT 24
Peak memory 204096 kb
Host smart-9c1a2552-e52f-4095-9d7a-57f883104d5d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894598095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2894598095
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.799906981
Short name T1102
Test name
Test status
Simulation time 391824878 ps
CPU time 4.45 seconds
Started Jul 16 07:46:21 PM PDT 24
Finished Jul 16 07:46:29 PM PDT 24
Peak memory 215692 kb
Host smart-a54df929-02de-4d28-a3e1-14c69728f500
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799906981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.799906981
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1796546600
Short name T1066
Test name
Test status
Simulation time 67742110 ps
CPU time 1.39 seconds
Started Jul 16 07:46:20 PM PDT 24
Finished Jul 16 07:46:24 PM PDT 24
Peak memory 215876 kb
Host smart-f70625a3-92c6-4750-bedc-0802b877343d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796546600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
796546600
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1345199513
Short name T1040
Test name
Test status
Simulation time 1135963018 ps
CPU time 6.88 seconds
Started Jul 16 07:46:20 PM PDT 24
Finished Jul 16 07:46:31 PM PDT 24
Peak memory 215300 kb
Host smart-c534cc10-22fe-416a-bd84-9e9435b8e324
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345199513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1345199513
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2786759402
Short name T111
Test name
Test status
Simulation time 420334841 ps
CPU time 14.79 seconds
Started Jul 16 07:46:19 PM PDT 24
Finished Jul 16 07:46:36 PM PDT 24
Peak memory 207492 kb
Host smart-90ff0346-b326-4018-a21c-472e02b654e5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786759402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2786759402
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.343402903
Short name T1062
Test name
Test status
Simulation time 5523520295 ps
CPU time 39 seconds
Started Jul 16 07:46:20 PM PDT 24
Finished Jul 16 07:47:03 PM PDT 24
Peak memory 215404 kb
Host smart-52b12405-fac5-4ce7-9e00-a6f2935a9b3c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343402903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.343402903
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3296118686
Short name T1119
Test name
Test status
Simulation time 72432579 ps
CPU time 1.02 seconds
Started Jul 16 07:46:20 PM PDT 24
Finished Jul 16 07:46:23 PM PDT 24
Peak memory 207268 kb
Host smart-28539086-3fea-4f84-bfb7-ffeac982952b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296118686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3296118686
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2237798385
Short name T129
Test name
Test status
Simulation time 292428766 ps
CPU time 3.7 seconds
Started Jul 16 07:46:21 PM PDT 24
Finished Jul 16 07:46:29 PM PDT 24
Peak memory 217940 kb
Host smart-a346ef8d-e976-4556-8307-93a038113a6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237798385 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2237798385
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3324983258
Short name T1104
Test name
Test status
Simulation time 100092365 ps
CPU time 1.99 seconds
Started Jul 16 07:46:21 PM PDT 24
Finished Jul 16 07:46:26 PM PDT 24
Peak memory 207456 kb
Host smart-4b539aad-3160-4c78-b1d8-c269e77acf61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324983258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
324983258
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2258063814
Short name T1075
Test name
Test status
Simulation time 210190640 ps
CPU time 0.71 seconds
Started Jul 16 07:46:22 PM PDT 24
Finished Jul 16 07:46:27 PM PDT 24
Peak memory 204192 kb
Host smart-8aec4c6f-2e65-4c9f-b46a-bd34c24f0e9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258063814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
258063814
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4057007080
Short name T1099
Test name
Test status
Simulation time 101663389 ps
CPU time 2.17 seconds
Started Jul 16 07:46:21 PM PDT 24
Finished Jul 16 07:46:27 PM PDT 24
Peak memory 215784 kb
Host smart-3d44e606-691c-4171-9b3d-17fc0a0c02b8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057007080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.4057007080
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3230390532
Short name T1043
Test name
Test status
Simulation time 11603329 ps
CPU time 0.68 seconds
Started Jul 16 07:46:22 PM PDT 24
Finished Jul 16 07:46:27 PM PDT 24
Peak memory 204396 kb
Host smart-e5c9de85-9d94-4875-855c-37a6fe70e2bf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230390532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3230390532
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1319328115
Short name T130
Test name
Test status
Simulation time 425183435 ps
CPU time 4.24 seconds
Started Jul 16 07:46:20 PM PDT 24
Finished Jul 16 07:46:28 PM PDT 24
Peak memory 215716 kb
Host smart-e4bd0547-7f12-4201-b853-d455ee69be07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319328115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1319328115
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4078949527
Short name T88
Test name
Test status
Simulation time 173967625 ps
CPU time 4.06 seconds
Started Jul 16 07:46:19 PM PDT 24
Finished Jul 16 07:46:26 PM PDT 24
Peak memory 215944 kb
Host smart-35cab64f-ee42-40e4-ac19-c88d43e54f3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078949527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.4
078949527
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.324805335
Short name T145
Test name
Test status
Simulation time 1604029392 ps
CPU time 20.54 seconds
Started Jul 16 07:46:20 PM PDT 24
Finished Jul 16 07:46:43 PM PDT 24
Peak memory 215736 kb
Host smart-114b00e8-7e1c-4265-a3f9-6df6ac3e1c44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324805335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.324805335
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3928903029
Short name T1067
Test name
Test status
Simulation time 264393354 ps
CPU time 4.15 seconds
Started Jul 16 07:46:47 PM PDT 24
Finished Jul 16 07:46:58 PM PDT 24
Peak memory 217960 kb
Host smart-b8f72c80-8f3b-4935-b40d-99eb934c76e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928903029 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3928903029
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2359026215
Short name T103
Test name
Test status
Simulation time 30391970 ps
CPU time 1.87 seconds
Started Jul 16 07:46:48 PM PDT 24
Finished Jul 16 07:46:56 PM PDT 24
Peak memory 215668 kb
Host smart-a2e861ba-f4de-4e47-a7e0-31a673b9195c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359026215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2359026215
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3857955661
Short name T1030
Test name
Test status
Simulation time 15524209 ps
CPU time 0.71 seconds
Started Jul 16 07:46:46 PM PDT 24
Finished Jul 16 07:46:53 PM PDT 24
Peak memory 204248 kb
Host smart-8bbfa645-4bb7-4cd3-b97e-9265db2a8dc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857955661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3857955661
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3287436500
Short name T1108
Test name
Test status
Simulation time 80660835 ps
CPU time 2.57 seconds
Started Jul 16 07:46:51 PM PDT 24
Finished Jul 16 07:47:00 PM PDT 24
Peak memory 215724 kb
Host smart-132da0dc-5234-4e20-ba61-e6e5352a6aad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287436500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3287436500
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1910197984
Short name T87
Test name
Test status
Simulation time 273697166 ps
CPU time 2.27 seconds
Started Jul 16 07:46:50 PM PDT 24
Finished Jul 16 07:46:59 PM PDT 24
Peak memory 215996 kb
Host smart-18c26984-dba1-462d-8bbb-2d09e512b619
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910197984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1910197984
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1012811633
Short name T147
Test name
Test status
Simulation time 363037823 ps
CPU time 6.12 seconds
Started Jul 16 07:46:49 PM PDT 24
Finished Jul 16 07:47:02 PM PDT 24
Peak memory 215820 kb
Host smart-bae8c8a3-5b44-4aee-842d-8ae46d137c90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012811633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1012811633
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2574753114
Short name T1098
Test name
Test status
Simulation time 85420471 ps
CPU time 2.5 seconds
Started Jul 16 07:46:47 PM PDT 24
Finished Jul 16 07:46:56 PM PDT 24
Peak memory 217388 kb
Host smart-6267dc32-c642-429a-b401-91b170fbb7a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574753114 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2574753114
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.986089877
Short name T109
Test name
Test status
Simulation time 127493079 ps
CPU time 1.75 seconds
Started Jul 16 07:46:52 PM PDT 24
Finished Jul 16 07:46:59 PM PDT 24
Peak memory 207540 kb
Host smart-f7d02bbf-5291-4a66-992b-567c7472cead
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986089877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.986089877
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3597020971
Short name T1122
Test name
Test status
Simulation time 23463114 ps
CPU time 0.7 seconds
Started Jul 16 07:46:31 PM PDT 24
Finished Jul 16 07:46:33 PM PDT 24
Peak memory 204624 kb
Host smart-89f510cb-edac-44ec-bf3d-c68b9dd77707
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597020971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3597020971
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1522564581
Short name T1083
Test name
Test status
Simulation time 163492051 ps
CPU time 2.77 seconds
Started Jul 16 07:46:48 PM PDT 24
Finished Jul 16 07:46:57 PM PDT 24
Peak memory 215824 kb
Host smart-2a74d08b-dff2-4344-a45a-44d71d140bcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522564581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1522564581
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1199040024
Short name T93
Test name
Test status
Simulation time 405653118 ps
CPU time 2.78 seconds
Started Jul 16 07:46:47 PM PDT 24
Finished Jul 16 07:46:56 PM PDT 24
Peak memory 216408 kb
Host smart-c644a05c-c713-42e0-9d23-80a946f9e1fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199040024 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1199040024
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2818459337
Short name T1028
Test name
Test status
Simulation time 77990427 ps
CPU time 2.17 seconds
Started Jul 16 07:46:43 PM PDT 24
Finished Jul 16 07:46:48 PM PDT 24
Peak memory 215676 kb
Host smart-c02708fe-f608-432b-8db8-19595a7526e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818459337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2818459337
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2843745354
Short name T1039
Test name
Test status
Simulation time 12961102 ps
CPU time 0.77 seconds
Started Jul 16 07:46:48 PM PDT 24
Finished Jul 16 07:46:55 PM PDT 24
Peak memory 204332 kb
Host smart-eef3c378-a836-4f94-826a-eb30d38b3fd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843745354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2843745354
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.703899022
Short name T1076
Test name
Test status
Simulation time 609440552 ps
CPU time 4.3 seconds
Started Jul 16 07:46:47 PM PDT 24
Finished Jul 16 07:46:58 PM PDT 24
Peak memory 215284 kb
Host smart-11ba4254-b192-4a54-b69a-ce871467824d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703899022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.703899022
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.549487218
Short name T1072
Test name
Test status
Simulation time 36862496 ps
CPU time 2.19 seconds
Started Jul 16 07:46:48 PM PDT 24
Finished Jul 16 07:46:57 PM PDT 24
Peak memory 216028 kb
Host smart-26d031c7-5453-4a16-8123-687401371254
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549487218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.549487218
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3630592844
Short name T1073
Test name
Test status
Simulation time 197886811 ps
CPU time 2.46 seconds
Started Jul 16 07:46:42 PM PDT 24
Finished Jul 16 07:46:46 PM PDT 24
Peak memory 216944 kb
Host smart-fd9a9065-fcc9-4410-b851-2cb16ae3b46c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630592844 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3630592844
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2580886065
Short name T99
Test name
Test status
Simulation time 665572582 ps
CPU time 2.36 seconds
Started Jul 16 07:46:46 PM PDT 24
Finished Jul 16 07:46:54 PM PDT 24
Peak memory 215840 kb
Host smart-9c1ef1d1-49d6-4e1b-85d7-5a7fa14d6b8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580886065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2580886065
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3327713796
Short name T1084
Test name
Test status
Simulation time 11303469 ps
CPU time 0.75 seconds
Started Jul 16 07:46:41 PM PDT 24
Finished Jul 16 07:46:43 PM PDT 24
Peak memory 204276 kb
Host smart-2a54b1d0-de7d-48d9-b21f-e3e07444d0c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327713796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3327713796
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2020663809
Short name T1106
Test name
Test status
Simulation time 86303900 ps
CPU time 2.6 seconds
Started Jul 16 07:46:45 PM PDT 24
Finished Jul 16 07:46:53 PM PDT 24
Peak memory 215820 kb
Host smart-05d25b21-5193-4f66-afa4-d19e5a9122fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020663809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2020663809
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1214251476
Short name T86
Test name
Test status
Simulation time 786610127 ps
CPU time 5.57 seconds
Started Jul 16 07:46:46 PM PDT 24
Finished Jul 16 07:46:58 PM PDT 24
Peak memory 215992 kb
Host smart-8a7db080-0fba-475a-82b5-ca5d7857518a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214251476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1214251476
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1716458159
Short name T143
Test name
Test status
Simulation time 214257009 ps
CPU time 7.77 seconds
Started Jul 16 07:46:50 PM PDT 24
Finished Jul 16 07:47:04 PM PDT 24
Peak memory 215784 kb
Host smart-0fb222a8-6412-4071-8bf2-52e04a28fd6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716458159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1716458159
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2391675670
Short name T1082
Test name
Test status
Simulation time 203705858 ps
CPU time 3.58 seconds
Started Jul 16 07:46:57 PM PDT 24
Finished Jul 16 07:47:04 PM PDT 24
Peak memory 217540 kb
Host smart-d1d855c0-72d6-4e80-9bf3-7f9a61f213d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391675670 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2391675670
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3296661003
Short name T1127
Test name
Test status
Simulation time 134378109 ps
CPU time 2.11 seconds
Started Jul 16 07:46:59 PM PDT 24
Finished Jul 16 07:47:04 PM PDT 24
Peak memory 215724 kb
Host smart-54387de9-5c6b-484e-9f91-ed7855c4252f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296661003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3296661003
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2825663663
Short name T1007
Test name
Test status
Simulation time 24466545 ps
CPU time 0.7 seconds
Started Jul 16 07:46:45 PM PDT 24
Finished Jul 16 07:46:51 PM PDT 24
Peak memory 204616 kb
Host smart-e43fe48f-ed6a-4aa1-85c7-1beff7d69fd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825663663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2825663663
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.399219313
Short name T1071
Test name
Test status
Simulation time 80323614 ps
CPU time 3.92 seconds
Started Jul 16 07:46:58 PM PDT 24
Finished Jul 16 07:47:05 PM PDT 24
Peak memory 215780 kb
Host smart-f1991675-913d-44f6-b8df-f070c0db100b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399219313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.399219313
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1682195792
Short name T1037
Test name
Test status
Simulation time 51745696 ps
CPU time 3.11 seconds
Started Jul 16 07:46:45 PM PDT 24
Finished Jul 16 07:46:53 PM PDT 24
Peak memory 216108 kb
Host smart-e3925ed0-19c8-45d4-a40e-1777199c54ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682195792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1682195792
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1833292121
Short name T1055
Test name
Test status
Simulation time 143344701 ps
CPU time 6.18 seconds
Started Jul 16 07:46:46 PM PDT 24
Finished Jul 16 07:46:57 PM PDT 24
Peak memory 215812 kb
Host smart-9c408a4c-e237-4f46-a151-eba3c6ebcedf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833292121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1833292121
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3292019888
Short name T63
Test name
Test status
Simulation time 201530223 ps
CPU time 1.69 seconds
Started Jul 16 07:46:58 PM PDT 24
Finished Jul 16 07:47:03 PM PDT 24
Peak memory 215880 kb
Host smart-4d687d6f-5a74-4df6-9753-dbddf3fba3e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292019888 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3292019888
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3874025008
Short name T1117
Test name
Test status
Simulation time 456326715 ps
CPU time 2.52 seconds
Started Jul 16 07:47:03 PM PDT 24
Finished Jul 16 07:47:07 PM PDT 24
Peak memory 207588 kb
Host smart-3b67ce96-4196-4588-a76c-46d1c990800e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874025008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3874025008
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3577791713
Short name T1008
Test name
Test status
Simulation time 60298509 ps
CPU time 0.74 seconds
Started Jul 16 07:46:59 PM PDT 24
Finished Jul 16 07:47:02 PM PDT 24
Peak memory 204300 kb
Host smart-625580ba-f699-4172-aa65-40ee28c5fcd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577791713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3577791713
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.405139222
Short name T1045
Test name
Test status
Simulation time 674811351 ps
CPU time 3.06 seconds
Started Jul 16 07:47:00 PM PDT 24
Finished Jul 16 07:47:06 PM PDT 24
Peak memory 215748 kb
Host smart-6b71dbd0-1add-4e82-a6d5-95bccc53cd33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405139222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.405139222
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.4104224385
Short name T1110
Test name
Test status
Simulation time 386214018 ps
CPU time 2.79 seconds
Started Jul 16 07:46:56 PM PDT 24
Finished Jul 16 07:47:03 PM PDT 24
Peak memory 216956 kb
Host smart-9748f16d-160d-4b64-997d-56dda8f062f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104224385 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.4104224385
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1322056220
Short name T1070
Test name
Test status
Simulation time 98185932 ps
CPU time 1.84 seconds
Started Jul 16 07:46:57 PM PDT 24
Finished Jul 16 07:47:02 PM PDT 24
Peak memory 207564 kb
Host smart-97f25aa7-935f-4b49-b5dc-9016cfa977f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322056220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1322056220
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3965065812
Short name T1020
Test name
Test status
Simulation time 54255390 ps
CPU time 0.76 seconds
Started Jul 16 07:46:58 PM PDT 24
Finished Jul 16 07:47:02 PM PDT 24
Peak memory 204296 kb
Host smart-a681caa8-a8ff-46df-afa1-b962305dad17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965065812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3965065812
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2748816166
Short name T1063
Test name
Test status
Simulation time 103658303 ps
CPU time 3.32 seconds
Started Jul 16 07:46:57 PM PDT 24
Finished Jul 16 07:47:04 PM PDT 24
Peak memory 215844 kb
Host smart-87703eab-fdac-48c8-b80e-c91060ff0372
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748816166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2748816166
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1193763926
Short name T1109
Test name
Test status
Simulation time 50588566 ps
CPU time 1.42 seconds
Started Jul 16 07:47:03 PM PDT 24
Finished Jul 16 07:47:06 PM PDT 24
Peak memory 216028 kb
Host smart-a56c80d2-f79a-46fc-8870-db29adaf31cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193763926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1193763926
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.75406817
Short name T151
Test name
Test status
Simulation time 4679994071 ps
CPU time 24.19 seconds
Started Jul 16 07:46:58 PM PDT 24
Finished Jul 16 07:47:25 PM PDT 24
Peak memory 216252 kb
Host smart-4d2eddbf-1934-4697-8a11-e14be74c9a5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75406817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_
tl_intg_err.75406817
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.785031446
Short name T1079
Test name
Test status
Simulation time 202436906 ps
CPU time 2.71 seconds
Started Jul 16 07:47:17 PM PDT 24
Finished Jul 16 07:47:23 PM PDT 24
Peak memory 218404 kb
Host smart-819e5086-720a-4f62-aeed-1ab887b0e42b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785031446 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.785031446
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3798817520
Short name T1094
Test name
Test status
Simulation time 40961755 ps
CPU time 2.29 seconds
Started Jul 16 07:47:20 PM PDT 24
Finished Jul 16 07:47:26 PM PDT 24
Peak memory 207508 kb
Host smart-d12f14bc-6236-4454-abc8-7c31bae9962e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798817520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3798817520
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1753279903
Short name T1105
Test name
Test status
Simulation time 15770787 ps
CPU time 0.79 seconds
Started Jul 16 07:47:16 PM PDT 24
Finished Jul 16 07:47:19 PM PDT 24
Peak memory 204612 kb
Host smart-1145c0f1-a08a-461b-a616-30a03a97ac5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753279903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1753279903
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3026210484
Short name T1100
Test name
Test status
Simulation time 262508353 ps
CPU time 2.99 seconds
Started Jul 16 07:47:18 PM PDT 24
Finished Jul 16 07:47:25 PM PDT 24
Peak memory 215696 kb
Host smart-c2480e47-5030-4c87-b63f-1b0c54003c39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026210484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3026210484
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.582545315
Short name T1051
Test name
Test status
Simulation time 32659591 ps
CPU time 2.32 seconds
Started Jul 16 07:47:02 PM PDT 24
Finished Jul 16 07:47:06 PM PDT 24
Peak memory 216092 kb
Host smart-a537deff-0c11-4f15-bfaa-0d131cc21fac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582545315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.582545315
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2901558229
Short name T1065
Test name
Test status
Simulation time 1327360102 ps
CPU time 13.01 seconds
Started Jul 16 07:47:02 PM PDT 24
Finished Jul 16 07:47:17 PM PDT 24
Peak memory 215732 kb
Host smart-72bb8cf4-8571-4808-bbd0-6ff4e794f3f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901558229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2901558229
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3476143269
Short name T1085
Test name
Test status
Simulation time 77452868 ps
CPU time 2.56 seconds
Started Jul 16 07:47:15 PM PDT 24
Finished Jul 16 07:47:18 PM PDT 24
Peak memory 217364 kb
Host smart-b697a952-1f01-4b21-a9a1-4d2888bd2cfb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476143269 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3476143269
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3294981319
Short name T1096
Test name
Test status
Simulation time 25899054 ps
CPU time 1.72 seconds
Started Jul 16 07:47:18 PM PDT 24
Finished Jul 16 07:47:23 PM PDT 24
Peak memory 215632 kb
Host smart-db0bfdd3-b5fd-4afc-8946-44ca7c2bae1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294981319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3294981319
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3977967000
Short name T1125
Test name
Test status
Simulation time 15895160 ps
CPU time 0.79 seconds
Started Jul 16 07:47:14 PM PDT 24
Finished Jul 16 07:47:16 PM PDT 24
Peak memory 204236 kb
Host smart-7e0ffa6a-66f9-457b-997c-3056b3d25b0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977967000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3977967000
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2473859452
Short name T1115
Test name
Test status
Simulation time 220145679 ps
CPU time 3.67 seconds
Started Jul 16 07:47:19 PM PDT 24
Finished Jul 16 07:47:26 PM PDT 24
Peak memory 215776 kb
Host smart-239f4131-a2c8-4dff-bbb1-90d2cba6734d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473859452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2473859452
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.667956969
Short name T1093
Test name
Test status
Simulation time 213354497 ps
CPU time 6.15 seconds
Started Jul 16 07:47:19 PM PDT 24
Finished Jul 16 07:47:29 PM PDT 24
Peak memory 215812 kb
Host smart-24be7f4e-e5aa-4dec-8df7-65ac7dcf8d0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667956969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.667956969
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1414694147
Short name T127
Test name
Test status
Simulation time 326461192 ps
CPU time 3.8 seconds
Started Jul 16 07:47:16 PM PDT 24
Finished Jul 16 07:47:22 PM PDT 24
Peak memory 218164 kb
Host smart-351678eb-1c41-47e4-aca0-635dab6fe12b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414694147 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1414694147
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1274942977
Short name T105
Test name
Test status
Simulation time 319171510 ps
CPU time 1.47 seconds
Started Jul 16 07:47:15 PM PDT 24
Finished Jul 16 07:47:18 PM PDT 24
Peak memory 207540 kb
Host smart-2afdea0a-70a2-464c-85fb-f26c015f9ca9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274942977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1274942977
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1108069472
Short name T1057
Test name
Test status
Simulation time 11195956 ps
CPU time 0.73 seconds
Started Jul 16 07:47:15 PM PDT 24
Finished Jul 16 07:47:18 PM PDT 24
Peak memory 204616 kb
Host smart-b6061801-8a35-4a3a-9428-66351f3278d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108069472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1108069472
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.845582246
Short name T1121
Test name
Test status
Simulation time 142029262 ps
CPU time 1.88 seconds
Started Jul 16 07:47:16 PM PDT 24
Finished Jul 16 07:47:21 PM PDT 24
Peak memory 215852 kb
Host smart-908ce388-4e56-4972-b8e6-ab6d2289d388
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845582246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.845582246
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.231571184
Short name T89
Test name
Test status
Simulation time 538107015 ps
CPU time 3.85 seconds
Started Jul 16 07:47:19 PM PDT 24
Finished Jul 16 07:47:26 PM PDT 24
Peak memory 216024 kb
Host smart-d8c8957f-cfc1-4771-8581-c678af72ce0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231571184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.231571184
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1171498553
Short name T142
Test name
Test status
Simulation time 2170841169 ps
CPU time 15.05 seconds
Started Jul 16 07:47:20 PM PDT 24
Finished Jul 16 07:47:39 PM PDT 24
Peak memory 217208 kb
Host smart-f8dbb8a9-7d50-4475-9796-dc793a7f70f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171498553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1171498553
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3357528170
Short name T110
Test name
Test status
Simulation time 1228319037 ps
CPU time 14.91 seconds
Started Jul 16 07:46:41 PM PDT 24
Finished Jul 16 07:46:57 PM PDT 24
Peak memory 207520 kb
Host smart-259650a5-a6da-4874-a92b-0ef049e3088a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357528170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3357528170
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.4277580772
Short name T1009
Test name
Test status
Simulation time 12094663096 ps
CPU time 25.7 seconds
Started Jul 16 07:46:23 PM PDT 24
Finished Jul 16 07:46:53 PM PDT 24
Peak memory 215820 kb
Host smart-594e0756-f530-48b7-8a11-50001b94b998
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277580772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.4277580772
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1851906806
Short name T71
Test name
Test status
Simulation time 40200270 ps
CPU time 1.45 seconds
Started Jul 16 07:46:22 PM PDT 24
Finished Jul 16 07:46:28 PM PDT 24
Peak memory 215704 kb
Host smart-57062d9f-f808-4045-8259-50f0c5fa9519
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851906806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1851906806
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.845884154
Short name T1074
Test name
Test status
Simulation time 99373516 ps
CPU time 3.59 seconds
Started Jul 16 07:46:45 PM PDT 24
Finished Jul 16 07:46:54 PM PDT 24
Peak memory 217580 kb
Host smart-5716061e-630e-4c57-97ac-4218c9799ee6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845884154 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.845884154
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4225975268
Short name T98
Test name
Test status
Simulation time 475624406 ps
CPU time 2.86 seconds
Started Jul 16 07:46:18 PM PDT 24
Finished Jul 16 07:46:23 PM PDT 24
Peak memory 215720 kb
Host smart-d06e8e23-8163-4072-8fd0-36bbbb5b52c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225975268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.4
225975268
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3554331324
Short name T1033
Test name
Test status
Simulation time 18748339 ps
CPU time 0.74 seconds
Started Jul 16 07:46:21 PM PDT 24
Finished Jul 16 07:46:25 PM PDT 24
Peak memory 204292 kb
Host smart-ba093bbf-0015-411c-9b64-4d8a7c2bd2c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554331324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
554331324
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.661672509
Short name T108
Test name
Test status
Simulation time 278649971 ps
CPU time 2.42 seconds
Started Jul 16 07:46:23 PM PDT 24
Finished Jul 16 07:46:30 PM PDT 24
Peak memory 215752 kb
Host smart-cb2d6484-c3d0-48e3-b1e2-1b31c9de7aac
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661672509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.661672509
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3887418798
Short name T1129
Test name
Test status
Simulation time 14050708 ps
CPU time 0.65 seconds
Started Jul 16 07:46:22 PM PDT 24
Finished Jul 16 07:46:27 PM PDT 24
Peak memory 204116 kb
Host smart-1e8f719e-214d-4264-9a0f-74290e977bf6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887418798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3887418798
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3197229407
Short name T1088
Test name
Test status
Simulation time 2453255505 ps
CPU time 4 seconds
Started Jul 16 07:46:45 PM PDT 24
Finished Jul 16 07:46:55 PM PDT 24
Peak memory 215824 kb
Host smart-facf1727-d624-4d83-8ba0-6516b1de54f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197229407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3197229407
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2732924918
Short name T1026
Test name
Test status
Simulation time 78894381 ps
CPU time 2.09 seconds
Started Jul 16 07:46:22 PM PDT 24
Finished Jul 16 07:46:29 PM PDT 24
Peak memory 217004 kb
Host smart-12a9ff69-72dd-4e8c-814a-f986345c2769
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732924918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
732924918
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1272645606
Short name T1107
Test name
Test status
Simulation time 289582289 ps
CPU time 18.08 seconds
Started Jul 16 07:46:21 PM PDT 24
Finished Jul 16 07:46:43 PM PDT 24
Peak memory 215724 kb
Host smart-ba87260e-e2b5-44fa-a74f-56e659a19e49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272645606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1272645606
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3726737319
Short name T1112
Test name
Test status
Simulation time 14431639 ps
CPU time 0.74 seconds
Started Jul 16 07:47:16 PM PDT 24
Finished Jul 16 07:47:20 PM PDT 24
Peak memory 204280 kb
Host smart-ca0ed5f8-07e1-4f14-a71d-81d230c51c94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726737319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3726737319
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.499580015
Short name T1013
Test name
Test status
Simulation time 98783804 ps
CPU time 0.72 seconds
Started Jul 16 07:47:15 PM PDT 24
Finished Jul 16 07:47:16 PM PDT 24
Peak memory 204636 kb
Host smart-5caf5fa1-6d3c-43ca-85a8-59363a264aaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499580015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.499580015
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1990605293
Short name T1041
Test name
Test status
Simulation time 14193557 ps
CPU time 0.76 seconds
Started Jul 16 07:47:15 PM PDT 24
Finished Jul 16 07:47:18 PM PDT 24
Peak memory 204240 kb
Host smart-810aee67-b0cd-4853-be10-e5a975720e7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990605293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1990605293
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.407411830
Short name T1118
Test name
Test status
Simulation time 20795261 ps
CPU time 0.76 seconds
Started Jul 16 07:47:17 PM PDT 24
Finished Jul 16 07:47:20 PM PDT 24
Peak memory 204300 kb
Host smart-7ced8ace-54c7-4da6-82c4-1ff4b028249b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407411830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.407411830
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.525094335
Short name T1120
Test name
Test status
Simulation time 16956233 ps
CPU time 0.75 seconds
Started Jul 16 07:47:19 PM PDT 24
Finished Jul 16 07:47:23 PM PDT 24
Peak memory 204300 kb
Host smart-2fc13ef3-5a49-4d2f-a944-4c30d7eca6b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525094335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.525094335
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.643352169
Short name T1053
Test name
Test status
Simulation time 19459826 ps
CPU time 0.8 seconds
Started Jul 16 07:47:16 PM PDT 24
Finished Jul 16 07:47:19 PM PDT 24
Peak memory 204584 kb
Host smart-46931be0-f398-4eca-b8e7-01be949e12e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643352169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.643352169
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2934559089
Short name T1103
Test name
Test status
Simulation time 58770279 ps
CPU time 0.71 seconds
Started Jul 16 07:47:18 PM PDT 24
Finished Jul 16 07:47:22 PM PDT 24
Peak memory 204264 kb
Host smart-390c3b8b-e0e5-4071-8393-9e98caf68790
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934559089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2934559089
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1964587051
Short name T1060
Test name
Test status
Simulation time 30588299 ps
CPU time 0.7 seconds
Started Jul 16 07:47:19 PM PDT 24
Finished Jul 16 07:47:23 PM PDT 24
Peak memory 204612 kb
Host smart-25c68578-f3c0-45b1-99a0-2081c6749391
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964587051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1964587051
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1460343164
Short name T1024
Test name
Test status
Simulation time 51268305 ps
CPU time 0.75 seconds
Started Jul 16 07:47:15 PM PDT 24
Finished Jul 16 07:47:18 PM PDT 24
Peak memory 204624 kb
Host smart-735e9b38-6fb4-43e3-b353-3e3a82df871a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460343164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1460343164
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.633572775
Short name T1091
Test name
Test status
Simulation time 24652542 ps
CPU time 0.7 seconds
Started Jul 16 07:47:16 PM PDT 24
Finished Jul 16 07:47:18 PM PDT 24
Peak memory 204576 kb
Host smart-0ade26ac-8d79-4d57-b00f-8c3ff92c4375
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633572775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.633572775
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.449229034
Short name T102
Test name
Test status
Simulation time 2633636143 ps
CPU time 16 seconds
Started Jul 16 07:46:43 PM PDT 24
Finished Jul 16 07:47:02 PM PDT 24
Peak memory 207576 kb
Host smart-bff1a84c-d313-4591-81e5-2118946580b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449229034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.449229034
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3739957223
Short name T1049
Test name
Test status
Simulation time 3156281978 ps
CPU time 12.65 seconds
Started Jul 16 07:46:47 PM PDT 24
Finished Jul 16 07:47:06 PM PDT 24
Peak memory 207480 kb
Host smart-f4bb4f30-95c8-4d41-ab66-d80ea3497a6f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739957223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3739957223
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1512176226
Short name T72
Test name
Test status
Simulation time 158023538 ps
CPU time 0.95 seconds
Started Jul 16 07:46:45 PM PDT 24
Finished Jul 16 07:46:51 PM PDT 24
Peak memory 207220 kb
Host smart-bc02d872-8b9c-4893-bc28-82118a246a04
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512176226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1512176226
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.973358376
Short name T1014
Test name
Test status
Simulation time 64120315 ps
CPU time 3.83 seconds
Started Jul 16 07:46:41 PM PDT 24
Finished Jul 16 07:46:47 PM PDT 24
Peak memory 217632 kb
Host smart-a0a78416-eb08-432c-8b86-849a2f08265c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973358376 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.973358376
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3330836543
Short name T1090
Test name
Test status
Simulation time 38726401 ps
CPU time 2.34 seconds
Started Jul 16 07:46:40 PM PDT 24
Finished Jul 16 07:46:43 PM PDT 24
Peak memory 215716 kb
Host smart-aa63eedb-54c4-4334-8c13-d4e0bccce90d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330836543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
330836543
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1047242800
Short name T1068
Test name
Test status
Simulation time 121921201 ps
CPU time 0.74 seconds
Started Jul 16 07:46:42 PM PDT 24
Finished Jul 16 07:46:45 PM PDT 24
Peak memory 204260 kb
Host smart-3f4ca593-5f33-4983-ba29-ecd8eafd7bd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047242800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
047242800
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2927408734
Short name T1097
Test name
Test status
Simulation time 181117875 ps
CPU time 1.92 seconds
Started Jul 16 07:46:41 PM PDT 24
Finished Jul 16 07:46:44 PM PDT 24
Peak memory 215752 kb
Host smart-c1d52679-6de7-4be8-9afa-7136ed2988c9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927408734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2927408734
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3725072539
Short name T1017
Test name
Test status
Simulation time 16306885 ps
CPU time 0.65 seconds
Started Jul 16 07:46:46 PM PDT 24
Finished Jul 16 07:46:52 PM PDT 24
Peak memory 204136 kb
Host smart-8fc16257-b55f-4dea-ae44-5f6ed289eb55
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725072539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3725072539
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3991213139
Short name T1130
Test name
Test status
Simulation time 1523836176 ps
CPU time 4.04 seconds
Started Jul 16 07:46:43 PM PDT 24
Finished Jul 16 07:46:50 PM PDT 24
Peak memory 215784 kb
Host smart-4a29a791-6748-4a5f-ac3d-d2f8665b6d7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991213139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3991213139
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2382086163
Short name T1036
Test name
Test status
Simulation time 398865353 ps
CPU time 5.35 seconds
Started Jul 16 07:46:40 PM PDT 24
Finished Jul 16 07:46:46 PM PDT 24
Peak memory 215952 kb
Host smart-78c78697-9149-4ec1-bcdc-8bb728a2c21d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382086163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
382086163
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3283953150
Short name T1078
Test name
Test status
Simulation time 1184630946 ps
CPU time 7.37 seconds
Started Jul 16 07:46:47 PM PDT 24
Finished Jul 16 07:47:01 PM PDT 24
Peak memory 215712 kb
Host smart-54b7c8eb-dcae-4022-980c-93cafb67a0b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283953150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3283953150
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3366852053
Short name T1046
Test name
Test status
Simulation time 20734279 ps
CPU time 0.69 seconds
Started Jul 16 07:47:18 PM PDT 24
Finished Jul 16 07:47:22 PM PDT 24
Peak memory 204560 kb
Host smart-812318fe-cb81-4020-9872-b0b27f5b4a44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366852053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3366852053
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1730912792
Short name T1124
Test name
Test status
Simulation time 25038507 ps
CPU time 0.75 seconds
Started Jul 16 07:47:14 PM PDT 24
Finished Jul 16 07:47:15 PM PDT 24
Peak memory 204324 kb
Host smart-e9bc3ed4-4c13-4295-9920-3c89cc9f52a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730912792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1730912792
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2150614620
Short name T1022
Test name
Test status
Simulation time 14080781 ps
CPU time 0.72 seconds
Started Jul 16 07:47:18 PM PDT 24
Finished Jul 16 07:47:22 PM PDT 24
Peak memory 204612 kb
Host smart-5fd3c1a5-f94b-4b55-9f48-7b2e74e2a3eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150614620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2150614620
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.616297356
Short name T1047
Test name
Test status
Simulation time 25782106 ps
CPU time 0.73 seconds
Started Jul 16 07:47:19 PM PDT 24
Finished Jul 16 07:47:24 PM PDT 24
Peak memory 204260 kb
Host smart-a293c545-493a-4946-b908-caca886423cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616297356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.616297356
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1508544321
Short name T1087
Test name
Test status
Simulation time 21199720 ps
CPU time 0.75 seconds
Started Jul 16 07:47:19 PM PDT 24
Finished Jul 16 07:47:23 PM PDT 24
Peak memory 204300 kb
Host smart-be8a6620-df8e-4850-9936-bc5561a026d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508544321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1508544321
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.4085285046
Short name T1027
Test name
Test status
Simulation time 15998286 ps
CPU time 0.78 seconds
Started Jul 16 07:47:18 PM PDT 24
Finished Jul 16 07:47:22 PM PDT 24
Peak memory 204232 kb
Host smart-001f816b-a7eb-48e9-a0b9-12a9b4efd6cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085285046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
4085285046
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3400537457
Short name T1064
Test name
Test status
Simulation time 26024930 ps
CPU time 0.72 seconds
Started Jul 16 07:47:20 PM PDT 24
Finished Jul 16 07:47:24 PM PDT 24
Peak memory 204372 kb
Host smart-eb330802-f751-4ca9-9e1c-821bc8fcb9f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400537457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3400537457
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1314082654
Short name T1023
Test name
Test status
Simulation time 14206738 ps
CPU time 0.76 seconds
Started Jul 16 07:47:16 PM PDT 24
Finished Jul 16 07:47:19 PM PDT 24
Peak memory 204360 kb
Host smart-bfe63690-004f-48b3-ab8f-e39af0695a9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314082654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1314082654
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2821921703
Short name T1011
Test name
Test status
Simulation time 44299497 ps
CPU time 0.77 seconds
Started Jul 16 07:47:16 PM PDT 24
Finished Jul 16 07:47:20 PM PDT 24
Peak memory 204288 kb
Host smart-f5228ee0-99c5-4f68-a756-6dc6fbd01a53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821921703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2821921703
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3020910473
Short name T1006
Test name
Test status
Simulation time 30687258 ps
CPU time 0.75 seconds
Started Jul 16 07:47:16 PM PDT 24
Finished Jul 16 07:47:20 PM PDT 24
Peak memory 204260 kb
Host smart-58511b9c-e648-49bd-879c-433160e0be4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020910473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3020910473
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1259763641
Short name T1019
Test name
Test status
Simulation time 1212878599 ps
CPU time 8.14 seconds
Started Jul 16 07:46:45 PM PDT 24
Finished Jul 16 07:46:58 PM PDT 24
Peak memory 215688 kb
Host smart-2f5a1d03-e526-4a9c-87c2-c9799d1c4313
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259763641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1259763641
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2239563888
Short name T107
Test name
Test status
Simulation time 3680561703 ps
CPU time 27.22 seconds
Started Jul 16 07:46:47 PM PDT 24
Finished Jul 16 07:47:21 PM PDT 24
Peak memory 207564 kb
Host smart-119df6a7-33bd-483c-b496-fca12519e8f8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239563888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2239563888
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.339118918
Short name T1086
Test name
Test status
Simulation time 75155694 ps
CPU time 2.52 seconds
Started Jul 16 07:46:42 PM PDT 24
Finished Jul 16 07:46:47 PM PDT 24
Peak memory 217488 kb
Host smart-39979114-986f-4919-b65c-35158707a4da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339118918 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.339118918
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2376284791
Short name T1042
Test name
Test status
Simulation time 21539039 ps
CPU time 1.33 seconds
Started Jul 16 07:46:46 PM PDT 24
Finished Jul 16 07:46:53 PM PDT 24
Peak memory 215724 kb
Host smart-edaf2adb-b30c-483a-90a5-7d29c056b4b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376284791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
376284791
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3899274286
Short name T1021
Test name
Test status
Simulation time 17609765 ps
CPU time 0.68 seconds
Started Jul 16 07:46:40 PM PDT 24
Finished Jul 16 07:46:42 PM PDT 24
Peak memory 204320 kb
Host smart-e1bce9e6-fb98-498e-9526-6d8f3762b521
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899274286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
899274286
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1844003555
Short name T1116
Test name
Test status
Simulation time 82815325 ps
CPU time 1.77 seconds
Started Jul 16 07:46:46 PM PDT 24
Finished Jul 16 07:46:53 PM PDT 24
Peak memory 215792 kb
Host smart-9f11e3f2-d589-47c2-a789-79f5aa6ba3ef
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844003555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1844003555
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2258957923
Short name T1111
Test name
Test status
Simulation time 39422663 ps
CPU time 0.66 seconds
Started Jul 16 07:46:47 PM PDT 24
Finished Jul 16 07:46:54 PM PDT 24
Peak memory 204424 kb
Host smart-e5119404-4e92-4ba4-80c1-f8377064f783
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258957923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2258957923
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1905894704
Short name T1059
Test name
Test status
Simulation time 159611745 ps
CPU time 4.18 seconds
Started Jul 16 07:46:41 PM PDT 24
Finished Jul 16 07:46:46 PM PDT 24
Peak memory 215648 kb
Host smart-efce8c29-1845-484f-ae28-af71348a1f06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905894704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1905894704
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1101091127
Short name T1054
Test name
Test status
Simulation time 193533034 ps
CPU time 1.84 seconds
Started Jul 16 07:46:40 PM PDT 24
Finished Jul 16 07:46:44 PM PDT 24
Peak memory 216080 kb
Host smart-38d8ff19-1615-443f-9a72-5c378a113dd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101091127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
101091127
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2375500632
Short name T148
Test name
Test status
Simulation time 368014738 ps
CPU time 8.36 seconds
Started Jul 16 07:46:51 PM PDT 24
Finished Jul 16 07:47:05 PM PDT 24
Peak memory 215984 kb
Host smart-07bf78f4-1032-4705-a323-e94c793197a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375500632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2375500632
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.4048049704
Short name T1113
Test name
Test status
Simulation time 18697463 ps
CPU time 0.79 seconds
Started Jul 16 07:47:18 PM PDT 24
Finished Jul 16 07:47:23 PM PDT 24
Peak memory 204252 kb
Host smart-6cf984be-b0a8-46fe-86df-a643527b3d92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048049704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
4048049704
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1925899512
Short name T1050
Test name
Test status
Simulation time 51502182 ps
CPU time 0.74 seconds
Started Jul 16 07:47:20 PM PDT 24
Finished Jul 16 07:47:24 PM PDT 24
Peak memory 204608 kb
Host smart-b013939f-9d38-49f3-a1a1-936d17b0913a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925899512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1925899512
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1139643723
Short name T1010
Test name
Test status
Simulation time 16428863 ps
CPU time 0.69 seconds
Started Jul 16 07:47:15 PM PDT 24
Finished Jul 16 07:47:17 PM PDT 24
Peak memory 204516 kb
Host smart-f5f7972d-4349-4b30-bc7c-670a56408c01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139643723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1139643723
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.946866284
Short name T1077
Test name
Test status
Simulation time 50719796 ps
CPU time 0.76 seconds
Started Jul 16 07:47:16 PM PDT 24
Finished Jul 16 07:47:19 PM PDT 24
Peak memory 204240 kb
Host smart-d1d52bfe-f7bb-4510-9d49-0194b8439b07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946866284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.946866284
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.254929458
Short name T1044
Test name
Test status
Simulation time 47828962 ps
CPU time 0.73 seconds
Started Jul 16 07:47:19 PM PDT 24
Finished Jul 16 07:47:23 PM PDT 24
Peak memory 204308 kb
Host smart-efacc5fa-fef3-4e59-b7ae-9dffa88ffbdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254929458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.254929458
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3143785070
Short name T1025
Test name
Test status
Simulation time 48989852 ps
CPU time 0.7 seconds
Started Jul 16 07:47:16 PM PDT 24
Finished Jul 16 07:47:19 PM PDT 24
Peak memory 204644 kb
Host smart-a1063da9-9653-4e90-a44e-b2a5808d992b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143785070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3143785070
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2424013570
Short name T1015
Test name
Test status
Simulation time 10756313 ps
CPU time 0.68 seconds
Started Jul 16 07:47:19 PM PDT 24
Finished Jul 16 07:47:23 PM PDT 24
Peak memory 204372 kb
Host smart-4f901c7d-e97f-426f-a3c2-19cff01bc53b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424013570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2424013570
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1187165133
Short name T1126
Test name
Test status
Simulation time 49181786 ps
CPU time 0.74 seconds
Started Jul 16 07:47:17 PM PDT 24
Finished Jul 16 07:47:21 PM PDT 24
Peak memory 204260 kb
Host smart-3821b83a-070f-4095-a60c-4eb7aaf9cbb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187165133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1187165133
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1591702872
Short name T1035
Test name
Test status
Simulation time 46293112 ps
CPU time 0.72 seconds
Started Jul 16 07:47:15 PM PDT 24
Finished Jul 16 07:47:17 PM PDT 24
Peak memory 204296 kb
Host smart-da5ccd42-0226-4464-b894-76a7a4b9e863
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591702872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1591702872
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3098790533
Short name T1081
Test name
Test status
Simulation time 50784084 ps
CPU time 0.71 seconds
Started Jul 16 07:47:17 PM PDT 24
Finished Jul 16 07:47:21 PM PDT 24
Peak memory 204252 kb
Host smart-8a164e1d-dd61-48ac-8181-e6b2aaefc340
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098790533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3098790533
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1206817025
Short name T1061
Test name
Test status
Simulation time 144760404 ps
CPU time 3.39 seconds
Started Jul 16 07:46:39 PM PDT 24
Finished Jul 16 07:46:43 PM PDT 24
Peak memory 218060 kb
Host smart-f31a0d47-b893-416f-8932-4ecfcf56ab60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206817025 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1206817025
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1915130672
Short name T106
Test name
Test status
Simulation time 138574000 ps
CPU time 1.2 seconds
Started Jul 16 07:46:46 PM PDT 24
Finished Jul 16 07:46:53 PM PDT 24
Peak memory 215784 kb
Host smart-250c4757-30aa-46b0-bf01-bdb6c16d74a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915130672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
915130672
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3579757049
Short name T1018
Test name
Test status
Simulation time 14613247 ps
CPU time 0.76 seconds
Started Jul 16 07:46:46 PM PDT 24
Finished Jul 16 07:46:53 PM PDT 24
Peak memory 204576 kb
Host smart-7b6b9344-ee72-4924-a3d7-9b57a70dcbe3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579757049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
579757049
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3364791758
Short name T1048
Test name
Test status
Simulation time 163189342 ps
CPU time 4.07 seconds
Started Jul 16 07:46:47 PM PDT 24
Finished Jul 16 07:46:57 PM PDT 24
Peak memory 215764 kb
Host smart-5b08bf01-6746-4a3a-8e90-ece3606f48d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364791758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3364791758
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.30396154
Short name T82
Test name
Test status
Simulation time 119427361 ps
CPU time 2.97 seconds
Started Jul 16 07:46:47 PM PDT 24
Finished Jul 16 07:46:56 PM PDT 24
Peak memory 215968 kb
Host smart-ed0e2fe1-b9d2-4e57-9d2c-7f5f7f44a5b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30396154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.30396154
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.296190048
Short name T150
Test name
Test status
Simulation time 455504854 ps
CPU time 6.84 seconds
Started Jul 16 07:46:48 PM PDT 24
Finished Jul 16 07:47:02 PM PDT 24
Peak memory 215872 kb
Host smart-c43f6579-4615-4799-86a6-b1545c0d5a8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296190048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.296190048
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3044087773
Short name T1034
Test name
Test status
Simulation time 115512957 ps
CPU time 3.19 seconds
Started Jul 16 07:46:45 PM PDT 24
Finished Jul 16 07:46:52 PM PDT 24
Peak memory 217752 kb
Host smart-316e47ae-9bed-4edc-812a-b271a10900d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044087773 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3044087773
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.4042846568
Short name T128
Test name
Test status
Simulation time 1332015149 ps
CPU time 2.26 seconds
Started Jul 16 07:46:48 PM PDT 24
Finished Jul 16 07:46:57 PM PDT 24
Peak memory 215720 kb
Host smart-7e72f27b-d6de-4df9-9a3a-fd4faf3ddfb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042846568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.4
042846568
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1640003183
Short name T1089
Test name
Test status
Simulation time 52832314 ps
CPU time 0.76 seconds
Started Jul 16 07:46:45 PM PDT 24
Finished Jul 16 07:46:51 PM PDT 24
Peak memory 204576 kb
Host smart-f3952948-c978-4201-a01c-5521474fbd2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640003183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
640003183
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3010416358
Short name T1038
Test name
Test status
Simulation time 496722566 ps
CPU time 3.9 seconds
Started Jul 16 07:46:45 PM PDT 24
Finished Jul 16 07:46:53 PM PDT 24
Peak memory 215784 kb
Host smart-fdb201df-2d70-4dce-90c7-f66a657825eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010416358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3010416358
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3220901221
Short name T1052
Test name
Test status
Simulation time 105488135 ps
CPU time 2.33 seconds
Started Jul 16 07:46:46 PM PDT 24
Finished Jul 16 07:46:54 PM PDT 24
Peak memory 216108 kb
Host smart-f67b4102-d496-4616-9ee2-dc4cc6c6e6fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220901221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
220901221
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.4099054078
Short name T1095
Test name
Test status
Simulation time 362551298 ps
CPU time 8.25 seconds
Started Jul 16 07:46:49 PM PDT 24
Finished Jul 16 07:47:04 PM PDT 24
Peak memory 216160 kb
Host smart-355d0f67-94f6-4a21-84f5-1700a2ada0c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099054078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.4099054078
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1912848959
Short name T1069
Test name
Test status
Simulation time 51808216 ps
CPU time 3.63 seconds
Started Jul 16 07:46:41 PM PDT 24
Finished Jul 16 07:46:47 PM PDT 24
Peak memory 218284 kb
Host smart-c9e6d44d-08cb-46ec-b42c-1ee75a468526
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912848959 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1912848959
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3902175449
Short name T101
Test name
Test status
Simulation time 345332739 ps
CPU time 1.44 seconds
Started Jul 16 07:46:47 PM PDT 24
Finished Jul 16 07:46:55 PM PDT 24
Peak memory 207516 kb
Host smart-b9da7f24-5282-4bfa-bd92-259546f1422e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902175449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
902175449
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2479112492
Short name T1101
Test name
Test status
Simulation time 45574489 ps
CPU time 0.72 seconds
Started Jul 16 07:46:41 PM PDT 24
Finished Jul 16 07:46:44 PM PDT 24
Peak memory 204580 kb
Host smart-6b989127-e786-47e6-97e0-e65cd1f28ca5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479112492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
479112492
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1136908973
Short name T116
Test name
Test status
Simulation time 103314537 ps
CPU time 1.93 seconds
Started Jul 16 07:46:43 PM PDT 24
Finished Jul 16 07:46:48 PM PDT 24
Peak memory 215836 kb
Host smart-ceaf2e3f-c5a3-4c4c-b536-c6ba198349ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136908973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1136908973
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2302606909
Short name T85
Test name
Test status
Simulation time 136480609 ps
CPU time 3.53 seconds
Started Jul 16 07:46:47 PM PDT 24
Finished Jul 16 07:46:57 PM PDT 24
Peak memory 216076 kb
Host smart-be907517-f962-4fce-a912-f52801921df4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302606909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
302606909
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1239676968
Short name T1031
Test name
Test status
Simulation time 58920979 ps
CPU time 1.93 seconds
Started Jul 16 07:46:51 PM PDT 24
Finished Jul 16 07:46:59 PM PDT 24
Peak memory 215844 kb
Host smart-63edcf6e-293a-48b3-8223-8a3773a25553
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239676968 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1239676968
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3561283048
Short name T1128
Test name
Test status
Simulation time 603748377 ps
CPU time 1.4 seconds
Started Jul 16 07:46:47 PM PDT 24
Finished Jul 16 07:46:54 PM PDT 24
Peak memory 207520 kb
Host smart-ae7963d4-9b20-492c-9882-fb30777a29b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561283048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
561283048
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3891118631
Short name T1032
Test name
Test status
Simulation time 11084366 ps
CPU time 0.7 seconds
Started Jul 16 07:46:47 PM PDT 24
Finished Jul 16 07:46:54 PM PDT 24
Peak memory 204264 kb
Host smart-aa1790b6-8de6-4d47-bde4-5c7920885475
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891118631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
891118631
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.20644703
Short name T1058
Test name
Test status
Simulation time 388477898 ps
CPU time 2.7 seconds
Started Jul 16 07:46:41 PM PDT 24
Finished Jul 16 07:46:45 PM PDT 24
Peak memory 215768 kb
Host smart-7a9c4900-c6ed-4b16-ba85-d3df41bdc4b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20644703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi
_device_same_csr_outstanding.20644703
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.618759538
Short name T91
Test name
Test status
Simulation time 43003325 ps
CPU time 1.26 seconds
Started Jul 16 07:46:43 PM PDT 24
Finished Jul 16 07:46:46 PM PDT 24
Peak memory 215964 kb
Host smart-c5d2737f-cb3e-44f9-b8c4-9e477037d19a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618759538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.618759538
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.714758930
Short name T146
Test name
Test status
Simulation time 737881947 ps
CPU time 17.83 seconds
Started Jul 16 07:46:42 PM PDT 24
Finished Jul 16 07:47:02 PM PDT 24
Peak memory 216204 kb
Host smart-a5bf4926-c5dc-4b5f-b9de-c2c52e14bde2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714758930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.714758930
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.479288614
Short name T1016
Test name
Test status
Simulation time 56976271 ps
CPU time 3.6 seconds
Started Jul 16 07:46:40 PM PDT 24
Finished Jul 16 07:46:45 PM PDT 24
Peak memory 217752 kb
Host smart-9b356980-d00c-4e7a-a661-5fd3f8bb9580
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479288614 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.479288614
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1238057496
Short name T115
Test name
Test status
Simulation time 40845833 ps
CPU time 1.35 seconds
Started Jul 16 07:46:47 PM PDT 24
Finished Jul 16 07:46:55 PM PDT 24
Peak memory 215596 kb
Host smart-5caac5c3-18be-4713-a43f-ec73f130d18b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238057496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
238057496
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3516149605
Short name T1012
Test name
Test status
Simulation time 43571327 ps
CPU time 0.71 seconds
Started Jul 16 07:46:46 PM PDT 24
Finished Jul 16 07:46:53 PM PDT 24
Peak memory 204568 kb
Host smart-0478a317-13a9-4422-90e8-10d61a113400
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516149605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
516149605
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4065975995
Short name T1029
Test name
Test status
Simulation time 515259158 ps
CPU time 3.47 seconds
Started Jul 16 07:46:40 PM PDT 24
Finished Jul 16 07:46:44 PM PDT 24
Peak memory 215780 kb
Host smart-f3a7dd91-b639-4081-badd-10c0d6cfa40d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065975995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.4065975995
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2858317168
Short name T1056
Test name
Test status
Simulation time 3743988504 ps
CPU time 5.91 seconds
Started Jul 16 07:46:49 PM PDT 24
Finished Jul 16 07:47:02 PM PDT 24
Peak memory 216988 kb
Host smart-2e094b72-42a4-46cf-a58f-b0b7eed52b22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858317168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
858317168
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2722894665
Short name T149
Test name
Test status
Simulation time 5800951870 ps
CPU time 18.57 seconds
Started Jul 16 07:46:51 PM PDT 24
Finished Jul 16 07:47:15 PM PDT 24
Peak memory 216156 kb
Host smart-cc61fdc7-52bd-49a5-b655-9e29cadfa5f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722894665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2722894665
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.997039917
Short name T711
Test name
Test status
Simulation time 55996049 ps
CPU time 0.71 seconds
Started Jul 16 07:59:33 PM PDT 24
Finished Jul 16 07:59:35 PM PDT 24
Peak memory 204896 kb
Host smart-73751a17-d4f7-42b2-a349-cd2e2e33a79a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997039917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.997039917
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1693162128
Short name T869
Test name
Test status
Simulation time 4144288711 ps
CPU time 7.47 seconds
Started Jul 16 07:59:32 PM PDT 24
Finished Jul 16 07:59:40 PM PDT 24
Peak memory 224564 kb
Host smart-799068c1-ebe3-404e-a587-7ca8749b4ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693162128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1693162128
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3859570209
Short name T796
Test name
Test status
Simulation time 50047427 ps
CPU time 0.79 seconds
Started Jul 16 07:59:15 PM PDT 24
Finished Jul 16 07:59:21 PM PDT 24
Peak memory 206632 kb
Host smart-64db7fe2-e227-4b3f-974c-573a4ca1832f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859570209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3859570209
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2252943970
Short name T5
Test name
Test status
Simulation time 1731867916 ps
CPU time 31.45 seconds
Started Jul 16 07:59:36 PM PDT 24
Finished Jul 16 08:00:08 PM PDT 24
Peak memory 254576 kb
Host smart-7ab9f210-6441-476a-9344-9bf8a0781a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252943970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2252943970
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3575451950
Short name T988
Test name
Test status
Simulation time 106163528003 ps
CPU time 171.9 seconds
Started Jul 16 07:59:26 PM PDT 24
Finished Jul 16 08:02:20 PM PDT 24
Peak memory 249276 kb
Host smart-7df495db-a4ee-4d05-a0e2-5c8af6095f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575451950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3575451950
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.472414160
Short name T783
Test name
Test status
Simulation time 3377302115 ps
CPU time 12.49 seconds
Started Jul 16 07:59:31 PM PDT 24
Finished Jul 16 07:59:45 PM PDT 24
Peak memory 224612 kb
Host smart-0e862cd7-f75e-4a2d-b5f2-a8187753edc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472414160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.472414160
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1642987731
Short name T487
Test name
Test status
Simulation time 133251897 ps
CPU time 2.52 seconds
Started Jul 16 07:59:27 PM PDT 24
Finished Jul 16 07:59:32 PM PDT 24
Peak memory 232356 kb
Host smart-a00185ea-5a1c-4a68-a533-493ceffa16b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642987731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1642987731
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.855319354
Short name T808
Test name
Test status
Simulation time 626941637 ps
CPU time 2.94 seconds
Started Jul 16 07:59:27 PM PDT 24
Finished Jul 16 07:59:32 PM PDT 24
Peak memory 232676 kb
Host smart-d7eb6173-e8f9-4ef7-9f2a-0a18dfcdd625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855319354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
855319354
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.4183675903
Short name T6
Test name
Test status
Simulation time 197532269 ps
CPU time 2.32 seconds
Started Jul 16 07:59:48 PM PDT 24
Finished Jul 16 07:59:53 PM PDT 24
Peak memory 223956 kb
Host smart-845c5373-d21d-4806-b5a7-cf9edb721cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183675903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.4183675903
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2057602398
Short name T338
Test name
Test status
Simulation time 1423604771 ps
CPU time 8.25 seconds
Started Jul 16 07:59:26 PM PDT 24
Finished Jul 16 07:59:36 PM PDT 24
Peak memory 219364 kb
Host smart-3a2d9225-4ec3-4dbd-9fb5-1dede3035819
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2057602398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2057602398
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.4262595586
Short name T954
Test name
Test status
Simulation time 3596026590 ps
CPU time 21.3 seconds
Started Jul 16 07:59:25 PM PDT 24
Finished Jul 16 07:59:49 PM PDT 24
Peak memory 216428 kb
Host smart-7456be98-3051-43b8-867d-3e764082433c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262595586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.4262595586
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3655891050
Short name T537
Test name
Test status
Simulation time 4151679425 ps
CPU time 13.74 seconds
Started Jul 16 07:59:31 PM PDT 24
Finished Jul 16 07:59:46 PM PDT 24
Peak memory 216372 kb
Host smart-f295e2c1-d7f7-44a4-8309-2dcbb4e06960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655891050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3655891050
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3049061457
Short name T800
Test name
Test status
Simulation time 86770169 ps
CPU time 1.13 seconds
Started Jul 16 07:59:25 PM PDT 24
Finished Jul 16 07:59:28 PM PDT 24
Peak memory 207908 kb
Host smart-c0891e64-0a22-4dcd-98f2-4312dd921af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049061457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3049061457
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2954911082
Short name T522
Test name
Test status
Simulation time 111970937 ps
CPU time 0.9 seconds
Started Jul 16 07:59:51 PM PDT 24
Finished Jul 16 07:59:53 PM PDT 24
Peak memory 206004 kb
Host smart-51c99ad5-2a64-420c-924b-12d8daa19682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954911082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2954911082
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1497756486
Short name T171
Test name
Test status
Simulation time 1339225026 ps
CPU time 8.61 seconds
Started Jul 16 07:59:47 PM PDT 24
Finished Jul 16 07:59:58 PM PDT 24
Peak memory 232684 kb
Host smart-0ef27f69-7361-4e17-a369-8c7d8297483e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497756486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1497756486
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3997072903
Short name T358
Test name
Test status
Simulation time 33671187 ps
CPU time 0.73 seconds
Started Jul 16 07:59:26 PM PDT 24
Finished Jul 16 07:59:29 PM PDT 24
Peak memory 205036 kb
Host smart-4c7ed893-6252-423c-bf05-1c21a79de3e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997072903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
997072903
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3383138960
Short name T995
Test name
Test status
Simulation time 1833618285 ps
CPU time 3.38 seconds
Started Jul 16 07:59:27 PM PDT 24
Finished Jul 16 07:59:33 PM PDT 24
Peak memory 224592 kb
Host smart-9368858a-542e-4e40-9bfe-0a7a62d49fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383138960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3383138960
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.4293684702
Short name T495
Test name
Test status
Simulation time 22062741 ps
CPU time 0.84 seconds
Started Jul 16 07:59:46 PM PDT 24
Finished Jul 16 07:59:49 PM PDT 24
Peak memory 206912 kb
Host smart-ac7b3aa7-a535-4cb6-b5a0-5161e891ba9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293684702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.4293684702
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3292307295
Short name T363
Test name
Test status
Simulation time 4681870038 ps
CPU time 50.38 seconds
Started Jul 16 07:59:28 PM PDT 24
Finished Jul 16 08:00:21 PM PDT 24
Peak memory 249204 kb
Host smart-8a3f0160-f8d0-4377-a5a1-39f73cef27f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292307295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3292307295
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1279257882
Short name T38
Test name
Test status
Simulation time 75629448836 ps
CPU time 177.36 seconds
Started Jul 16 07:59:24 PM PDT 24
Finished Jul 16 08:02:22 PM PDT 24
Peak memory 257480 kb
Host smart-020f2d0d-48da-4ec0-bc70-75fc4a37fd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279257882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1279257882
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3134639976
Short name T892
Test name
Test status
Simulation time 2247842568 ps
CPU time 54.24 seconds
Started Jul 16 07:59:26 PM PDT 24
Finished Jul 16 08:00:22 PM PDT 24
Peak memory 250628 kb
Host smart-29af831b-e9a6-407b-9820-636c9af424b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134639976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3134639976
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1718489618
Short name T690
Test name
Test status
Simulation time 542920797 ps
CPU time 7.28 seconds
Started Jul 16 07:59:26 PM PDT 24
Finished Jul 16 07:59:35 PM PDT 24
Peak memory 224480 kb
Host smart-a6602156-fdb3-4332-909a-d065138bc136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718489618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1718489618
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.1013710809
Short name T210
Test name
Test status
Simulation time 17315402686 ps
CPU time 69.63 seconds
Started Jul 16 07:59:27 PM PDT 24
Finished Jul 16 08:00:40 PM PDT 24
Peak memory 255004 kb
Host smart-28fd66dc-30ec-4c20-ad02-0a932845a058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013710809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.1013710809
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2564222763
Short name T559
Test name
Test status
Simulation time 470200126 ps
CPU time 6.98 seconds
Started Jul 16 07:59:31 PM PDT 24
Finished Jul 16 07:59:39 PM PDT 24
Peak memory 224444 kb
Host smart-8e73909f-35ee-4c31-bdac-abfbd71f3ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564222763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2564222763
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1700083231
Short name T19
Test name
Test status
Simulation time 5412690268 ps
CPU time 18.3 seconds
Started Jul 16 07:59:43 PM PDT 24
Finished Jul 16 08:00:02 PM PDT 24
Peak memory 239396 kb
Host smart-212521df-941e-4db3-ba45-521857f429f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700083231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1700083231
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3329442861
Short name T489
Test name
Test status
Simulation time 306322169 ps
CPU time 3.09 seconds
Started Jul 16 07:59:28 PM PDT 24
Finished Jul 16 07:59:34 PM PDT 24
Peak memory 224424 kb
Host smart-925b597b-bcb6-416c-aca0-40dcd29a6a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329442861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3329442861
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2813345594
Short name T336
Test name
Test status
Simulation time 1149103471 ps
CPU time 3.46 seconds
Started Jul 16 07:59:25 PM PDT 24
Finished Jul 16 07:59:31 PM PDT 24
Peak memory 224448 kb
Host smart-5148c5d6-4e6d-4bc3-bd5c-bb24c922ed47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813345594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2813345594
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1301887615
Short name T67
Test name
Test status
Simulation time 235994166 ps
CPU time 1.08 seconds
Started Jul 16 07:59:34 PM PDT 24
Finished Jul 16 07:59:36 PM PDT 24
Peak memory 236592 kb
Host smart-6e2462c6-d5c5-4136-bdd6-ba98848e4c62
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301887615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1301887615
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1792423638
Short name T732
Test name
Test status
Simulation time 559822714 ps
CPU time 6.72 seconds
Started Jul 16 07:59:32 PM PDT 24
Finished Jul 16 07:59:40 PM PDT 24
Peak memory 216140 kb
Host smart-7537b6b4-c86c-452e-bc31-a6a2f9acba1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792423638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1792423638
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3561067470
Short name T553
Test name
Test status
Simulation time 423576144 ps
CPU time 1.63 seconds
Started Jul 16 07:59:33 PM PDT 24
Finished Jul 16 07:59:35 PM PDT 24
Peak memory 207832 kb
Host smart-8f66f13e-66b0-4ce6-a9cb-603a97fedec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561067470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3561067470
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3607291143
Short name T25
Test name
Test status
Simulation time 91673815 ps
CPU time 2.79 seconds
Started Jul 16 07:59:24 PM PDT 24
Finished Jul 16 07:59:29 PM PDT 24
Peak memory 216236 kb
Host smart-391e6d66-03d8-4e3f-b8ea-308659e2258d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607291143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3607291143
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.755592922
Short name T822
Test name
Test status
Simulation time 250452352 ps
CPU time 0.88 seconds
Started Jul 16 07:59:32 PM PDT 24
Finished Jul 16 07:59:34 PM PDT 24
Peak memory 206208 kb
Host smart-552dae6c-7769-4296-a72e-bb7636708de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755592922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.755592922
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1371053572
Short name T362
Test name
Test status
Simulation time 317565903 ps
CPU time 3.75 seconds
Started Jul 16 07:59:25 PM PDT 24
Finished Jul 16 07:59:31 PM PDT 24
Peak memory 232624 kb
Host smart-05d642bc-f780-46fd-9fe5-fdb299aa8ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371053572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1371053572
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2556408438
Short name T484
Test name
Test status
Simulation time 25633842 ps
CPU time 0.74 seconds
Started Jul 16 07:59:58 PM PDT 24
Finished Jul 16 08:00:02 PM PDT 24
Peak memory 205888 kb
Host smart-c5b4d9c7-44f4-49cf-82ec-82492ac634fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556408438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2556408438
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.138188728
Short name T838
Test name
Test status
Simulation time 96133856 ps
CPU time 2.22 seconds
Started Jul 16 08:00:05 PM PDT 24
Finished Jul 16 08:00:12 PM PDT 24
Peak memory 223532 kb
Host smart-83d5ac0c-7fc9-4452-85ad-42ed3c847612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138188728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.138188728
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.412253120
Short name T948
Test name
Test status
Simulation time 48223989 ps
CPU time 0.8 seconds
Started Jul 16 08:00:01 PM PDT 24
Finished Jul 16 08:00:07 PM PDT 24
Peak memory 206620 kb
Host smart-7b9dbd50-8c34-4bdc-be98-bf67e3aa9fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412253120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.412253120
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2809133926
Short name T867
Test name
Test status
Simulation time 8760005562 ps
CPU time 50.7 seconds
Started Jul 16 08:00:00 PM PDT 24
Finished Jul 16 08:00:55 PM PDT 24
Peak memory 252228 kb
Host smart-2ed497c3-1597-4867-953a-5e2ac2b4e4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809133926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2809133926
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2628793681
Short name T602
Test name
Test status
Simulation time 3347936474 ps
CPU time 66.14 seconds
Started Jul 16 08:00:02 PM PDT 24
Finished Jul 16 08:01:13 PM PDT 24
Peak memory 249652 kb
Host smart-f245e976-2dd1-41cd-9920-447bb20d5921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628793681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2628793681
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2094894472
Short name T460
Test name
Test status
Simulation time 4006682253 ps
CPU time 48.83 seconds
Started Jul 16 08:00:05 PM PDT 24
Finished Jul 16 08:00:58 PM PDT 24
Peak memory 252352 kb
Host smart-bbc15460-171d-4815-9880-61868cb70121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094894472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2094894472
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.2007915269
Short name T816
Test name
Test status
Simulation time 22803367491 ps
CPU time 64.16 seconds
Started Jul 16 08:00:05 PM PDT 24
Finished Jul 16 08:01:14 PM PDT 24
Peak memory 251220 kb
Host smart-767c1da4-8cc4-4127-8506-6c37b84e676b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007915269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.2007915269
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1129778902
Short name T1001
Test name
Test status
Simulation time 6810327504 ps
CPU time 11.9 seconds
Started Jul 16 07:59:58 PM PDT 24
Finished Jul 16 08:00:13 PM PDT 24
Peak memory 232776 kb
Host smart-1f31abe4-7c54-4fae-bfee-6f7122dd9e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129778902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1129778902
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.985328343
Short name T708
Test name
Test status
Simulation time 8345177661 ps
CPU time 51.65 seconds
Started Jul 16 08:00:06 PM PDT 24
Finished Jul 16 08:01:02 PM PDT 24
Peak memory 232504 kb
Host smart-fbeab764-ee3f-409f-bc5e-d108470244e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985328343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.985328343
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2470335155
Short name T927
Test name
Test status
Simulation time 5212022973 ps
CPU time 10.06 seconds
Started Jul 16 08:00:03 PM PDT 24
Finished Jul 16 08:00:18 PM PDT 24
Peak memory 232292 kb
Host smart-0eb3fe60-8077-4bb6-8e46-3bfbf584e598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470335155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2470335155
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3588840506
Short name T419
Test name
Test status
Simulation time 169276338 ps
CPU time 4.36 seconds
Started Jul 16 08:00:05 PM PDT 24
Finished Jul 16 08:00:14 PM PDT 24
Peak memory 232592 kb
Host smart-c8ce2130-ec7e-4694-ab58-86be2a49844e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588840506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3588840506
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.213655950
Short name T962
Test name
Test status
Simulation time 898250098 ps
CPU time 4.47 seconds
Started Jul 16 08:00:00 PM PDT 24
Finished Jul 16 08:00:08 PM PDT 24
Peak memory 222960 kb
Host smart-dde0650a-ae6c-4f4a-8c00-403873da6d7f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=213655950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.213655950
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2168168158
Short name T950
Test name
Test status
Simulation time 71729486 ps
CPU time 1.28 seconds
Started Jul 16 08:00:02 PM PDT 24
Finished Jul 16 08:00:08 PM PDT 24
Peak memory 215124 kb
Host smart-b9bae459-db61-4777-be8f-febe5d080f1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168168158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2168168158
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2766611890
Short name T865
Test name
Test status
Simulation time 36509725098 ps
CPU time 43.11 seconds
Started Jul 16 08:00:01 PM PDT 24
Finished Jul 16 08:00:48 PM PDT 24
Peak memory 216304 kb
Host smart-def5ea8f-a68a-4cea-894e-e4938377ab03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766611890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2766611890
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.21214871
Short name T624
Test name
Test status
Simulation time 2717872102 ps
CPU time 4.51 seconds
Started Jul 16 08:00:03 PM PDT 24
Finished Jul 16 08:00:13 PM PDT 24
Peak memory 216324 kb
Host smart-dcd76582-f248-4d1f-bc0a-40b609123241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21214871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.21214871
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.746956000
Short name T873
Test name
Test status
Simulation time 26732132 ps
CPU time 0.93 seconds
Started Jul 16 07:59:59 PM PDT 24
Finished Jul 16 08:00:02 PM PDT 24
Peak memory 206864 kb
Host smart-f1288f10-b8cf-4dd4-bc2d-1f88e8428715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746956000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.746956000
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3520343665
Short name T614
Test name
Test status
Simulation time 16879514 ps
CPU time 0.76 seconds
Started Jul 16 07:59:59 PM PDT 24
Finished Jul 16 08:00:02 PM PDT 24
Peak memory 205912 kb
Host smart-25591cab-1be9-4e38-b232-f12e77332c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520343665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3520343665
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.4216509087
Short name T692
Test name
Test status
Simulation time 10007928278 ps
CPU time 8.86 seconds
Started Jul 16 07:59:59 PM PDT 24
Finished Jul 16 08:00:10 PM PDT 24
Peak memory 232800 kb
Host smart-71c35ef6-c9bf-4718-bfc9-fc9dccd88c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216509087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.4216509087
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.4241062013
Short name T350
Test name
Test status
Simulation time 47266803 ps
CPU time 0.78 seconds
Started Jul 16 08:00:06 PM PDT 24
Finished Jul 16 08:00:11 PM PDT 24
Peak memory 205856 kb
Host smart-e1f5a764-dc3a-43c8-b0fd-decf24d43a91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241062013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
4241062013
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.4267216364
Short name T311
Test name
Test status
Simulation time 869222716 ps
CPU time 3.52 seconds
Started Jul 16 08:00:01 PM PDT 24
Finished Jul 16 08:00:09 PM PDT 24
Peak memory 232652 kb
Host smart-3e9931a4-9d99-4827-9511-9bc095d63a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267216364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.4267216364
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.497689979
Short name T352
Test name
Test status
Simulation time 13229905 ps
CPU time 0.8 seconds
Started Jul 16 08:00:01 PM PDT 24
Finished Jul 16 08:00:06 PM PDT 24
Peak memory 206564 kb
Host smart-315f50f5-4814-4546-a615-49f8130441dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497689979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.497689979
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2547350078
Short name T891
Test name
Test status
Simulation time 11521142885 ps
CPU time 119.36 seconds
Started Jul 16 08:00:05 PM PDT 24
Finished Jul 16 08:02:09 PM PDT 24
Peak memory 252320 kb
Host smart-c793f107-70c2-4999-a0fe-dcffc41220cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547350078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2547350078
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.4044840805
Short name T113
Test name
Test status
Simulation time 26974042168 ps
CPU time 248.83 seconds
Started Jul 16 08:00:04 PM PDT 24
Finished Jul 16 08:04:18 PM PDT 24
Peak memory 257424 kb
Host smart-072bee2f-614d-4e22-a999-5f333d835046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044840805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.4044840805
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.556065033
Short name T874
Test name
Test status
Simulation time 5728070887 ps
CPU time 75.37 seconds
Started Jul 16 08:00:05 PM PDT 24
Finished Jul 16 08:01:25 PM PDT 24
Peak memory 260408 kb
Host smart-6d8104d4-be70-4ab3-9033-5a9b5399685c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556065033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.556065033
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3923545422
Short name T833
Test name
Test status
Simulation time 380767102 ps
CPU time 7.07 seconds
Started Jul 16 08:00:04 PM PDT 24
Finished Jul 16 08:00:16 PM PDT 24
Peak memory 232656 kb
Host smart-57930159-1368-4a8c-86a0-46373d0b7629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923545422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3923545422
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.446109791
Short name T777
Test name
Test status
Simulation time 1379876494 ps
CPU time 4.55 seconds
Started Jul 16 07:59:58 PM PDT 24
Finished Jul 16 08:00:05 PM PDT 24
Peak memory 232656 kb
Host smart-75a8466c-e6b2-4ccc-aaaf-7a54b26df093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446109791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.446109791
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2589283775
Short name T653
Test name
Test status
Simulation time 201932214 ps
CPU time 2.38 seconds
Started Jul 16 08:00:02 PM PDT 24
Finished Jul 16 08:00:09 PM PDT 24
Peak memory 223836 kb
Host smart-5f0c3e8c-d037-44a0-a314-4281a6466c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589283775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2589283775
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2823917590
Short name T80
Test name
Test status
Simulation time 15261253808 ps
CPU time 12.57 seconds
Started Jul 16 08:00:00 PM PDT 24
Finished Jul 16 08:00:17 PM PDT 24
Peak memory 224584 kb
Host smart-6e1baf45-f41e-41a6-86da-9a148d26cb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823917590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2823917590
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2914235811
Short name T807
Test name
Test status
Simulation time 27201852328 ps
CPU time 26.75 seconds
Started Jul 16 08:00:01 PM PDT 24
Finished Jul 16 08:00:33 PM PDT 24
Peak memory 248996 kb
Host smart-c6a10df5-216f-4bbc-b040-65c715257521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914235811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2914235811
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1981473016
Short name T581
Test name
Test status
Simulation time 5574404061 ps
CPU time 5.46 seconds
Started Jul 16 08:00:05 PM PDT 24
Finished Jul 16 08:00:15 PM PDT 24
Peak memory 219124 kb
Host smart-fe441923-471c-4569-8214-c235db14972b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1981473016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1981473016
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.711429949
Short name T372
Test name
Test status
Simulation time 2031423209 ps
CPU time 32.33 seconds
Started Jul 16 08:00:05 PM PDT 24
Finished Jul 16 08:00:42 PM PDT 24
Peak memory 249192 kb
Host smart-6c8e8343-7a55-40bd-b065-352b8eb3a11c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711429949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.711429949
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3658895264
Short name T842
Test name
Test status
Simulation time 7417974906 ps
CPU time 39.16 seconds
Started Jul 16 08:00:02 PM PDT 24
Finished Jul 16 08:00:46 PM PDT 24
Peak memory 216360 kb
Host smart-321e9e5d-78a6-46d3-a286-44f5158a3a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658895264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3658895264
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2171283418
Short name T734
Test name
Test status
Simulation time 3624663234 ps
CPU time 14.83 seconds
Started Jul 16 07:59:58 PM PDT 24
Finished Jul 16 08:00:15 PM PDT 24
Peak memory 216352 kb
Host smart-285a0827-c62f-42f7-8083-ff994a49626d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171283418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2171283418
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1839307764
Short name T621
Test name
Test status
Simulation time 374112053 ps
CPU time 1 seconds
Started Jul 16 08:00:03 PM PDT 24
Finished Jul 16 08:00:09 PM PDT 24
Peak memory 206744 kb
Host smart-4e0b5751-07bc-4bee-82e7-c87c821e78a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839307764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1839307764
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1805172136
Short name T304
Test name
Test status
Simulation time 151863143 ps
CPU time 0.99 seconds
Started Jul 16 08:00:03 PM PDT 24
Finished Jul 16 08:00:09 PM PDT 24
Peak memory 205976 kb
Host smart-e5b688cc-cf4a-4645-be13-870dbe826846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805172136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1805172136
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.426951894
Short name T955
Test name
Test status
Simulation time 144590031 ps
CPU time 2.26 seconds
Started Jul 16 08:00:04 PM PDT 24
Finished Jul 16 08:00:11 PM PDT 24
Peak memory 232592 kb
Host smart-1800a7d6-c340-41db-9461-a3841b8e537d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426951894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.426951894
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3479441715
Short name T720
Test name
Test status
Simulation time 12182005 ps
CPU time 0.71 seconds
Started Jul 16 08:00:12 PM PDT 24
Finished Jul 16 08:00:14 PM PDT 24
Peak memory 205484 kb
Host smart-2a944fd7-f20a-4fc2-957b-604e19661600
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479441715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3479441715
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1377136667
Short name T619
Test name
Test status
Simulation time 924219357 ps
CPU time 3.72 seconds
Started Jul 16 08:00:12 PM PDT 24
Finished Jul 16 08:00:17 PM PDT 24
Peak memory 232696 kb
Host smart-829eee22-e570-4465-b40e-7e933e07ecc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377136667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1377136667
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.449223168
Short name T947
Test name
Test status
Simulation time 15557262 ps
CPU time 0.8 seconds
Started Jul 16 08:00:05 PM PDT 24
Finished Jul 16 08:00:11 PM PDT 24
Peak memory 205816 kb
Host smart-c0e0e136-1530-4cc8-bc33-321fee73a653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449223168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.449223168
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3227071693
Short name T411
Test name
Test status
Simulation time 164671907890 ps
CPU time 145.43 seconds
Started Jul 16 08:00:15 PM PDT 24
Finished Jul 16 08:02:42 PM PDT 24
Peak memory 251092 kb
Host smart-2e74a022-67cc-49e3-8340-4971f9673e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227071693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3227071693
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1753401894
Short name T805
Test name
Test status
Simulation time 19289377493 ps
CPU time 146.17 seconds
Started Jul 16 08:00:13 PM PDT 24
Finished Jul 16 08:02:47 PM PDT 24
Peak memory 252036 kb
Host smart-3be43f6e-07fc-49de-9439-7c54c86dc98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753401894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1753401894
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2773768607
Short name T597
Test name
Test status
Simulation time 51731913318 ps
CPU time 134.09 seconds
Started Jul 16 08:00:29 PM PDT 24
Finished Jul 16 08:02:44 PM PDT 24
Peak memory 257388 kb
Host smart-d51534fe-d85d-4beb-9e61-a6491a109aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773768607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2773768607
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3064747483
Short name T263
Test name
Test status
Simulation time 703790534 ps
CPU time 8.32 seconds
Started Jul 16 08:00:13 PM PDT 24
Finished Jul 16 08:00:23 PM PDT 24
Peak memory 236944 kb
Host smart-671342d0-06e7-47a9-8177-85204c4ec8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064747483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3064747483
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3181672826
Short name T688
Test name
Test status
Simulation time 809978971 ps
CPU time 5.5 seconds
Started Jul 16 08:00:14 PM PDT 24
Finished Jul 16 08:00:22 PM PDT 24
Peak memory 224600 kb
Host smart-763a9be2-0c3a-44cd-b0bd-121221b82e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181672826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3181672826
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2686064120
Short name T686
Test name
Test status
Simulation time 10765943165 ps
CPU time 64.19 seconds
Started Jul 16 08:00:13 PM PDT 24
Finished Jul 16 08:01:18 PM PDT 24
Peak memory 224548 kb
Host smart-602593f3-3e65-4314-9525-90062e699dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686064120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2686064120
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1169085815
Short name T831
Test name
Test status
Simulation time 2347060777 ps
CPU time 7.66 seconds
Started Jul 16 08:00:17 PM PDT 24
Finished Jul 16 08:00:28 PM PDT 24
Peak memory 232772 kb
Host smart-24e9b45b-1941-4f0e-9f59-a2c347c24c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169085815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1169085815
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1268806440
Short name T449
Test name
Test status
Simulation time 31237517 ps
CPU time 2.28 seconds
Started Jul 16 08:00:13 PM PDT 24
Finished Jul 16 08:00:16 PM PDT 24
Peak memory 232360 kb
Host smart-ab9d5d17-7b56-4e3b-88b7-d4ced77b8e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268806440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1268806440
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3512013420
Short name T707
Test name
Test status
Simulation time 689453863 ps
CPU time 10.07 seconds
Started Jul 16 08:00:16 PM PDT 24
Finished Jul 16 08:00:28 PM PDT 24
Peak memory 222412 kb
Host smart-e485e526-3172-41ba-9229-4c5d1b68df85
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3512013420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3512013420
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3772419698
Short name T342
Test name
Test status
Simulation time 41632053 ps
CPU time 0.73 seconds
Started Jul 16 08:00:02 PM PDT 24
Finished Jul 16 08:00:08 PM PDT 24
Peak memory 205804 kb
Host smart-8e1a2800-091c-408d-aed7-a66b6236d23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772419698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3772419698
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3436166146
Short name T918
Test name
Test status
Simulation time 2552850814 ps
CPU time 4.82 seconds
Started Jul 16 08:00:05 PM PDT 24
Finished Jul 16 08:00:15 PM PDT 24
Peak memory 216360 kb
Host smart-0815a3dc-4fea-43c0-afef-cf12eebb0b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436166146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3436166146
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.787901804
Short name T864
Test name
Test status
Simulation time 589992107 ps
CPU time 1.36 seconds
Started Jul 16 08:00:07 PM PDT 24
Finished Jul 16 08:00:12 PM PDT 24
Peak memory 216212 kb
Host smart-e14478c3-b997-47d9-bf5f-10f125158430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787901804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.787901804
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2537944659
Short name T547
Test name
Test status
Simulation time 87794030 ps
CPU time 0.96 seconds
Started Jul 16 08:00:02 PM PDT 24
Finished Jul 16 08:00:08 PM PDT 24
Peak memory 206484 kb
Host smart-f4bff9b8-95d6-48eb-bd84-80ade06db58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537944659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2537944659
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.3107749223
Short name T529
Test name
Test status
Simulation time 4709359541 ps
CPU time 20.65 seconds
Started Jul 16 08:00:14 PM PDT 24
Finished Jul 16 08:00:36 PM PDT 24
Peak memory 232760 kb
Host smart-e75664ef-c5fe-4dd7-adfd-80a1254a174d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107749223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3107749223
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.337790016
Short name T344
Test name
Test status
Simulation time 13301311 ps
CPU time 0.75 seconds
Started Jul 16 08:00:33 PM PDT 24
Finished Jul 16 08:00:36 PM PDT 24
Peak memory 205548 kb
Host smart-6f494831-bc17-4dd7-8dbe-0a267b21a0f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337790016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.337790016
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2555954638
Short name T841
Test name
Test status
Simulation time 768245399 ps
CPU time 4.92 seconds
Started Jul 16 08:00:21 PM PDT 24
Finished Jul 16 08:00:29 PM PDT 24
Peak memory 232624 kb
Host smart-5ced937e-63a5-47f1-b77b-a832edb30f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555954638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2555954638
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2818694761
Short name T659
Test name
Test status
Simulation time 19273405 ps
CPU time 0.77 seconds
Started Jul 16 08:00:14 PM PDT 24
Finished Jul 16 08:00:16 PM PDT 24
Peak memory 206520 kb
Host smart-c132f905-f3ed-423c-9681-9a87c243a82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818694761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2818694761
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.572315078
Short name T176
Test name
Test status
Simulation time 3733037200 ps
CPU time 28.64 seconds
Started Jul 16 08:00:14 PM PDT 24
Finished Jul 16 08:00:44 PM PDT 24
Peak memory 234376 kb
Host smart-a060b7e9-ea9b-428b-89ef-1e4f702ffc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572315078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.572315078
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.4149429469
Short name T33
Test name
Test status
Simulation time 38030356939 ps
CPU time 80.8 seconds
Started Jul 16 08:00:11 PM PDT 24
Finished Jul 16 08:01:33 PM PDT 24
Peak memory 263288 kb
Host smart-3fec5a42-81db-4b62-934c-07e07e5f8085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149429469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.4149429469
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1109468565
Short name T574
Test name
Test status
Simulation time 10519531755 ps
CPU time 54.87 seconds
Started Jul 16 08:00:20 PM PDT 24
Finished Jul 16 08:01:18 PM PDT 24
Peak memory 249224 kb
Host smart-888a3ff3-00b8-400b-acb7-3115baf8ff29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109468565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1109468565
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1921422601
Short name T885
Test name
Test status
Simulation time 114879583 ps
CPU time 3.08 seconds
Started Jul 16 08:00:15 PM PDT 24
Finished Jul 16 08:00:20 PM PDT 24
Peak memory 224508 kb
Host smart-7d55df76-65f2-474e-b43a-32da40e09086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921422601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1921422601
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.1357787785
Short name T967
Test name
Test status
Simulation time 10825907913 ps
CPU time 26.63 seconds
Started Jul 16 08:00:22 PM PDT 24
Finished Jul 16 08:00:52 PM PDT 24
Peak memory 249208 kb
Host smart-36a50f0a-28a1-459f-89cd-8e67fe61fdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357787785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.1357787785
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1445529968
Short name T169
Test name
Test status
Simulation time 30955213 ps
CPU time 2.02 seconds
Started Jul 16 08:00:17 PM PDT 24
Finished Jul 16 08:00:22 PM PDT 24
Peak memory 224484 kb
Host smart-2a16aee1-d256-439e-bb3c-50a2dfc56cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445529968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1445529968
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3744408305
Short name T456
Test name
Test status
Simulation time 3864138531 ps
CPU time 19.33 seconds
Started Jul 16 08:00:33 PM PDT 24
Finished Jul 16 08:00:54 PM PDT 24
Peak memory 232852 kb
Host smart-6594d52b-b3a8-443a-9bc7-8da16a360a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744408305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3744408305
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1397687829
Short name T629
Test name
Test status
Simulation time 73243965 ps
CPU time 3 seconds
Started Jul 16 08:00:18 PM PDT 24
Finished Jul 16 08:00:24 PM PDT 24
Peak memory 224364 kb
Host smart-e530a8be-4739-4f18-b867-986b2a08c911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397687829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1397687829
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1109438218
Short name T222
Test name
Test status
Simulation time 325318516 ps
CPU time 5.36 seconds
Started Jul 16 08:00:11 PM PDT 24
Finished Jul 16 08:00:18 PM PDT 24
Peak memory 224476 kb
Host smart-723cb89c-0dc7-4291-9bfb-8683b9b0b27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109438218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1109438218
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1957887903
Short name T599
Test name
Test status
Simulation time 633853120 ps
CPU time 8.37 seconds
Started Jul 16 08:00:14 PM PDT 24
Finished Jul 16 08:00:24 PM PDT 24
Peak memory 220420 kb
Host smart-451b7334-e3bc-4730-b442-f3c8fe97eba3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1957887903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1957887903
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1801115691
Short name T973
Test name
Test status
Simulation time 2724376515 ps
CPU time 53.34 seconds
Started Jul 16 08:00:15 PM PDT 24
Finished Jul 16 08:01:10 PM PDT 24
Peak memory 256172 kb
Host smart-e9686bad-83d0-4c59-ba65-c757e3954125
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801115691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1801115691
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3876711380
Short name T853
Test name
Test status
Simulation time 5648707525 ps
CPU time 24.63 seconds
Started Jul 16 08:00:13 PM PDT 24
Finished Jul 16 08:00:39 PM PDT 24
Peak memory 216564 kb
Host smart-7cbddcd7-4eb5-4280-9b8f-b9d26e10f14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876711380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3876711380
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2963591460
Short name T792
Test name
Test status
Simulation time 2654296636 ps
CPU time 10.59 seconds
Started Jul 16 08:00:11 PM PDT 24
Finished Jul 16 08:00:23 PM PDT 24
Peak memory 216396 kb
Host smart-dfe57fcd-f311-4bf2-b438-098d7f707cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963591460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2963591460
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.4027383364
Short name T285
Test name
Test status
Simulation time 169272048 ps
CPU time 6.09 seconds
Started Jul 16 08:00:19 PM PDT 24
Finished Jul 16 08:00:28 PM PDT 24
Peak memory 216212 kb
Host smart-b608804f-a65c-45fe-ab35-4ac8809a1893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027383364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.4027383364
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.76470823
Short name T339
Test name
Test status
Simulation time 47190070 ps
CPU time 0.73 seconds
Started Jul 16 08:00:16 PM PDT 24
Finished Jul 16 08:00:19 PM PDT 24
Peak memory 206056 kb
Host smart-bb03921b-be54-4108-baa3-459f8bd71710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76470823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.76470823
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2341425811
Short name T628
Test name
Test status
Simulation time 222253614 ps
CPU time 3.01 seconds
Started Jul 16 08:00:15 PM PDT 24
Finished Jul 16 08:00:20 PM PDT 24
Peak memory 236572 kb
Host smart-2ae56bef-fe11-44e7-ab08-a3beeaf3f81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341425811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2341425811
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1751873844
Short name T1005
Test name
Test status
Simulation time 15177164 ps
CPU time 0.74 seconds
Started Jul 16 08:00:20 PM PDT 24
Finished Jul 16 08:00:24 PM PDT 24
Peak memory 205540 kb
Host smart-285294bb-c5b9-4cc7-90f5-f7fbe38fbe18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751873844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1751873844
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2689803263
Short name T207
Test name
Test status
Simulation time 581770626 ps
CPU time 3.84 seconds
Started Jul 16 08:00:22 PM PDT 24
Finished Jul 16 08:00:29 PM PDT 24
Peak memory 224496 kb
Host smart-05865dd9-34d5-423b-ae98-fa8b2cfb1cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689803263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2689803263
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1687772382
Short name T868
Test name
Test status
Simulation time 52955247 ps
CPU time 0.77 seconds
Started Jul 16 08:00:17 PM PDT 24
Finished Jul 16 08:00:21 PM PDT 24
Peak memory 206688 kb
Host smart-547d573b-974b-4aad-9a66-5d22e2978ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687772382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1687772382
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3662372808
Short name T909
Test name
Test status
Simulation time 81928502245 ps
CPU time 67.57 seconds
Started Jul 16 08:00:18 PM PDT 24
Finished Jul 16 08:01:28 PM PDT 24
Peak memory 250268 kb
Host smart-45b6ff5f-8972-42c3-8128-998b5fabccff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662372808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3662372808
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.402948918
Short name T970
Test name
Test status
Simulation time 15430286408 ps
CPU time 123.47 seconds
Started Jul 16 08:00:28 PM PDT 24
Finished Jul 16 08:02:33 PM PDT 24
Peak memory 254652 kb
Host smart-3f2bb991-91cb-4812-9220-a28bec1cbf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402948918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.402948918
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.489122767
Short name T122
Test name
Test status
Simulation time 226569369 ps
CPU time 4.07 seconds
Started Jul 16 08:00:18 PM PDT 24
Finished Jul 16 08:00:26 PM PDT 24
Peak memory 232600 kb
Host smart-35ff4b1c-ed99-4ee1-be88-2a196ba3b92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489122767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.489122767
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.347942571
Short name T859
Test name
Test status
Simulation time 264905707834 ps
CPU time 221.63 seconds
Started Jul 16 08:00:20 PM PDT 24
Finished Jul 16 08:04:05 PM PDT 24
Peak memory 249236 kb
Host smart-217a64a3-c544-489b-b602-7e3f9061f1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347942571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds
.347942571
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2224153690
Short name T693
Test name
Test status
Simulation time 162108471 ps
CPU time 3.74 seconds
Started Jul 16 08:00:17 PM PDT 24
Finished Jul 16 08:00:23 PM PDT 24
Peak memory 224528 kb
Host smart-29b5cb8b-d2ba-4616-a568-64ad69a2225b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224153690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2224153690
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1721772308
Short name T895
Test name
Test status
Simulation time 19681133834 ps
CPU time 44.24 seconds
Started Jul 16 08:00:17 PM PDT 24
Finished Jul 16 08:01:03 PM PDT 24
Peak memory 240768 kb
Host smart-b71c9f4f-b5f5-4a0e-8723-8648a8cd1675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721772308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1721772308
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3093321424
Short name T180
Test name
Test status
Simulation time 17844643791 ps
CPU time 29.4 seconds
Started Jul 16 08:00:21 PM PDT 24
Finished Jul 16 08:00:53 PM PDT 24
Peak memory 228404 kb
Host smart-ac9fdd6f-1f92-4e34-8cfe-7b7195c46e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093321424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3093321424
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.793225199
Short name T401
Test name
Test status
Simulation time 249555054 ps
CPU time 3.55 seconds
Started Jul 16 08:00:22 PM PDT 24
Finished Jul 16 08:00:29 PM PDT 24
Peak memory 224456 kb
Host smart-6302f12d-d71f-4e52-9de1-3fd192b2fed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793225199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.793225199
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3198440971
Short name T325
Test name
Test status
Simulation time 73886841 ps
CPU time 3.83 seconds
Started Jul 16 08:00:20 PM PDT 24
Finished Jul 16 08:00:26 PM PDT 24
Peak memory 223184 kb
Host smart-e7132429-522e-48c5-b248-d8918384d99c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3198440971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3198440971
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3723719282
Short name T35
Test name
Test status
Simulation time 22582623387 ps
CPU time 107.94 seconds
Started Jul 16 08:00:32 PM PDT 24
Finished Jul 16 08:02:22 PM PDT 24
Peak memory 249796 kb
Host smart-05597350-f78f-465a-98a6-50409e677991
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723719282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3723719282
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3812791144
Short name T680
Test name
Test status
Simulation time 9814553275 ps
CPU time 53.82 seconds
Started Jul 16 08:00:22 PM PDT 24
Finished Jul 16 08:01:19 PM PDT 24
Peak memory 216392 kb
Host smart-e2bf6e8a-7f26-441c-a8c7-b6c45053251c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812791144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3812791144
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3963375211
Short name T695
Test name
Test status
Simulation time 8980236664 ps
CPU time 8.11 seconds
Started Jul 16 08:00:16 PM PDT 24
Finished Jul 16 08:00:26 PM PDT 24
Peak memory 216340 kb
Host smart-b0e56759-6a75-4c60-8ee9-a4d1b7aa6628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963375211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3963375211
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.639114543
Short name T307
Test name
Test status
Simulation time 81726163 ps
CPU time 1.2 seconds
Started Jul 16 08:00:19 PM PDT 24
Finished Jul 16 08:00:24 PM PDT 24
Peak memory 216120 kb
Host smart-92e2a9f0-8fdb-448e-b5c0-252c2d5c416f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639114543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.639114543
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1426838761
Short name T598
Test name
Test status
Simulation time 16544939 ps
CPU time 0.76 seconds
Started Jul 16 08:00:19 PM PDT 24
Finished Jul 16 08:00:23 PM PDT 24
Peak memory 206000 kb
Host smart-2f6cf2b6-a132-400a-bba2-1af84a8e3f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426838761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1426838761
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1000782950
Short name T911
Test name
Test status
Simulation time 11686855132 ps
CPU time 10.71 seconds
Started Jul 16 08:00:18 PM PDT 24
Finished Jul 16 08:00:31 PM PDT 24
Peak memory 224564 kb
Host smart-95ab2870-b9d9-4242-b0e1-dc72d5533c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000782950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1000782950
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.901951105
Short name T97
Test name
Test status
Simulation time 125784883 ps
CPU time 3.27 seconds
Started Jul 16 08:00:35 PM PDT 24
Finished Jul 16 08:00:41 PM PDT 24
Peak memory 232664 kb
Host smart-153a153c-d2df-4685-96ec-2df304f42e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901951105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.901951105
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.443004451
Short name T713
Test name
Test status
Simulation time 41421618 ps
CPU time 0.74 seconds
Started Jul 16 08:00:27 PM PDT 24
Finished Jul 16 08:00:29 PM PDT 24
Peak memory 206604 kb
Host smart-02098662-353c-4f32-a599-076311862f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443004451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.443004451
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2501431042
Short name T199
Test name
Test status
Simulation time 128320933405 ps
CPU time 366.89 seconds
Started Jul 16 08:00:37 PM PDT 24
Finished Jul 16 08:06:47 PM PDT 24
Peak memory 256988 kb
Host smart-85175018-f00f-4a4b-b34e-1c12cc53fe5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501431042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2501431042
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.497819278
Short name T174
Test name
Test status
Simulation time 155121795760 ps
CPU time 316.44 seconds
Started Jul 16 08:00:36 PM PDT 24
Finished Jul 16 08:05:56 PM PDT 24
Peak memory 251200 kb
Host smart-b2dc38ce-d0c6-4e47-a45c-aad84fa050c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497819278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.497819278
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2180258417
Short name T112
Test name
Test status
Simulation time 70639251831 ps
CPU time 186.24 seconds
Started Jul 16 08:00:23 PM PDT 24
Finished Jul 16 08:03:33 PM PDT 24
Peak memory 254556 kb
Host smart-0d1fb82b-b326-48b5-a7df-1a232eb3243c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180258417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2180258417
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1630853127
Short name T443
Test name
Test status
Simulation time 77229075 ps
CPU time 3.39 seconds
Started Jul 16 08:00:17 PM PDT 24
Finished Jul 16 08:00:23 PM PDT 24
Peak memory 232688 kb
Host smart-08b722c6-54bd-4956-a122-aadfc6b62172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630853127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1630853127
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.2971073653
Short name T882
Test name
Test status
Simulation time 5024912944 ps
CPU time 69.77 seconds
Started Jul 16 08:00:24 PM PDT 24
Finished Jul 16 08:01:36 PM PDT 24
Peak memory 249208 kb
Host smart-f3347dea-0349-42a0-9a08-1015ce54d617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971073653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.2971073653
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.456373251
Short name T706
Test name
Test status
Simulation time 2025542355 ps
CPU time 7.8 seconds
Started Jul 16 08:00:28 PM PDT 24
Finished Jul 16 08:00:38 PM PDT 24
Peak memory 224444 kb
Host smart-2f8fc09b-6f9f-4fae-98d2-5171da13eaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456373251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.456373251
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.114584448
Short name T189
Test name
Test status
Simulation time 17683062837 ps
CPU time 48.84 seconds
Started Jul 16 08:00:21 PM PDT 24
Finished Jul 16 08:01:13 PM PDT 24
Peak memory 239700 kb
Host smart-3c70d062-040a-4cee-8adf-39aa87d87006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114584448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.114584448
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.699032615
Short name T999
Test name
Test status
Simulation time 1819409035 ps
CPU time 3.55 seconds
Started Jul 16 08:00:34 PM PDT 24
Finished Jul 16 08:00:39 PM PDT 24
Peak memory 224384 kb
Host smart-e7fecfc4-c3d8-47a7-9c94-efd69c61ca32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699032615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.699032615
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.4025647978
Short name T201
Test name
Test status
Simulation time 3383471578 ps
CPU time 4.83 seconds
Started Jul 16 08:00:22 PM PDT 24
Finished Jul 16 08:00:30 PM PDT 24
Peak memory 232772 kb
Host smart-2e363c06-241b-4efe-a847-950351849d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025647978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.4025647978
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1133163071
Short name T648
Test name
Test status
Simulation time 353401030 ps
CPU time 3.97 seconds
Started Jul 16 08:00:23 PM PDT 24
Finished Jul 16 08:00:30 PM PDT 24
Peak memory 223188 kb
Host smart-a04334ea-c65d-476f-a9d3-71d31b2c805d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1133163071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1133163071
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1477366614
Short name T921
Test name
Test status
Simulation time 28632337825 ps
CPU time 38.52 seconds
Started Jul 16 08:00:14 PM PDT 24
Finished Jul 16 08:00:54 PM PDT 24
Peak memory 216324 kb
Host smart-244aae7d-b919-4b2e-a34f-b29f4c683fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477366614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1477366614
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.525792774
Short name T324
Test name
Test status
Simulation time 590788692 ps
CPU time 2.67 seconds
Started Jul 16 08:00:33 PM PDT 24
Finished Jul 16 08:00:37 PM PDT 24
Peak memory 216268 kb
Host smart-fd32362e-8fcd-4b73-81bf-e59f8945dd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525792774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.525792774
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2286860471
Short name T564
Test name
Test status
Simulation time 33956172 ps
CPU time 0.91 seconds
Started Jul 16 08:00:21 PM PDT 24
Finished Jul 16 08:00:25 PM PDT 24
Peak memory 206664 kb
Host smart-70e41557-0449-4c26-8a15-cae521783a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286860471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2286860471
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2898621679
Short name T424
Test name
Test status
Simulation time 120777022 ps
CPU time 0.91 seconds
Started Jul 16 08:00:20 PM PDT 24
Finished Jul 16 08:00:23 PM PDT 24
Peak memory 205980 kb
Host smart-0c9f1249-d1f2-427c-97c2-a81d333fb09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898621679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2898621679
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3999874497
Short name T196
Test name
Test status
Simulation time 780962913 ps
CPU time 5.72 seconds
Started Jul 16 08:00:23 PM PDT 24
Finished Jul 16 08:00:32 PM PDT 24
Peak memory 224476 kb
Host smart-b1232a91-8b5c-4097-b9ba-9ebbe6fbdb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999874497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3999874497
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3812107466
Short name T880
Test name
Test status
Simulation time 11283493 ps
CPU time 0.72 seconds
Started Jul 16 08:00:27 PM PDT 24
Finished Jul 16 08:00:29 PM PDT 24
Peak memory 205528 kb
Host smart-7db9b4d6-e0e6-4b6c-b11d-121808a249b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812107466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3812107466
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1758135395
Short name T507
Test name
Test status
Simulation time 849446966 ps
CPU time 3.99 seconds
Started Jul 16 08:00:22 PM PDT 24
Finished Jul 16 08:00:30 PM PDT 24
Peak memory 224452 kb
Host smart-c119d41f-efd6-47af-9495-22751b4c3984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758135395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1758135395
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3034222217
Short name T817
Test name
Test status
Simulation time 55794448 ps
CPU time 0.8 seconds
Started Jul 16 08:00:26 PM PDT 24
Finished Jul 16 08:00:28 PM PDT 24
Peak memory 206632 kb
Host smart-9b757ba8-f926-4e00-8091-489575449a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034222217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3034222217
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.920494653
Short name T357
Test name
Test status
Simulation time 13677453784 ps
CPU time 103.48 seconds
Started Jul 16 08:00:25 PM PDT 24
Finished Jul 16 08:02:11 PM PDT 24
Peak memory 249192 kb
Host smart-3926a3c5-347d-4532-ac1f-ed8389211e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920494653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.920494653
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.4284814444
Short name T114
Test name
Test status
Simulation time 119426971522 ps
CPU time 500.09 seconds
Started Jul 16 08:00:17 PM PDT 24
Finished Jul 16 08:08:40 PM PDT 24
Peak memory 256744 kb
Host smart-7a256991-0870-42f0-8ba6-2aa693976b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284814444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.4284814444
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.4120471045
Short name T246
Test name
Test status
Simulation time 26375604010 ps
CPU time 76.69 seconds
Started Jul 16 08:00:20 PM PDT 24
Finished Jul 16 08:01:40 PM PDT 24
Peak memory 254412 kb
Host smart-78918800-7d8d-4406-9649-6ea67d4ad3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120471045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.4120471045
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1282208212
Short name T901
Test name
Test status
Simulation time 3378760518 ps
CPU time 29.12 seconds
Started Jul 16 08:00:14 PM PDT 24
Finished Jul 16 08:00:45 PM PDT 24
Peak memory 240944 kb
Host smart-92686a89-8267-450d-a508-31c06051de19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282208212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1282208212
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3397650931
Short name T52
Test name
Test status
Simulation time 519987071 ps
CPU time 3.39 seconds
Started Jul 16 08:00:32 PM PDT 24
Finished Jul 16 08:00:37 PM PDT 24
Peak memory 224504 kb
Host smart-e3c346d7-d810-4542-93eb-b34c6e7a463e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397650931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3397650931
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2239884348
Short name T211
Test name
Test status
Simulation time 12965982790 ps
CPU time 36.3 seconds
Started Jul 16 08:00:15 PM PDT 24
Finished Jul 16 08:00:53 PM PDT 24
Peak memory 232736 kb
Host smart-fb9178d0-9d7c-414f-bb04-7e8c8b04b7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239884348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2239884348
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1373795416
Short name T563
Test name
Test status
Simulation time 4281053289 ps
CPU time 5.7 seconds
Started Jul 16 08:00:13 PM PDT 24
Finished Jul 16 08:00:20 PM PDT 24
Peak memory 224444 kb
Host smart-e8564954-dfe9-416f-9b3f-c790f2e3840e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373795416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1373795416
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2221338922
Short name T41
Test name
Test status
Simulation time 33378358753 ps
CPU time 27.76 seconds
Started Jul 16 08:00:27 PM PDT 24
Finished Jul 16 08:00:57 PM PDT 24
Peak memory 233860 kb
Host smart-395f92c5-2618-43d2-91ea-9b98b5cefc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221338922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2221338922
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.4032536381
Short name T871
Test name
Test status
Simulation time 743345442 ps
CPU time 10.16 seconds
Started Jul 16 08:00:22 PM PDT 24
Finished Jul 16 08:00:36 PM PDT 24
Peak memory 222140 kb
Host smart-87badceb-b4e8-460e-a86b-33911e6d8ca4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4032536381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.4032536381
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.837123966
Short name T646
Test name
Test status
Simulation time 2493343670 ps
CPU time 13.78 seconds
Started Jul 16 08:00:16 PM PDT 24
Finished Jul 16 08:00:31 PM PDT 24
Peak memory 220144 kb
Host smart-4bab6dc8-4f1e-4984-beea-9da62bc6db56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837123966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.837123966
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3265698060
Short name T511
Test name
Test status
Simulation time 1685110275 ps
CPU time 4.53 seconds
Started Jul 16 08:00:24 PM PDT 24
Finished Jul 16 08:00:31 PM PDT 24
Peak memory 216172 kb
Host smart-4b24ae22-9e4a-4d43-a24f-83a0beba2248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265698060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3265698060
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3757684214
Short name T617
Test name
Test status
Simulation time 41052256 ps
CPU time 1.06 seconds
Started Jul 16 08:00:17 PM PDT 24
Finished Jul 16 08:00:20 PM PDT 24
Peak memory 207124 kb
Host smart-70709d70-3f60-4efd-bf81-f29f5647ed15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757684214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3757684214
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3887580688
Short name T335
Test name
Test status
Simulation time 168140655 ps
CPU time 1 seconds
Started Jul 16 08:00:27 PM PDT 24
Finished Jul 16 08:00:30 PM PDT 24
Peak memory 207020 kb
Host smart-7432b879-5a4c-40cf-9206-1c93d723218b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887580688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3887580688
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.496823575
Short name T232
Test name
Test status
Simulation time 3583879974 ps
CPU time 16.48 seconds
Started Jul 16 08:00:17 PM PDT 24
Finished Jul 16 08:00:35 PM PDT 24
Peak memory 233800 kb
Host smart-a286832e-ac77-46c7-96a1-28f8c3682408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496823575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.496823575
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3566048792
Short name T778
Test name
Test status
Simulation time 11253356 ps
CPU time 0.7 seconds
Started Jul 16 08:00:22 PM PDT 24
Finished Jul 16 08:00:26 PM PDT 24
Peak memory 204948 kb
Host smart-99bdfacc-ba80-4f74-9b29-3bbdfd8df990
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566048792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3566048792
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.113038802
Short name T377
Test name
Test status
Simulation time 17491839 ps
CPU time 0.78 seconds
Started Jul 16 08:00:18 PM PDT 24
Finished Jul 16 08:00:22 PM PDT 24
Peak memory 206584 kb
Host smart-9af2ca74-99cd-4dc6-9262-9b85312e7e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113038802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.113038802
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3003162161
Short name T224
Test name
Test status
Simulation time 27707219246 ps
CPU time 179.81 seconds
Started Jul 16 08:00:28 PM PDT 24
Finished Jul 16 08:03:30 PM PDT 24
Peak memory 257364 kb
Host smart-4b3bb8f1-92ba-4988-822b-e0a6decabf71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003162161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3003162161
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.799900934
Short name T977
Test name
Test status
Simulation time 5955940135 ps
CPU time 47 seconds
Started Jul 16 08:00:32 PM PDT 24
Finished Jul 16 08:01:21 PM PDT 24
Peak memory 249292 kb
Host smart-0dc8f1a1-bd1b-445f-af7c-6a03ba2ad7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799900934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.799900934
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3378795957
Short name T269
Test name
Test status
Simulation time 66162491 ps
CPU time 4.14 seconds
Started Jul 16 08:00:21 PM PDT 24
Finished Jul 16 08:00:29 PM PDT 24
Peak memory 224440 kb
Host smart-5be97581-77c8-4536-9e84-f48cbcd12342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378795957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3378795957
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.4211642420
Short name T76
Test name
Test status
Simulation time 5483160264 ps
CPU time 57.55 seconds
Started Jul 16 08:00:34 PM PDT 24
Finished Jul 16 08:01:33 PM PDT 24
Peak memory 253080 kb
Host smart-2d5da230-8fbd-4c8f-a7dd-595a4af4d4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211642420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.4211642420
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1553568542
Short name T175
Test name
Test status
Simulation time 1747393840 ps
CPU time 9.86 seconds
Started Jul 16 08:00:20 PM PDT 24
Finished Jul 16 08:00:34 PM PDT 24
Peak memory 232724 kb
Host smart-11097805-2f60-4790-8261-ef8cdfbabf07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553568542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1553568542
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3399451589
Short name T94
Test name
Test status
Simulation time 57526903 ps
CPU time 2.68 seconds
Started Jul 16 08:00:20 PM PDT 24
Finished Jul 16 08:00:26 PM PDT 24
Peak memory 227984 kb
Host smart-4170c380-ab4a-4956-89e8-8c7ae5531a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399451589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3399451589
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.541730266
Short name T221
Test name
Test status
Simulation time 561225694 ps
CPU time 3.24 seconds
Started Jul 16 08:00:28 PM PDT 24
Finished Jul 16 08:00:33 PM PDT 24
Peak memory 224436 kb
Host smart-faecaaed-2abd-4ee0-8d40-95b9aed141a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541730266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.541730266
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.620509168
Short name T482
Test name
Test status
Simulation time 1734135634 ps
CPU time 10.62 seconds
Started Jul 16 08:00:16 PM PDT 24
Finished Jul 16 08:00:28 PM PDT 24
Peak memory 232640 kb
Host smart-12b592a0-1121-443f-ab21-636ee49e2321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620509168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.620509168
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1988070596
Short name T476
Test name
Test status
Simulation time 2637981178 ps
CPU time 4.16 seconds
Started Jul 16 08:00:27 PM PDT 24
Finished Jul 16 08:00:33 PM PDT 24
Peak memory 219444 kb
Host smart-1ee5da93-80d5-4aa8-9118-c0730e0aadab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1988070596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1988070596
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3508837179
Short name T31
Test name
Test status
Simulation time 3571548201 ps
CPU time 27.64 seconds
Started Jul 16 08:00:23 PM PDT 24
Finished Jul 16 08:00:54 PM PDT 24
Peak memory 238212 kb
Host smart-d3ea9fd9-6fbb-4424-a9f6-62d0ec7d9abc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508837179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3508837179
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.490565631
Short name T569
Test name
Test status
Simulation time 6043680011 ps
CPU time 33.83 seconds
Started Jul 16 08:00:21 PM PDT 24
Finished Jul 16 08:00:58 PM PDT 24
Peak memory 216460 kb
Host smart-514166ee-3016-445a-ba84-08d833ba36ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490565631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.490565631
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3382682712
Short name T714
Test name
Test status
Simulation time 3068208789 ps
CPU time 4.93 seconds
Started Jul 16 08:00:26 PM PDT 24
Finished Jul 16 08:00:32 PM PDT 24
Peak memory 216276 kb
Host smart-e7d7367b-5a55-4408-9cbd-712bdcd6fe0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382682712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3382682712
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3596805373
Short name T519
Test name
Test status
Simulation time 250572449 ps
CPU time 3.29 seconds
Started Jul 16 08:00:17 PM PDT 24
Finished Jul 16 08:00:22 PM PDT 24
Peak memory 216220 kb
Host smart-a0d07529-72fd-4aaf-8174-0881afd7bd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596805373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3596805373
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3666443343
Short name T687
Test name
Test status
Simulation time 183435763 ps
CPU time 0.7 seconds
Started Jul 16 08:00:20 PM PDT 24
Finished Jul 16 08:00:24 PM PDT 24
Peak memory 206000 kb
Host smart-0b22ab07-73bc-43b2-876b-542d747c5c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666443343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3666443343
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.510571199
Short name T462
Test name
Test status
Simulation time 373566170 ps
CPU time 2.86 seconds
Started Jul 16 08:00:34 PM PDT 24
Finished Jul 16 08:00:38 PM PDT 24
Peak memory 224452 kb
Host smart-f0ea9aad-b711-480d-ba5d-5fac4af6cb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510571199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.510571199
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3362369760
Short name T535
Test name
Test status
Simulation time 32624921 ps
CPU time 0.73 seconds
Started Jul 16 08:00:38 PM PDT 24
Finished Jul 16 08:00:42 PM PDT 24
Peak memory 205860 kb
Host smart-15db1f30-08b2-406c-8e87-b398a4aa1aa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362369760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3362369760
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2286342982
Short name T95
Test name
Test status
Simulation time 36631664 ps
CPU time 2.63 seconds
Started Jul 16 08:00:33 PM PDT 24
Finished Jul 16 08:00:37 PM PDT 24
Peak memory 232692 kb
Host smart-e3e18b96-fc3b-4d08-9f7d-f7cec0de972a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286342982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2286342982
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3858006552
Short name T769
Test name
Test status
Simulation time 22902744 ps
CPU time 0.83 seconds
Started Jul 16 08:00:15 PM PDT 24
Finished Jul 16 08:00:18 PM PDT 24
Peak memory 206592 kb
Host smart-8202aa7f-a8af-4a7c-88d3-f407d1f7e489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858006552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3858006552
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3803214846
Short name T667
Test name
Test status
Simulation time 213908061 ps
CPU time 4.04 seconds
Started Jul 16 08:00:33 PM PDT 24
Finished Jul 16 08:00:38 PM PDT 24
Peak memory 234188 kb
Host smart-b54253bc-b484-4d88-a2d2-aaa463b893a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803214846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3803214846
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.148398828
Short name T586
Test name
Test status
Simulation time 65572600028 ps
CPU time 154.73 seconds
Started Jul 16 08:00:42 PM PDT 24
Finished Jul 16 08:03:18 PM PDT 24
Peak memory 256644 kb
Host smart-4dc12824-5be4-4eed-bde5-c409208b923c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148398828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.148398828
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.4282087363
Short name T627
Test name
Test status
Simulation time 7216833034 ps
CPU time 27.05 seconds
Started Jul 16 08:00:36 PM PDT 24
Finished Jul 16 08:01:06 PM PDT 24
Peak memory 224164 kb
Host smart-cff198bb-3827-40ad-baed-f08a81519ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282087363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.4282087363
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.1257350251
Short name T152
Test name
Test status
Simulation time 5409046028 ps
CPU time 28.99 seconds
Started Jul 16 08:00:35 PM PDT 24
Finished Jul 16 08:01:06 PM PDT 24
Peak memory 249204 kb
Host smart-220de04c-eeae-426f-a01c-60fde9358629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257350251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.1257350251
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3920252660
Short name T216
Test name
Test status
Simulation time 632371878 ps
CPU time 5.65 seconds
Started Jul 16 08:00:36 PM PDT 24
Finished Jul 16 08:00:46 PM PDT 24
Peak memory 232624 kb
Host smart-b1dc697f-7513-4239-a02f-fbba2db472df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920252660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3920252660
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2207786387
Short name T917
Test name
Test status
Simulation time 1028674578 ps
CPU time 7.85 seconds
Started Jul 16 08:00:31 PM PDT 24
Finished Jul 16 08:00:40 PM PDT 24
Peak memory 232656 kb
Host smart-160623a0-91eb-415b-aa55-d0c2aac6f802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207786387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2207786387
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3972269184
Short name T750
Test name
Test status
Simulation time 210848175 ps
CPU time 2.49 seconds
Started Jul 16 08:00:34 PM PDT 24
Finished Jul 16 08:00:38 PM PDT 24
Peak memory 224416 kb
Host smart-48462d0f-cbc1-4b5f-83ac-85a0ca3552b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972269184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3972269184
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3139359947
Short name T875
Test name
Test status
Simulation time 21317672950 ps
CPU time 20.68 seconds
Started Jul 16 08:00:36 PM PDT 24
Finished Jul 16 08:01:00 PM PDT 24
Peak memory 232856 kb
Host smart-3132262c-cb26-433c-94bc-9dd5e45de148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139359947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3139359947
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1987059898
Short name T635
Test name
Test status
Simulation time 1111776401 ps
CPU time 3.65 seconds
Started Jul 16 08:00:37 PM PDT 24
Finished Jul 16 08:00:44 PM PDT 24
Peak memory 222988 kb
Host smart-31b8d3f0-facf-4a7e-8651-943b5c821779
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1987059898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1987059898
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1550329738
Short name T253
Test name
Test status
Simulation time 375013902931 ps
CPU time 395.2 seconds
Started Jul 16 08:00:32 PM PDT 24
Finished Jul 16 08:07:09 PM PDT 24
Peak memory 293740 kb
Host smart-0bcf52d7-d663-47ed-a225-0d330a1f64cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550329738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1550329738
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3998844110
Short name T57
Test name
Test status
Simulation time 1782268527 ps
CPU time 10.07 seconds
Started Jul 16 08:00:35 PM PDT 24
Finished Jul 16 08:00:48 PM PDT 24
Peak memory 218264 kb
Host smart-c0858b73-c76e-4bc0-a446-7a7319b268a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998844110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3998844110
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.414558939
Short name T302
Test name
Test status
Simulation time 6599913727 ps
CPU time 6.23 seconds
Started Jul 16 08:00:16 PM PDT 24
Finished Jul 16 08:00:24 PM PDT 24
Peak memory 216376 kb
Host smart-0fa09155-22cb-442d-8ee0-b53f03d513d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414558939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.414558939
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2537746476
Short name T520
Test name
Test status
Simulation time 10499638 ps
CPU time 0.68 seconds
Started Jul 16 08:00:35 PM PDT 24
Finished Jul 16 08:00:38 PM PDT 24
Peak memory 205664 kb
Host smart-10060b2a-f1d5-4553-b2b2-602c563bc5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537746476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2537746476
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.578601179
Short name T388
Test name
Test status
Simulation time 32216348 ps
CPU time 0.75 seconds
Started Jul 16 08:00:36 PM PDT 24
Finished Jul 16 08:00:40 PM PDT 24
Peak memory 206136 kb
Host smart-bea6159f-1fd7-4b0e-a4c2-87dda2f4fa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578601179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.578601179
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2282596787
Short name T903
Test name
Test status
Simulation time 6631880940 ps
CPU time 23.29 seconds
Started Jul 16 08:00:39 PM PDT 24
Finished Jul 16 08:01:04 PM PDT 24
Peak memory 240744 kb
Host smart-b9d520f0-f296-4136-b017-b7a28f42f18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282596787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2282596787
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.627707926
Short name T442
Test name
Test status
Simulation time 19197864 ps
CPU time 0.78 seconds
Started Jul 16 08:00:35 PM PDT 24
Finished Jul 16 08:00:38 PM PDT 24
Peak memory 204980 kb
Host smart-8ec8567d-5e19-4967-85ae-072b9eaa6766
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627707926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.627707926
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.856054484
Short name T779
Test name
Test status
Simulation time 316136089 ps
CPU time 4.02 seconds
Started Jul 16 08:00:36 PM PDT 24
Finished Jul 16 08:00:43 PM PDT 24
Peak memory 232628 kb
Host smart-bc8e1fb8-66e3-45fb-8b7d-58139004620a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856054484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.856054484
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2782913564
Short name T897
Test name
Test status
Simulation time 19265193 ps
CPU time 0.84 seconds
Started Jul 16 08:00:31 PM PDT 24
Finished Jul 16 08:00:33 PM PDT 24
Peak memory 206628 kb
Host smart-a85e0d5b-0f3c-4d25-8d32-c8661c2a2f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782913564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2782913564
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.653330335
Short name T404
Test name
Test status
Simulation time 1917826313 ps
CPU time 11.46 seconds
Started Jul 16 08:00:37 PM PDT 24
Finished Jul 16 08:00:52 PM PDT 24
Peak memory 238716 kb
Host smart-cfa00296-9889-4b31-863c-0a11b342980a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653330335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.653330335
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2675828428
Short name T539
Test name
Test status
Simulation time 68962888917 ps
CPU time 118.51 seconds
Started Jul 16 08:00:32 PM PDT 24
Finished Jul 16 08:02:33 PM PDT 24
Peak memory 251404 kb
Host smart-08d26550-bdb7-4707-967c-c5b8b07b5899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675828428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2675828428
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3563048572
Short name T446
Test name
Test status
Simulation time 1834705605 ps
CPU time 5.42 seconds
Started Jul 16 08:00:42 PM PDT 24
Finished Jul 16 08:00:49 PM PDT 24
Peak memory 241036 kb
Host smart-d63b3008-1164-4efa-b6ad-96104d8e7348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563048572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3563048572
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3307073023
Short name T55
Test name
Test status
Simulation time 1504654011 ps
CPU time 11.8 seconds
Started Jul 16 08:00:30 PM PDT 24
Finished Jul 16 08:00:43 PM PDT 24
Peak memory 224452 kb
Host smart-c789856a-eed3-4396-970a-38756a7114d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307073023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3307073023
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3977981651
Short name T631
Test name
Test status
Simulation time 11425124069 ps
CPU time 21.25 seconds
Started Jul 16 08:00:31 PM PDT 24
Finished Jul 16 08:00:53 PM PDT 24
Peak memory 232776 kb
Host smart-90856470-f6b8-4b7e-9f2d-c1afb0d3cd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977981651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3977981651
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2682936948
Short name T655
Test name
Test status
Simulation time 8877870223 ps
CPU time 10.2 seconds
Started Jul 16 08:00:32 PM PDT 24
Finished Jul 16 08:00:44 PM PDT 24
Peak memory 237080 kb
Host smart-4ed2ffe7-1eab-4fe2-a46d-21398eb5cde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682936948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2682936948
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.319126296
Short name T187
Test name
Test status
Simulation time 1757642450 ps
CPU time 5.48 seconds
Started Jul 16 08:00:32 PM PDT 24
Finished Jul 16 08:00:40 PM PDT 24
Peak memory 224476 kb
Host smart-1e299bff-178a-46cc-ad72-72866ca8da96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319126296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.319126296
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2726462858
Short name T121
Test name
Test status
Simulation time 141100143 ps
CPU time 3.83 seconds
Started Jul 16 08:00:36 PM PDT 24
Finished Jul 16 08:00:42 PM PDT 24
Peak memory 219264 kb
Host smart-5b52d28f-78a2-423f-8787-f9971222fe8c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2726462858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2726462858
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1067267262
Short name T136
Test name
Test status
Simulation time 20534128397 ps
CPU time 132.64 seconds
Started Jul 16 08:00:37 PM PDT 24
Finished Jul 16 08:02:53 PM PDT 24
Peak memory 266024 kb
Host smart-9efb2671-9bc3-4d8b-86d4-2b6f80f5369d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067267262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1067267262
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3178580254
Short name T840
Test name
Test status
Simulation time 3456795118 ps
CPU time 16.97 seconds
Started Jul 16 08:00:41 PM PDT 24
Finished Jul 16 08:00:59 PM PDT 24
Peak memory 220136 kb
Host smart-53d04431-4dd8-46e6-b8fd-7bf4e12e0491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178580254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3178580254
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.794340861
Short name T139
Test name
Test status
Simulation time 1051835867 ps
CPU time 6.14 seconds
Started Jul 16 08:00:36 PM PDT 24
Finished Jul 16 08:00:46 PM PDT 24
Peak memory 216172 kb
Host smart-2492014f-80d1-441e-adb7-b459147ce68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794340861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.794340861
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2090145007
Short name T313
Test name
Test status
Simulation time 572682735 ps
CPU time 3.18 seconds
Started Jul 16 08:00:31 PM PDT 24
Finished Jul 16 08:00:36 PM PDT 24
Peak memory 216156 kb
Host smart-99cd1b75-f978-43ea-9798-567ca5c32306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090145007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2090145007
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.285500885
Short name T298
Test name
Test status
Simulation time 71425176 ps
CPU time 0.8 seconds
Started Jul 16 08:00:32 PM PDT 24
Finished Jul 16 08:00:34 PM PDT 24
Peak memory 206040 kb
Host smart-bc33cf38-607b-489f-8074-222da88cc7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285500885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.285500885
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3436924295
Short name T762
Test name
Test status
Simulation time 77855596 ps
CPU time 2.93 seconds
Started Jul 16 08:00:42 PM PDT 24
Finished Jul 16 08:00:46 PM PDT 24
Peak memory 232680 kb
Host smart-3a0378ed-00a3-4e2d-b854-d7e62e3cd639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436924295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3436924295
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1101648696
Short name T935
Test name
Test status
Simulation time 39536643 ps
CPU time 0.75 seconds
Started Jul 16 07:59:48 PM PDT 24
Finished Jul 16 07:59:51 PM PDT 24
Peak memory 205548 kb
Host smart-1ca54973-a7d7-4c8e-853e-71dbae24d45a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101648696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
101648696
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.304335950
Short name T215
Test name
Test status
Simulation time 2067097613 ps
CPU time 5.28 seconds
Started Jul 16 07:59:35 PM PDT 24
Finished Jul 16 07:59:41 PM PDT 24
Peak memory 224432 kb
Host smart-eb78ba3a-e420-4fa0-82ba-218bb3ad4d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304335950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.304335950
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3550485362
Short name T972
Test name
Test status
Simulation time 14264597 ps
CPU time 0.77 seconds
Started Jul 16 07:59:29 PM PDT 24
Finished Jul 16 07:59:31 PM PDT 24
Peak memory 205592 kb
Host smart-3f03ed6c-e6ba-48c5-ac5a-47cbe7000c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550485362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3550485362
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.894083097
Short name T259
Test name
Test status
Simulation time 12556493047 ps
CPU time 60.82 seconds
Started Jul 16 07:59:25 PM PDT 24
Finished Jul 16 08:00:29 PM PDT 24
Peak memory 249324 kb
Host smart-1bcd5507-36f6-4786-a352-d96669b71511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894083097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.894083097
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3643861961
Short name T274
Test name
Test status
Simulation time 18162102759 ps
CPU time 92.72 seconds
Started Jul 16 07:59:28 PM PDT 24
Finished Jul 16 08:01:03 PM PDT 24
Peak memory 240992 kb
Host smart-bcacd01c-3677-46e7-af25-7122e4f5e327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643861961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3643861961
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1582263113
Short name T636
Test name
Test status
Simulation time 2013093535 ps
CPU time 33.21 seconds
Started Jul 16 07:59:35 PM PDT 24
Finished Jul 16 08:00:09 PM PDT 24
Peak memory 240884 kb
Host smart-5cfd2543-7262-4f25-97eb-d42d1ad7ade8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582263113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1582263113
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.242390778
Short name T810
Test name
Test status
Simulation time 5729421835 ps
CPU time 82.14 seconds
Started Jul 16 07:59:34 PM PDT 24
Finished Jul 16 08:00:58 PM PDT 24
Peak memory 249212 kb
Host smart-ac005d37-1e71-4f6c-a009-6deae3457d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242390778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.
242390778
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3145517419
Short name T677
Test name
Test status
Simulation time 70860679 ps
CPU time 2.45 seconds
Started Jul 16 07:59:27 PM PDT 24
Finished Jul 16 07:59:32 PM PDT 24
Peak memory 226704 kb
Host smart-4feb358c-1054-4d95-95ab-1d14e5173512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145517419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3145517419
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1763194244
Short name T672
Test name
Test status
Simulation time 73993035 ps
CPU time 2.3 seconds
Started Jul 16 07:59:28 PM PDT 24
Finished Jul 16 07:59:33 PM PDT 24
Peak memory 223060 kb
Host smart-ee6041b1-1f5f-46da-9497-1cba7d9a406e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763194244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1763194244
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2700359832
Short name T933
Test name
Test status
Simulation time 354311575 ps
CPU time 2.72 seconds
Started Jul 16 07:59:25 PM PDT 24
Finished Jul 16 07:59:31 PM PDT 24
Peak memory 232604 kb
Host smart-6d1b8452-6abd-4aff-a833-4eb5a00d30c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700359832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2700359832
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.563503999
Short name T746
Test name
Test status
Simulation time 1872690837 ps
CPU time 7.77 seconds
Started Jul 16 07:59:36 PM PDT 24
Finished Jul 16 07:59:44 PM PDT 24
Peak memory 232648 kb
Host smart-7d9c0a91-0a41-45d3-a0d1-06260a06232c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563503999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.563503999
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3126940742
Short name T120
Test name
Test status
Simulation time 1870025886 ps
CPU time 4.1 seconds
Started Jul 16 07:59:41 PM PDT 24
Finished Jul 16 07:59:46 PM PDT 24
Peak memory 222768 kb
Host smart-0cfeec72-61f2-4039-bfeb-5765a64ad5ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3126940742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3126940742
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1286920825
Short name T66
Test name
Test status
Simulation time 67311266 ps
CPU time 0.98 seconds
Started Jul 16 07:59:51 PM PDT 24
Finished Jul 16 07:59:54 PM PDT 24
Peak memory 236596 kb
Host smart-a9761cf6-0347-40f8-b055-a4261546942e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286920825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1286920825
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1508302699
Short name T786
Test name
Test status
Simulation time 36475522640 ps
CPU time 352.9 seconds
Started Jul 16 07:59:28 PM PDT 24
Finished Jul 16 08:05:24 PM PDT 24
Peak memory 260524 kb
Host smart-9005fc48-454b-45b3-be80-aeca39bbf9bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508302699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1508302699
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.127488264
Short name T608
Test name
Test status
Simulation time 4283541083 ps
CPU time 7.71 seconds
Started Jul 16 07:59:27 PM PDT 24
Finished Jul 16 07:59:37 PM PDT 24
Peak memory 216332 kb
Host smart-c6398ed3-a931-4151-8c30-53974f2accab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127488264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.127488264
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2374179883
Short name T823
Test name
Test status
Simulation time 2590596400 ps
CPU time 12.05 seconds
Started Jul 16 07:59:25 PM PDT 24
Finished Jul 16 07:59:39 PM PDT 24
Peak memory 216332 kb
Host smart-b38a6d61-6d89-46eb-bac4-e874210d6272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374179883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2374179883
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.6460481
Short name T378
Test name
Test status
Simulation time 34970965 ps
CPU time 0.75 seconds
Started Jul 16 07:59:26 PM PDT 24
Finished Jul 16 07:59:29 PM PDT 24
Peak memory 206040 kb
Host smart-d6483c1a-d8bc-44f8-a34a-b904284bf0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6460481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.6460481
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.538696502
Short name T390
Test name
Test status
Simulation time 52200907 ps
CPU time 0.73 seconds
Started Jul 16 07:59:26 PM PDT 24
Finished Jul 16 07:59:29 PM PDT 24
Peak memory 205996 kb
Host smart-2342fd09-fc5f-4923-ab37-751142275d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538696502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.538696502
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1917357733
Short name T161
Test name
Test status
Simulation time 1979825554 ps
CPU time 5.62 seconds
Started Jul 16 07:59:49 PM PDT 24
Finished Jul 16 07:59:57 PM PDT 24
Peak memory 224496 kb
Host smart-b702ea14-7a11-4024-bfa0-39512051a718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917357733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1917357733
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3146952670
Short name T355
Test name
Test status
Simulation time 27914006 ps
CPU time 0.7 seconds
Started Jul 16 08:00:36 PM PDT 24
Finished Jul 16 08:00:40 PM PDT 24
Peak memory 205892 kb
Host smart-6e8b6805-7794-4c06-b665-10124fd1eb59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146952670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3146952670
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2596544639
Short name T715
Test name
Test status
Simulation time 3118187714 ps
CPU time 6.97 seconds
Started Jul 16 08:00:36 PM PDT 24
Finished Jul 16 08:00:46 PM PDT 24
Peak memory 232804 kb
Host smart-d592895f-a5ef-4faf-8a53-d806dcf11d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596544639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2596544639
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3597701835
Short name T641
Test name
Test status
Simulation time 49326394 ps
CPU time 0.77 seconds
Started Jul 16 08:00:41 PM PDT 24
Finished Jul 16 08:00:43 PM PDT 24
Peak memory 206944 kb
Host smart-3f42c564-8b04-4d8e-881c-ff6b5e1e0d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597701835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3597701835
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3090410457
Short name T658
Test name
Test status
Simulation time 6214967833 ps
CPU time 43.38 seconds
Started Jul 16 08:00:32 PM PDT 24
Finished Jul 16 08:01:17 PM PDT 24
Peak memory 249196 kb
Host smart-364595fa-a407-4fbe-864b-18d9cec7fd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090410457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3090410457
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2071070393
Short name T913
Test name
Test status
Simulation time 6915281485 ps
CPU time 69.9 seconds
Started Jul 16 08:00:38 PM PDT 24
Finished Jul 16 08:01:51 PM PDT 24
Peak memory 249488 kb
Host smart-8930b151-e058-4ea8-97e6-6cbc269a5331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071070393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2071070393
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1113341610
Short name T415
Test name
Test status
Simulation time 533816875 ps
CPU time 4.14 seconds
Started Jul 16 08:00:36 PM PDT 24
Finished Jul 16 08:00:44 PM PDT 24
Peak memory 232628 kb
Host smart-c2d692ca-9bed-4742-88ac-bfbf549a4cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113341610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1113341610
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.2626287090
Short name T730
Test name
Test status
Simulation time 44490430153 ps
CPU time 56.42 seconds
Started Jul 16 08:00:34 PM PDT 24
Finished Jul 16 08:01:32 PM PDT 24
Peak memory 256736 kb
Host smart-9f7ef788-76b9-4ee6-861b-f1315956500d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626287090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.2626287090
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2716127035
Short name T491
Test name
Test status
Simulation time 195749513 ps
CPU time 4.24 seconds
Started Jul 16 08:00:37 PM PDT 24
Finished Jul 16 08:00:45 PM PDT 24
Peak memory 224408 kb
Host smart-d09037aa-5012-4849-aa33-91062971ce20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716127035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2716127035
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1404864223
Short name T351
Test name
Test status
Simulation time 615491786 ps
CPU time 6.74 seconds
Started Jul 16 08:00:37 PM PDT 24
Finished Jul 16 08:00:47 PM PDT 24
Peak memory 224452 kb
Host smart-30ed6f84-d3e2-41e9-8bbf-e2f20d64a2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404864223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1404864223
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1091611738
Short name T622
Test name
Test status
Simulation time 6406659782 ps
CPU time 12.55 seconds
Started Jul 16 08:00:37 PM PDT 24
Finished Jul 16 08:00:53 PM PDT 24
Peak memory 224548 kb
Host smart-5359cb33-4d3f-4b1e-a30f-d691f1997366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091611738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1091611738
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1558959815
Short name T946
Test name
Test status
Simulation time 121933932 ps
CPU time 2.51 seconds
Started Jul 16 08:00:37 PM PDT 24
Finished Jul 16 08:00:43 PM PDT 24
Peak memory 232400 kb
Host smart-94faeae8-a2bb-4a83-8490-17455dd26997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558959815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1558959815
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3689227085
Short name T125
Test name
Test status
Simulation time 299545878 ps
CPU time 4.31 seconds
Started Jul 16 08:00:41 PM PDT 24
Finished Jul 16 08:00:47 PM PDT 24
Peak memory 219328 kb
Host smart-eececcc4-5b98-45d4-ab80-91a98d7aeaab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3689227085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3689227085
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1814016128
Short name T811
Test name
Test status
Simulation time 3047850951 ps
CPU time 23.91 seconds
Started Jul 16 08:00:31 PM PDT 24
Finished Jul 16 08:00:55 PM PDT 24
Peak memory 240468 kb
Host smart-7b52c85b-56e1-4b5c-adb8-7c11bb13c283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814016128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1814016128
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.189661634
Short name T644
Test name
Test status
Simulation time 4841303877 ps
CPU time 25.47 seconds
Started Jul 16 08:00:32 PM PDT 24
Finished Jul 16 08:00:59 PM PDT 24
Peak memory 216332 kb
Host smart-38a5d1e2-58a3-4dca-b85a-ccc8d852b7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189661634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.189661634
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.4038308635
Short name T829
Test name
Test status
Simulation time 1500564499 ps
CPU time 2.76 seconds
Started Jul 16 08:00:38 PM PDT 24
Finished Jul 16 08:00:44 PM PDT 24
Peak memory 216172 kb
Host smart-77fd74c2-ed5a-491c-a68c-55a9a9687eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038308635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.4038308635
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2206347734
Short name T623
Test name
Test status
Simulation time 679439648 ps
CPU time 7.24 seconds
Started Jul 16 08:00:36 PM PDT 24
Finished Jul 16 08:00:47 PM PDT 24
Peak memory 216144 kb
Host smart-f972b05c-c114-49d8-a9d4-0789bda742f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206347734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2206347734
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2309052046
Short name T613
Test name
Test status
Simulation time 254217034 ps
CPU time 0.9 seconds
Started Jul 16 08:00:38 PM PDT 24
Finished Jul 16 08:00:42 PM PDT 24
Peak memory 205940 kb
Host smart-47a8ce17-60dc-4331-9535-1c166b9d99db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309052046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2309052046
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1079908312
Short name T461
Test name
Test status
Simulation time 9417324817 ps
CPU time 10.48 seconds
Started Jul 16 08:00:34 PM PDT 24
Finished Jul 16 08:00:46 PM PDT 24
Peak memory 240280 kb
Host smart-c568cfbb-68cb-41d8-a010-ea5a6bdf53b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079908312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1079908312
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2437727812
Short name T572
Test name
Test status
Simulation time 46394763 ps
CPU time 0.74 seconds
Started Jul 16 08:00:52 PM PDT 24
Finished Jul 16 08:00:55 PM PDT 24
Peak memory 204956 kb
Host smart-973bd5b8-57a3-43b7-9928-07410514cec2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437727812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2437727812
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2257555304
Short name T932
Test name
Test status
Simulation time 275533026 ps
CPU time 5.34 seconds
Started Jul 16 08:00:56 PM PDT 24
Finished Jul 16 08:01:02 PM PDT 24
Peak memory 224444 kb
Host smart-a460ad8d-5a70-4501-9977-0cc865fb1b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257555304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2257555304
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2802394298
Short name T846
Test name
Test status
Simulation time 22645218 ps
CPU time 0.83 seconds
Started Jul 16 08:00:36 PM PDT 24
Finished Jul 16 08:00:40 PM PDT 24
Peak memory 206844 kb
Host smart-2b1ff56f-7497-4d58-bc33-09433a484f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802394298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2802394298
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2627930292
Short name T140
Test name
Test status
Simulation time 11594814529 ps
CPU time 91.77 seconds
Started Jul 16 08:00:48 PM PDT 24
Finished Jul 16 08:02:21 PM PDT 24
Peak memory 250388 kb
Host smart-efb620b7-01ff-4ec4-a405-8770361e1563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627930292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2627930292
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1687255387
Short name T162
Test name
Test status
Simulation time 135830449175 ps
CPU time 401.54 seconds
Started Jul 16 08:00:52 PM PDT 24
Finished Jul 16 08:07:36 PM PDT 24
Peak memory 265208 kb
Host smart-451fbee6-713e-4a30-abdb-cff7a7253a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687255387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1687255387
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.544283687
Short name T380
Test name
Test status
Simulation time 5049929209 ps
CPU time 65.62 seconds
Started Jul 16 08:00:52 PM PDT 24
Finished Jul 16 08:02:00 PM PDT 24
Peak memory 265668 kb
Host smart-b33185bc-4559-459f-93ab-099765c04266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544283687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.544283687
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.3785079672
Short name T861
Test name
Test status
Simulation time 37359238 ps
CPU time 0.84 seconds
Started Jul 16 08:00:48 PM PDT 24
Finished Jul 16 08:00:51 PM PDT 24
Peak memory 215948 kb
Host smart-1e849c7d-6856-48cf-9116-ce01502ddb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785079672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.3785079672
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.838422391
Short name T601
Test name
Test status
Simulation time 471281569 ps
CPU time 3.16 seconds
Started Jul 16 08:00:42 PM PDT 24
Finished Jul 16 08:00:46 PM PDT 24
Peak memory 224520 kb
Host smart-eca5d0e2-c84c-4e79-a30d-60c0ff2c81c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838422391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.838422391
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1500933944
Short name T584
Test name
Test status
Simulation time 31649336 ps
CPU time 2.06 seconds
Started Jul 16 08:00:37 PM PDT 24
Finished Jul 16 08:00:42 PM PDT 24
Peak memory 223700 kb
Host smart-9f97b4da-c63e-48e6-9e29-626d1e5d4fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500933944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1500933944
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.4046610811
Short name T616
Test name
Test status
Simulation time 1683672581 ps
CPU time 7.74 seconds
Started Jul 16 08:00:36 PM PDT 24
Finished Jul 16 08:00:48 PM PDT 24
Peak memory 224500 kb
Host smart-adec19e0-0fe1-4fb9-8fe4-86cb5481927b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046610811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.4046610811
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1319877036
Short name T682
Test name
Test status
Simulation time 579164150 ps
CPU time 2.81 seconds
Started Jul 16 08:00:35 PM PDT 24
Finished Jul 16 08:00:39 PM PDT 24
Peak memory 224384 kb
Host smart-61d8e9ba-846e-4498-af9f-d4a60b7782a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319877036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1319877036
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.672636234
Short name T883
Test name
Test status
Simulation time 10448735830 ps
CPU time 16.42 seconds
Started Jul 16 08:00:47 PM PDT 24
Finished Jul 16 08:01:05 PM PDT 24
Peak memory 220248 kb
Host smart-cc7843b6-fada-4b7a-9834-bf8b506bc5d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=672636234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.672636234
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1532584429
Short name T905
Test name
Test status
Simulation time 9041198913 ps
CPU time 66.75 seconds
Started Jul 16 08:00:47 PM PDT 24
Finished Jul 16 08:01:55 PM PDT 24
Peak memory 249432 kb
Host smart-107223ac-2d67-4fca-9cab-7329cdf5eaac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532584429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1532584429
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2750991518
Short name T815
Test name
Test status
Simulation time 1892537505 ps
CPU time 28.71 seconds
Started Jul 16 08:00:36 PM PDT 24
Finished Jul 16 08:01:09 PM PDT 24
Peak memory 216524 kb
Host smart-492f9347-1419-474d-b0c1-60badd996c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750991518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2750991518
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1060057857
Short name T770
Test name
Test status
Simulation time 588054851 ps
CPU time 4.47 seconds
Started Jul 16 08:00:38 PM PDT 24
Finished Jul 16 08:00:45 PM PDT 24
Peak memory 216144 kb
Host smart-cf269d17-549c-4d6a-860e-fecb4ec765ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060057857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1060057857
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3082089284
Short name T447
Test name
Test status
Simulation time 108006739 ps
CPU time 0.88 seconds
Started Jul 16 08:00:37 PM PDT 24
Finished Jul 16 08:00:42 PM PDT 24
Peak memory 206564 kb
Host smart-221b917d-a1ad-4bc1-b144-1df0d307fc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082089284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3082089284
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1708769940
Short name T299
Test name
Test status
Simulation time 479005227 ps
CPU time 1.12 seconds
Started Jul 16 08:00:33 PM PDT 24
Finished Jul 16 08:00:36 PM PDT 24
Peak memory 206928 kb
Host smart-af225e28-219c-4773-bc2f-761ec026e6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708769940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1708769940
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.2339428958
Short name T825
Test name
Test status
Simulation time 2271019477 ps
CPU time 7.76 seconds
Started Jul 16 08:00:50 PM PDT 24
Finished Jul 16 08:01:00 PM PDT 24
Peak memory 232752 kb
Host smart-d6d3d187-127f-4bcb-afe6-d362114a2316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339428958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2339428958
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1735955010
Short name T440
Test name
Test status
Simulation time 11743318 ps
CPU time 0.7 seconds
Started Jul 16 08:00:49 PM PDT 24
Finished Jul 16 08:00:51 PM PDT 24
Peak memory 205576 kb
Host smart-fc8a68e2-78ef-4182-9dce-cff279f237df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735955010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1735955010
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1686748267
Short name T666
Test name
Test status
Simulation time 972802928 ps
CPU time 4.82 seconds
Started Jul 16 08:00:47 PM PDT 24
Finished Jul 16 08:00:53 PM PDT 24
Peak memory 224408 kb
Host smart-9df20eb2-ef2d-4836-ac74-21d020f38002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686748267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1686748267
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1175237296
Short name T508
Test name
Test status
Simulation time 26586782 ps
CPU time 0.84 seconds
Started Jul 16 08:00:47 PM PDT 24
Finished Jul 16 08:00:50 PM PDT 24
Peak memory 206600 kb
Host smart-03b7aab1-80fd-4e87-8b8a-53e92408f204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175237296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1175237296
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1500173275
Short name T561
Test name
Test status
Simulation time 9607159912 ps
CPU time 43.53 seconds
Started Jul 16 08:00:53 PM PDT 24
Finished Jul 16 08:01:39 PM PDT 24
Peak memory 249156 kb
Host smart-738b8bd2-d436-4051-a790-b4cd64024c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500173275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1500173275
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2571837026
Short name T49
Test name
Test status
Simulation time 73204947657 ps
CPU time 362.94 seconds
Started Jul 16 08:00:53 PM PDT 24
Finished Jul 16 08:06:59 PM PDT 24
Peak memory 254944 kb
Host smart-5f371211-e42b-4f06-b9be-99af4ced26e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571837026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2571837026
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1222932243
Short name T190
Test name
Test status
Simulation time 3820620029 ps
CPU time 42.3 seconds
Started Jul 16 08:00:56 PM PDT 24
Finished Jul 16 08:01:40 PM PDT 24
Peak memory 257444 kb
Host smart-d4a79398-17d3-4096-b209-a3d40b4a3327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222932243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1222932243
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1079743271
Short name T981
Test name
Test status
Simulation time 3940178438 ps
CPU time 11.76 seconds
Started Jul 16 08:00:48 PM PDT 24
Finished Jul 16 08:01:01 PM PDT 24
Peak memory 240864 kb
Host smart-b0a1b0c5-f5e8-4be4-8922-f1ac9f2171ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079743271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1079743271
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.259050396
Short name T53
Test name
Test status
Simulation time 15247231 ps
CPU time 0.77 seconds
Started Jul 16 08:00:48 PM PDT 24
Finished Jul 16 08:00:51 PM PDT 24
Peak memory 215808 kb
Host smart-9483b1dd-c55d-4541-b138-f378eb8e5d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259050396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds
.259050396
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3940469627
Short name T483
Test name
Test status
Simulation time 1135824367 ps
CPU time 3.33 seconds
Started Jul 16 08:00:50 PM PDT 24
Finished Jul 16 08:00:56 PM PDT 24
Peak memory 232724 kb
Host smart-765a7375-3142-41c6-9f6f-b6384560f137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940469627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3940469627
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3934550999
Short name T625
Test name
Test status
Simulation time 2797613430 ps
CPU time 11.05 seconds
Started Jul 16 08:00:49 PM PDT 24
Finished Jul 16 08:01:02 PM PDT 24
Peak memory 224700 kb
Host smart-0ab61d53-fd8a-464a-875b-f4b363aeda17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934550999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3934550999
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2145152907
Short name T585
Test name
Test status
Simulation time 22433552815 ps
CPU time 14.94 seconds
Started Jul 16 08:00:47 PM PDT 24
Finished Jul 16 08:01:03 PM PDT 24
Peak memory 238356 kb
Host smart-0dae59c8-7e90-4a80-9ace-3e5b4e8598d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145152907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2145152907
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.142029723
Short name T330
Test name
Test status
Simulation time 209835723 ps
CPU time 4.46 seconds
Started Jul 16 08:00:49 PM PDT 24
Finished Jul 16 08:00:55 PM PDT 24
Peak memory 232636 kb
Host smart-c82c09cc-32cd-48ac-afa1-e8a2e5731aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142029723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.142029723
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2042320864
Short name T383
Test name
Test status
Simulation time 186889998 ps
CPU time 3.54 seconds
Started Jul 16 08:00:53 PM PDT 24
Finished Jul 16 08:00:59 PM PDT 24
Peak memory 223080 kb
Host smart-72f7cee7-204c-44af-a07f-aa84c73d793d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2042320864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2042320864
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.476080237
Short name T22
Test name
Test status
Simulation time 136629630 ps
CPU time 0.99 seconds
Started Jul 16 08:00:48 PM PDT 24
Finished Jul 16 08:00:51 PM PDT 24
Peak memory 206808 kb
Host smart-4dcb6fe2-f6fc-4eff-b888-8dfbbc509332
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476080237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.476080237
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3915434726
Short name T96
Test name
Test status
Simulation time 423979773 ps
CPU time 5.12 seconds
Started Jul 16 08:00:48 PM PDT 24
Finished Jul 16 08:00:55 PM PDT 24
Peak memory 216420 kb
Host smart-b96dfcaa-c27c-4586-8f03-f8431b494a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915434726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3915434726
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3671342264
Short name T702
Test name
Test status
Simulation time 22063807499 ps
CPU time 15.91 seconds
Started Jul 16 08:00:51 PM PDT 24
Finished Jul 16 08:01:09 PM PDT 24
Peak memory 216312 kb
Host smart-7b880459-d75f-48e7-afb9-a5a190b7250f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671342264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3671342264
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3213925148
Short name T642
Test name
Test status
Simulation time 16308342 ps
CPU time 0.83 seconds
Started Jul 16 08:00:48 PM PDT 24
Finished Jul 16 08:00:50 PM PDT 24
Peak memory 206656 kb
Host smart-7a577cda-3dbd-470d-89c5-735713c89a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213925148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3213925148
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1762570228
Short name T626
Test name
Test status
Simulation time 138433398 ps
CPU time 0.81 seconds
Started Jul 16 08:00:50 PM PDT 24
Finished Jul 16 08:00:53 PM PDT 24
Peak memory 205952 kb
Host smart-fceb8526-94ea-4cdf-bc35-7b5a1418c5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762570228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1762570228
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1501730622
Short name T202
Test name
Test status
Simulation time 5281527038 ps
CPU time 8.83 seconds
Started Jul 16 08:00:49 PM PDT 24
Finished Jul 16 08:01:00 PM PDT 24
Peak memory 224568 kb
Host smart-3d8211f8-683c-4a5a-8ea3-3ca2de3844c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501730622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1501730622
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.159751607
Short name T477
Test name
Test status
Simulation time 11315744 ps
CPU time 0.72 seconds
Started Jul 16 08:00:50 PM PDT 24
Finished Jul 16 08:00:53 PM PDT 24
Peak memory 204980 kb
Host smart-b3d1127a-a517-49b5-86c0-d6e063063e81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159751607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.159751607
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3686807981
Short name T741
Test name
Test status
Simulation time 147613928 ps
CPU time 2.27 seconds
Started Jul 16 08:00:52 PM PDT 24
Finished Jul 16 08:00:57 PM PDT 24
Peak memory 224552 kb
Host smart-6fbcfaa7-7373-4fc2-ae28-818f7b9042e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686807981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3686807981
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2670479679
Short name T643
Test name
Test status
Simulation time 44237799 ps
CPU time 0.79 seconds
Started Jul 16 08:00:51 PM PDT 24
Finished Jul 16 08:00:54 PM PDT 24
Peak memory 206616 kb
Host smart-3fae55e8-b7c1-454b-a8a1-5ae9bc89330d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670479679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2670479679
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1349536196
Short name T694
Test name
Test status
Simulation time 1175300485 ps
CPU time 20.89 seconds
Started Jul 16 08:00:54 PM PDT 24
Finished Jul 16 08:01:17 PM PDT 24
Peak memory 250296 kb
Host smart-2c74b35a-9c1d-4efa-b0c0-46cffbf2e65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349536196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1349536196
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2287846472
Short name T757
Test name
Test status
Simulation time 131531958368 ps
CPU time 313.17 seconds
Started Jul 16 08:00:50 PM PDT 24
Finished Jul 16 08:06:06 PM PDT 24
Peak memory 256968 kb
Host smart-ecb10f94-6fd1-49ff-bc12-c26360d612b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287846472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2287846472
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.4034338255
Short name T609
Test name
Test status
Simulation time 139850888021 ps
CPU time 290.11 seconds
Started Jul 16 08:00:50 PM PDT 24
Finished Jul 16 08:05:43 PM PDT 24
Peak memory 265536 kb
Host smart-42e92d43-8644-4a2f-ba66-e6e99119b352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034338255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.4034338255
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1031325278
Short name T366
Test name
Test status
Simulation time 172837193 ps
CPU time 3.27 seconds
Started Jul 16 08:00:50 PM PDT 24
Finished Jul 16 08:00:56 PM PDT 24
Peak memory 232672 kb
Host smart-4663b5f0-4b71-40da-b96f-d97f58014a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031325278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1031325278
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.2331339160
Short name T78
Test name
Test status
Simulation time 27768808422 ps
CPU time 58.51 seconds
Started Jul 16 08:00:49 PM PDT 24
Finished Jul 16 08:01:49 PM PDT 24
Peak memory 251152 kb
Host smart-3514ed7e-4d5c-4868-80bf-a756756a138c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331339160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.2331339160
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2997716151
Short name T784
Test name
Test status
Simulation time 120631718 ps
CPU time 3.74 seconds
Started Jul 16 08:00:51 PM PDT 24
Finished Jul 16 08:00:58 PM PDT 24
Peak memory 218880 kb
Host smart-cb6a6c6e-c88d-4121-820e-552e48d0ecf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997716151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2997716151
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1919323564
Short name T633
Test name
Test status
Simulation time 2210907637 ps
CPU time 15.82 seconds
Started Jul 16 08:00:51 PM PDT 24
Finished Jul 16 08:01:09 PM PDT 24
Peak memory 240420 kb
Host smart-9b131d34-7501-49cc-b24c-f010c21603a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919323564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1919323564
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3949517111
Short name T745
Test name
Test status
Simulation time 90213834 ps
CPU time 2.11 seconds
Started Jul 16 08:00:53 PM PDT 24
Finished Jul 16 08:00:58 PM PDT 24
Peak memory 224124 kb
Host smart-6376898f-1ba3-4feb-adc9-423269f00931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949517111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3949517111
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3152847604
Short name T226
Test name
Test status
Simulation time 13073595756 ps
CPU time 9.73 seconds
Started Jul 16 08:00:48 PM PDT 24
Finished Jul 16 08:00:59 PM PDT 24
Peak memory 224632 kb
Host smart-2a617c72-28e9-4441-92fe-b90598b1530b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152847604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3152847604
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.4041304259
Short name T354
Test name
Test status
Simulation time 738672763 ps
CPU time 8.52 seconds
Started Jul 16 08:00:47 PM PDT 24
Finished Jul 16 08:00:56 PM PDT 24
Peak memory 219256 kb
Host smart-93a7bffb-787f-475b-b396-c2314994b4c2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4041304259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.4041304259
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.277401298
Short name T801
Test name
Test status
Simulation time 357684759714 ps
CPU time 330.8 seconds
Started Jul 16 08:00:51 PM PDT 24
Finished Jul 16 08:06:24 PM PDT 24
Peak memory 256612 kb
Host smart-d30f211e-8123-4fd0-b0ea-e2d28138007e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277401298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.277401298
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.139559151
Short name T554
Test name
Test status
Simulation time 14770175242 ps
CPU time 31.32 seconds
Started Jul 16 08:00:53 PM PDT 24
Finished Jul 16 08:01:27 PM PDT 24
Peak memory 216356 kb
Host smart-7196f60f-f23b-472e-8f2c-80a98f9bd445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139559151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.139559151
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1720896712
Short name T364
Test name
Test status
Simulation time 709734046 ps
CPU time 3.77 seconds
Started Jul 16 08:00:54 PM PDT 24
Finished Jul 16 08:01:00 PM PDT 24
Peak memory 215940 kb
Host smart-c260965b-e783-4c9a-a395-a254c990bb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720896712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1720896712
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3248804285
Short name T281
Test name
Test status
Simulation time 547836145 ps
CPU time 2.41 seconds
Started Jul 16 08:00:47 PM PDT 24
Finished Jul 16 08:00:51 PM PDT 24
Peak memory 216212 kb
Host smart-f714f587-1d0e-4796-a5ea-b7c4d8f43e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248804285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3248804285
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.172950160
Short name T414
Test name
Test status
Simulation time 115373670 ps
CPU time 0.86 seconds
Started Jul 16 08:00:51 PM PDT 24
Finished Jul 16 08:00:54 PM PDT 24
Peak memory 206008 kb
Host smart-536ca698-106f-4a45-82a5-f0546ea6ed3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172950160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.172950160
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1863267798
Short name T287
Test name
Test status
Simulation time 63460163 ps
CPU time 2.09 seconds
Started Jul 16 08:00:50 PM PDT 24
Finished Jul 16 08:00:55 PM PDT 24
Peak memory 224092 kb
Host smart-9be9a3e7-9241-44d8-8dc7-2d547e6f3738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863267798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1863267798
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3846843759
Short name T407
Test name
Test status
Simulation time 70347727 ps
CPU time 0.73 seconds
Started Jul 16 08:00:53 PM PDT 24
Finished Jul 16 08:00:56 PM PDT 24
Peak memory 205368 kb
Host smart-50bdcb7b-e577-4e6d-8060-c9f26e400d3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846843759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3846843759
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3344818918
Short name T591
Test name
Test status
Simulation time 29450435092 ps
CPU time 16.1 seconds
Started Jul 16 08:00:50 PM PDT 24
Finished Jul 16 08:01:08 PM PDT 24
Peak memory 232812 kb
Host smart-d852dc19-56b9-4a94-b21d-ad0ab414b2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344818918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3344818918
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3291164567
Short name T504
Test name
Test status
Simulation time 44564665 ps
CPU time 0.78 seconds
Started Jul 16 08:00:49 PM PDT 24
Finished Jul 16 08:00:52 PM PDT 24
Peak memory 206596 kb
Host smart-3c7cd189-c17a-400f-9ebb-ec6ba034a67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291164567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3291164567
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1909219239
Short name T218
Test name
Test status
Simulation time 285087903223 ps
CPU time 401.8 seconds
Started Jul 16 08:00:49 PM PDT 24
Finished Jul 16 08:07:33 PM PDT 24
Peak memory 257384 kb
Host smart-e3e6bbb5-1956-4956-9384-66eb8d7ce830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909219239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1909219239
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1479576809
Short name T153
Test name
Test status
Simulation time 17659435025 ps
CPU time 122.48 seconds
Started Jul 16 08:00:53 PM PDT 24
Finished Jul 16 08:02:58 PM PDT 24
Peak memory 256496 kb
Host smart-f09cd2ac-bdc7-49bd-b5cf-ee09ee3c1869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479576809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1479576809
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2952021746
Short name T276
Test name
Test status
Simulation time 20973147137 ps
CPU time 62.25 seconds
Started Jul 16 08:00:56 PM PDT 24
Finished Jul 16 08:01:59 PM PDT 24
Peak memory 249272 kb
Host smart-d5836fc2-42cb-4626-8a1f-d1b287ffa820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952021746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2952021746
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1362264762
Short name T264
Test name
Test status
Simulation time 3573932250 ps
CPU time 55.92 seconds
Started Jul 16 08:00:47 PM PDT 24
Finished Jul 16 08:01:44 PM PDT 24
Peak memory 232840 kb
Host smart-6dfb102e-1e7f-42c1-a36a-21ea1ca6e802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362264762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1362264762
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.2218773302
Short name T804
Test name
Test status
Simulation time 964416518 ps
CPU time 22.93 seconds
Started Jul 16 08:00:49 PM PDT 24
Finished Jul 16 08:01:13 PM PDT 24
Peak memory 238188 kb
Host smart-6bfb934b-7165-4eaf-ac8a-19290f2716c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218773302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.2218773302
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3698364392
Short name T548
Test name
Test status
Simulation time 383760156 ps
CPU time 4.05 seconds
Started Jul 16 08:00:51 PM PDT 24
Finished Jul 16 08:00:58 PM PDT 24
Peak memory 224408 kb
Host smart-6232ca53-6725-4f33-aefe-4b1ad19c8735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698364392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3698364392
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.505198607
Short name T185
Test name
Test status
Simulation time 679073878 ps
CPU time 8.5 seconds
Started Jul 16 08:00:52 PM PDT 24
Finished Jul 16 08:01:02 PM PDT 24
Peak memory 232664 kb
Host smart-f1958319-658b-47c7-b0b1-7a34c129a32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505198607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.505198607
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3351916435
Short name T438
Test name
Test status
Simulation time 21979948870 ps
CPU time 12.12 seconds
Started Jul 16 08:00:49 PM PDT 24
Finished Jul 16 08:01:03 PM PDT 24
Peak memory 232872 kb
Host smart-e3f7ab32-f7ab-4340-a04d-da2aa36cf343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351916435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3351916435
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3694680159
Short name T723
Test name
Test status
Simulation time 67252436571 ps
CPU time 12.17 seconds
Started Jul 16 08:00:51 PM PDT 24
Finished Jul 16 08:01:06 PM PDT 24
Peak memory 224612 kb
Host smart-678394c0-dc2a-4a41-93b8-de72af34530a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694680159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3694680159
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2301392271
Short name T432
Test name
Test status
Simulation time 1128553743 ps
CPU time 9.78 seconds
Started Jul 16 08:00:49 PM PDT 24
Finished Jul 16 08:01:00 PM PDT 24
Peak memory 223124 kb
Host smart-02a40e6c-a091-4e96-a248-b583aaf30d8f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2301392271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2301392271
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3340069637
Short name T402
Test name
Test status
Simulation time 2457721892 ps
CPU time 55.43 seconds
Started Jul 16 08:00:53 PM PDT 24
Finished Jul 16 08:01:51 PM PDT 24
Peak memory 265600 kb
Host smart-551fbbd5-1946-4001-ba86-83f3831e8598
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340069637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3340069637
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1098434620
Short name T279
Test name
Test status
Simulation time 5994095792 ps
CPU time 8.58 seconds
Started Jul 16 08:00:51 PM PDT 24
Finished Jul 16 08:01:01 PM PDT 24
Peak memory 216552 kb
Host smart-f0d8b204-8e7a-4044-86c3-5ecf07b8a27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098434620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1098434620
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2910200553
Short name T795
Test name
Test status
Simulation time 510163250 ps
CPU time 1.48 seconds
Started Jul 16 08:00:49 PM PDT 24
Finished Jul 16 08:00:53 PM PDT 24
Peak memory 207888 kb
Host smart-61317b6f-4507-40ca-a0a9-0ee19ad8bc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910200553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2910200553
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3370035168
Short name T748
Test name
Test status
Simulation time 26539960 ps
CPU time 1.55 seconds
Started Jul 16 08:00:48 PM PDT 24
Finished Jul 16 08:00:52 PM PDT 24
Peak memory 216352 kb
Host smart-465d2c0e-fc8e-4a20-879b-63980bbd650c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370035168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3370035168
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1567411963
Short name T724
Test name
Test status
Simulation time 28555978 ps
CPU time 0.7 seconds
Started Jul 16 08:00:51 PM PDT 24
Finished Jul 16 08:00:54 PM PDT 24
Peak memory 205672 kb
Host smart-848c02fa-3211-4b63-96b1-2ceb92febb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567411963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1567411963
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1281902340
Short name T772
Test name
Test status
Simulation time 514701546 ps
CPU time 6.2 seconds
Started Jul 16 08:00:47 PM PDT 24
Finished Jul 16 08:00:55 PM PDT 24
Peak memory 232680 kb
Host smart-d622c048-cda2-4c1e-86a3-758a75cedb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281902340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1281902340
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.943068975
Short name T934
Test name
Test status
Simulation time 12970534 ps
CPU time 0.7 seconds
Started Jul 16 08:01:10 PM PDT 24
Finished Jul 16 08:01:12 PM PDT 24
Peak memory 204912 kb
Host smart-0eb54f97-f29b-4e96-9eaa-7dd03d2569d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943068975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.943068975
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3594453103
Short name T650
Test name
Test status
Simulation time 110685464 ps
CPU time 2.88 seconds
Started Jul 16 08:01:11 PM PDT 24
Finished Jul 16 08:01:18 PM PDT 24
Peak memory 232652 kb
Host smart-3058063d-5095-4240-808b-e87037c44c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594453103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3594453103
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.351518052
Short name T843
Test name
Test status
Simulation time 57770690 ps
CPU time 0.77 seconds
Started Jul 16 08:00:52 PM PDT 24
Finished Jul 16 08:00:55 PM PDT 24
Peak memory 205924 kb
Host smart-ba0d373b-f2dd-404a-b745-eadb4d678a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351518052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.351518052
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2137697874
Short name T998
Test name
Test status
Simulation time 114872071 ps
CPU time 0.75 seconds
Started Jul 16 08:01:12 PM PDT 24
Finished Jul 16 08:01:17 PM PDT 24
Peak memory 215804 kb
Host smart-85df8d85-1c2d-4bb9-8e3e-4c874d0bf66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137697874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2137697874
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1961888809
Short name T241
Test name
Test status
Simulation time 2936078306 ps
CPU time 67.53 seconds
Started Jul 16 08:01:10 PM PDT 24
Finished Jul 16 08:02:20 PM PDT 24
Peak memory 253960 kb
Host smart-2444bac3-2039-45c5-9b1e-0560e6a95c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961888809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1961888809
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3824902799
Short name T904
Test name
Test status
Simulation time 93672166620 ps
CPU time 318.27 seconds
Started Jul 16 08:01:10 PM PDT 24
Finished Jul 16 08:06:32 PM PDT 24
Peak memory 249628 kb
Host smart-674bade4-d1b9-42dc-b2cb-a0a446e17f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824902799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3824902799
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.3389213759
Short name T854
Test name
Test status
Simulation time 11378069004 ps
CPU time 41.53 seconds
Started Jul 16 08:01:14 PM PDT 24
Finished Jul 16 08:01:59 PM PDT 24
Peak memory 234192 kb
Host smart-5bda2af5-9a86-41c1-9b6f-345cdaac7d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389213759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.3389213759
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1341472497
Short name T422
Test name
Test status
Simulation time 4330830760 ps
CPU time 6.99 seconds
Started Jul 16 08:00:57 PM PDT 24
Finished Jul 16 08:01:05 PM PDT 24
Peak memory 224568 kb
Host smart-1b0dd6d7-12d3-47b3-835e-51c0fa1d55d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341472497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1341472497
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.4169877037
Short name T312
Test name
Test status
Simulation time 267348238 ps
CPU time 5 seconds
Started Jul 16 08:01:09 PM PDT 24
Finished Jul 16 08:01:16 PM PDT 24
Peak memory 232636 kb
Host smart-a31ea432-3ecf-422a-bba3-0ef3a13d1018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169877037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.4169877037
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3833579503
Short name T785
Test name
Test status
Simulation time 1593657466 ps
CPU time 3.42 seconds
Started Jul 16 08:00:57 PM PDT 24
Finished Jul 16 08:01:02 PM PDT 24
Peak memory 232708 kb
Host smart-da552a58-d751-4471-a17f-6498b3112feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833579503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3833579503
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.770979238
Short name T429
Test name
Test status
Simulation time 7365864490 ps
CPU time 18.46 seconds
Started Jul 16 08:00:57 PM PDT 24
Finished Jul 16 08:01:17 PM PDT 24
Peak memory 224608 kb
Host smart-56eaf3f7-5f94-4206-80c7-cbf8bdabb372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770979238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.770979238
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3461162865
Short name T15
Test name
Test status
Simulation time 1298510359 ps
CPU time 13.68 seconds
Started Jul 16 08:01:12 PM PDT 24
Finished Jul 16 08:01:30 PM PDT 24
Peak memory 222132 kb
Host smart-a2068c12-57b8-467d-ab00-aa841e0f4bf0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3461162865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3461162865
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.214145687
Short name T821
Test name
Test status
Simulation time 657891742 ps
CPU time 1.24 seconds
Started Jul 16 08:01:11 PM PDT 24
Finished Jul 16 08:01:17 PM PDT 24
Peak memory 207096 kb
Host smart-6f202f63-5fde-48b8-ab22-20ddda232917
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214145687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.214145687
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.494580995
Short name T766
Test name
Test status
Simulation time 2424883053 ps
CPU time 20.93 seconds
Started Jul 16 08:00:53 PM PDT 24
Finished Jul 16 08:01:16 PM PDT 24
Peak memory 216512 kb
Host smart-a3253fd3-cac7-4a20-87d4-6538bec4da1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494580995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.494580995
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1647869218
Short name T305
Test name
Test status
Simulation time 11572084075 ps
CPU time 16.15 seconds
Started Jul 16 08:00:53 PM PDT 24
Finished Jul 16 08:01:12 PM PDT 24
Peak memory 216080 kb
Host smart-f72a0ee6-8d7e-4e1f-85d8-b7d60203df5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647869218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1647869218
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3876314565
Short name T349
Test name
Test status
Simulation time 92522514 ps
CPU time 3.85 seconds
Started Jul 16 08:00:57 PM PDT 24
Finished Jul 16 08:01:02 PM PDT 24
Peak memory 216324 kb
Host smart-d7769a6d-aa8d-4a39-9e70-7b76446fb578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876314565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3876314565
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3317131645
Short name T292
Test name
Test status
Simulation time 48939592 ps
CPU time 0.76 seconds
Started Jul 16 08:00:55 PM PDT 24
Finished Jul 16 08:00:57 PM PDT 24
Peak memory 206000 kb
Host smart-3d15d755-ea23-46d6-bf48-bb283a31fe81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317131645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3317131645
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3318360269
Short name T849
Test name
Test status
Simulation time 4964745701 ps
CPU time 19.14 seconds
Started Jul 16 08:01:09 PM PDT 24
Finished Jul 16 08:01:29 PM PDT 24
Peak memory 249088 kb
Host smart-69564291-2dac-4a55-bdbb-482a9c85b0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318360269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3318360269
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2241613872
Short name T478
Test name
Test status
Simulation time 17102075 ps
CPU time 0.68 seconds
Started Jul 16 08:01:10 PM PDT 24
Finished Jul 16 08:01:14 PM PDT 24
Peak memory 204984 kb
Host smart-47212ac7-dbb5-4ec9-93b9-3fac497b0e14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241613872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2241613872
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1424403039
Short name T565
Test name
Test status
Simulation time 2019242097 ps
CPU time 15.98 seconds
Started Jul 16 08:01:12 PM PDT 24
Finished Jul 16 08:01:33 PM PDT 24
Peak memory 224520 kb
Host smart-3fe47441-767e-41c0-88cd-4a42aee49f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424403039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1424403039
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1689826272
Short name T309
Test name
Test status
Simulation time 20339306 ps
CPU time 0.78 seconds
Started Jul 16 08:01:40 PM PDT 24
Finished Jul 16 08:01:41 PM PDT 24
Peak memory 206616 kb
Host smart-857ad51a-8531-4cce-932c-6c9e073d2258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689826272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1689826272
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3226925724
Short name T898
Test name
Test status
Simulation time 3396201396 ps
CPU time 33.86 seconds
Started Jul 16 08:01:08 PM PDT 24
Finished Jul 16 08:01:42 PM PDT 24
Peak memory 243576 kb
Host smart-8ce4a6a8-6771-4073-bbd1-68bf5cd12ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226925724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3226925724
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3774951702
Short name T205
Test name
Test status
Simulation time 7111532177 ps
CPU time 47.6 seconds
Started Jul 16 08:01:10 PM PDT 24
Finished Jul 16 08:01:59 PM PDT 24
Peak memory 240940 kb
Host smart-db749ca1-b7da-491d-85f6-903cd4665069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774951702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3774951702
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3039645497
Short name T36
Test name
Test status
Simulation time 25889316403 ps
CPU time 83.26 seconds
Started Jul 16 08:01:10 PM PDT 24
Finished Jul 16 08:02:37 PM PDT 24
Peak memory 253824 kb
Host smart-a1e2c3da-eb66-40f0-8825-112f8befa555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039645497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3039645497
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1568748425
Short name T611
Test name
Test status
Simulation time 3788900628 ps
CPU time 33.43 seconds
Started Jul 16 08:01:12 PM PDT 24
Finished Jul 16 08:01:50 PM PDT 24
Peak memory 234000 kb
Host smart-a21647ee-7c92-42ff-ad78-55d404ab99e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568748425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1568748425
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.2909989099
Short name T42
Test name
Test status
Simulation time 81144325219 ps
CPU time 90.31 seconds
Started Jul 16 08:01:13 PM PDT 24
Finished Jul 16 08:02:48 PM PDT 24
Peak memory 257404 kb
Host smart-60301e83-bc56-47fa-a8d8-96e45bd1ad6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909989099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.2909989099
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.982631785
Short name T293
Test name
Test status
Simulation time 198852469 ps
CPU time 2.5 seconds
Started Jul 16 08:01:14 PM PDT 24
Finished Jul 16 08:01:20 PM PDT 24
Peak memory 232632 kb
Host smart-2b46f9bc-b37b-496a-9b64-21562b96b3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982631785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.982631785
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1544741700
Short name T223
Test name
Test status
Simulation time 767475929 ps
CPU time 9.07 seconds
Started Jul 16 08:01:11 PM PDT 24
Finished Jul 16 08:01:24 PM PDT 24
Peak memory 232732 kb
Host smart-4a0b1ad8-96fa-4a87-8d58-d21826fa1620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544741700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1544741700
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3298243020
Short name T427
Test name
Test status
Simulation time 3393197625 ps
CPU time 12.31 seconds
Started Jul 16 08:01:09 PM PDT 24
Finished Jul 16 08:01:24 PM PDT 24
Peak memory 232800 kb
Host smart-ec4e7736-7c56-473b-bab5-8052bb5ae2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298243020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3298243020
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2682153932
Short name T634
Test name
Test status
Simulation time 1865078133 ps
CPU time 3.61 seconds
Started Jul 16 08:01:10 PM PDT 24
Finished Jul 16 08:01:17 PM PDT 24
Peak memory 224488 kb
Host smart-8d7921c9-8585-439c-bdb3-14f8456d711a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682153932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2682153932
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.384562662
Short name T914
Test name
Test status
Simulation time 194546728 ps
CPU time 5.08 seconds
Started Jul 16 08:01:09 PM PDT 24
Finished Jul 16 08:01:16 PM PDT 24
Peak memory 218972 kb
Host smart-e527428f-e6b9-4edc-8f19-0d370880f71b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=384562662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.384562662
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.3485171074
Short name T881
Test name
Test status
Simulation time 289942600133 ps
CPU time 637.38 seconds
Started Jul 16 08:01:08 PM PDT 24
Finished Jul 16 08:11:47 PM PDT 24
Peak memory 269000 kb
Host smart-fc680de5-c15a-49a8-b810-84ad33b935ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485171074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3485171074
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3438394725
Short name T925
Test name
Test status
Simulation time 6392131108 ps
CPU time 32.99 seconds
Started Jul 16 08:01:08 PM PDT 24
Finished Jul 16 08:01:42 PM PDT 24
Peak memory 216360 kb
Host smart-2ad7cc05-310a-48ae-bbc0-c97a50685dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438394725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3438394725
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2990263611
Short name T961
Test name
Test status
Simulation time 609355811 ps
CPU time 2.12 seconds
Started Jul 16 08:01:10 PM PDT 24
Finished Jul 16 08:01:15 PM PDT 24
Peak memory 216268 kb
Host smart-52c1111e-c0ad-4d5a-827f-fbd704262476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990263611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2990263611
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2631770427
Short name T306
Test name
Test status
Simulation time 413341888 ps
CPU time 1.17 seconds
Started Jul 16 08:01:09 PM PDT 24
Finished Jul 16 08:01:11 PM PDT 24
Peak memory 216268 kb
Host smart-83f7c168-6ebd-4e95-a0e4-7edbbf29574f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631770427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2631770427
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2604468215
Short name T494
Test name
Test status
Simulation time 43571705 ps
CPU time 0.69 seconds
Started Jul 16 08:01:12 PM PDT 24
Finished Jul 16 08:01:17 PM PDT 24
Peak memory 205648 kb
Host smart-28fb1fb1-56b7-4822-8612-1f7d4d2236b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604468215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2604468215
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.575897437
Short name T1000
Test name
Test status
Simulation time 13776281640 ps
CPU time 10.81 seconds
Started Jul 16 08:01:13 PM PDT 24
Finished Jul 16 08:01:28 PM PDT 24
Peak memory 232792 kb
Host smart-5123d634-063e-4714-a814-16650a151863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575897437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.575897437
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2434767896
Short name T490
Test name
Test status
Simulation time 13126140 ps
CPU time 0.7 seconds
Started Jul 16 08:01:11 PM PDT 24
Finished Jul 16 08:01:16 PM PDT 24
Peak memory 205516 kb
Host smart-8c58ed4b-ea14-4fb7-95c4-dea99ff8de40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434767896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2434767896
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1136619682
Short name T558
Test name
Test status
Simulation time 406356985 ps
CPU time 2.69 seconds
Started Jul 16 08:01:09 PM PDT 24
Finished Jul 16 08:01:14 PM PDT 24
Peak memory 224440 kb
Host smart-0c565477-7f42-4036-aae2-711d9a25cca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136619682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1136619682
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.303561214
Short name T543
Test name
Test status
Simulation time 51667971 ps
CPU time 0.73 seconds
Started Jul 16 08:01:10 PM PDT 24
Finished Jul 16 08:01:15 PM PDT 24
Peak memory 205584 kb
Host smart-f5cddc29-0aa6-49bd-b1fe-341f27b59a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303561214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.303561214
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2630851109
Short name T188
Test name
Test status
Simulation time 896996092846 ps
CPU time 605 seconds
Started Jul 16 08:01:11 PM PDT 24
Finished Jul 16 08:11:20 PM PDT 24
Peak memory 264016 kb
Host smart-f4ee8ad3-1de8-4498-ae3d-cbecaf4c8082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630851109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2630851109
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3711743409
Short name T663
Test name
Test status
Simulation time 10246093124 ps
CPU time 47.93 seconds
Started Jul 16 08:01:11 PM PDT 24
Finished Jul 16 08:02:03 PM PDT 24
Peak memory 240924 kb
Host smart-6aed160f-a243-43b5-b659-868ba2a7a922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711743409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3711743409
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1403603139
Short name T272
Test name
Test status
Simulation time 590478579 ps
CPU time 7.77 seconds
Started Jul 16 08:01:13 PM PDT 24
Finished Jul 16 08:01:25 PM PDT 24
Peak memory 224492 kb
Host smart-c1d53b38-0850-407d-aac5-6df0328c5003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403603139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1403603139
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.1000332811
Short name T557
Test name
Test status
Simulation time 21860469726 ps
CPU time 150.66 seconds
Started Jul 16 08:01:12 PM PDT 24
Finished Jul 16 08:03:47 PM PDT 24
Peak memory 250468 kb
Host smart-885e5080-ff4b-48d8-aac6-81bcf7d73665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000332811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.1000332811
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3415764883
Short name T540
Test name
Test status
Simulation time 1133614468 ps
CPU time 5.84 seconds
Started Jul 16 08:01:10 PM PDT 24
Finished Jul 16 08:01:19 PM PDT 24
Peak memory 224476 kb
Host smart-d1dfd753-4017-4e0c-9164-9befb737031d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415764883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3415764883
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.4197751437
Short name T291
Test name
Test status
Simulation time 14116810504 ps
CPU time 13.9 seconds
Started Jul 16 08:01:12 PM PDT 24
Finished Jul 16 08:01:31 PM PDT 24
Peak memory 224592 kb
Host smart-b4851bbe-1d9e-4c83-b6a8-1fbec2017946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197751437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.4197751437
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1411308439
Short name T159
Test name
Test status
Simulation time 1817735382 ps
CPU time 4.28 seconds
Started Jul 16 08:01:13 PM PDT 24
Finished Jul 16 08:01:22 PM PDT 24
Peak memory 224476 kb
Host smart-33adb816-939f-4365-b4d0-8394da09e12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411308439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1411308439
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1090901247
Short name T645
Test name
Test status
Simulation time 424938059 ps
CPU time 6.41 seconds
Started Jul 16 08:01:09 PM PDT 24
Finished Jul 16 08:01:16 PM PDT 24
Peak memory 232664 kb
Host smart-06136a7a-d29a-4c93-97a9-7c3c72e94cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090901247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1090901247
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3039781028
Short name T118
Test name
Test status
Simulation time 743271939 ps
CPU time 4.63 seconds
Started Jul 16 08:01:14 PM PDT 24
Finished Jul 16 08:01:23 PM PDT 24
Peak memory 222540 kb
Host smart-94172175-33d0-43f3-86e6-df7b1c753be6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3039781028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3039781028
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1469655072
Short name T749
Test name
Test status
Simulation time 234342650 ps
CPU time 1.06 seconds
Started Jul 16 08:01:10 PM PDT 24
Finished Jul 16 08:01:14 PM PDT 24
Peak memory 206968 kb
Host smart-cb1085bd-0a85-4b57-b982-e1f8bab48267
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469655072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1469655072
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3127860532
Short name T696
Test name
Test status
Simulation time 879854383 ps
CPU time 12.37 seconds
Started Jul 16 08:01:16 PM PDT 24
Finished Jul 16 08:01:31 PM PDT 24
Peak memory 216448 kb
Host smart-f69b672f-382f-46dd-bfc8-ecfd18c18685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127860532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3127860532
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3629797905
Short name T423
Test name
Test status
Simulation time 7555919128 ps
CPU time 20.56 seconds
Started Jul 16 08:01:13 PM PDT 24
Finished Jul 16 08:01:38 PM PDT 24
Peak memory 216264 kb
Host smart-0085e129-9f3e-41e4-a3da-16d68885352b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629797905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3629797905
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1106170022
Short name T661
Test name
Test status
Simulation time 68602516 ps
CPU time 1.92 seconds
Started Jul 16 08:01:12 PM PDT 24
Finished Jul 16 08:01:19 PM PDT 24
Peak memory 217424 kb
Host smart-16085f13-a676-4fc4-a287-201db0f34881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106170022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1106170022
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1913367508
Short name T503
Test name
Test status
Simulation time 230005411 ps
CPU time 0.88 seconds
Started Jul 16 08:01:10 PM PDT 24
Finished Jul 16 08:01:14 PM PDT 24
Peak memory 205976 kb
Host smart-d53e02ea-b43b-4d0e-a963-540899dd0638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913367508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1913367508
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3464045360
Short name T793
Test name
Test status
Simulation time 2391172190 ps
CPU time 6.99 seconds
Started Jul 16 08:01:10 PM PDT 24
Finished Jul 16 08:01:20 PM PDT 24
Peak memory 224608 kb
Host smart-b8d83bde-5a6d-49dd-af6f-88c106c0820f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464045360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3464045360
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.871230625
Short name T759
Test name
Test status
Simulation time 84190503 ps
CPU time 0.71 seconds
Started Jul 16 08:01:14 PM PDT 24
Finished Jul 16 08:01:19 PM PDT 24
Peak memory 204976 kb
Host smart-72769fc6-45cb-487e-a0b9-d36604a17efb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871230625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.871230625
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.4142503753
Short name T1003
Test name
Test status
Simulation time 891819902 ps
CPU time 5.34 seconds
Started Jul 16 08:01:11 PM PDT 24
Finished Jul 16 08:01:21 PM PDT 24
Peak memory 232672 kb
Host smart-76953aff-44b8-4f02-95f1-770b867b2546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142503753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.4142503753
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3756604699
Short name T332
Test name
Test status
Simulation time 13093369 ps
CPU time 0.73 seconds
Started Jul 16 08:01:10 PM PDT 24
Finished Jul 16 08:01:12 PM PDT 24
Peak memory 206924 kb
Host smart-a08d76ff-83c0-4250-80ea-e40558d4dcc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756604699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3756604699
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.4258948576
Short name T525
Test name
Test status
Simulation time 5853398836 ps
CPU time 61.41 seconds
Started Jul 16 08:01:11 PM PDT 24
Finished Jul 16 08:02:16 PM PDT 24
Peak memory 249200 kb
Host smart-d36c8e89-2815-49c8-9574-d9ca462b69d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258948576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.4258948576
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3447569989
Short name T237
Test name
Test status
Simulation time 71009810567 ps
CPU time 575.2 seconds
Started Jul 16 08:01:10 PM PDT 24
Finished Jul 16 08:10:48 PM PDT 24
Peak memory 266680 kb
Host smart-7cc5f752-076a-4a20-af23-bab2871884d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447569989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3447569989
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.4237038610
Short name T434
Test name
Test status
Simulation time 12232979309 ps
CPU time 77.81 seconds
Started Jul 16 08:01:14 PM PDT 24
Finished Jul 16 08:02:36 PM PDT 24
Peak memory 256792 kb
Host smart-dec2917b-33d2-4795-b0ae-b5672f82f9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237038610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.4237038610
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2683847832
Short name T971
Test name
Test status
Simulation time 287843475 ps
CPU time 9.5 seconds
Started Jul 16 08:01:11 PM PDT 24
Finished Jul 16 08:01:25 PM PDT 24
Peak memory 232448 kb
Host smart-3ea0fa7b-202b-4aa4-a64c-6cc51aedb5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683847832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2683847832
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.557364606
Short name T916
Test name
Test status
Simulation time 21469353183 ps
CPU time 148.28 seconds
Started Jul 16 08:01:10 PM PDT 24
Finished Jul 16 08:03:41 PM PDT 24
Peak memory 239712 kb
Host smart-3c384024-a68f-422e-a5e4-aaa96e498a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557364606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds
.557364606
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.464269676
Short name T193
Test name
Test status
Simulation time 17353603557 ps
CPU time 26.17 seconds
Started Jul 16 08:01:12 PM PDT 24
Finished Jul 16 08:01:43 PM PDT 24
Peak memory 224580 kb
Host smart-b377dd63-0d0c-42ed-ae3c-89e022a0a765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464269676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.464269676
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1694817437
Short name T420
Test name
Test status
Simulation time 900663426 ps
CPU time 10 seconds
Started Jul 16 08:01:11 PM PDT 24
Finished Jul 16 08:01:25 PM PDT 24
Peak memory 224480 kb
Host smart-52957d34-bb67-40e0-a501-2e9505857627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694817437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1694817437
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3867187109
Short name T16
Test name
Test status
Simulation time 4680150473 ps
CPU time 14.99 seconds
Started Jul 16 08:01:11 PM PDT 24
Finished Jul 16 08:01:30 PM PDT 24
Peak memory 224540 kb
Host smart-a1620f24-fd66-4f20-bf98-e72e076b723c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867187109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3867187109
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2200888905
Short name T893
Test name
Test status
Simulation time 9832914485 ps
CPU time 9.68 seconds
Started Jul 16 08:01:11 PM PDT 24
Finished Jul 16 08:01:25 PM PDT 24
Peak memory 224640 kb
Host smart-49181f08-a294-4227-8c9b-57ddab425938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200888905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2200888905
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1394632067
Short name T673
Test name
Test status
Simulation time 92604380 ps
CPU time 3.73 seconds
Started Jul 16 08:01:11 PM PDT 24
Finished Jul 16 08:01:19 PM PDT 24
Peak memory 223076 kb
Host smart-b9ee370d-6570-4e4b-98db-12f376912097
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1394632067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1394632067
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1838779293
Short name T229
Test name
Test status
Simulation time 44274146317 ps
CPU time 244.93 seconds
Started Jul 16 08:01:15 PM PDT 24
Finished Jul 16 08:05:23 PM PDT 24
Peak memory 260316 kb
Host smart-c865abab-7fe4-4d4f-9a3a-ada5dea38acc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838779293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1838779293
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2831101500
Short name T721
Test name
Test status
Simulation time 78407004054 ps
CPU time 22.29 seconds
Started Jul 16 08:01:11 PM PDT 24
Finished Jul 16 08:01:38 PM PDT 24
Peak memory 216392 kb
Host smart-f4b6242a-0140-476e-a3c7-ffabd9aca2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831101500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2831101500
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3645977304
Short name T320
Test name
Test status
Simulation time 814161834 ps
CPU time 4.73 seconds
Started Jul 16 08:01:16 PM PDT 24
Finished Jul 16 08:01:24 PM PDT 24
Peak memory 216216 kb
Host smart-fa7ab9d7-fcfa-48e0-8b2d-c32b4f40cd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645977304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3645977304
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1406274197
Short name T660
Test name
Test status
Simulation time 36288103 ps
CPU time 0.69 seconds
Started Jul 16 08:01:11 PM PDT 24
Finished Jul 16 08:01:15 PM PDT 24
Peak memory 205660 kb
Host smart-f289dad5-7ee7-444c-8fc3-964b8b9c397e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406274197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1406274197
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2715532398
Short name T894
Test name
Test status
Simulation time 65168761 ps
CPU time 0.84 seconds
Started Jul 16 08:01:11 PM PDT 24
Finished Jul 16 08:01:16 PM PDT 24
Peak memory 205992 kb
Host smart-e08c5f0c-77dc-49d2-8608-375a224d1b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715532398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2715532398
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2987649284
Short name T428
Test name
Test status
Simulation time 374070309 ps
CPU time 5.09 seconds
Started Jul 16 08:01:12 PM PDT 24
Finished Jul 16 08:01:22 PM PDT 24
Peak memory 237824 kb
Host smart-175b5ecf-3467-490d-a23a-70b31842522d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987649284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2987649284
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3592635820
Short name T600
Test name
Test status
Simulation time 39773393 ps
CPU time 0.69 seconds
Started Jul 16 08:02:16 PM PDT 24
Finished Jul 16 08:02:22 PM PDT 24
Peak memory 205576 kb
Host smart-93130cc8-44b5-4998-b3bf-13eb963b94cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592635820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3592635820
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.256328738
Short name T410
Test name
Test status
Simulation time 171943954 ps
CPU time 2.4 seconds
Started Jul 16 08:01:13 PM PDT 24
Finished Jul 16 08:01:20 PM PDT 24
Peak memory 224636 kb
Host smart-9357205a-783d-4e47-bd5b-69b80db7fd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256328738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.256328738
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1590215154
Short name T675
Test name
Test status
Simulation time 69269808 ps
CPU time 0.85 seconds
Started Jul 16 08:01:12 PM PDT 24
Finished Jul 16 08:01:18 PM PDT 24
Peak memory 206632 kb
Host smart-e4535909-9ba5-47d2-8984-fd6418d4c5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590215154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1590215154
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1918195514
Short name T409
Test name
Test status
Simulation time 781445059 ps
CPU time 13.79 seconds
Started Jul 16 08:01:11 PM PDT 24
Finished Jul 16 08:01:28 PM PDT 24
Peak memory 232764 kb
Host smart-fc349971-521b-4bc9-9bc0-e74ef1df6c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918195514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1918195514
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2969759306
Short name T844
Test name
Test status
Simulation time 16737939399 ps
CPU time 68.05 seconds
Started Jul 16 08:01:14 PM PDT 24
Finished Jul 16 08:02:26 PM PDT 24
Peak memory 252504 kb
Host smart-a1e7cda6-d814-438d-8760-3a6240e0ca1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969759306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2969759306
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3616626951
Short name T594
Test name
Test status
Simulation time 219422885158 ps
CPU time 150.61 seconds
Started Jul 16 08:01:11 PM PDT 24
Finished Jul 16 08:03:46 PM PDT 24
Peak memory 253984 kb
Host smart-6c6b6004-7fa2-47fb-81a2-604f6efee98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616626951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3616626951
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1557072405
Short name T265
Test name
Test status
Simulation time 1687173952 ps
CPU time 19.54 seconds
Started Jul 16 08:01:14 PM PDT 24
Finished Jul 16 08:01:38 PM PDT 24
Peak memory 224624 kb
Host smart-ae5f568e-1b96-4121-b515-55c6a7a63efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557072405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1557072405
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.3665693694
Short name T191
Test name
Test status
Simulation time 24422135119 ps
CPU time 115.43 seconds
Started Jul 16 08:01:14 PM PDT 24
Finished Jul 16 08:03:13 PM PDT 24
Peak memory 241152 kb
Host smart-7fb377ca-d67e-48f8-a230-5862c9b35e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665693694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.3665693694
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1410138181
Short name T532
Test name
Test status
Simulation time 624081839 ps
CPU time 3.65 seconds
Started Jul 16 08:01:13 PM PDT 24
Finished Jul 16 08:01:21 PM PDT 24
Peak memory 224456 kb
Host smart-c4a65148-201f-4bc2-a684-7fc8373b23a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410138181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1410138181
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.427979188
Short name T870
Test name
Test status
Simulation time 2419748286 ps
CPU time 12.01 seconds
Started Jul 16 08:01:15 PM PDT 24
Finished Jul 16 08:01:30 PM PDT 24
Peak memory 224580 kb
Host smart-bfe90b3b-3156-4a88-bef5-3df59f76a3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427979188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.427979188
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3716097554
Short name T433
Test name
Test status
Simulation time 30559897 ps
CPU time 2.18 seconds
Started Jul 16 08:01:11 PM PDT 24
Finished Jul 16 08:01:18 PM PDT 24
Peak memory 232380 kb
Host smart-ff316413-83b6-47ee-9913-b9994582eaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716097554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3716097554
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2624276635
Short name T589
Test name
Test status
Simulation time 1362697748 ps
CPU time 6.52 seconds
Started Jul 16 08:01:13 PM PDT 24
Finished Jul 16 08:01:24 PM PDT 24
Peak memory 232664 kb
Host smart-a1b29969-3001-498c-affe-0be311cdd38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624276635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2624276635
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.931654285
Short name T910
Test name
Test status
Simulation time 481319804 ps
CPU time 7.1 seconds
Started Jul 16 08:00:55 PM PDT 24
Finished Jul 16 08:01:04 PM PDT 24
Peak memory 222140 kb
Host smart-3e4ff068-45c8-4594-b91a-06d12978a103
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=931654285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.931654285
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2659990257
Short name T826
Test name
Test status
Simulation time 16932393609 ps
CPU time 238.51 seconds
Started Jul 16 08:01:11 PM PDT 24
Finished Jul 16 08:05:15 PM PDT 24
Peak memory 268968 kb
Host smart-81f7dbe2-e67c-442a-af6f-5c91d0133f8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659990257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2659990257
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3171749707
Short name T827
Test name
Test status
Simulation time 6144366071 ps
CPU time 5.45 seconds
Started Jul 16 08:01:11 PM PDT 24
Finished Jul 16 08:01:20 PM PDT 24
Peak memory 216632 kb
Host smart-aaad43ec-692d-4a3d-a9c9-43b3fc5ade20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171749707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3171749707
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.4117376890
Short name T14
Test name
Test status
Simulation time 2520611974 ps
CPU time 8.07 seconds
Started Jul 16 08:01:11 PM PDT 24
Finished Jul 16 08:01:23 PM PDT 24
Peak memory 216352 kb
Host smart-8f1fc52f-5e00-4878-9d71-d4328e9ce377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117376890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.4117376890
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1802589178
Short name T437
Test name
Test status
Simulation time 44457234 ps
CPU time 0.87 seconds
Started Jul 16 08:01:15 PM PDT 24
Finished Jul 16 08:01:19 PM PDT 24
Peak memory 207176 kb
Host smart-5b4b8fe6-d2b2-4811-8d62-5c39936a68b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802589178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1802589178
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1347831526
Short name T322
Test name
Test status
Simulation time 42128905 ps
CPU time 0.7 seconds
Started Jul 16 08:01:12 PM PDT 24
Finished Jul 16 08:01:18 PM PDT 24
Peak memory 205996 kb
Host smart-4456f7a9-cb8f-403a-bdd6-24b7fa88a3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347831526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1347831526
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2321073132
Short name T393
Test name
Test status
Simulation time 426474295 ps
CPU time 4.67 seconds
Started Jul 16 08:01:13 PM PDT 24
Finished Jul 16 08:01:22 PM PDT 24
Peak memory 234108 kb
Host smart-f2d8d70f-987c-4d7e-87a5-8f991b95a769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321073132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2321073132
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.256225919
Short name T318
Test name
Test status
Simulation time 23153692 ps
CPU time 0.77 seconds
Started Jul 16 07:59:44 PM PDT 24
Finished Jul 16 07:59:47 PM PDT 24
Peak memory 205536 kb
Host smart-0690e130-9ec1-4876-b85b-286a567e7b07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256225919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.256225919
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2948249096
Short name T75
Test name
Test status
Simulation time 1207077233 ps
CPU time 10.58 seconds
Started Jul 16 07:59:28 PM PDT 24
Finished Jul 16 07:59:41 PM PDT 24
Peak memory 232708 kb
Host smart-4ce86a22-c024-4efd-adad-d8181e4f6251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948249096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2948249096
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2143144379
Short name T457
Test name
Test status
Simulation time 17738396 ps
CPU time 0.78 seconds
Started Jul 16 07:59:27 PM PDT 24
Finished Jul 16 07:59:29 PM PDT 24
Peak memory 206908 kb
Host smart-d597bb21-9aa7-4153-bab3-097d085c4896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143144379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2143144379
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1720870272
Short name T403
Test name
Test status
Simulation time 61118525 ps
CPU time 0.79 seconds
Started Jul 16 07:59:27 PM PDT 24
Finished Jul 16 07:59:31 PM PDT 24
Peak memory 215788 kb
Host smart-46174d28-fa3b-419e-ba36-9a036ea11e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720870272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1720870272
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1824879789
Short name T492
Test name
Test status
Simulation time 1971241315 ps
CPU time 22.2 seconds
Started Jul 16 07:59:45 PM PDT 24
Finished Jul 16 08:00:10 PM PDT 24
Peak memory 237660 kb
Host smart-86009778-5c73-46f8-818a-20a43d538c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824879789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1824879789
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.843660716
Short name T234
Test name
Test status
Simulation time 2982442102 ps
CPU time 75.64 seconds
Started Jul 16 07:59:44 PM PDT 24
Finished Jul 16 08:01:02 PM PDT 24
Peak memory 273188 kb
Host smart-077715bf-3d58-46ac-988d-178b188d9bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843660716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
843660716
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3787825001
Short name T697
Test name
Test status
Simulation time 1849054805 ps
CPU time 8.58 seconds
Started Jul 16 07:59:27 PM PDT 24
Finished Jul 16 07:59:38 PM PDT 24
Peak memory 224460 kb
Host smart-6fa47b1e-dce0-4687-a05a-7a140e83e205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787825001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3787825001
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.535742888
Short name T386
Test name
Test status
Simulation time 46720748616 ps
CPU time 93.77 seconds
Started Jul 16 07:59:27 PM PDT 24
Finished Jul 16 08:01:03 PM PDT 24
Peak memory 257376 kb
Host smart-82648715-b502-41a2-928b-3702cd33b972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535742888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.
535742888
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1466816309
Short name T704
Test name
Test status
Simulation time 294679469 ps
CPU time 4.83 seconds
Started Jul 16 07:59:49 PM PDT 24
Finished Jul 16 07:59:56 PM PDT 24
Peak memory 224424 kb
Host smart-f9cde090-82d4-44d5-82d5-2d6974830089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466816309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1466816309
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3771183954
Short name T902
Test name
Test status
Simulation time 4284732747 ps
CPU time 18.26 seconds
Started Jul 16 07:59:27 PM PDT 24
Finished Jul 16 07:59:48 PM PDT 24
Peak memory 241016 kb
Host smart-0d6c5959-6ea3-4c20-9147-ae6d46793131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771183954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3771183954
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.487342284
Short name T412
Test name
Test status
Simulation time 5849786537 ps
CPU time 9.56 seconds
Started Jul 16 07:59:27 PM PDT 24
Finished Jul 16 07:59:40 PM PDT 24
Peak memory 232856 kb
Host smart-25a6cacc-e139-4ffc-87a6-711b5f7ed942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487342284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
487342284
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2239118648
Short name T888
Test name
Test status
Simulation time 1081574589 ps
CPU time 5.26 seconds
Started Jul 16 07:59:49 PM PDT 24
Finished Jul 16 07:59:57 PM PDT 24
Peak memory 232424 kb
Host smart-092b16f4-948d-45e7-abbb-479783386d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239118648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2239118648
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1505986199
Short name T717
Test name
Test status
Simulation time 733853882 ps
CPU time 3.89 seconds
Started Jul 16 07:59:28 PM PDT 24
Finished Jul 16 07:59:34 PM PDT 24
Peak memory 223148 kb
Host smart-0d6742a0-8b2f-4590-b940-dc00a2c5cb7b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1505986199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1505986199
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1021530456
Short name T32
Test name
Test status
Simulation time 285513137 ps
CPU time 1.55 seconds
Started Jul 16 07:59:47 PM PDT 24
Finished Jul 16 07:59:52 PM PDT 24
Peak memory 236552 kb
Host smart-48ddf5f3-8472-4771-98c9-dcf17964b373
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021530456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1021530456
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1332351359
Short name T131
Test name
Test status
Simulation time 81253325636 ps
CPU time 195.8 seconds
Started Jul 16 07:59:48 PM PDT 24
Finished Jul 16 08:03:06 PM PDT 24
Peak memory 249532 kb
Host smart-5b1caa79-4b18-4aca-a859-28ca05e6e959
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332351359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1332351359
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.921363427
Short name T610
Test name
Test status
Simulation time 6455980776 ps
CPU time 6.83 seconds
Started Jul 16 07:59:34 PM PDT 24
Finished Jul 16 07:59:41 PM PDT 24
Peak memory 216340 kb
Host smart-39abac1a-098a-4dfa-97a9-e40c85966704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921363427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.921363427
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.66730447
Short name T979
Test name
Test status
Simulation time 4483494834 ps
CPU time 5.14 seconds
Started Jul 16 07:59:32 PM PDT 24
Finished Jul 16 07:59:38 PM PDT 24
Peak memory 216292 kb
Host smart-49e4cd85-a64d-4960-8899-effac0352147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66730447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.66730447
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.4002635354
Short name T699
Test name
Test status
Simulation time 609149470 ps
CPU time 5.27 seconds
Started Jul 16 07:59:26 PM PDT 24
Finished Jul 16 07:59:34 PM PDT 24
Peak memory 216212 kb
Host smart-93978ad4-31ab-4aee-a64b-1b7a0023332d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002635354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.4002635354
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2263839607
Short name T341
Test name
Test status
Simulation time 69544771 ps
CPU time 0.75 seconds
Started Jul 16 07:59:49 PM PDT 24
Finished Jul 16 07:59:52 PM PDT 24
Peak memory 205804 kb
Host smart-e739df78-c64c-4f4b-ac5a-40577301045b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263839607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2263839607
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2660722400
Short name T612
Test name
Test status
Simulation time 362932462 ps
CPU time 2.09 seconds
Started Jul 16 07:59:27 PM PDT 24
Finished Jul 16 07:59:31 PM PDT 24
Peak memory 232328 kb
Host smart-567b396b-b491-4ae1-bbcd-0d5f71c79523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660722400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2660722400
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2585373453
Short name T776
Test name
Test status
Simulation time 27391171 ps
CPU time 0.72 seconds
Started Jul 16 08:02:16 PM PDT 24
Finished Jul 16 08:02:21 PM PDT 24
Peak memory 204992 kb
Host smart-4d1adf33-1564-4531-97a3-e0d122d260cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585373453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2585373453
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3399517932
Short name T488
Test name
Test status
Simulation time 83194278 ps
CPU time 3.75 seconds
Started Jul 16 08:02:13 PM PDT 24
Finished Jul 16 08:02:19 PM PDT 24
Peak memory 232640 kb
Host smart-768a52f7-257c-4500-a033-0ee94eeefb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399517932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3399517932
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2953590166
Short name T527
Test name
Test status
Simulation time 62725990 ps
CPU time 0.78 seconds
Started Jul 16 08:02:10 PM PDT 24
Finished Jul 16 08:02:12 PM PDT 24
Peak memory 206912 kb
Host smart-d1aa3dd2-b50d-42d6-85b3-40fa30db9590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953590166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2953590166
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.472090741
Short name T997
Test name
Test status
Simulation time 4846876108 ps
CPU time 38.32 seconds
Started Jul 16 08:02:10 PM PDT 24
Finished Jul 16 08:02:49 PM PDT 24
Peak memory 240996 kb
Host smart-561bef7f-68ec-41ef-bd83-936731b6f6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472090741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.472090741
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2780966521
Short name T996
Test name
Test status
Simulation time 52802732240 ps
CPU time 407.26 seconds
Started Jul 16 08:01:58 PM PDT 24
Finished Jul 16 08:08:46 PM PDT 24
Peak memory 255228 kb
Host smart-3187b209-6474-4f74-964f-e38712d66bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780966521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2780966521
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.634689325
Short name T551
Test name
Test status
Simulation time 26829308109 ps
CPU time 260.97 seconds
Started Jul 16 08:02:17 PM PDT 24
Finished Jul 16 08:06:44 PM PDT 24
Peak memory 249244 kb
Host smart-1d19957b-9f97-4460-808e-5772172f1c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634689325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.634689325
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3529438414
Short name T900
Test name
Test status
Simulation time 5959142092 ps
CPU time 18.82 seconds
Started Jul 16 08:01:31 PM PDT 24
Finished Jul 16 08:01:51 PM PDT 24
Peak memory 232832 kb
Host smart-28e97ff4-4609-429f-aefa-78a934a383eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529438414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3529438414
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.1477726635
Short name T452
Test name
Test status
Simulation time 3156413795 ps
CPU time 24.2 seconds
Started Jul 16 08:02:16 PM PDT 24
Finished Jul 16 08:02:45 PM PDT 24
Peak memory 224652 kb
Host smart-6686dac8-e4d3-4165-a74e-3b14f60981b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477726635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.1477726635
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.112054117
Short name T534
Test name
Test status
Simulation time 28700310 ps
CPU time 2.41 seconds
Started Jul 16 08:02:12 PM PDT 24
Finished Jul 16 08:02:15 PM PDT 24
Peak memory 232324 kb
Host smart-aae822ac-16a2-47e3-9b46-115fa0059d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112054117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.112054117
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2252278425
Short name T975
Test name
Test status
Simulation time 8833748550 ps
CPU time 78.73 seconds
Started Jul 16 08:02:13 PM PDT 24
Finished Jul 16 08:03:34 PM PDT 24
Peak memory 232788 kb
Host smart-90b07110-5ece-45d6-9b01-6f5a0561c93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252278425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2252278425
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2795152280
Short name T509
Test name
Test status
Simulation time 703015232 ps
CPU time 2.95 seconds
Started Jul 16 08:02:16 PM PDT 24
Finished Jul 16 08:02:24 PM PDT 24
Peak memory 224412 kb
Host smart-72711da2-4574-4bdd-92d2-47a61f4692fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795152280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2795152280
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1444847473
Short name T756
Test name
Test status
Simulation time 253587558 ps
CPU time 5.04 seconds
Started Jul 16 08:02:14 PM PDT 24
Finished Jul 16 08:02:22 PM PDT 24
Peak memory 232568 kb
Host smart-fa1d602c-de41-4e77-8da0-633bcdf5dd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444847473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1444847473
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.340433738
Short name T813
Test name
Test status
Simulation time 23938986464 ps
CPU time 12.82 seconds
Started Jul 16 08:02:15 PM PDT 24
Finished Jul 16 08:02:31 PM PDT 24
Peak memory 221744 kb
Host smart-f17af75d-db13-4cdf-9c49-4c3cdd0d5abe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=340433738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.340433738
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3078763776
Short name T595
Test name
Test status
Simulation time 3635733520 ps
CPU time 22.91 seconds
Started Jul 16 08:01:59 PM PDT 24
Finished Jul 16 08:02:23 PM PDT 24
Peak memory 224576 kb
Host smart-1aaf92aa-602c-40c7-9372-30e9748f055c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078763776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3078763776
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3046301756
Short name T879
Test name
Test status
Simulation time 5973933760 ps
CPU time 6.6 seconds
Started Jul 16 08:02:14 PM PDT 24
Finished Jul 16 08:02:22 PM PDT 24
Peak memory 216284 kb
Host smart-4b217f6d-4b9c-46c3-9e13-2ec562393525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046301756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3046301756
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1723505814
Short name T945
Test name
Test status
Simulation time 5006338535 ps
CPU time 6 seconds
Started Jul 16 08:01:56 PM PDT 24
Finished Jul 16 08:02:03 PM PDT 24
Peak memory 216348 kb
Host smart-e5aba48e-c445-456c-b6c7-c57b096b6980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723505814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1723505814
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3462830945
Short name T733
Test name
Test status
Simulation time 62086489 ps
CPU time 0.99 seconds
Started Jul 16 08:02:14 PM PDT 24
Finished Jul 16 08:02:18 PM PDT 24
Peak memory 206984 kb
Host smart-7212db91-8278-47ee-bfbc-93bf8cf9a09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462830945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3462830945
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3968056317
Short name T705
Test name
Test status
Simulation time 117740271 ps
CPU time 0.78 seconds
Started Jul 16 08:02:15 PM PDT 24
Finished Jul 16 08:02:19 PM PDT 24
Peak memory 206004 kb
Host smart-2abb3e06-5713-42c2-9fd2-275c5b560cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968056317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3968056317
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3849032570
Short name T582
Test name
Test status
Simulation time 8528627248 ps
CPU time 16.52 seconds
Started Jul 16 08:02:10 PM PDT 24
Finished Jul 16 08:02:28 PM PDT 24
Peak memory 240600 kb
Host smart-1c3a720b-5ade-4c70-91f5-14c3a359fdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849032570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3849032570
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.4263454672
Short name T303
Test name
Test status
Simulation time 16256760 ps
CPU time 0.72 seconds
Started Jul 16 08:02:16 PM PDT 24
Finished Jul 16 08:02:22 PM PDT 24
Peak memory 204972 kb
Host smart-1508b32b-dc98-43dc-ba6f-f88c19dc41b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263454672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
4263454672
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.636785726
Short name T751
Test name
Test status
Simulation time 517975527 ps
CPU time 2.54 seconds
Started Jul 16 08:02:14 PM PDT 24
Finished Jul 16 08:02:18 PM PDT 24
Peak memory 224524 kb
Host smart-112f4adb-64d2-48b8-a63b-8234fd3c5de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636785726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.636785726
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2246965752
Short name T872
Test name
Test status
Simulation time 38528362 ps
CPU time 0.76 seconds
Started Jul 16 08:02:17 PM PDT 24
Finished Jul 16 08:02:24 PM PDT 24
Peak memory 206612 kb
Host smart-7e1a87ba-6182-4cf9-bcac-0e9d934fb5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246965752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2246965752
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3758562107
Short name T165
Test name
Test status
Simulation time 65699292916 ps
CPU time 134.21 seconds
Started Jul 16 08:02:06 PM PDT 24
Finished Jul 16 08:04:21 PM PDT 24
Peak memory 251328 kb
Host smart-15cf524e-8db3-4155-a0c3-4dcebefb49c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758562107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3758562107
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3213976436
Short name T463
Test name
Test status
Simulation time 91786718515 ps
CPU time 244.61 seconds
Started Jul 16 08:02:16 PM PDT 24
Finished Jul 16 08:06:26 PM PDT 24
Peak memory 253088 kb
Host smart-e27f2ecd-39a3-4cf9-9593-6e1363d79419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213976436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3213976436
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.4040319857
Short name T44
Test name
Test status
Simulation time 5957442232 ps
CPU time 90.81 seconds
Started Jul 16 08:02:16 PM PDT 24
Finished Jul 16 08:03:52 PM PDT 24
Peak memory 250392 kb
Host smart-1e8a0dcf-c495-4bda-b52c-f18375386342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040319857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.4040319857
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.1954042861
Short name T240
Test name
Test status
Simulation time 9260777597 ps
CPU time 85.58 seconds
Started Jul 16 08:02:17 PM PDT 24
Finished Jul 16 08:03:48 PM PDT 24
Peak memory 271208 kb
Host smart-01139f0e-4ef7-4ca7-a924-af72fc92ec0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954042861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.1954042861
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.310769249
Short name T607
Test name
Test status
Simulation time 1707081660 ps
CPU time 9.39 seconds
Started Jul 16 08:02:17 PM PDT 24
Finished Jul 16 08:02:32 PM PDT 24
Peak memory 224456 kb
Host smart-0d50d7d7-6222-4ed5-b368-27143fd30a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310769249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.310769249
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1208883196
Short name T502
Test name
Test status
Simulation time 264130341 ps
CPU time 4.01 seconds
Started Jul 16 08:02:14 PM PDT 24
Finished Jul 16 08:02:21 PM PDT 24
Peak memory 224376 kb
Host smart-acffc89d-4ec1-4d3b-a513-a3a90f15d353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208883196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1208883196
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3830715011
Short name T220
Test name
Test status
Simulation time 570241743 ps
CPU time 2.98 seconds
Started Jul 16 08:02:05 PM PDT 24
Finished Jul 16 08:02:08 PM PDT 24
Peak memory 224516 kb
Host smart-36bed64a-eeba-4102-9fc7-1d2780415515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830715011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3830715011
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3477183817
Short name T301
Test name
Test status
Simulation time 4649361587 ps
CPU time 10.45 seconds
Started Jul 16 08:02:15 PM PDT 24
Finished Jul 16 08:02:29 PM PDT 24
Peak memory 224664 kb
Host smart-ef446839-10d3-4ad7-8d3f-ce2cd2fe053b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477183817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3477183817
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1289778314
Short name T472
Test name
Test status
Simulation time 1346984506 ps
CPU time 9.86 seconds
Started Jul 16 08:02:20 PM PDT 24
Finished Jul 16 08:02:36 PM PDT 24
Peak memory 220772 kb
Host smart-2a2a23fe-636c-48cb-9bb7-4c61942117ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1289778314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1289778314
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1084150634
Short name T21
Test name
Test status
Simulation time 171384025 ps
CPU time 0.95 seconds
Started Jul 16 08:02:16 PM PDT 24
Finished Jul 16 08:02:21 PM PDT 24
Peak memory 206892 kb
Host smart-0d523972-8fba-4c17-9329-e5a6c119e2fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084150634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1084150634
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1493184788
Short name T327
Test name
Test status
Simulation time 6989733687 ps
CPU time 38.42 seconds
Started Jul 16 08:02:16 PM PDT 24
Finished Jul 16 08:03:00 PM PDT 24
Peak memory 216356 kb
Host smart-634ea9a7-00cd-4b1f-b8b7-3eb687a3ea46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493184788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1493184788
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2705499203
Short name T993
Test name
Test status
Simulation time 2305976954 ps
CPU time 8.48 seconds
Started Jul 16 08:02:10 PM PDT 24
Finished Jul 16 08:02:19 PM PDT 24
Peak memory 216376 kb
Host smart-f27d58f3-9e6f-4ac2-afaa-88708fbf8a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705499203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2705499203
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3842502274
Short name T803
Test name
Test status
Simulation time 171263687 ps
CPU time 5.5 seconds
Started Jul 16 08:02:15 PM PDT 24
Finished Jul 16 08:02:24 PM PDT 24
Peak memory 216276 kb
Host smart-7e427ebd-225d-4aee-a890-875850a2f4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842502274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3842502274
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.679864551
Short name T7
Test name
Test status
Simulation time 23782646 ps
CPU time 0.83 seconds
Started Jul 16 08:02:02 PM PDT 24
Finished Jul 16 08:02:03 PM PDT 24
Peak memory 205972 kb
Host smart-83034419-6763-437b-bc45-4d82a407777c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679864551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.679864551
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2411879396
Short name T337
Test name
Test status
Simulation time 52890816 ps
CPU time 2.77 seconds
Started Jul 16 08:01:56 PM PDT 24
Finished Jul 16 08:02:00 PM PDT 24
Peak memory 224460 kb
Host smart-c9b30174-9bf9-4413-9dcf-5a1a7b488573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411879396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2411879396
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1113314501
Short name T937
Test name
Test status
Simulation time 42902199 ps
CPU time 0.78 seconds
Started Jul 16 08:02:17 PM PDT 24
Finished Jul 16 08:02:23 PM PDT 24
Peak memory 204896 kb
Host smart-677677d5-b701-4064-af42-ee0f1119bf33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113314501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1113314501
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3003647549
Short name T74
Test name
Test status
Simulation time 195466069 ps
CPU time 4.56 seconds
Started Jul 16 08:02:14 PM PDT 24
Finished Jul 16 08:02:21 PM PDT 24
Peak memory 224412 kb
Host smart-84816741-5526-46ce-9bde-811511ecbbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003647549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3003647549
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.170916469
Short name T329
Test name
Test status
Simulation time 48051033 ps
CPU time 0.76 seconds
Started Jul 16 08:02:17 PM PDT 24
Finished Jul 16 08:02:24 PM PDT 24
Peak memory 206920 kb
Host smart-ec70077f-ee9f-40d1-93cf-f6facd0a7afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170916469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.170916469
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.14467197
Short name T542
Test name
Test status
Simulation time 276160679740 ps
CPU time 212.05 seconds
Started Jul 16 08:01:58 PM PDT 24
Finished Jul 16 08:05:31 PM PDT 24
Peak memory 252720 kb
Host smart-c776b13e-798e-439b-b070-1622ec1f8f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14467197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.14467197
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2948932477
Short name T989
Test name
Test status
Simulation time 34893340279 ps
CPU time 299.92 seconds
Started Jul 16 08:02:16 PM PDT 24
Finished Jul 16 08:07:21 PM PDT 24
Peak memory 265672 kb
Host smart-18ec03fb-8240-442e-9998-5b03b3fe8e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948932477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2948932477
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1128837069
Short name T512
Test name
Test status
Simulation time 264860116 ps
CPU time 3.64 seconds
Started Jul 16 08:02:16 PM PDT 24
Finished Jul 16 08:02:25 PM PDT 24
Peak memory 224472 kb
Host smart-db6cdda8-886b-49f4-8a1c-5cce633d0543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128837069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1128837069
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.1032701920
Short name T50
Test name
Test status
Simulation time 2676619029 ps
CPU time 30.99 seconds
Started Jul 16 08:02:14 PM PDT 24
Finished Jul 16 08:02:47 PM PDT 24
Peak memory 249188 kb
Host smart-f05e45f9-8ff2-45b5-86f4-0badde9d29e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032701920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.1032701920
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3686196270
Short name T395
Test name
Test status
Simulation time 397163950 ps
CPU time 3.74 seconds
Started Jul 16 08:02:16 PM PDT 24
Finished Jul 16 08:02:25 PM PDT 24
Peak memory 232660 kb
Host smart-bad6ab04-a0a4-4801-b487-aa31f5364131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686196270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3686196270
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.4196752134
Short name T385
Test name
Test status
Simulation time 9405282304 ps
CPU time 82.82 seconds
Started Jul 16 08:02:17 PM PDT 24
Finished Jul 16 08:03:46 PM PDT 24
Peak memory 232772 kb
Host smart-6aa9d08d-6e13-4932-ac4f-8ab9bc4f31a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196752134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.4196752134
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3965378302
Short name T239
Test name
Test status
Simulation time 2446104012 ps
CPU time 7.55 seconds
Started Jul 16 08:02:20 PM PDT 24
Finished Jul 16 08:02:34 PM PDT 24
Peak memory 232816 kb
Host smart-26563548-de5e-4cbb-a2cf-df299bf84cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965378302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3965378302
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.59683338
Short name T851
Test name
Test status
Simulation time 108013085 ps
CPU time 2.22 seconds
Started Jul 16 08:02:15 PM PDT 24
Finished Jul 16 08:02:21 PM PDT 24
Peak memory 223692 kb
Host smart-378aed26-091c-4bdf-982d-667983c53883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59683338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.59683338
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.713452541
Short name T445
Test name
Test status
Simulation time 272206904 ps
CPU time 3.57 seconds
Started Jul 16 08:02:00 PM PDT 24
Finished Jul 16 08:02:05 PM PDT 24
Peak memory 222804 kb
Host smart-6c243db9-f158-40b4-aeb7-7f5988e49cf2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=713452541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.713452541
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3407528487
Short name T392
Test name
Test status
Simulation time 107014329648 ps
CPU time 238.75 seconds
Started Jul 16 08:02:18 PM PDT 24
Finished Jul 16 08:06:23 PM PDT 24
Peak memory 264548 kb
Host smart-21e8d3e5-de43-484e-a596-e40a3920bddb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407528487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3407528487
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2429770574
Short name T418
Test name
Test status
Simulation time 15028618034 ps
CPU time 17.91 seconds
Started Jul 16 08:02:16 PM PDT 24
Finished Jul 16 08:02:39 PM PDT 24
Peak memory 220644 kb
Host smart-4b18b0bc-8489-401b-81e2-b00c98a9e41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429770574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2429770574
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3542413210
Short name T752
Test name
Test status
Simulation time 3053234027 ps
CPU time 11 seconds
Started Jul 16 08:02:00 PM PDT 24
Finished Jul 16 08:02:12 PM PDT 24
Peak memory 216356 kb
Host smart-8a54dc07-f4e1-4162-8c3a-67d1a23cbeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542413210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3542413210
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2015426093
Short name T510
Test name
Test status
Simulation time 87743510 ps
CPU time 1.42 seconds
Started Jul 16 08:02:05 PM PDT 24
Finished Jul 16 08:02:07 PM PDT 24
Peak memory 216204 kb
Host smart-cfde3d85-b5ae-4eca-91f6-7fdba2f35bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015426093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2015426093
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.284800450
Short name T469
Test name
Test status
Simulation time 177214237 ps
CPU time 0.78 seconds
Started Jul 16 08:02:14 PM PDT 24
Finished Jul 16 08:02:17 PM PDT 24
Peak memory 206008 kb
Host smart-03f6cca6-bf2c-46f4-92fd-bf05d5137a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284800450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.284800450
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1338288248
Short name T587
Test name
Test status
Simulation time 324865621 ps
CPU time 3.16 seconds
Started Jul 16 08:02:16 PM PDT 24
Finished Jul 16 08:02:24 PM PDT 24
Peak memory 232680 kb
Host smart-fcba0a84-df36-4deb-b1ae-8ff51554862b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338288248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1338288248
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2470955674
Short name T314
Test name
Test status
Simulation time 34897603 ps
CPU time 0.71 seconds
Started Jul 16 08:02:17 PM PDT 24
Finished Jul 16 08:02:24 PM PDT 24
Peak memory 205528 kb
Host smart-c25e71a0-801e-4259-8e50-8e662a5dc092
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470955674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2470955674
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.917641602
Short name T77
Test name
Test status
Simulation time 1630347074 ps
CPU time 6.44 seconds
Started Jul 16 08:02:16 PM PDT 24
Finished Jul 16 08:02:27 PM PDT 24
Peak memory 224452 kb
Host smart-12aaa04f-389d-43c5-ad68-df7344a61d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917641602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.917641602
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1488734473
Short name T58
Test name
Test status
Simulation time 23066055 ps
CPU time 0.8 seconds
Started Jul 16 08:01:58 PM PDT 24
Finished Jul 16 08:01:59 PM PDT 24
Peak memory 206640 kb
Host smart-61057e05-ad0d-4c4d-bf31-37cf32c5dc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488734473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1488734473
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1070166071
Short name T236
Test name
Test status
Simulation time 3128714472 ps
CPU time 29.26 seconds
Started Jul 16 08:02:07 PM PDT 24
Finished Jul 16 08:02:37 PM PDT 24
Peak memory 232832 kb
Host smart-5f8d0ea9-112c-482c-80dd-af1a846aecb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070166071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1070166071
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.752799873
Short name T368
Test name
Test status
Simulation time 45347080042 ps
CPU time 62.78 seconds
Started Jul 16 08:02:18 PM PDT 24
Finished Jul 16 08:03:28 PM PDT 24
Peak memory 249348 kb
Host smart-db6e7dd9-f713-41fe-87be-346cfbcc81f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752799873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.752799873
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1181747095
Short name T855
Test name
Test status
Simulation time 11074912960 ps
CPU time 65.54 seconds
Started Jul 16 08:02:17 PM PDT 24
Finished Jul 16 08:03:29 PM PDT 24
Peak memory 255528 kb
Host smart-6bbb05fd-2a8d-4bf4-9452-a324b17886de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181747095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1181747095
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.376687452
Short name T345
Test name
Test status
Simulation time 1962582435 ps
CPU time 10.74 seconds
Started Jul 16 08:02:09 PM PDT 24
Finished Jul 16 08:02:20 PM PDT 24
Peak memory 234248 kb
Host smart-f23301d8-9268-4609-90ae-f4f595a9965f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376687452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.376687452
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.863266557
Short name T742
Test name
Test status
Simulation time 265532048 ps
CPU time 3.94 seconds
Started Jul 16 08:02:16 PM PDT 24
Finished Jul 16 08:02:25 PM PDT 24
Peak memory 224520 kb
Host smart-e2bd1bd1-e606-4be9-a884-74cc21a265e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863266557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.863266557
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2915322930
Short name T620
Test name
Test status
Simulation time 6462326595 ps
CPU time 67.51 seconds
Started Jul 16 08:02:17 PM PDT 24
Finished Jul 16 08:03:31 PM PDT 24
Peak memory 240520 kb
Host smart-492b06fb-1975-4800-95eb-b0186fc3ba29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915322930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2915322930
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1812397934
Short name T812
Test name
Test status
Simulation time 4810188189 ps
CPU time 13.39 seconds
Started Jul 16 08:02:18 PM PDT 24
Finished Jul 16 08:02:38 PM PDT 24
Peak memory 232784 kb
Host smart-07ed8825-1c44-4767-88e3-31858c4f5c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812397934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1812397934
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2043677338
Short name T550
Test name
Test status
Simulation time 2397930862 ps
CPU time 4.31 seconds
Started Jul 16 08:02:17 PM PDT 24
Finished Jul 16 08:02:27 PM PDT 24
Peak memory 232752 kb
Host smart-eb326243-09ff-45ee-94e1-273522d136cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043677338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2043677338
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.624812543
Short name T431
Test name
Test status
Simulation time 1175705393 ps
CPU time 13.4 seconds
Started Jul 16 08:02:16 PM PDT 24
Finished Jul 16 08:02:35 PM PDT 24
Peak memory 219392 kb
Host smart-d4420dc1-59ed-4036-a47a-b9f74ad3f870
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=624812543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.624812543
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2506864393
Short name T132
Test name
Test status
Simulation time 231895871 ps
CPU time 1.04 seconds
Started Jul 16 08:02:15 PM PDT 24
Finished Jul 16 08:02:20 PM PDT 24
Peak memory 216008 kb
Host smart-8693b583-3c69-4fac-a981-d6862cf1c8ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506864393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2506864393
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.635433609
Short name T832
Test name
Test status
Simulation time 8458083742 ps
CPU time 42.71 seconds
Started Jul 16 08:02:08 PM PDT 24
Finished Jul 16 08:02:52 PM PDT 24
Peak memory 216392 kb
Host smart-5e19f948-a3dd-4c1c-880a-8a69d0d3de09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635433609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.635433609
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2121522230
Short name T373
Test name
Test status
Simulation time 1330714083 ps
CPU time 4.23 seconds
Started Jul 16 08:02:18 PM PDT 24
Finished Jul 16 08:02:29 PM PDT 24
Peak memory 216240 kb
Host smart-0c3f2b22-6704-422f-9d8e-b2296a9f9ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121522230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2121522230
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1833916270
Short name T288
Test name
Test status
Simulation time 12528865 ps
CPU time 0.74 seconds
Started Jul 16 08:02:17 PM PDT 24
Finished Jul 16 08:02:24 PM PDT 24
Peak memory 205572 kb
Host smart-35356267-6a9f-4559-8a19-93173466c586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833916270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1833916270
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3914529911
Short name T346
Test name
Test status
Simulation time 567384413 ps
CPU time 0.93 seconds
Started Jul 16 08:02:17 PM PDT 24
Finished Jul 16 08:02:23 PM PDT 24
Peak memory 206308 kb
Host smart-1afe24cd-b4ce-4958-85bb-bf1e6086f967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914529911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3914529911
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2846360817
Short name T467
Test name
Test status
Simulation time 2168890731 ps
CPU time 8.25 seconds
Started Jul 16 08:01:58 PM PDT 24
Finished Jul 16 08:02:07 PM PDT 24
Peak memory 232684 kb
Host smart-19c7f08c-b5d1-40ec-a357-648be5693beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846360817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2846360817
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3244427335
Short name T896
Test name
Test status
Simulation time 13904447 ps
CPU time 0.7 seconds
Started Jul 16 08:02:12 PM PDT 24
Finished Jul 16 08:02:14 PM PDT 24
Peak memory 205636 kb
Host smart-acf2ec1e-db8e-4d73-8282-0ff932b047a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244427335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3244427335
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3500603628
Short name T455
Test name
Test status
Simulation time 175338473 ps
CPU time 2.36 seconds
Started Jul 16 08:02:12 PM PDT 24
Finished Jul 16 08:02:15 PM PDT 24
Peak memory 224588 kb
Host smart-69f2df73-f44b-4ec1-aad4-c7686a46b790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500603628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3500603628
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1414912365
Short name T289
Test name
Test status
Simulation time 13118502 ps
CPU time 0.74 seconds
Started Jul 16 08:02:16 PM PDT 24
Finished Jul 16 08:02:22 PM PDT 24
Peak memory 205896 kb
Host smart-b26dc223-2a12-437a-8254-51522e925976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414912365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1414912365
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1866325414
Short name T583
Test name
Test status
Simulation time 30586237239 ps
CPU time 213.03 seconds
Started Jul 16 08:02:13 PM PDT 24
Finished Jul 16 08:05:48 PM PDT 24
Peak memory 251648 kb
Host smart-be55673c-dcd3-4c99-8910-c86d5372879b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866325414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1866325414
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3448747478
Short name T944
Test name
Test status
Simulation time 16062625319 ps
CPU time 119.88 seconds
Started Jul 16 08:02:19 PM PDT 24
Finished Jul 16 08:04:26 PM PDT 24
Peak memory 254196 kb
Host smart-e9f97b93-5b40-4eac-ba96-bf6a3025bbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448747478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3448747478
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.957666225
Short name T170
Test name
Test status
Simulation time 327097494885 ps
CPU time 440.38 seconds
Started Jul 16 08:02:19 PM PDT 24
Finished Jul 16 08:09:46 PM PDT 24
Peak memory 264880 kb
Host smart-fb9847ae-f4ca-4880-87bd-52ab61a26a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957666225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.957666225
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1726843378
Short name T763
Test name
Test status
Simulation time 9777438514 ps
CPU time 35.8 seconds
Started Jul 16 08:02:15 PM PDT 24
Finished Jul 16 08:02:55 PM PDT 24
Peak memory 232844 kb
Host smart-08d2ba5e-0d3c-4c0b-8fc5-3cfe0a5fcfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726843378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1726843378
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.529380177
Short name T184
Test name
Test status
Simulation time 3427922528 ps
CPU time 18.7 seconds
Started Jul 16 08:02:16 PM PDT 24
Finished Jul 16 08:02:40 PM PDT 24
Peak memory 241000 kb
Host smart-231df27f-9fbe-43fb-b09c-dae04fe6e301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529380177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds
.529380177
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3924156302
Short name T493
Test name
Test status
Simulation time 1423838677 ps
CPU time 6.37 seconds
Started Jul 16 08:02:11 PM PDT 24
Finished Jul 16 08:02:18 PM PDT 24
Peak memory 224436 kb
Host smart-490b47e2-eac9-4a26-a764-2e0bb61ac86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924156302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3924156302
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2893398453
Short name T727
Test name
Test status
Simulation time 2663299295 ps
CPU time 22.76 seconds
Started Jul 16 08:02:17 PM PDT 24
Finished Jul 16 08:02:46 PM PDT 24
Peak memory 237456 kb
Host smart-854eeaa0-7534-49d6-9599-0217a38a9e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893398453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2893398453
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3013220131
Short name T701
Test name
Test status
Simulation time 6678001163 ps
CPU time 7.57 seconds
Started Jul 16 08:02:13 PM PDT 24
Finished Jul 16 08:02:22 PM PDT 24
Peak memory 224652 kb
Host smart-351809d6-39bb-4e77-85c1-e75609b49017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013220131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3013220131
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3416113892
Short name T384
Test name
Test status
Simulation time 6717626708 ps
CPU time 13.82 seconds
Started Jul 16 08:01:31 PM PDT 24
Finished Jul 16 08:01:45 PM PDT 24
Peak memory 224616 kb
Host smart-44e5c17d-6656-47da-86c2-75407a45d525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416113892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3416113892
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.697415953
Short name T712
Test name
Test status
Simulation time 231219683 ps
CPU time 5.91 seconds
Started Jul 16 08:02:13 PM PDT 24
Finished Jul 16 08:02:20 PM PDT 24
Peak memory 220016 kb
Host smart-0bcd8956-57bf-457f-b8b1-8fb3668aac24
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=697415953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.697415953
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3596239298
Short name T135
Test name
Test status
Simulation time 48653343523 ps
CPU time 451.94 seconds
Started Jul 16 08:02:18 PM PDT 24
Finished Jul 16 08:09:56 PM PDT 24
Peak memory 273840 kb
Host smart-77707859-c962-4e09-a57d-3751127d777f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596239298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3596239298
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2658733173
Short name T647
Test name
Test status
Simulation time 864443636 ps
CPU time 11.96 seconds
Started Jul 16 08:02:17 PM PDT 24
Finished Jul 16 08:02:35 PM PDT 24
Peak memory 216624 kb
Host smart-8c2116cb-aa2c-4063-aee4-356b28c5f279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658733173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2658733173
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.11277436
Short name T814
Test name
Test status
Simulation time 1297228481 ps
CPU time 6.75 seconds
Started Jul 16 08:02:06 PM PDT 24
Finished Jul 16 08:02:14 PM PDT 24
Peak memory 216260 kb
Host smart-df01929b-4cc3-4fab-833f-2660254481c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11277436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.11277436
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2290615453
Short name T718
Test name
Test status
Simulation time 16235662 ps
CPU time 0.77 seconds
Started Jul 16 08:02:18 PM PDT 24
Finished Jul 16 08:02:25 PM PDT 24
Peak memory 206052 kb
Host smart-3188163c-c595-4ad6-8e5a-3dc236ec537e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290615453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2290615453
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3717331047
Short name T681
Test name
Test status
Simulation time 88493870 ps
CPU time 0.75 seconds
Started Jul 16 08:02:15 PM PDT 24
Finished Jul 16 08:02:20 PM PDT 24
Peak memory 206060 kb
Host smart-1decec27-e8ec-43c0-88b8-bc65084bdb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717331047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3717331047
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3924388025
Short name T20
Test name
Test status
Simulation time 894348247 ps
CPU time 10.21 seconds
Started Jul 16 08:02:12 PM PDT 24
Finished Jul 16 08:02:23 PM PDT 24
Peak memory 232704 kb
Host smart-d1158ead-3131-47e0-916e-74c095c4f721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924388025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3924388025
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3377388830
Short name T450
Test name
Test status
Simulation time 11176107 ps
CPU time 0.74 seconds
Started Jul 16 08:02:20 PM PDT 24
Finished Jul 16 08:02:27 PM PDT 24
Peak memory 205896 kb
Host smart-3639177f-fa3a-43f3-831f-4127894b4780
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377388830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3377388830
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1409912091
Short name T225
Test name
Test status
Simulation time 1900867621 ps
CPU time 8.11 seconds
Started Jul 16 08:02:17 PM PDT 24
Finished Jul 16 08:02:31 PM PDT 24
Peak memory 232624 kb
Host smart-b273ecdb-3ccc-43e8-b8bf-baeb9c0ff2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409912091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1409912091
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1551563986
Short name T316
Test name
Test status
Simulation time 23711176 ps
CPU time 0.82 seconds
Started Jul 16 08:02:11 PM PDT 24
Finished Jul 16 08:02:13 PM PDT 24
Peak memory 206916 kb
Host smart-c7f657f9-8604-4da7-8c3b-5cd7c78ee800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551563986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1551563986
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1937627627
Short name T179
Test name
Test status
Simulation time 18023586310 ps
CPU time 80.43 seconds
Started Jul 16 08:02:08 PM PDT 24
Finished Jul 16 08:03:29 PM PDT 24
Peak memory 250312 kb
Host smart-74863d90-8c66-4000-8e8b-e303f20425e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937627627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1937627627
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.305789659
Short name T570
Test name
Test status
Simulation time 139327881193 ps
CPU time 305.86 seconds
Started Jul 16 08:02:26 PM PDT 24
Finished Jul 16 08:07:37 PM PDT 24
Peak memory 250316 kb
Host smart-62086e3d-533e-44e9-9104-41ea193470d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305789659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.305789659
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3192085261
Short name T399
Test name
Test status
Simulation time 7938419642 ps
CPU time 76.19 seconds
Started Jul 16 08:02:32 PM PDT 24
Finished Jul 16 08:04:00 PM PDT 24
Peak memory 240888 kb
Host smart-00832337-5d3b-4c96-b278-f07ed175fe5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192085261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3192085261
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1878333753
Short name T261
Test name
Test status
Simulation time 9111801641 ps
CPU time 31.89 seconds
Started Jul 16 08:02:13 PM PDT 24
Finished Jul 16 08:02:47 PM PDT 24
Peak memory 233872 kb
Host smart-8828ca9d-6304-4fd8-872c-7c82492247d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878333753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1878333753
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.4139903792
Short name T768
Test name
Test status
Simulation time 14591537743 ps
CPU time 58.59 seconds
Started Jul 16 08:02:12 PM PDT 24
Finished Jul 16 08:03:11 PM PDT 24
Peak memory 249284 kb
Host smart-e1e02a7c-72de-4a5b-8837-0dd867da3333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139903792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.4139903792
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2632046166
Short name T976
Test name
Test status
Simulation time 3806695680 ps
CPU time 20.31 seconds
Started Jul 16 08:02:14 PM PDT 24
Finished Jul 16 08:02:36 PM PDT 24
Peak memory 232748 kb
Host smart-c7d73f7c-6ad0-4841-b87d-7f0a0be4738b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632046166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2632046166
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1812582077
Short name T458
Test name
Test status
Simulation time 408465776 ps
CPU time 6.19 seconds
Started Jul 16 08:02:16 PM PDT 24
Finished Jul 16 08:02:27 PM PDT 24
Peak memory 224580 kb
Host smart-9e06dc1a-2849-4e0d-bb19-4dc056fa929e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812582077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1812582077
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.967203853
Short name T725
Test name
Test status
Simulation time 314087102 ps
CPU time 2.31 seconds
Started Jul 16 08:02:12 PM PDT 24
Finished Jul 16 08:02:15 PM PDT 24
Peak memory 232372 kb
Host smart-16edd591-bb0e-4189-b2c3-3a43432967a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967203853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.967203853
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2270810871
Short name T637
Test name
Test status
Simulation time 1875048919 ps
CPU time 8.03 seconds
Started Jul 16 08:02:17 PM PDT 24
Finished Jul 16 08:02:31 PM PDT 24
Peak memory 240332 kb
Host smart-56b0985d-74d0-4c60-8688-524210f18a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270810871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2270810871
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.562777367
Short name T781
Test name
Test status
Simulation time 18924048005 ps
CPU time 18 seconds
Started Jul 16 08:02:13 PM PDT 24
Finished Jul 16 08:02:33 PM PDT 24
Peak memory 221656 kb
Host smart-c3b53c48-0a2d-4850-b0ba-987260fc3634
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=562777367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.562777367
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.440804671
Short name T134
Test name
Test status
Simulation time 177144443 ps
CPU time 1.05 seconds
Started Jul 16 08:02:28 PM PDT 24
Finished Jul 16 08:02:37 PM PDT 24
Peak memory 207756 kb
Host smart-49bee916-acdb-43e0-8672-550e0f8f7cf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440804671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.440804671
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1349844320
Short name T280
Test name
Test status
Simulation time 2362362207 ps
CPU time 29.81 seconds
Started Jul 16 08:02:17 PM PDT 24
Finished Jul 16 08:02:53 PM PDT 24
Peak memory 219568 kb
Host smart-4e8fee9f-009c-47e9-8fa6-b401e63ed25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349844320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1349844320
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.4239100333
Short name T439
Test name
Test status
Simulation time 1242902351 ps
CPU time 6.84 seconds
Started Jul 16 08:02:12 PM PDT 24
Finished Jul 16 08:02:20 PM PDT 24
Peak memory 216168 kb
Host smart-1eda1e23-d72b-47a0-a525-d06c13002b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239100333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.4239100333
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1246216992
Short name T475
Test name
Test status
Simulation time 202606492 ps
CPU time 3.66 seconds
Started Jul 16 08:02:12 PM PDT 24
Finished Jul 16 08:02:17 PM PDT 24
Peak memory 216244 kb
Host smart-89267ddb-f14a-466f-b045-98cc49e36dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246216992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1246216992
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.543699852
Short name T670
Test name
Test status
Simulation time 43193382 ps
CPU time 0.76 seconds
Started Jul 16 08:02:16 PM PDT 24
Finished Jul 16 08:02:22 PM PDT 24
Peak memory 206072 kb
Host smart-b3500da7-c4a1-4ee5-b012-87ebf52ec2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543699852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.543699852
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.942024967
Short name T544
Test name
Test status
Simulation time 4788957091 ps
CPU time 19.36 seconds
Started Jul 16 08:02:14 PM PDT 24
Finished Jul 16 08:02:35 PM PDT 24
Peak memory 232772 kb
Host smart-cd479242-3d7c-4b83-9f1e-03bd68402948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942024967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.942024967
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2152440624
Short name T365
Test name
Test status
Simulation time 15206534 ps
CPU time 0.72 seconds
Started Jul 16 08:02:19 PM PDT 24
Finished Jul 16 08:02:26 PM PDT 24
Peak memory 205868 kb
Host smart-6ef64454-0932-41fb-afb2-f3d99d69c1f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152440624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2152440624
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.629994538
Short name T562
Test name
Test status
Simulation time 677929373 ps
CPU time 6.98 seconds
Started Jul 16 08:02:28 PM PDT 24
Finished Jul 16 08:02:42 PM PDT 24
Peak memory 232376 kb
Host smart-fe4e2bae-6391-4769-9ba5-dc22b07d81d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629994538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.629994538
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1046020121
Short name T747
Test name
Test status
Simulation time 13789606 ps
CPU time 0.73 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:02:38 PM PDT 24
Peak memory 205608 kb
Host smart-8315b618-bfdc-4a48-a7fa-cb509cc73837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046020121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1046020121
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.4169088915
Short name T328
Test name
Test status
Simulation time 6974692399 ps
CPU time 37.17 seconds
Started Jul 16 08:02:19 PM PDT 24
Finished Jul 16 08:03:02 PM PDT 24
Peak memory 255332 kb
Host smart-30585019-fa2e-4c72-bc1b-f6e20f0b4596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169088915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.4169088915
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.387279329
Short name T217
Test name
Test status
Simulation time 1760506116 ps
CPU time 35.93 seconds
Started Jul 16 08:02:30 PM PDT 24
Finished Jul 16 08:03:15 PM PDT 24
Peak memory 249040 kb
Host smart-fc6e571e-d987-4183-a11b-0fa6a0cbd3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387279329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.387279329
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.4257905230
Short name T736
Test name
Test status
Simulation time 158670828542 ps
CPU time 366.62 seconds
Started Jul 16 08:02:28 PM PDT 24
Finished Jul 16 08:08:41 PM PDT 24
Peak memory 264244 kb
Host smart-ba9145ae-896b-4798-bcc3-bbf4ed1da8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257905230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.4257905230
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3362388984
Short name T923
Test name
Test status
Simulation time 1749818429 ps
CPU time 12.28 seconds
Started Jul 16 08:02:28 PM PDT 24
Finished Jul 16 08:02:48 PM PDT 24
Peak memory 232708 kb
Host smart-f5be06e6-61bf-4da1-8db6-fd0953867b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362388984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3362388984
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.1329974695
Short name T46
Test name
Test status
Simulation time 24944369982 ps
CPU time 109.92 seconds
Started Jul 16 08:02:24 PM PDT 24
Finished Jul 16 08:04:18 PM PDT 24
Peak memory 256972 kb
Host smart-d3ff7428-2687-4d3d-b9fe-7e9c54e5c005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329974695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.1329974695
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.4248183212
Short name T845
Test name
Test status
Simulation time 2638566518 ps
CPU time 24.19 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:03:02 PM PDT 24
Peak memory 224544 kb
Host smart-189faab8-94b9-4340-ba0c-d7e08822cf7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248183212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.4248183212
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1511413660
Short name T953
Test name
Test status
Simulation time 1233774681 ps
CPU time 10.8 seconds
Started Jul 16 08:02:33 PM PDT 24
Finished Jul 16 08:02:56 PM PDT 24
Peak memory 238988 kb
Host smart-95f24117-7bec-41b1-a841-e5ed932cc986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511413660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1511413660
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1985261132
Short name T753
Test name
Test status
Simulation time 1702871811 ps
CPU time 5.78 seconds
Started Jul 16 08:02:20 PM PDT 24
Finished Jul 16 08:02:32 PM PDT 24
Peak memory 232692 kb
Host smart-5f331c62-c58d-4649-8a9f-58d4f4608017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985261132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1985261132
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2150682051
Short name T862
Test name
Test status
Simulation time 728715696 ps
CPU time 2.97 seconds
Started Jul 16 08:02:27 PM PDT 24
Finished Jul 16 08:02:36 PM PDT 24
Peak memory 232624 kb
Host smart-d36474bc-bb0f-495c-9f9a-6fd671dc0b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150682051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2150682051
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1631356866
Short name T126
Test name
Test status
Simulation time 1857345103 ps
CPU time 3.67 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:02:42 PM PDT 24
Peak memory 220504 kb
Host smart-64a1e2d8-6da4-44ae-ad2e-c2c5e882d7a3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1631356866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1631356866
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2631652848
Short name T824
Test name
Test status
Simulation time 16255930405 ps
CPU time 22.87 seconds
Started Jul 16 08:02:33 PM PDT 24
Finished Jul 16 08:03:07 PM PDT 24
Peak memory 219944 kb
Host smart-00641a0b-7b09-4bcc-84a4-ee6024a0431d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631652848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2631652848
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.456979554
Short name T649
Test name
Test status
Simulation time 39763197732 ps
CPU time 6.68 seconds
Started Jul 16 08:02:24 PM PDT 24
Finished Jul 16 08:02:35 PM PDT 24
Peak memory 217320 kb
Host smart-eef878fe-509f-441e-9e3b-9216d9a7c804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456979554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.456979554
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.30880135
Short name T394
Test name
Test status
Simulation time 24518728 ps
CPU time 0.86 seconds
Started Jul 16 08:02:33 PM PDT 24
Finished Jul 16 08:02:46 PM PDT 24
Peak memory 206568 kb
Host smart-403bb007-f95e-44a3-8c5e-1ab87069cc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30880135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.30880135
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1180215824
Short name T806
Test name
Test status
Simulation time 205659019 ps
CPU time 0.84 seconds
Started Jul 16 08:02:24 PM PDT 24
Finished Jul 16 08:02:29 PM PDT 24
Peak memory 205972 kb
Host smart-48639f6a-c8b4-43eb-a4e8-86ea67e9f59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180215824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1180215824
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3186815198
Short name T830
Test name
Test status
Simulation time 1057155206 ps
CPU time 8.56 seconds
Started Jul 16 08:02:32 PM PDT 24
Finished Jul 16 08:02:51 PM PDT 24
Peak memory 224520 kb
Host smart-c7b6d339-b609-4d52-ac05-7f4f7f3a8122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186815198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3186815198
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1297885656
Short name T526
Test name
Test status
Simulation time 15536196 ps
CPU time 0.75 seconds
Started Jul 16 08:02:28 PM PDT 24
Finished Jul 16 08:02:35 PM PDT 24
Peak memory 205560 kb
Host smart-f50ce23e-3dc5-404a-85bd-7c08db0e6247
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297885656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1297885656
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3713528201
Short name T907
Test name
Test status
Simulation time 494326473 ps
CPU time 5.13 seconds
Started Jul 16 08:02:24 PM PDT 24
Finished Jul 16 08:02:33 PM PDT 24
Peak memory 232640 kb
Host smart-10080ae6-efe7-491b-a0ba-cb16323c2d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713528201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3713528201
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1720340041
Short name T1002
Test name
Test status
Simulation time 24286630 ps
CPU time 0.74 seconds
Started Jul 16 08:02:24 PM PDT 24
Finished Jul 16 08:02:29 PM PDT 24
Peak memory 206908 kb
Host smart-b8620f38-010f-4f8f-910e-6ed852712208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720340041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1720340041
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3923801347
Short name T797
Test name
Test status
Simulation time 9895546022 ps
CPU time 47.91 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:03:25 PM PDT 24
Peak memory 252964 kb
Host smart-0a7dfc61-491b-441f-aa8a-2edf82bc0876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923801347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3923801347
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1321003007
Short name T878
Test name
Test status
Simulation time 208349754561 ps
CPU time 144.14 seconds
Started Jul 16 08:02:21 PM PDT 24
Finished Jul 16 08:04:51 PM PDT 24
Peak memory 256800 kb
Host smart-9ed14d80-0055-4686-928a-add0dd5c6366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321003007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1321003007
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3100931048
Short name T256
Test name
Test status
Simulation time 8219750606 ps
CPU time 127.04 seconds
Started Jul 16 08:02:28 PM PDT 24
Finished Jul 16 08:04:42 PM PDT 24
Peak memory 255456 kb
Host smart-aaece49e-58f5-46d2-8191-f0e9474bd07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100931048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3100931048
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.598632023
Short name T936
Test name
Test status
Simulation time 8990331713 ps
CPU time 32.22 seconds
Started Jul 16 08:02:24 PM PDT 24
Finished Jul 16 08:03:01 PM PDT 24
Peak memory 240996 kb
Host smart-1b1327e6-0914-45be-8ee1-3c54667f5688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598632023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.598632023
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.3977117709
Short name T182
Test name
Test status
Simulation time 16165232224 ps
CPU time 115.33 seconds
Started Jul 16 08:02:28 PM PDT 24
Finished Jul 16 08:04:30 PM PDT 24
Peak memory 238384 kb
Host smart-7c25b7cb-2588-4530-8b9b-4507b16f2522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977117709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.3977117709
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.11199981
Short name T117
Test name
Test status
Simulation time 121788244 ps
CPU time 2.43 seconds
Started Jul 16 08:02:23 PM PDT 24
Finished Jul 16 08:02:30 PM PDT 24
Peak memory 232324 kb
Host smart-695713b0-9d33-41f9-ab59-6bad9c514a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11199981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.11199981
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.970169337
Short name T13
Test name
Test status
Simulation time 8067351117 ps
CPU time 22.05 seconds
Started Jul 16 08:02:18 PM PDT 24
Finished Jul 16 08:02:47 PM PDT 24
Peak memory 233356 kb
Host smart-6dbdf494-0d1d-483b-998e-039b2b152924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970169337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.970169337
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2549182569
Short name T709
Test name
Test status
Simulation time 95562428 ps
CPU time 2.3 seconds
Started Jul 16 08:02:31 PM PDT 24
Finished Jul 16 08:02:43 PM PDT 24
Peak memory 223712 kb
Host smart-2d8a4e2e-a572-46e7-908d-359faa2c0c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549182569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2549182569
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.506675560
Short name T889
Test name
Test status
Simulation time 8652786020 ps
CPU time 9.42 seconds
Started Jul 16 08:02:24 PM PDT 24
Finished Jul 16 08:02:38 PM PDT 24
Peak memory 232584 kb
Host smart-0cee677b-acb5-4504-a1f6-79403ef42660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506675560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.506675560
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1508406541
Short name T820
Test name
Test status
Simulation time 408720915 ps
CPU time 4.36 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:02:42 PM PDT 24
Peak memory 222796 kb
Host smart-15e855a2-1fcb-4a08-a51b-b0f413fced27
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1508406541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1508406541
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2740147109
Short name T684
Test name
Test status
Simulation time 92454390576 ps
CPU time 237.77 seconds
Started Jul 16 08:02:25 PM PDT 24
Finished Jul 16 08:06:28 PM PDT 24
Peak memory 250308 kb
Host smart-a55ecab6-7b8e-460e-bb34-68d1d0a5b836
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740147109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2740147109
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.106583951
Short name T538
Test name
Test status
Simulation time 4309902913 ps
CPU time 6.28 seconds
Started Jul 16 08:02:25 PM PDT 24
Finished Jul 16 08:02:35 PM PDT 24
Peak memory 219772 kb
Host smart-d5cbabd4-583b-44c0-8f58-b48b7542c343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106583951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.106583951
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.199423992
Short name T761
Test name
Test status
Simulation time 34451481 ps
CPU time 0.69 seconds
Started Jul 16 08:02:27 PM PDT 24
Finished Jul 16 08:02:33 PM PDT 24
Peak memory 205644 kb
Host smart-a5d1c376-fb3b-4548-b51a-21a8256df577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199423992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.199423992
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1348985250
Short name T605
Test name
Test status
Simulation time 31778470 ps
CPU time 1 seconds
Started Jul 16 08:02:33 PM PDT 24
Finished Jul 16 08:02:46 PM PDT 24
Peak memory 207060 kb
Host smart-210d5e7a-a078-4ec6-b503-bdcb724cfb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348985250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1348985250
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.701006279
Short name T448
Test name
Test status
Simulation time 382535546 ps
CPU time 0.77 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:02:40 PM PDT 24
Peak memory 205984 kb
Host smart-e8ec15d8-c249-4689-983f-565aa9cc57b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701006279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.701006279
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3897614192
Short name T676
Test name
Test status
Simulation time 4728759938 ps
CPU time 18.29 seconds
Started Jul 16 08:02:31 PM PDT 24
Finished Jul 16 08:03:00 PM PDT 24
Peak memory 249200 kb
Host smart-1fc03a18-fd4b-493e-822f-a114011069e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897614192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3897614192
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1382521199
Short name T513
Test name
Test status
Simulation time 22612155 ps
CPU time 0.71 seconds
Started Jul 16 08:02:28 PM PDT 24
Finished Jul 16 08:02:35 PM PDT 24
Peak memory 205484 kb
Host smart-245d16e6-ab15-4d2c-ae8f-1932b3977814
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382521199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1382521199
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1480101073
Short name T912
Test name
Test status
Simulation time 23661075269 ps
CPU time 23.06 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:03:01 PM PDT 24
Peak memory 232756 kb
Host smart-e7e96ef4-6b55-4d9e-a780-809bcaf3cc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480101073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1480101073
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1595613163
Short name T326
Test name
Test status
Simulation time 17442760 ps
CPU time 0.83 seconds
Started Jul 16 08:02:28 PM PDT 24
Finished Jul 16 08:02:37 PM PDT 24
Peak memory 206140 kb
Host smart-49780181-a6b2-4aed-b824-5d34d1c4a1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595613163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1595613163
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2235337361
Short name T764
Test name
Test status
Simulation time 9155691822 ps
CPU time 121.97 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:04:39 PM PDT 24
Peak memory 251288 kb
Host smart-1b0bb9a2-b6ac-43f4-9b17-fe03df54c76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235337361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2235337361
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1939335873
Short name T248
Test name
Test status
Simulation time 102724194858 ps
CPU time 609.47 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:12:49 PM PDT 24
Peak memory 264824 kb
Host smart-c88a5115-f17c-406a-8ef2-3c3f2c44cace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939335873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1939335873
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3321769272
Short name T48
Test name
Test status
Simulation time 13273889606 ps
CPU time 105.34 seconds
Started Jul 16 08:02:28 PM PDT 24
Finished Jul 16 08:04:21 PM PDT 24
Peak memory 254720 kb
Host smart-7794a286-a560-4606-af99-1ac6c6ddf744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321769272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3321769272
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.251810394
Short name T683
Test name
Test status
Simulation time 490487251 ps
CPU time 8.38 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:02:46 PM PDT 24
Peak memory 240868 kb
Host smart-050b9cd3-44b5-4d0e-bab3-89f840d75e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251810394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.251810394
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.377195550
Short name T980
Test name
Test status
Simulation time 1127106618 ps
CPU time 19.12 seconds
Started Jul 16 08:02:28 PM PDT 24
Finished Jul 16 08:02:54 PM PDT 24
Peak memory 249084 kb
Host smart-84a7b645-4880-412a-bce9-d9f7a0d05c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377195550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds
.377195550
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3662183030
Short name T592
Test name
Test status
Simulation time 3614614471 ps
CPU time 29 seconds
Started Jul 16 08:02:28 PM PDT 24
Finished Jul 16 08:03:05 PM PDT 24
Peak memory 224508 kb
Host smart-209d2652-789e-4e24-ac7d-9827a8e4c96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662183030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3662183030
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1703475410
Short name T497
Test name
Test status
Simulation time 5851392807 ps
CPU time 15.94 seconds
Started Jul 16 08:02:25 PM PDT 24
Finished Jul 16 08:02:45 PM PDT 24
Peak memory 249248 kb
Host smart-ec2feb38-314e-4375-befb-18315175068f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703475410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1703475410
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1519674516
Short name T915
Test name
Test status
Simulation time 25393999603 ps
CPU time 9.16 seconds
Started Jul 16 08:02:26 PM PDT 24
Finished Jul 16 08:02:39 PM PDT 24
Peak memory 232784 kb
Host smart-1afcc9a8-4700-4861-8dca-5c2082aa661f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519674516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1519674516
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2557045442
Short name T209
Test name
Test status
Simulation time 9708553343 ps
CPU time 19.62 seconds
Started Jul 16 08:02:28 PM PDT 24
Finished Jul 16 08:02:54 PM PDT 24
Peak memory 232464 kb
Host smart-3f555baf-ad08-4811-8f1d-bd232512d0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557045442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2557045442
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2509144092
Short name T978
Test name
Test status
Simulation time 4647138363 ps
CPU time 12.24 seconds
Started Jul 16 08:02:25 PM PDT 24
Finished Jul 16 08:02:42 PM PDT 24
Peak memory 223304 kb
Host smart-a70e7bec-b98d-4635-ae58-7c32f0fbf7dd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2509144092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2509144092
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2910163167
Short name T245
Test name
Test status
Simulation time 142190120724 ps
CPU time 308.29 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:07:46 PM PDT 24
Peak memory 281960 kb
Host smart-cc2dbdac-9052-462f-8e04-bff786226c1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910163167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2910163167
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3946613708
Short name T277
Test name
Test status
Simulation time 9281743430 ps
CPU time 47.37 seconds
Started Jul 16 08:02:22 PM PDT 24
Finished Jul 16 08:03:15 PM PDT 24
Peak memory 216380 kb
Host smart-5f22b1dc-b984-4bac-b5a3-76068b9faf3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946613708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3946613708
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3916601451
Short name T654
Test name
Test status
Simulation time 16449281432 ps
CPU time 9.36 seconds
Started Jul 16 08:02:28 PM PDT 24
Finished Jul 16 08:02:45 PM PDT 24
Peak memory 216468 kb
Host smart-98177c10-dbe4-46d9-b9f5-f6a6fabb9790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916601451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3916601451
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2587498570
Short name T848
Test name
Test status
Simulation time 55702197 ps
CPU time 1.09 seconds
Started Jul 16 08:02:26 PM PDT 24
Finished Jul 16 08:02:33 PM PDT 24
Peak memory 207556 kb
Host smart-4237ee31-2250-488d-a7f6-f9e3f65424c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587498570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2587498570
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3187613662
Short name T480
Test name
Test status
Simulation time 211114550 ps
CPU time 0.88 seconds
Started Jul 16 08:02:28 PM PDT 24
Finished Jul 16 08:02:35 PM PDT 24
Peak memory 205920 kb
Host smart-a5ba59c7-84fa-470a-a803-cc4753be8e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187613662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3187613662
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3552499591
Short name T943
Test name
Test status
Simulation time 322486478 ps
CPU time 3.08 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:02:41 PM PDT 24
Peak memory 224412 kb
Host smart-29ed021a-feea-475a-bc7e-3b52739d789c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552499591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3552499591
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3077874314
Short name T566
Test name
Test status
Simulation time 45289954 ps
CPU time 0.71 seconds
Started Jul 16 08:02:27 PM PDT 24
Finished Jul 16 08:02:33 PM PDT 24
Peak memory 205408 kb
Host smart-a6ed384d-110b-4186-b528-77359cf6532a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077874314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3077874314
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1030649536
Short name T389
Test name
Test status
Simulation time 98774501 ps
CPU time 2.68 seconds
Started Jul 16 08:02:27 PM PDT 24
Finished Jul 16 08:02:35 PM PDT 24
Peak memory 232528 kb
Host smart-87386f0b-939e-4a71-8a26-1bf967e31693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030649536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1030649536
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3603037402
Short name T731
Test name
Test status
Simulation time 27266016 ps
CPU time 0.74 seconds
Started Jul 16 08:02:32 PM PDT 24
Finished Jul 16 08:02:44 PM PDT 24
Peak memory 205608 kb
Host smart-cd0c386e-960a-4ea5-b7bd-7e4692bf4be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603037402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3603037402
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.985611636
Short name T183
Test name
Test status
Simulation time 14581042643 ps
CPU time 49.11 seconds
Started Jul 16 08:02:30 PM PDT 24
Finished Jul 16 08:03:28 PM PDT 24
Peak memory 249124 kb
Host smart-81945016-fd9d-4705-a9b9-4af8b00f598e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985611636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.985611636
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.316495562
Short name T499
Test name
Test status
Simulation time 5720680824 ps
CPU time 20.25 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:02:58 PM PDT 24
Peak memory 224644 kb
Host smart-500a796f-08f5-4764-908e-e1a7ec775625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316495562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.316495562
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2284092413
Short name T249
Test name
Test status
Simulation time 116287399451 ps
CPU time 237.02 seconds
Started Jul 16 08:02:28 PM PDT 24
Finished Jul 16 08:06:33 PM PDT 24
Peak memory 253516 kb
Host smart-705cf92e-243f-44f6-99e5-8c753ccfe117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284092413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2284092413
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3914338965
Short name T262
Test name
Test status
Simulation time 364809086 ps
CPU time 9.02 seconds
Started Jul 16 08:02:21 PM PDT 24
Finished Jul 16 08:02:36 PM PDT 24
Peak memory 224484 kb
Host smart-f3b67161-2640-45ba-994a-a8f49a1f079c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914338965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3914338965
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.1205320492
Short name T417
Test name
Test status
Simulation time 89341563627 ps
CPU time 147.38 seconds
Started Jul 16 08:02:26 PM PDT 24
Finished Jul 16 08:04:57 PM PDT 24
Peak memory 249236 kb
Host smart-8eb342fa-5993-4a58-abd0-c465513a739a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205320492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.1205320492
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2381771442
Short name T361
Test name
Test status
Simulation time 289228092 ps
CPU time 4.21 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:02:42 PM PDT 24
Peak memory 232628 kb
Host smart-493f213d-b58e-4139-9902-2bb4af4c68ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381771442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2381771442
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2108642011
Short name T940
Test name
Test status
Simulation time 221691451 ps
CPU time 7.57 seconds
Started Jul 16 08:02:20 PM PDT 24
Finished Jul 16 08:02:34 PM PDT 24
Peak memory 232640 kb
Host smart-61fa2f2a-3085-4cd0-a299-2794d07af859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108642011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2108642011
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2402728464
Short name T251
Test name
Test status
Simulation time 646023625 ps
CPU time 3.79 seconds
Started Jul 16 08:02:22 PM PDT 24
Finished Jul 16 08:02:31 PM PDT 24
Peak memory 224516 kb
Host smart-a5fcdfb3-aaa5-43b5-ae7a-cd780215d653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402728464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2402728464
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2115730724
Short name T834
Test name
Test status
Simulation time 3691474638 ps
CPU time 14.02 seconds
Started Jul 16 08:02:28 PM PDT 24
Finished Jul 16 08:02:50 PM PDT 24
Peak memory 232792 kb
Host smart-a54299d1-f383-46c4-8f76-92c5b6fc6ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115730724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2115730724
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1569460389
Short name T473
Test name
Test status
Simulation time 4720678365 ps
CPU time 7.91 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:02:45 PM PDT 24
Peak memory 220444 kb
Host smart-b4cb300c-c026-480a-9bce-02d6f213d46d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1569460389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1569460389
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.4065934655
Short name T230
Test name
Test status
Simulation time 133958505755 ps
CPU time 252.48 seconds
Started Jul 16 08:02:31 PM PDT 24
Finished Jul 16 08:06:53 PM PDT 24
Peak memory 268240 kb
Host smart-16c00dbd-86c0-4f91-8ab4-0c723fb1e9d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065934655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.4065934655
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1398091362
Short name T496
Test name
Test status
Simulation time 32094765 ps
CPU time 0.74 seconds
Started Jul 16 08:02:20 PM PDT 24
Finished Jul 16 08:02:27 PM PDT 24
Peak memory 206068 kb
Host smart-8e8a71bc-1fb4-4153-8fe3-d54acf66a47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398091362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1398091362
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1976664509
Short name T323
Test name
Test status
Simulation time 6900270513 ps
CPU time 11.72 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:02:49 PM PDT 24
Peak memory 216272 kb
Host smart-2a37ada5-734e-4671-a8ff-d3428d7cfb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976664509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1976664509
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.4115732522
Short name T674
Test name
Test status
Simulation time 1102266240 ps
CPU time 4.34 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:02:42 PM PDT 24
Peak memory 216280 kb
Host smart-27ac9823-4c9e-482c-8cf2-ba3de85243bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115732522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.4115732522
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.362506839
Short name T514
Test name
Test status
Simulation time 144595210 ps
CPU time 0.79 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:02:38 PM PDT 24
Peak memory 205952 kb
Host smart-be725ba2-4552-44ad-968d-784bdeadfab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362506839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.362506839
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3181116758
Short name T573
Test name
Test status
Simulation time 299814887 ps
CPU time 2.05 seconds
Started Jul 16 08:02:20 PM PDT 24
Finished Jul 16 08:02:28 PM PDT 24
Peak memory 224004 kb
Host smart-decd32d8-5fd8-486c-8b05-cdf334f5f2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181116758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3181116758
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3204002274
Short name T794
Test name
Test status
Simulation time 38186071 ps
CPU time 0.74 seconds
Started Jul 16 07:59:46 PM PDT 24
Finished Jul 16 07:59:49 PM PDT 24
Peak memory 204948 kb
Host smart-34e36e2e-aded-4911-940a-1b0143e88d2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204002274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
204002274
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2067805977
Short name T906
Test name
Test status
Simulation time 39566191 ps
CPU time 2.77 seconds
Started Jul 16 07:59:45 PM PDT 24
Finished Jul 16 07:59:50 PM PDT 24
Peak memory 232548 kb
Host smart-ebb39b7b-7565-4651-bea4-c5e5ff426d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067805977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2067805977
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2600535807
Short name T451
Test name
Test status
Simulation time 45066130 ps
CPU time 0.79 seconds
Started Jul 16 07:59:45 PM PDT 24
Finished Jul 16 07:59:48 PM PDT 24
Peak memory 206552 kb
Host smart-0e411e14-b13f-42f4-9008-07673da2fd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600535807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2600535807
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.643190005
Short name T167
Test name
Test status
Simulation time 6428650135 ps
CPU time 68.2 seconds
Started Jul 16 07:59:47 PM PDT 24
Finished Jul 16 08:00:58 PM PDT 24
Peak memory 257360 kb
Host smart-376f1b27-2c7c-483c-81d1-08765565fd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643190005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.643190005
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1677878575
Short name T505
Test name
Test status
Simulation time 88047683770 ps
CPU time 297.58 seconds
Started Jul 16 07:59:48 PM PDT 24
Finished Jul 16 08:04:49 PM PDT 24
Peak memory 256844 kb
Host smart-d3d7a3f7-386a-483a-8138-fcc1a673b7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677878575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1677878575
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3065914733
Short name T578
Test name
Test status
Simulation time 41528443545 ps
CPU time 402.72 seconds
Started Jul 16 07:59:47 PM PDT 24
Finished Jul 16 08:06:32 PM PDT 24
Peak memory 265612 kb
Host smart-c0033a1b-e454-4872-a5d0-5710c21eca05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065914733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3065914733
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3189669342
Short name T370
Test name
Test status
Simulation time 6919322986 ps
CPU time 11.11 seconds
Started Jul 16 07:59:43 PM PDT 24
Finished Jul 16 07:59:55 PM PDT 24
Peak memory 224548 kb
Host smart-bbcd1f34-bb42-4f3e-9dc6-79503864c6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189669342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3189669342
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.2017930233
Short name T964
Test name
Test status
Simulation time 37487092837 ps
CPU time 71.31 seconds
Started Jul 16 07:59:42 PM PDT 24
Finished Jul 16 08:00:54 PM PDT 24
Peak memory 253284 kb
Host smart-ceb8d379-052b-4af6-aae6-8d72ff96dc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017930233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.2017930233
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3824355775
Short name T908
Test name
Test status
Simulation time 1895173470 ps
CPU time 14.26 seconds
Started Jul 16 07:59:43 PM PDT 24
Finished Jul 16 07:59:58 PM PDT 24
Peak memory 224516 kb
Host smart-3b2b8200-f0a1-478f-a75f-229589d41ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824355775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3824355775
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2184145917
Short name T668
Test name
Test status
Simulation time 834641487 ps
CPU time 7.44 seconds
Started Jul 16 07:59:48 PM PDT 24
Finished Jul 16 07:59:58 PM PDT 24
Peak memory 232784 kb
Host smart-252ab950-86fa-43c6-be80-d4f384ede808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184145917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2184145917
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2223398344
Short name T580
Test name
Test status
Simulation time 405668385 ps
CPU time 2.58 seconds
Started Jul 16 07:59:44 PM PDT 24
Finished Jul 16 07:59:49 PM PDT 24
Peak memory 224360 kb
Host smart-58583ffd-4429-4c08-857b-72dc90850a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223398344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2223398344
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.4271021145
Short name T296
Test name
Test status
Simulation time 105689152 ps
CPU time 2.21 seconds
Started Jul 16 07:59:43 PM PDT 24
Finished Jul 16 07:59:46 PM PDT 24
Peak memory 223012 kb
Host smart-e7657119-8e10-4166-9478-eaf119a3cf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271021145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.4271021145
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3305890318
Short name T123
Test name
Test status
Simulation time 6117787575 ps
CPU time 8.41 seconds
Started Jul 16 07:59:48 PM PDT 24
Finished Jul 16 07:59:59 PM PDT 24
Peak memory 223220 kb
Host smart-a54c1561-bcce-42dd-b737-20384ff77d3a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3305890318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3305890318
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.4112652602
Short name T68
Test name
Test status
Simulation time 106971598 ps
CPU time 1.15 seconds
Started Jul 16 07:59:43 PM PDT 24
Finished Jul 16 07:59:45 PM PDT 24
Peak memory 236028 kb
Host smart-c95fcfc4-bd56-4cdd-944f-39fa53458256
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112652602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.4112652602
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2783541884
Short name T863
Test name
Test status
Simulation time 97796408848 ps
CPU time 557.48 seconds
Started Jul 16 07:59:41 PM PDT 24
Finished Jul 16 08:08:59 PM PDT 24
Peak memory 273872 kb
Host smart-91ebfc16-0d76-458d-9be5-a13003bb338c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783541884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2783541884
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1797170964
Short name T719
Test name
Test status
Simulation time 54771636429 ps
CPU time 32.87 seconds
Started Jul 16 07:59:48 PM PDT 24
Finished Jul 16 08:00:23 PM PDT 24
Peak memory 216384 kb
Host smart-24cadd15-4dea-4f17-ba37-e873b73fc74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797170964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1797170964
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3239906822
Short name T521
Test name
Test status
Simulation time 14152869 ps
CPU time 0.75 seconds
Started Jul 16 07:59:44 PM PDT 24
Finished Jul 16 07:59:46 PM PDT 24
Peak memory 205736 kb
Host smart-1ac0d6fe-79b7-41d5-8928-466244982c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239906822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3239906822
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2406395432
Short name T924
Test name
Test status
Simulation time 671503648 ps
CPU time 2.17 seconds
Started Jul 16 07:59:49 PM PDT 24
Finished Jul 16 07:59:54 PM PDT 24
Peak memory 216192 kb
Host smart-0c7b88ea-2910-475e-9dd6-008e5016c5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406395432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2406395432
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2182856537
Short name T137
Test name
Test status
Simulation time 23452249 ps
CPU time 0.88 seconds
Started Jul 16 07:59:47 PM PDT 24
Finished Jul 16 07:59:50 PM PDT 24
Peak memory 206000 kb
Host smart-2cc9f60d-27b6-4386-b799-845205e8af67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182856537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2182856537
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.4120215326
Short name T181
Test name
Test status
Simulation time 916016438 ps
CPU time 6.09 seconds
Started Jul 16 07:59:40 PM PDT 24
Finished Jul 16 07:59:47 PM PDT 24
Peak memory 232708 kb
Host smart-60347149-8cce-4107-b92e-51eec92fd43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120215326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.4120215326
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.4027386154
Short name T308
Test name
Test status
Simulation time 11185351 ps
CPU time 0.76 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:02:39 PM PDT 24
Peak memory 205884 kb
Host smart-6af3f218-9648-4bc2-be0e-b5bd7458eee7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027386154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
4027386154
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.413346095
Short name T231
Test name
Test status
Simulation time 425325435 ps
CPU time 7.86 seconds
Started Jul 16 08:02:30 PM PDT 24
Finished Jul 16 08:02:48 PM PDT 24
Peak memory 224664 kb
Host smart-74444872-ea7a-4f91-851d-b35521aae9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413346095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.413346095
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.242075522
Short name T958
Test name
Test status
Simulation time 33481546 ps
CPU time 0.76 seconds
Started Jul 16 08:02:26 PM PDT 24
Finished Jul 16 08:02:32 PM PDT 24
Peak memory 205592 kb
Host smart-a519a737-a247-4665-895d-8cd9be8f9fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242075522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.242075522
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1019492378
Short name T852
Test name
Test status
Simulation time 20995975729 ps
CPU time 106.38 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:04:26 PM PDT 24
Peak memory 241016 kb
Host smart-5e5f5010-9b22-4cc0-8905-29dafdc78293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019492378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1019492378
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.107562929
Short name T588
Test name
Test status
Simulation time 6553923079 ps
CPU time 67.22 seconds
Started Jul 16 08:02:27 PM PDT 24
Finished Jul 16 08:03:40 PM PDT 24
Peak memory 261096 kb
Host smart-472d8a8c-8ac5-4342-ba25-5176dc066581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107562929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.107562929
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.4166469392
Short name T268
Test name
Test status
Simulation time 3702304025 ps
CPU time 50.87 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:03:29 PM PDT 24
Peak memory 238976 kb
Host smart-9f6f621f-d5c1-4013-898b-81d1c61207e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166469392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.4166469392
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.3376152518
Short name T798
Test name
Test status
Simulation time 3571415222 ps
CPU time 52.34 seconds
Started Jul 16 08:02:31 PM PDT 24
Finished Jul 16 08:03:33 PM PDT 24
Peak memory 257488 kb
Host smart-bb6f8e41-1dbe-40b4-abf6-bc0f22304164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376152518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.3376152518
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2009570575
Short name T665
Test name
Test status
Simulation time 1511316181 ps
CPU time 10.73 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:02:48 PM PDT 24
Peak memory 232648 kb
Host smart-9f0514a0-7585-47f6-a97d-f8e40ef95e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009570575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2009570575
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3878997993
Short name T435
Test name
Test status
Simulation time 10928789709 ps
CPU time 92.76 seconds
Started Jul 16 08:02:26 PM PDT 24
Finished Jul 16 08:04:04 PM PDT 24
Peak memory 239700 kb
Host smart-5b4a784c-6d15-4fee-9a52-969d61e31a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878997993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3878997993
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.507343199
Short name T928
Test name
Test status
Simulation time 21105067571 ps
CPU time 15.34 seconds
Started Jul 16 08:02:28 PM PDT 24
Finished Jul 16 08:02:50 PM PDT 24
Peak memory 232772 kb
Host smart-ab69c6f0-24b9-49cc-9e3e-def7ab606f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507343199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.507343199
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.932457376
Short name T965
Test name
Test status
Simulation time 512135820 ps
CPU time 6.04 seconds
Started Jul 16 08:02:31 PM PDT 24
Finished Jul 16 08:02:47 PM PDT 24
Peak memory 224524 kb
Host smart-908efc23-ef3e-4e15-923f-7837ef3a9eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932457376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.932457376
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2515519429
Short name T331
Test name
Test status
Simulation time 7572243742 ps
CPU time 11.57 seconds
Started Jul 16 08:02:28 PM PDT 24
Finished Jul 16 08:02:47 PM PDT 24
Peak memory 219076 kb
Host smart-a4cfa710-d1fe-485f-90e3-874a7c2f92e0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2515519429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2515519429
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1122065566
Short name T133
Test name
Test status
Simulation time 21712829612 ps
CPU time 181.43 seconds
Started Jul 16 08:02:32 PM PDT 24
Finished Jul 16 08:05:44 PM PDT 24
Peak memory 254940 kb
Host smart-78cb69be-848b-4c92-bd81-0c568fa0fff3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122065566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1122065566
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2854362201
Short name T524
Test name
Test status
Simulation time 7009141947 ps
CPU time 39.81 seconds
Started Jul 16 08:02:21 PM PDT 24
Finished Jul 16 08:03:07 PM PDT 24
Peak memory 216376 kb
Host smart-519f91e3-b20f-4c32-bef1-397bb2d5143e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854362201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2854362201
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2697460942
Short name T3
Test name
Test status
Simulation time 3695011419 ps
CPU time 9.22 seconds
Started Jul 16 08:02:28 PM PDT 24
Finished Jul 16 08:02:45 PM PDT 24
Peak memory 216364 kb
Host smart-b3147f82-29f1-42da-8914-3395471a2dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697460942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2697460942
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.432622694
Short name T360
Test name
Test status
Simulation time 1371604443 ps
CPU time 2.52 seconds
Started Jul 16 08:02:28 PM PDT 24
Finished Jul 16 08:02:39 PM PDT 24
Peak memory 216324 kb
Host smart-fada497e-3ed3-4b86-a9ef-38b20bbf5eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432622694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.432622694
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1515802603
Short name T960
Test name
Test status
Simulation time 127046250 ps
CPU time 0.84 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:02:38 PM PDT 24
Peak memory 205992 kb
Host smart-29597446-ef05-4616-a53a-67b07565d2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515802603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1515802603
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2853685692
Short name T227
Test name
Test status
Simulation time 5728334061 ps
CPU time 6.73 seconds
Started Jul 16 08:02:26 PM PDT 24
Finished Jul 16 08:02:38 PM PDT 24
Peak memory 232936 kb
Host smart-8731139d-ce1c-4f91-ab97-9f52c3fd0a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853685692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2853685692
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1323139544
Short name T406
Test name
Test status
Simulation time 50967300 ps
CPU time 0.74 seconds
Started Jul 16 08:02:30 PM PDT 24
Finished Jul 16 08:02:40 PM PDT 24
Peak memory 204936 kb
Host smart-8e63f7a8-4919-47c8-8758-2ede768f4449
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323139544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1323139544
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.780052420
Short name T444
Test name
Test status
Simulation time 168804514 ps
CPU time 2.47 seconds
Started Jul 16 08:02:34 PM PDT 24
Finished Jul 16 08:02:48 PM PDT 24
Peak memory 224420 kb
Host smart-45a1ca41-7dab-404f-9d13-0f94ef337111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780052420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.780052420
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3980786248
Short name T560
Test name
Test status
Simulation time 23561794 ps
CPU time 0.73 seconds
Started Jul 16 08:02:31 PM PDT 24
Finished Jul 16 08:02:41 PM PDT 24
Peak memory 206940 kb
Host smart-3df46610-e568-46b3-b014-75d8e8e194bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980786248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3980786248
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3419357026
Short name T850
Test name
Test status
Simulation time 8760782834 ps
CPU time 69.31 seconds
Started Jul 16 08:02:34 PM PDT 24
Finished Jul 16 08:03:55 PM PDT 24
Peak memory 238228 kb
Host smart-87478643-c57c-4294-a1aa-dbfd5cd3d62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419357026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3419357026
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3013686009
Short name T986
Test name
Test status
Simulation time 14402472891 ps
CPU time 79.84 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:03:59 PM PDT 24
Peak memory 257168 kb
Host smart-ac194663-1334-4799-8989-b5feb139480b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013686009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3013686009
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.36942380
Short name T413
Test name
Test status
Simulation time 5412220521 ps
CPU time 4.07 seconds
Started Jul 16 08:02:32 PM PDT 24
Finished Jul 16 08:02:47 PM PDT 24
Peak memory 217876 kb
Host smart-66cc5957-ca07-413b-b66b-90f3d41b49a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36942380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle.36942380
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1135232022
Short name T966
Test name
Test status
Simulation time 326719920 ps
CPU time 8.18 seconds
Started Jul 16 08:02:35 PM PDT 24
Finished Jul 16 08:02:56 PM PDT 24
Peak memory 238332 kb
Host smart-5c3ddcce-25c7-44ca-a407-cbec26b4e825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135232022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1135232022
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.280402061
Short name T258
Test name
Test status
Simulation time 22736042776 ps
CPU time 167.62 seconds
Started Jul 16 08:02:31 PM PDT 24
Finished Jul 16 08:05:30 PM PDT 24
Peak memory 250324 kb
Host smart-88464d3f-3c91-4379-af18-0739e45417b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280402061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds
.280402061
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2368209785
Short name T576
Test name
Test status
Simulation time 1592353350 ps
CPU time 6.46 seconds
Started Jul 16 08:02:35 PM PDT 24
Finished Jul 16 08:02:54 PM PDT 24
Peak memory 232648 kb
Host smart-47c0a5ce-b935-4461-8b1b-baf780b6855e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368209785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2368209785
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3013826682
Short name T515
Test name
Test status
Simulation time 13511070037 ps
CPU time 43.61 seconds
Started Jul 16 08:02:34 PM PDT 24
Finished Jul 16 08:03:29 PM PDT 24
Peak memory 232768 kb
Host smart-5c2ac649-9b78-4445-9f87-07ea60de913e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013826682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3013826682
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.842867945
Short name T238
Test name
Test status
Simulation time 3963636603 ps
CPU time 13.77 seconds
Started Jul 16 08:02:31 PM PDT 24
Finished Jul 16 08:02:56 PM PDT 24
Peak memory 232708 kb
Host smart-c120f676-688c-4fc2-901b-554a3a9e7799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842867945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.842867945
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2341174344
Short name T310
Test name
Test status
Simulation time 59318201 ps
CPU time 2.44 seconds
Started Jul 16 08:02:35 PM PDT 24
Finished Jul 16 08:02:50 PM PDT 24
Peak memory 232256 kb
Host smart-dd7474e2-9a4a-4d3e-a314-62a93672eaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341174344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2341174344
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2558469400
Short name T789
Test name
Test status
Simulation time 3559814309 ps
CPU time 5.06 seconds
Started Jul 16 08:02:30 PM PDT 24
Finished Jul 16 08:02:44 PM PDT 24
Peak memory 219616 kb
Host smart-50908ba7-ec1c-4c16-96ff-aa8ee83bc415
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2558469400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2558469400
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2135725175
Short name T213
Test name
Test status
Simulation time 65424877752 ps
CPU time 195.85 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:05:54 PM PDT 24
Peak memory 273184 kb
Host smart-df9ca00e-b885-4741-bf29-f1e93098b786
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135725175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2135725175
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.890746465
Short name T416
Test name
Test status
Simulation time 6600379719 ps
CPU time 3.48 seconds
Started Jul 16 08:02:32 PM PDT 24
Finished Jul 16 08:02:47 PM PDT 24
Peak memory 218404 kb
Host smart-6b21f204-224b-48b2-a9a1-1a4387476fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890746465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.890746465
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1153186966
Short name T951
Test name
Test status
Simulation time 16447411738 ps
CPU time 14.54 seconds
Started Jul 16 08:02:31 PM PDT 24
Finished Jul 16 08:02:55 PM PDT 24
Peak memory 216360 kb
Host smart-f1909340-5faa-4108-981b-0d205ae7ab8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153186966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1153186966
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2638059002
Short name T533
Test name
Test status
Simulation time 607070020 ps
CPU time 2.71 seconds
Started Jul 16 08:02:35 PM PDT 24
Finished Jul 16 08:02:50 PM PDT 24
Peak memory 216140 kb
Host smart-033bbd18-ed84-4ed3-a191-72c5846a3334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638059002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2638059002
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3932144749
Short name T630
Test name
Test status
Simulation time 24236012 ps
CPU time 0.74 seconds
Started Jul 16 08:02:35 PM PDT 24
Finished Jul 16 08:02:48 PM PDT 24
Peak memory 205924 kb
Host smart-8951b816-0141-45c3-98f3-8e268f63ddf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932144749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3932144749
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2230785705
Short name T593
Test name
Test status
Simulation time 2932478729 ps
CPU time 6.49 seconds
Started Jul 16 08:02:32 PM PDT 24
Finished Jul 16 08:02:49 PM PDT 24
Peak memory 232824 kb
Host smart-bacbb93f-7bcc-43bd-8555-8ad3b0f94618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230785705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2230785705
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2318618630
Short name T729
Test name
Test status
Simulation time 25288281 ps
CPU time 0.69 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:02:39 PM PDT 24
Peak memory 205544 kb
Host smart-0d9b4d29-504a-4962-bd61-404801d89a51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318618630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2318618630
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2119535030
Short name T836
Test name
Test status
Simulation time 414070184 ps
CPU time 2.23 seconds
Started Jul 16 08:02:31 PM PDT 24
Finished Jul 16 08:02:43 PM PDT 24
Peak memory 224120 kb
Host smart-a383ea62-95fd-416d-ba03-753c8ccea1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119535030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2119535030
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1417641810
Short name T436
Test name
Test status
Simulation time 51364362 ps
CPU time 0.78 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:02:38 PM PDT 24
Peak memory 206564 kb
Host smart-2664da9c-bb49-432e-87bd-4dd86119c2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417641810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1417641810
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3696189187
Short name T678
Test name
Test status
Simulation time 2100158375 ps
CPU time 15.99 seconds
Started Jul 16 08:02:33 PM PDT 24
Finished Jul 16 08:03:01 PM PDT 24
Peak memory 254972 kb
Host smart-e4a32e05-ddde-40dd-b285-bdee7bd9ca0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696189187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3696189187
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.4193566102
Short name T391
Test name
Test status
Simulation time 16052618567 ps
CPU time 17.16 seconds
Started Jul 16 08:02:32 PM PDT 24
Finished Jul 16 08:03:00 PM PDT 24
Peak memory 217488 kb
Host smart-ce3f93a4-6463-426b-80a9-9148e5886009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193566102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.4193566102
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1686918527
Short name T464
Test name
Test status
Simulation time 1346939066 ps
CPU time 23.12 seconds
Started Jul 16 08:02:30 PM PDT 24
Finished Jul 16 08:03:02 PM PDT 24
Peak memory 249068 kb
Host smart-548da767-c0bb-4a0b-8295-43553ba94a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686918527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1686918527
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.432444364
Short name T652
Test name
Test status
Simulation time 1243833227 ps
CPU time 8.61 seconds
Started Jul 16 08:02:32 PM PDT 24
Finished Jul 16 08:02:52 PM PDT 24
Peak memory 224420 kb
Host smart-aa469786-41dd-4bc2-8758-202d2277acf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432444364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds
.432444364
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2874911362
Short name T347
Test name
Test status
Simulation time 641664809 ps
CPU time 2.55 seconds
Started Jul 16 08:02:30 PM PDT 24
Finished Jul 16 08:02:42 PM PDT 24
Peak memory 224408 kb
Host smart-9aec8c38-6dd9-4628-b4ed-e36dde98fb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874911362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2874911362
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.4179007066
Short name T767
Test name
Test status
Simulation time 404816231 ps
CPU time 8.21 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:02:47 PM PDT 24
Peak memory 232668 kb
Host smart-b402e563-736d-47bf-92aa-8f975de6f295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179007066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.4179007066
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2444809283
Short name T257
Test name
Test status
Simulation time 9630085657 ps
CPU time 26.61 seconds
Started Jul 16 08:02:31 PM PDT 24
Finished Jul 16 08:03:09 PM PDT 24
Peak memory 232756 kb
Host smart-46b67087-05f3-41b8-be75-99f530b986b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444809283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2444809283
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.766275778
Short name T546
Test name
Test status
Simulation time 6863542272 ps
CPU time 6.49 seconds
Started Jul 16 08:02:25 PM PDT 24
Finished Jul 16 08:02:36 PM PDT 24
Peak memory 224620 kb
Host smart-e93387c7-038c-400b-8f83-cdd0fcdf538e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766275778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.766275778
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.464442786
Short name T819
Test name
Test status
Simulation time 1078490721 ps
CPU time 6.97 seconds
Started Jul 16 08:02:32 PM PDT 24
Finished Jul 16 08:02:50 PM PDT 24
Peak memory 223116 kb
Host smart-f05a0f8b-9a9d-497b-ab27-643bd3dab6a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=464442786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.464442786
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3225281117
Short name T286
Test name
Test status
Simulation time 44039559743 ps
CPU time 200.42 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:05:59 PM PDT 24
Peak memory 253156 kb
Host smart-1f3e8e5f-c9c3-43cb-a4f3-9adc2155cdef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225281117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3225281117
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.248555434
Short name T828
Test name
Test status
Simulation time 15167935817 ps
CPU time 21.04 seconds
Started Jul 16 08:02:31 PM PDT 24
Finished Jul 16 08:03:03 PM PDT 24
Peak memory 216360 kb
Host smart-91f632f2-bcab-4f86-9a31-578b3a6824cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248555434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.248555434
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2124475074
Short name T536
Test name
Test status
Simulation time 108886715 ps
CPU time 0.68 seconds
Started Jul 16 08:02:30 PM PDT 24
Finished Jul 16 08:02:41 PM PDT 24
Peak memory 205696 kb
Host smart-3f1e263c-30d2-4150-9ac0-99da823c71fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124475074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2124475074
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1631784200
Short name T710
Test name
Test status
Simulation time 207213954 ps
CPU time 1.7 seconds
Started Jul 16 08:02:32 PM PDT 24
Finished Jul 16 08:02:44 PM PDT 24
Peak memory 216244 kb
Host smart-36c9ef87-86c8-4d8c-9eea-7cd0976caa71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631784200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1631784200
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1746798195
Short name T949
Test name
Test status
Simulation time 77069638 ps
CPU time 0.81 seconds
Started Jul 16 08:02:30 PM PDT 24
Finished Jul 16 08:02:41 PM PDT 24
Peak memory 205960 kb
Host smart-77eaf0b6-a43c-4257-a00d-c933e647adf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746798195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1746798195
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1357540205
Short name T662
Test name
Test status
Simulation time 9338075016 ps
CPU time 4.89 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:02:42 PM PDT 24
Peak memory 232784 kb
Host smart-0d57d466-6a80-4e1f-978c-8645e4fa1a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357540205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1357540205
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3424482295
Short name T334
Test name
Test status
Simulation time 14143522 ps
CPU time 0.71 seconds
Started Jul 16 08:02:33 PM PDT 24
Finished Jul 16 08:02:46 PM PDT 24
Peak memory 205500 kb
Host smart-9ee67ecd-2f07-4b3b-96ac-3e8da75e6655
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424482295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3424482295
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.854567317
Short name T541
Test name
Test status
Simulation time 139122343 ps
CPU time 4.14 seconds
Started Jul 16 08:02:31 PM PDT 24
Finished Jul 16 08:02:45 PM PDT 24
Peak memory 232724 kb
Host smart-0588a5d3-6d5e-468a-ba71-ca053801bafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854567317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.854567317
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2163866598
Short name T376
Test name
Test status
Simulation time 124254491 ps
CPU time 0.76 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:02:38 PM PDT 24
Peak memory 206604 kb
Host smart-b6225bc7-6309-44d0-a8ea-e916a2b64c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163866598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2163866598
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2165725395
Short name T141
Test name
Test status
Simulation time 10974537985 ps
CPU time 40.02 seconds
Started Jul 16 08:02:40 PM PDT 24
Finished Jul 16 08:03:32 PM PDT 24
Peak memory 249452 kb
Host smart-3c38b444-1f1d-4f79-9f9c-0f909fa185b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165725395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2165725395
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1607230354
Short name T278
Test name
Test status
Simulation time 11778305961 ps
CPU time 48.93 seconds
Started Jul 16 08:02:39 PM PDT 24
Finished Jul 16 08:03:39 PM PDT 24
Peak memory 233892 kb
Host smart-d8112b95-55b6-42ac-b057-48e4179b4719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607230354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1607230354
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.4052521835
Short name T657
Test name
Test status
Simulation time 714316496031 ps
CPU time 378.45 seconds
Started Jul 16 08:02:41 PM PDT 24
Finished Jul 16 08:09:11 PM PDT 24
Peak memory 251856 kb
Host smart-7be528f8-5694-4570-a643-e9144938b41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052521835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.4052521835
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2994517701
Short name T317
Test name
Test status
Simulation time 3893660492 ps
CPU time 9.48 seconds
Started Jul 16 08:02:35 PM PDT 24
Finished Jul 16 08:02:57 PM PDT 24
Peak memory 236680 kb
Host smart-317f50ff-4c93-493f-82eb-ce8f451be4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994517701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2994517701
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.4159154965
Short name T397
Test name
Test status
Simulation time 3306588526 ps
CPU time 38.66 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:03:16 PM PDT 24
Peak memory 249216 kb
Host smart-7f0ccbbd-6a1c-4c08-876f-628e49eddb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159154965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.4159154965
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.282689893
Short name T421
Test name
Test status
Simulation time 197245261 ps
CPU time 2.82 seconds
Started Jul 16 08:02:35 PM PDT 24
Finished Jul 16 08:02:50 PM PDT 24
Peak memory 224180 kb
Host smart-92ad59f3-faae-4302-9dc0-66004b6741e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282689893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.282689893
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.876844454
Short name T639
Test name
Test status
Simulation time 6156894878 ps
CPU time 13.85 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:02:51 PM PDT 24
Peak memory 224632 kb
Host smart-7003dff0-7bb9-4782-bce9-3d744cff3005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876844454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.876844454
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1489692084
Short name T930
Test name
Test status
Simulation time 268360664 ps
CPU time 2.58 seconds
Started Jul 16 08:02:26 PM PDT 24
Finished Jul 16 08:02:33 PM PDT 24
Peak memory 224652 kb
Host smart-b1e89eba-86d3-4737-b8f7-f0b616e6cca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489692084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1489692084
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2962517470
Short name T739
Test name
Test status
Simulation time 8939683427 ps
CPU time 16.18 seconds
Started Jul 16 08:02:31 PM PDT 24
Finished Jul 16 08:02:57 PM PDT 24
Peak memory 232840 kb
Host smart-662a7afa-502b-436f-a5b7-9d49a094ea6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962517470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2962517470
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2915749421
Short name T754
Test name
Test status
Simulation time 1151887563 ps
CPU time 5.89 seconds
Started Jul 16 08:02:35 PM PDT 24
Finished Jul 16 08:02:53 PM PDT 24
Peak memory 219680 kb
Host smart-fba3b724-b234-4645-9c6e-d8c15206f5f3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2915749421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2915749421
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.855610252
Short name T640
Test name
Test status
Simulation time 72209843832 ps
CPU time 207.31 seconds
Started Jul 16 08:02:41 PM PDT 24
Finished Jul 16 08:06:19 PM PDT 24
Peak memory 265828 kb
Host smart-5a079ccc-d4ed-47f9-9388-5746794feffe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855610252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.855610252
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1077437839
Short name T773
Test name
Test status
Simulation time 5163474155 ps
CPU time 25.34 seconds
Started Jul 16 08:02:31 PM PDT 24
Finished Jul 16 08:03:06 PM PDT 24
Peak memory 216388 kb
Host smart-ffc19b01-a839-41eb-af65-b9caf6741ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077437839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1077437839
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3971150560
Short name T73
Test name
Test status
Simulation time 1131002287 ps
CPU time 2.38 seconds
Started Jul 16 08:02:19 PM PDT 24
Finished Jul 16 08:02:27 PM PDT 24
Peak memory 207884 kb
Host smart-da4b87be-0dbf-4e99-925e-19764cd24269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971150560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3971150560
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1668673938
Short name T774
Test name
Test status
Simulation time 83093002 ps
CPU time 1.26 seconds
Started Jul 16 08:02:27 PM PDT 24
Finished Jul 16 08:02:34 PM PDT 24
Peak memory 216352 kb
Host smart-0eb29b95-ae05-47fc-b0c8-abb1ebc6fc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668673938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1668673938
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.644822676
Short name T517
Test name
Test status
Simulation time 59939621 ps
CPU time 0.81 seconds
Started Jul 16 08:02:33 PM PDT 24
Finished Jul 16 08:02:46 PM PDT 24
Peak memory 206004 kb
Host smart-a16c9cb4-cf91-483e-91e5-edf49917077b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644822676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.644822676
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2434316564
Short name T603
Test name
Test status
Simulation time 149408762 ps
CPU time 2.26 seconds
Started Jul 16 08:02:28 PM PDT 24
Finished Jul 16 08:02:39 PM PDT 24
Peak memory 224180 kb
Host smart-7683537e-182c-49ac-b2cc-789c9e7647ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434316564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2434316564
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.750548331
Short name T969
Test name
Test status
Simulation time 70868493 ps
CPU time 0.71 seconds
Started Jul 16 08:02:42 PM PDT 24
Finished Jul 16 08:02:54 PM PDT 24
Peak memory 204944 kb
Host smart-7d8b8fca-0029-4aa0-bd16-31377eec5a1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750548331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.750548331
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3580722577
Short name T17
Test name
Test status
Simulation time 317415815 ps
CPU time 6.12 seconds
Started Jul 16 08:02:39 PM PDT 24
Finished Jul 16 08:02:56 PM PDT 24
Peak memory 224504 kb
Host smart-a67e8e8f-8843-4879-8d4a-8a0d84a6eb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580722577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3580722577
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1558127379
Short name T671
Test name
Test status
Simulation time 66784854 ps
CPU time 0.77 seconds
Started Jul 16 08:02:32 PM PDT 24
Finished Jul 16 08:02:44 PM PDT 24
Peak memory 206576 kb
Host smart-c88857d1-00ce-45b4-9ce0-1175f2b1a298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558127379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1558127379
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1866464202
Short name T987
Test name
Test status
Simulation time 18841568454 ps
CPU time 140.96 seconds
Started Jul 16 08:02:38 PM PDT 24
Finished Jul 16 08:05:11 PM PDT 24
Peak memory 257356 kb
Host smart-b6caeab9-d2fa-4140-94f7-0e870f7f05f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866464202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1866464202
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3140594950
Short name T700
Test name
Test status
Simulation time 6243412062 ps
CPU time 145.29 seconds
Started Jul 16 08:02:41 PM PDT 24
Finished Jul 16 08:05:18 PM PDT 24
Peak memory 257224 kb
Host smart-3f690d81-dd20-4b31-b7ac-f1f9d5ab6d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140594950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3140594950
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.4225635570
Short name T426
Test name
Test status
Simulation time 13547395955 ps
CPU time 95.81 seconds
Started Jul 16 08:02:38 PM PDT 24
Finished Jul 16 08:04:26 PM PDT 24
Peak memory 251640 kb
Host smart-d493c921-a8c7-481b-9e3e-91ade7312518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225635570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.4225635570
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1339931272
Short name T271
Test name
Test status
Simulation time 4810817344 ps
CPU time 9.25 seconds
Started Jul 16 08:02:30 PM PDT 24
Finished Jul 16 08:02:50 PM PDT 24
Peak memory 249224 kb
Host smart-a3979da3-334a-437b-8bac-d7aff0f6a282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339931272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1339931272
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.2596800868
Short name T679
Test name
Test status
Simulation time 3476563698 ps
CPU time 58.29 seconds
Started Jul 16 08:02:41 PM PDT 24
Finished Jul 16 08:03:51 PM PDT 24
Peak memory 254648 kb
Host smart-ac96e194-ff04-48f4-96b2-4dac25d7026e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596800868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.2596800868
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1482750914
Short name T985
Test name
Test status
Simulation time 8231218638 ps
CPU time 16.72 seconds
Started Jul 16 08:02:32 PM PDT 24
Finished Jul 16 08:03:00 PM PDT 24
Peak memory 224528 kb
Host smart-1dca3fa1-245a-4423-8cf7-f716c0be9d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482750914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1482750914
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1630937959
Short name T178
Test name
Test status
Simulation time 5965913174 ps
CPU time 33.02 seconds
Started Jul 16 08:02:41 PM PDT 24
Finished Jul 16 08:03:25 PM PDT 24
Peak memory 240736 kb
Host smart-7efec31a-cae7-4756-b3a8-724dbc85839d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630937959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1630937959
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.4236255356
Short name T890
Test name
Test status
Simulation time 24014258814 ps
CPU time 15.61 seconds
Started Jul 16 08:02:33 PM PDT 24
Finished Jul 16 08:03:00 PM PDT 24
Peak memory 224600 kb
Host smart-8658e101-01ec-4844-b898-4e66ac181bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236255356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.4236255356
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2585435138
Short name T939
Test name
Test status
Simulation time 1355999031 ps
CPU time 6.68 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:02:44 PM PDT 24
Peak memory 232696 kb
Host smart-65835f4e-06bd-45df-b3dc-984f6cbed6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585435138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2585435138
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1066031198
Short name T498
Test name
Test status
Simulation time 309741091 ps
CPU time 3.37 seconds
Started Jul 16 08:02:42 PM PDT 24
Finished Jul 16 08:02:56 PM PDT 24
Peak memory 222640 kb
Host smart-fdba1d56-75b3-462d-a963-f3aaf6673a65
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1066031198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1066031198
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.59973444
Short name T282
Test name
Test status
Simulation time 150424732574 ps
CPU time 421 seconds
Started Jul 16 08:02:33 PM PDT 24
Finished Jul 16 08:09:46 PM PDT 24
Peak memory 266704 kb
Host smart-66cb0e78-9e78-40a9-9bcf-d5e5a1477623
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59973444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stress
_all.59973444
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.181634665
Short name T984
Test name
Test status
Simulation time 1571137553 ps
CPU time 5.45 seconds
Started Jul 16 08:02:40 PM PDT 24
Finished Jul 16 08:02:57 PM PDT 24
Peak memory 216212 kb
Host smart-fcb4f18c-5b98-4f5d-9236-921e041744a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181634665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.181634665
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.960469141
Short name T56
Test name
Test status
Simulation time 1687968343 ps
CPU time 3.1 seconds
Started Jul 16 08:02:28 PM PDT 24
Finished Jul 16 08:02:39 PM PDT 24
Peak memory 216264 kb
Host smart-2930df87-a3d2-4063-8d78-f26352d9f897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960469141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.960469141
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.922836726
Short name T974
Test name
Test status
Simulation time 312501712 ps
CPU time 4.21 seconds
Started Jul 16 08:02:33 PM PDT 24
Finished Jul 16 08:02:48 PM PDT 24
Peak memory 216304 kb
Host smart-7b5639f5-64fe-4e57-8e69-fde36438f13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922836726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.922836726
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1820088919
Short name T703
Test name
Test status
Simulation time 99805412 ps
CPU time 0.96 seconds
Started Jul 16 08:02:40 PM PDT 24
Finished Jul 16 08:02:52 PM PDT 24
Peak memory 206456 kb
Host smart-424bcacc-5475-4fa9-ba9c-de48610b494a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820088919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1820088919
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2616256491
Short name T214
Test name
Test status
Simulation time 2467637120 ps
CPU time 8.51 seconds
Started Jul 16 08:02:42 PM PDT 24
Finished Jul 16 08:03:02 PM PDT 24
Peak memory 224560 kb
Host smart-95a27f54-9e2e-4f6f-9f4a-134c46e8b7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616256491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2616256491
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1761366393
Short name T632
Test name
Test status
Simulation time 18030062 ps
CPU time 0.7 seconds
Started Jul 16 08:02:39 PM PDT 24
Finished Jul 16 08:02:51 PM PDT 24
Peak memory 205544 kb
Host smart-99549f7e-a5cd-4cf6-b3eb-535b74215af2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761366393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1761366393
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.308955821
Short name T233
Test name
Test status
Simulation time 94105594 ps
CPU time 3.09 seconds
Started Jul 16 08:02:41 PM PDT 24
Finished Jul 16 08:02:56 PM PDT 24
Peak memory 232692 kb
Host smart-ea9b2557-1453-4416-89c9-8f73abb1ceb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308955821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.308955821
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2592964498
Short name T468
Test name
Test status
Simulation time 37117940 ps
CPU time 0.76 seconds
Started Jul 16 08:02:41 PM PDT 24
Finished Jul 16 08:02:53 PM PDT 24
Peak memory 206676 kb
Host smart-f5dff234-a3a0-433e-bffc-d0900e2541d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592964498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2592964498
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.693795732
Short name T957
Test name
Test status
Simulation time 20613244 ps
CPU time 0.73 seconds
Started Jul 16 08:02:37 PM PDT 24
Finished Jul 16 08:02:49 PM PDT 24
Peak memory 215796 kb
Host smart-41b036b7-1505-4539-bdc4-5aa93d73e2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693795732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.693795732
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1935522455
Short name T860
Test name
Test status
Simulation time 1889737980 ps
CPU time 7.57 seconds
Started Jul 16 08:02:41 PM PDT 24
Finished Jul 16 08:03:00 PM PDT 24
Peak memory 219260 kb
Host smart-6317fdba-ed3e-4d84-a490-819740b1c7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935522455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1935522455
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3065648438
Short name T163
Test name
Test status
Simulation time 12961006623 ps
CPU time 121.52 seconds
Started Jul 16 08:02:40 PM PDT 24
Finished Jul 16 08:04:54 PM PDT 24
Peak memory 249472 kb
Host smart-a7db89e2-8708-49c6-b3a9-03d0a7e60f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065648438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3065648438
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2115314090
Short name T266
Test name
Test status
Simulation time 1256902232 ps
CPU time 6.41 seconds
Started Jul 16 08:02:38 PM PDT 24
Finished Jul 16 08:02:56 PM PDT 24
Peak memory 232648 kb
Host smart-8c0597fd-621b-4224-83af-d2cc4826e951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115314090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2115314090
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.2550535809
Short name T79
Test name
Test status
Simulation time 21944373030 ps
CPU time 144.87 seconds
Started Jul 16 08:02:41 PM PDT 24
Finished Jul 16 08:05:17 PM PDT 24
Peak memory 251336 kb
Host smart-7336cd0d-f85e-4306-8237-00900e9e0bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550535809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.2550535809
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1946028998
Short name T374
Test name
Test status
Simulation time 335375918 ps
CPU time 6.12 seconds
Started Jul 16 08:02:32 PM PDT 24
Finished Jul 16 08:02:50 PM PDT 24
Peak memory 232696 kb
Host smart-c031a7dd-59ca-440f-8ce9-0cafc3582ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946028998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1946028998
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.166181502
Short name T405
Test name
Test status
Simulation time 16558496270 ps
CPU time 29.74 seconds
Started Jul 16 08:02:39 PM PDT 24
Finished Jul 16 08:03:20 PM PDT 24
Peak memory 237780 kb
Host smart-bdecc4b6-7bdd-4142-9253-8023a6bf8550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166181502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.166181502
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.771108796
Short name T398
Test name
Test status
Simulation time 7319620189 ps
CPU time 11.69 seconds
Started Jul 16 08:02:40 PM PDT 24
Finished Jul 16 08:03:03 PM PDT 24
Peak memory 232796 kb
Host smart-a8994048-89c1-4e9f-99e4-6d6316711e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771108796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.771108796
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.40241821
Short name T474
Test name
Test status
Simulation time 4198610107 ps
CPU time 4.61 seconds
Started Jul 16 08:02:41 PM PDT 24
Finished Jul 16 08:02:57 PM PDT 24
Peak memory 224648 kb
Host smart-d4f0322f-1366-4be6-9ddf-d420bf7a1778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40241821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.40241821
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1482186299
Short name T884
Test name
Test status
Simulation time 538410432 ps
CPU time 5.41 seconds
Started Jul 16 08:02:38 PM PDT 24
Finished Jul 16 08:02:55 PM PDT 24
Peak memory 220492 kb
Host smart-fe5cd4b9-d9c0-4a32-aba8-f4dcc5be4700
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1482186299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1482186299
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2087962535
Short name T30
Test name
Test status
Simulation time 163743554 ps
CPU time 0.92 seconds
Started Jul 16 08:02:41 PM PDT 24
Finished Jul 16 08:02:53 PM PDT 24
Peak memory 205772 kb
Host smart-1af83f74-0379-489b-90e1-b866f5c3b1cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087962535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2087962535
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3844350538
Short name T275
Test name
Test status
Simulation time 5458121468 ps
CPU time 19.28 seconds
Started Jul 16 08:02:41 PM PDT 24
Finished Jul 16 08:03:12 PM PDT 24
Peak memory 216644 kb
Host smart-c045801e-82d4-4f48-8d5d-855d12895159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844350538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3844350538
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.135456474
Short name T691
Test name
Test status
Simulation time 1283289005 ps
CPU time 3 seconds
Started Jul 16 08:02:29 PM PDT 24
Finished Jul 16 08:02:41 PM PDT 24
Peak memory 216208 kb
Host smart-84c08498-8742-4e52-a3f5-c6639ca6a26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135456474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.135456474
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2578477576
Short name T359
Test name
Test status
Simulation time 78994970 ps
CPU time 1.79 seconds
Started Jul 16 08:02:39 PM PDT 24
Finished Jul 16 08:02:53 PM PDT 24
Peak memory 216216 kb
Host smart-d0992add-a7ba-43d2-8628-8d039742d4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578477576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2578477576
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2590155302
Short name T549
Test name
Test status
Simulation time 135861765 ps
CPU time 1 seconds
Started Jul 16 08:02:38 PM PDT 24
Finished Jul 16 08:02:51 PM PDT 24
Peak memory 206460 kb
Host smart-85e2e5b9-8032-4a5c-9e5f-c01bff856ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590155302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2590155302
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.721248469
Short name T479
Test name
Test status
Simulation time 81315292 ps
CPU time 3.05 seconds
Started Jul 16 08:02:40 PM PDT 24
Finished Jul 16 08:02:54 PM PDT 24
Peak memory 232656 kb
Host smart-a268bdb9-84c6-4e83-8b9c-f0c9d1a744eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721248469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.721248469
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2639864878
Short name T51
Test name
Test status
Simulation time 17214392 ps
CPU time 0.74 seconds
Started Jul 16 08:02:40 PM PDT 24
Finished Jul 16 08:02:52 PM PDT 24
Peak memory 205000 kb
Host smart-bd6ce3fd-f13b-4a0e-9376-77d4a6144052
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639864878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2639864878
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1416511378
Short name T155
Test name
Test status
Simulation time 122313168 ps
CPU time 2.66 seconds
Started Jul 16 08:02:37 PM PDT 24
Finished Jul 16 08:02:52 PM PDT 24
Peak memory 232664 kb
Host smart-699a65da-d846-417e-9565-9627c1304332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416511378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1416511378
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3058269595
Short name T290
Test name
Test status
Simulation time 44237572 ps
CPU time 0.82 seconds
Started Jul 16 08:02:39 PM PDT 24
Finished Jul 16 08:02:52 PM PDT 24
Peak memory 206632 kb
Host smart-ba38d462-7ee2-4c7a-aacf-ca8d2647d08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058269595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3058269595
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1947484446
Short name T45
Test name
Test status
Simulation time 164957697180 ps
CPU time 281.1 seconds
Started Jul 16 08:02:40 PM PDT 24
Finished Jul 16 08:07:32 PM PDT 24
Peak memory 254704 kb
Host smart-388c96d9-9eeb-4cf6-9751-fda348ba3b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947484446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1947484446
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1934572705
Short name T856
Test name
Test status
Simulation time 11563657592 ps
CPU time 75.27 seconds
Started Jul 16 08:02:42 PM PDT 24
Finished Jul 16 08:04:08 PM PDT 24
Peak memory 240444 kb
Host smart-83851903-0bb8-4232-9d8b-a9ea4d08faf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934572705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1934572705
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.445627180
Short name T929
Test name
Test status
Simulation time 30031818850 ps
CPU time 46.93 seconds
Started Jul 16 08:02:31 PM PDT 24
Finished Jul 16 08:03:29 PM PDT 24
Peak memory 217404 kb
Host smart-c9837af1-a980-4297-9eec-8a838808492c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445627180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.445627180
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.405505947
Short name T124
Test name
Test status
Simulation time 258192818 ps
CPU time 7.24 seconds
Started Jul 16 08:02:42 PM PDT 24
Finished Jul 16 08:03:00 PM PDT 24
Peak memory 232696 kb
Host smart-718621db-37c3-4570-9762-5541e67a3308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405505947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.405505947
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2874756914
Short name T481
Test name
Test status
Simulation time 2687597634 ps
CPU time 47.52 seconds
Started Jul 16 08:02:32 PM PDT 24
Finished Jul 16 08:03:30 PM PDT 24
Peak memory 249168 kb
Host smart-3ddeb24a-359a-42bb-9f6a-dfb4d3d46ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874756914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2874756914
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1166416453
Short name T1004
Test name
Test status
Simulation time 9963203460 ps
CPU time 10.06 seconds
Started Jul 16 08:02:38 PM PDT 24
Finished Jul 16 08:03:00 PM PDT 24
Peak memory 232772 kb
Host smart-7d65759e-2ef5-4f80-a367-fed22930bfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166416453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1166416453
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1238703152
Short name T780
Test name
Test status
Simulation time 2098757640 ps
CPU time 23.51 seconds
Started Jul 16 08:02:41 PM PDT 24
Finished Jul 16 08:03:16 PM PDT 24
Peak memory 238928 kb
Host smart-4ead3c02-7cd6-4081-a91d-3f08e8ac70ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238703152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1238703152
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.745171804
Short name T506
Test name
Test status
Simulation time 3970670575 ps
CPU time 14.99 seconds
Started Jul 16 08:02:41 PM PDT 24
Finished Jul 16 08:03:07 PM PDT 24
Peak memory 232788 kb
Host smart-40100bb2-fec9-40d4-8c10-6d945ed11b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745171804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.745171804
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.4222746271
Short name T486
Test name
Test status
Simulation time 6425453637 ps
CPU time 18.83 seconds
Started Jul 16 08:02:38 PM PDT 24
Finished Jul 16 08:03:08 PM PDT 24
Peak memory 232816 kb
Host smart-67476bf7-9ed6-47f7-8cbf-7a068bd4b570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222746271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.4222746271
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.4056185038
Short name T485
Test name
Test status
Simulation time 4356511993 ps
CPU time 13.77 seconds
Started Jul 16 08:02:41 PM PDT 24
Finished Jul 16 08:03:06 PM PDT 24
Peak memory 222196 kb
Host smart-9d3a15a4-71c0-4aad-bee2-7f829dec9831
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4056185038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.4056185038
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.841025134
Short name T787
Test name
Test status
Simulation time 185371824 ps
CPU time 0.93 seconds
Started Jul 16 08:02:40 PM PDT 24
Finished Jul 16 08:02:53 PM PDT 24
Peak memory 206616 kb
Host smart-8d261810-edbc-4caf-a0eb-4a43dcc7a986
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841025134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.841025134
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2085902250
Short name T858
Test name
Test status
Simulation time 875877996 ps
CPU time 5.13 seconds
Started Jul 16 08:02:42 PM PDT 24
Finished Jul 16 08:02:58 PM PDT 24
Peak memory 216176 kb
Host smart-7115ffb4-6355-4d67-91a3-1663bc0b8340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085902250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2085902250
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1048438070
Short name T340
Test name
Test status
Simulation time 4203201692 ps
CPU time 14.18 seconds
Started Jul 16 08:02:33 PM PDT 24
Finished Jul 16 08:02:59 PM PDT 24
Peak memory 216276 kb
Host smart-6b8b5302-815f-48c8-b135-b7b0f526d5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048438070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1048438070
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.4073714057
Short name T356
Test name
Test status
Simulation time 1014686254 ps
CPU time 1.91 seconds
Started Jul 16 08:02:38 PM PDT 24
Finished Jul 16 08:02:51 PM PDT 24
Peak memory 216208 kb
Host smart-d5fd87e3-4578-4d04-ae24-f2c3d2e96399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073714057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.4073714057
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1475658222
Short name T371
Test name
Test status
Simulation time 490446070 ps
CPU time 0.82 seconds
Started Jul 16 08:02:39 PM PDT 24
Finished Jul 16 08:02:52 PM PDT 24
Peak memory 206000 kb
Host smart-8dc529b6-fdc7-49b2-a7f5-b62524485127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475658222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1475658222
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.944030396
Short name T212
Test name
Test status
Simulation time 321819211 ps
CPU time 8.05 seconds
Started Jul 16 08:02:40 PM PDT 24
Finished Jul 16 08:03:00 PM PDT 24
Peak memory 232664 kb
Host smart-f68c9dba-d0fd-4195-a319-6f1ca79b6bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944030396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.944030396
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3711717944
Short name T61
Test name
Test status
Simulation time 13004339 ps
CPU time 0.72 seconds
Started Jul 16 08:02:40 PM PDT 24
Finished Jul 16 08:02:52 PM PDT 24
Peak memory 204968 kb
Host smart-53296fd2-6ba1-4f5c-9ee7-fef0bf3a63f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711717944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3711717944
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.106796696
Short name T887
Test name
Test status
Simulation time 491809062 ps
CPU time 6.22 seconds
Started Jul 16 08:02:35 PM PDT 24
Finished Jul 16 08:02:53 PM PDT 24
Peak memory 224416 kb
Host smart-502b8673-0d1a-4b90-94d5-070f54c7af95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106796696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.106796696
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3178966422
Short name T799
Test name
Test status
Simulation time 17719243 ps
CPU time 0.82 seconds
Started Jul 16 08:02:30 PM PDT 24
Finished Jul 16 08:02:41 PM PDT 24
Peak memory 206952 kb
Host smart-68c73ec4-8509-490c-bdb4-f846183c3183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178966422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3178966422
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2206220833
Short name T242
Test name
Test status
Simulation time 9036623908 ps
CPU time 124.8 seconds
Started Jul 16 08:02:35 PM PDT 24
Finished Jul 16 08:04:52 PM PDT 24
Peak memory 262868 kb
Host smart-6a19339e-0183-4479-ac16-6813af3e112e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206220833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2206220833
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2898407552
Short name T254
Test name
Test status
Simulation time 8281327841 ps
CPU time 116.12 seconds
Started Jul 16 08:02:31 PM PDT 24
Finished Jul 16 08:04:38 PM PDT 24
Peak memory 249340 kb
Host smart-fb2dee8b-407a-4a9a-9867-2e0975d38943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898407552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2898407552
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.993297359
Short name T40
Test name
Test status
Simulation time 25274423074 ps
CPU time 217.61 seconds
Started Jul 16 08:02:35 PM PDT 24
Finished Jul 16 08:06:25 PM PDT 24
Peak memory 255780 kb
Host smart-b336e656-50dc-453a-afce-ed19e29cde89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993297359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.993297359
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1257681369
Short name T963
Test name
Test status
Simulation time 489197248 ps
CPU time 11.6 seconds
Started Jul 16 08:02:40 PM PDT 24
Finished Jul 16 08:03:03 PM PDT 24
Peak memory 232544 kb
Host smart-08aba1fe-2f18-432b-8226-e4864fbc97aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257681369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1257681369
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.2243996170
Short name T809
Test name
Test status
Simulation time 5337388595 ps
CPU time 59.3 seconds
Started Jul 16 08:02:40 PM PDT 24
Finished Jul 16 08:03:51 PM PDT 24
Peak memory 249212 kb
Host smart-8ec6a6b9-b688-4365-9a3a-fbc55d792843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243996170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.2243996170
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.4210299271
Short name T531
Test name
Test status
Simulation time 8462185894 ps
CPU time 22.58 seconds
Started Jul 16 08:02:41 PM PDT 24
Finished Jul 16 08:03:15 PM PDT 24
Peak memory 224644 kb
Host smart-55748d68-9eed-4280-b499-7f24b9c0b540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210299271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.4210299271
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3148265525
Short name T382
Test name
Test status
Simulation time 3390989521 ps
CPU time 29.56 seconds
Started Jul 16 08:02:30 PM PDT 24
Finished Jul 16 08:03:10 PM PDT 24
Peak memory 232932 kb
Host smart-6e2da694-dc7f-48a0-8389-0c083ca26b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148265525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3148265525
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2285217005
Short name T941
Test name
Test status
Simulation time 3562946760 ps
CPU time 15.34 seconds
Started Jul 16 08:02:35 PM PDT 24
Finished Jul 16 08:03:03 PM PDT 24
Peak memory 224464 kb
Host smart-d6720687-005e-4ffd-87b4-991abde9e27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285217005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2285217005
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.357453583
Short name T775
Test name
Test status
Simulation time 11604818259 ps
CPU time 12.36 seconds
Started Jul 16 08:02:41 PM PDT 24
Finished Jul 16 08:03:04 PM PDT 24
Peak memory 232852 kb
Host smart-2abf9948-5831-483c-9201-5c2869ac474c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357453583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.357453583
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1976672467
Short name T791
Test name
Test status
Simulation time 794264231 ps
CPU time 8.2 seconds
Started Jul 16 08:02:35 PM PDT 24
Finished Jul 16 08:02:56 PM PDT 24
Peak memory 222012 kb
Host smart-082185a7-f14f-44f9-8494-dba07fafae63
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1976672467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1976672467
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.816278340
Short name T685
Test name
Test status
Simulation time 4197844301 ps
CPU time 23.18 seconds
Started Jul 16 08:02:30 PM PDT 24
Finished Jul 16 08:03:04 PM PDT 24
Peak memory 216472 kb
Host smart-c73e65d7-d1ac-497f-81c1-96c94008ab44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816278340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.816278340
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2659125390
Short name T983
Test name
Test status
Simulation time 5014355587 ps
CPU time 7.31 seconds
Started Jul 16 08:02:42 PM PDT 24
Finished Jul 16 08:03:00 PM PDT 24
Peak memory 216396 kb
Host smart-0f3612ca-7f6c-4bbb-a87c-af27532af85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659125390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2659125390
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1944502684
Short name T12
Test name
Test status
Simulation time 57689208 ps
CPU time 1.65 seconds
Started Jul 16 08:02:41 PM PDT 24
Finished Jul 16 08:02:54 PM PDT 24
Peak memory 216268 kb
Host smart-19678e18-6838-4315-8217-cad036b25a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944502684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1944502684
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2126768234
Short name T387
Test name
Test status
Simulation time 11816480 ps
CPU time 0.71 seconds
Started Jul 16 08:02:31 PM PDT 24
Finished Jul 16 08:02:43 PM PDT 24
Peak memory 206080 kb
Host smart-3889825f-3fe0-4e8d-b0a3-676cde8f39f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126768234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2126768234
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1957951642
Short name T899
Test name
Test status
Simulation time 1082381152 ps
CPU time 8.6 seconds
Started Jul 16 08:02:35 PM PDT 24
Finished Jul 16 08:02:56 PM PDT 24
Peak memory 232596 kb
Host smart-88c9133f-97c5-4ed4-a236-ef58365aecc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957951642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1957951642
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3592499672
Short name T353
Test name
Test status
Simulation time 65864738 ps
CPU time 0.71 seconds
Started Jul 16 08:02:46 PM PDT 24
Finished Jul 16 08:02:56 PM PDT 24
Peak memory 205544 kb
Host smart-412ffbc1-852e-45ce-8ce3-8a907bd4be6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592499672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3592499672
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1388738185
Short name T321
Test name
Test status
Simulation time 118382415 ps
CPU time 2.26 seconds
Started Jul 16 08:02:57 PM PDT 24
Finished Jul 16 08:03:00 PM PDT 24
Peak memory 224408 kb
Host smart-e4ea4b6a-9ef5-440b-aa75-e1080b934ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388738185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1388738185
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1881042723
Short name T11
Test name
Test status
Simulation time 22411608 ps
CPU time 0.88 seconds
Started Jul 16 08:02:40 PM PDT 24
Finished Jul 16 08:02:52 PM PDT 24
Peak memory 206400 kb
Host smart-b95b8ecf-c42c-423b-b22b-923eec5c3b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881042723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1881042723
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2116045034
Short name T758
Test name
Test status
Simulation time 8352388995 ps
CPU time 68.16 seconds
Started Jul 16 08:02:45 PM PDT 24
Finished Jul 16 08:04:03 PM PDT 24
Peak memory 249504 kb
Host smart-451811f6-2627-46fe-b808-57db8bf331b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116045034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2116045034
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2098153724
Short name T425
Test name
Test status
Simulation time 17775437678 ps
CPU time 43.33 seconds
Started Jul 16 08:02:44 PM PDT 24
Finished Jul 16 08:03:37 PM PDT 24
Peak memory 217884 kb
Host smart-91af0d19-95a6-495b-9cea-43e86ccb5213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098153724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2098153724
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3864887081
Short name T24
Test name
Test status
Simulation time 33923565142 ps
CPU time 16.02 seconds
Started Jul 16 08:02:43 PM PDT 24
Finished Jul 16 08:03:10 PM PDT 24
Peak memory 217632 kb
Host smart-c3e2084f-f1d2-4b39-9285-aaf71dbe0608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864887081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3864887081
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1745530313
Short name T396
Test name
Test status
Simulation time 144183531 ps
CPU time 3.27 seconds
Started Jul 16 08:02:43 PM PDT 24
Finished Jul 16 08:02:57 PM PDT 24
Peak memory 234584 kb
Host smart-892e210a-631e-483d-a912-2102f76eb7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745530313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1745530313
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.732023551
Short name T194
Test name
Test status
Simulation time 6646738856 ps
CPU time 50.45 seconds
Started Jul 16 08:02:44 PM PDT 24
Finished Jul 16 08:03:44 PM PDT 24
Peak memory 254392 kb
Host smart-63b92857-6d9c-463b-8594-9d7e15ef71d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732023551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds
.732023551
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.220728720
Short name T375
Test name
Test status
Simulation time 2528095685 ps
CPU time 13.84 seconds
Started Jul 16 08:02:49 PM PDT 24
Finished Jul 16 08:03:10 PM PDT 24
Peak memory 232796 kb
Host smart-c3351c49-39b0-4ae2-9364-6ca6f44a6844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220728720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.220728720
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1755438637
Short name T722
Test name
Test status
Simulation time 2534245483 ps
CPU time 5.53 seconds
Started Jul 16 08:02:46 PM PDT 24
Finished Jul 16 08:03:00 PM PDT 24
Peak memory 232760 kb
Host smart-f50669ea-6aa5-4133-9a1d-6d8b16a0c7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755438637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1755438637
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1874799147
Short name T615
Test name
Test status
Simulation time 4656889451 ps
CPU time 12.77 seconds
Started Jul 16 08:02:46 PM PDT 24
Finished Jul 16 08:03:08 PM PDT 24
Peak memory 224576 kb
Host smart-523b32db-7ada-4d69-9d9a-43fff030258d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874799147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1874799147
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3636261567
Short name T556
Test name
Test status
Simulation time 848603505 ps
CPU time 2.93 seconds
Started Jul 16 08:02:50 PM PDT 24
Finished Jul 16 08:02:59 PM PDT 24
Peak memory 232640 kb
Host smart-eb8be4de-422f-41fe-8c22-2282491004a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636261567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3636261567
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2953969538
Short name T471
Test name
Test status
Simulation time 635099641 ps
CPU time 8.3 seconds
Started Jul 16 08:02:50 PM PDT 24
Finished Jul 16 08:03:04 PM PDT 24
Peak memory 219580 kb
Host smart-f0907116-cc10-4ecf-9500-13e8fdc72bd1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2953969538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2953969538
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1919951539
Short name T4
Test name
Test status
Simulation time 5521060790 ps
CPU time 21.16 seconds
Started Jul 16 08:02:49 PM PDT 24
Finished Jul 16 08:03:17 PM PDT 24
Peak memory 216328 kb
Host smart-ff22df89-c1f8-474c-95f2-d005c8d0dd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919951539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1919951539
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3626816263
Short name T651
Test name
Test status
Simulation time 2434720086 ps
CPU time 7.14 seconds
Started Jul 16 08:02:49 PM PDT 24
Finished Jul 16 08:03:03 PM PDT 24
Peak memory 216276 kb
Host smart-b5343dfa-e6d8-4f99-84ef-5e113e30ba33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626816263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3626816263
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2412319706
Short name T991
Test name
Test status
Simulation time 34699304 ps
CPU time 0.9 seconds
Started Jul 16 08:02:46 PM PDT 24
Finished Jul 16 08:02:56 PM PDT 24
Peak memory 207012 kb
Host smart-6de56c67-3e1d-4c8c-92c4-4755e99f1e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412319706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2412319706
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2255163956
Short name T738
Test name
Test status
Simulation time 50166496 ps
CPU time 0.68 seconds
Started Jul 16 08:02:57 PM PDT 24
Finished Jul 16 08:02:59 PM PDT 24
Peak memory 205980 kb
Host smart-c05b4a56-806d-4fef-91d4-4fcbd89ae0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255163956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2255163956
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.561063305
Short name T208
Test name
Test status
Simulation time 609788331 ps
CPU time 3.66 seconds
Started Jul 16 08:02:57 PM PDT 24
Finished Jul 16 08:03:01 PM PDT 24
Peak memory 224488 kb
Host smart-5d9adebc-8b74-411d-ad63-ffc748df2c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561063305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.561063305
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2789284258
Short name T333
Test name
Test status
Simulation time 46952974 ps
CPU time 0.74 seconds
Started Jul 16 08:03:00 PM PDT 24
Finished Jul 16 08:03:03 PM PDT 24
Peak memory 205460 kb
Host smart-57dd7a14-ae72-49da-8efc-9b1b66c328fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789284258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2789284258
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1253308965
Short name T952
Test name
Test status
Simulation time 934074098 ps
CPU time 4.11 seconds
Started Jul 16 08:02:45 PM PDT 24
Finished Jul 16 08:02:59 PM PDT 24
Peak memory 224480 kb
Host smart-acd29c9f-40e8-4d6d-8cd1-2a33e558e8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253308965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1253308965
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1094280340
Short name T294
Test name
Test status
Simulation time 33520710 ps
CPU time 0.76 seconds
Started Jul 16 08:02:57 PM PDT 24
Finished Jul 16 08:02:58 PM PDT 24
Peak memory 206576 kb
Host smart-96a9d143-2eca-4b36-93fd-22b4c3b379a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094280340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1094280340
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.734613684
Short name T959
Test name
Test status
Simulation time 6236805606 ps
CPU time 79.99 seconds
Started Jul 16 08:02:57 PM PDT 24
Finished Jul 16 08:04:18 PM PDT 24
Peak memory 249192 kb
Host smart-0ba460bb-c225-4d85-94e7-64ef61abe25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734613684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.734613684
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2728381160
Short name T173
Test name
Test status
Simulation time 89366992067 ps
CPU time 195.23 seconds
Started Jul 16 08:02:59 PM PDT 24
Finished Jul 16 08:06:15 PM PDT 24
Peak memory 241012 kb
Host smart-9b5a4c28-20e8-4b1f-804e-c100c7b856a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728381160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2728381160
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.360500688
Short name T922
Test name
Test status
Simulation time 269976408372 ps
CPU time 455.84 seconds
Started Jul 16 08:02:59 PM PDT 24
Finished Jul 16 08:10:35 PM PDT 24
Peak memory 255360 kb
Host smart-e1e132ad-8fa8-4cb2-8045-01ffc8b93ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360500688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.360500688
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2241584100
Short name T857
Test name
Test status
Simulation time 1541830213 ps
CPU time 23.69 seconds
Started Jul 16 08:02:48 PM PDT 24
Finished Jul 16 08:03:19 PM PDT 24
Peak memory 236816 kb
Host smart-a01aa3e5-be45-4b3f-b3e3-27bd09877bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241584100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2241584100
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.988025705
Short name T866
Test name
Test status
Simulation time 43038953571 ps
CPU time 112.81 seconds
Started Jul 16 08:02:47 PM PDT 24
Finished Jul 16 08:04:48 PM PDT 24
Peak memory 249176 kb
Host smart-4b188137-526a-4032-b9bc-ac34f2e873b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988025705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds
.988025705
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.450224124
Short name T454
Test name
Test status
Simulation time 1488168161 ps
CPU time 14.63 seconds
Started Jul 16 08:02:46 PM PDT 24
Finished Jul 16 08:03:09 PM PDT 24
Peak memory 224420 kb
Host smart-776daf9d-b905-4334-a316-40fec7d1b695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450224124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.450224124
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3992872488
Short name T656
Test name
Test status
Simulation time 2228790128 ps
CPU time 18.96 seconds
Started Jul 16 08:02:45 PM PDT 24
Finished Jul 16 08:03:13 PM PDT 24
Peak memory 232720 kb
Host smart-bd167cfa-f63c-4d7e-9e1c-806c4d78e4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992872488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3992872488
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1759529272
Short name T604
Test name
Test status
Simulation time 4758180331 ps
CPU time 6.52 seconds
Started Jul 16 08:02:46 PM PDT 24
Finished Jul 16 08:03:02 PM PDT 24
Peak memory 227672 kb
Host smart-a6b04b47-f506-44c5-9f10-dae13cb2e180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759529272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1759529272
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1440531707
Short name T982
Test name
Test status
Simulation time 3784630747 ps
CPU time 12.71 seconds
Started Jul 16 08:02:43 PM PDT 24
Finished Jul 16 08:03:07 PM PDT 24
Peak memory 232732 kb
Host smart-014694f8-b1ff-447c-8110-8156e461b3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440531707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1440531707
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2063798230
Short name T523
Test name
Test status
Simulation time 1101259321 ps
CPU time 5.62 seconds
Started Jul 16 08:02:45 PM PDT 24
Finished Jul 16 08:03:00 PM PDT 24
Peak memory 219100 kb
Host smart-fe9e3a06-5a02-45cf-805a-c8357fa75fce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2063798230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2063798230
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.4100498621
Short name T252
Test name
Test status
Simulation time 50784070330 ps
CPU time 511.46 seconds
Started Jul 16 08:03:02 PM PDT 24
Finished Jul 16 08:11:35 PM PDT 24
Peak memory 254332 kb
Host smart-ace28204-ed00-400f-88f9-b214943d88c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100498621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.4100498621
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3825044613
Short name T726
Test name
Test status
Simulation time 339310651 ps
CPU time 2.95 seconds
Started Jul 16 08:02:52 PM PDT 24
Finished Jul 16 08:02:59 PM PDT 24
Peak memory 216316 kb
Host smart-9ce86a59-e93b-45c8-8ea3-623c7516e7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825044613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3825044613
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.513239448
Short name T348
Test name
Test status
Simulation time 85705833959 ps
CPU time 21.9 seconds
Started Jul 16 08:02:45 PM PDT 24
Finished Jul 16 08:03:16 PM PDT 24
Peak memory 218120 kb
Host smart-f1c13644-44c4-498e-95df-482661f348ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513239448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.513239448
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1531842326
Short name T23
Test name
Test status
Simulation time 92563707 ps
CPU time 3.31 seconds
Started Jul 16 08:02:45 PM PDT 24
Finished Jul 16 08:02:58 PM PDT 24
Peak memory 216204 kb
Host smart-3f038ac2-a8dd-4b1e-ab54-747abe3cc822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531842326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1531842326
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2530300895
Short name T295
Test name
Test status
Simulation time 32089006 ps
CPU time 0.85 seconds
Started Jul 16 08:02:45 PM PDT 24
Finished Jul 16 08:02:55 PM PDT 24
Peak memory 206004 kb
Host smart-637d2085-73f8-42a7-8676-d97d227822a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530300895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2530300895
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.707254175
Short name T206
Test name
Test status
Simulation time 26752445196 ps
CPU time 44.48 seconds
Started Jul 16 08:02:46 PM PDT 24
Finished Jul 16 08:03:39 PM PDT 24
Peak memory 239528 kb
Host smart-c8c31dbe-645a-4617-995c-21f1c54ff10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707254175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.707254175
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1576741822
Short name T579
Test name
Test status
Simulation time 11746419 ps
CPU time 0.71 seconds
Started Jul 16 07:59:48 PM PDT 24
Finished Jul 16 07:59:52 PM PDT 24
Peak memory 204956 kb
Host smart-79b20df8-011d-4bde-ac66-beee9f527fd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576741822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
576741822
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3357045801
Short name T518
Test name
Test status
Simulation time 87094136 ps
CPU time 2.5 seconds
Started Jul 16 07:59:42 PM PDT 24
Finished Jul 16 07:59:45 PM PDT 24
Peak memory 224436 kb
Host smart-6cdb4d9c-1b71-402d-b1c5-a309ba9f9aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357045801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3357045801
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1734558261
Short name T839
Test name
Test status
Simulation time 69265948 ps
CPU time 0.77 seconds
Started Jul 16 07:59:49 PM PDT 24
Finished Jul 16 07:59:53 PM PDT 24
Peak memory 206624 kb
Host smart-c5c9b236-6c14-4878-ac57-e6a5dfe5af79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734558261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1734558261
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.233075743
Short name T138
Test name
Test status
Simulation time 8372599465 ps
CPU time 42.53 seconds
Started Jul 16 07:59:45 PM PDT 24
Finished Jul 16 08:00:29 PM PDT 24
Peak memory 217808 kb
Host smart-095685ac-38c6-4b51-9680-654e8010b46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233075743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.233075743
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3815423535
Short name T195
Test name
Test status
Simulation time 148041977348 ps
CPU time 497.55 seconds
Started Jul 16 07:59:44 PM PDT 24
Finished Jul 16 08:08:02 PM PDT 24
Peak memory 270872 kb
Host smart-d2decbfd-0c15-4d6a-8066-b391756a1593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815423535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3815423535
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.971511000
Short name T343
Test name
Test status
Simulation time 767734019 ps
CPU time 5.19 seconds
Started Jul 16 07:59:48 PM PDT 24
Finished Jul 16 07:59:56 PM PDT 24
Peak memory 240872 kb
Host smart-113bb637-fbda-49e9-abf5-090671682a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971511000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.971511000
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2811830431
Short name T728
Test name
Test status
Simulation time 263053418 ps
CPU time 5.61 seconds
Started Jul 16 07:59:44 PM PDT 24
Finished Jul 16 07:59:52 PM PDT 24
Peak memory 224340 kb
Host smart-5cb0161d-746d-4ab9-82de-4cedd256f6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811830431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2811830431
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1836461850
Short name T590
Test name
Test status
Simulation time 10742374298 ps
CPU time 53.01 seconds
Started Jul 16 07:59:50 PM PDT 24
Finished Jul 16 08:00:45 PM PDT 24
Peak memory 238120 kb
Host smart-73fc134e-47d1-42d2-8a32-881d6bba32b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836461850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1836461850
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2259353402
Short name T243
Test name
Test status
Simulation time 4238215630 ps
CPU time 9.67 seconds
Started Jul 16 07:59:44 PM PDT 24
Finished Jul 16 07:59:56 PM PDT 24
Peak memory 238604 kb
Host smart-3637e8a0-da75-48bf-ba27-ec91e109b23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259353402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2259353402
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.416755373
Short name T992
Test name
Test status
Simulation time 119576910 ps
CPU time 3.56 seconds
Started Jul 16 07:59:43 PM PDT 24
Finished Jul 16 07:59:47 PM PDT 24
Peak memory 224528 kb
Host smart-1afadbbe-fccf-47f8-86e3-10cebc7257e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416755373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.416755373
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3615771605
Short name T919
Test name
Test status
Simulation time 901087744 ps
CPU time 9.94 seconds
Started Jul 16 07:59:47 PM PDT 24
Finished Jul 16 08:00:00 PM PDT 24
Peak memory 222044 kb
Host smart-5291b070-1691-44c1-a701-1c027f05360c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3615771605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3615771605
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.4228563836
Short name T765
Test name
Test status
Simulation time 95871850557 ps
CPU time 446.82 seconds
Started Jul 16 07:59:44 PM PDT 24
Finished Jul 16 08:07:13 PM PDT 24
Peak memory 268564 kb
Host smart-4076cfda-5fee-4cc1-ba64-68a243bd788a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228563836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.4228563836
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.359307744
Short name T284
Test name
Test status
Simulation time 10293937465 ps
CPU time 16.51 seconds
Started Jul 16 07:59:44 PM PDT 24
Finished Jul 16 08:00:02 PM PDT 24
Peak memory 216396 kb
Host smart-0c12b571-ba4a-4900-a366-6fc47c806fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359307744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.359307744
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2250439350
Short name T441
Test name
Test status
Simulation time 2782683366 ps
CPU time 6.81 seconds
Started Jul 16 07:59:45 PM PDT 24
Finished Jul 16 07:59:54 PM PDT 24
Peak memory 216348 kb
Host smart-9dbcbad0-e48d-430f-afcb-8ded4b8cd8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250439350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2250439350
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3945469544
Short name T367
Test name
Test status
Simulation time 225923686 ps
CPU time 1.13 seconds
Started Jul 16 07:59:46 PM PDT 24
Finished Jul 16 07:59:49 PM PDT 24
Peak memory 207964 kb
Host smart-bffddd00-8938-4f4f-8843-48b4791c0590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945469544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3945469544
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2679417824
Short name T886
Test name
Test status
Simulation time 44177136 ps
CPU time 0.83 seconds
Started Jul 16 07:59:48 PM PDT 24
Finished Jul 16 07:59:52 PM PDT 24
Peak memory 205976 kb
Host smart-83ae42bf-8a0b-46bf-8a01-a1d37310612b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679417824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2679417824
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1044414412
Short name T931
Test name
Test status
Simulation time 651864761 ps
CPU time 5.01 seconds
Started Jul 16 07:59:49 PM PDT 24
Finished Jul 16 07:59:57 PM PDT 24
Peak memory 224468 kb
Host smart-46e461d2-9da9-40f1-af09-65f0a7d807fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044414412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1044414412
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1962998886
Short name T60
Test name
Test status
Simulation time 13901193 ps
CPU time 0.81 seconds
Started Jul 16 07:59:44 PM PDT 24
Finished Jul 16 07:59:47 PM PDT 24
Peak memory 205872 kb
Host smart-726151eb-9a5f-4f22-8209-e98ac11394ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962998886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
962998886
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2926537810
Short name T156
Test name
Test status
Simulation time 452996229 ps
CPU time 2.23 seconds
Started Jul 16 07:59:44 PM PDT 24
Finished Jul 16 07:59:49 PM PDT 24
Peak memory 224448 kb
Host smart-06bd82d7-eb90-4152-a319-65f97dab4f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926537810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2926537810
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.36149461
Short name T790
Test name
Test status
Simulation time 19284767 ps
CPU time 0.8 seconds
Started Jul 16 07:59:48 PM PDT 24
Finished Jul 16 07:59:51 PM PDT 24
Peak memory 206932 kb
Host smart-b9d8bf85-61b9-41fa-a697-ea820ad402a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36149461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.36149461
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.4130203414
Short name T942
Test name
Test status
Simulation time 21399584185 ps
CPU time 171.61 seconds
Started Jul 16 07:59:46 PM PDT 24
Finished Jul 16 08:02:40 PM PDT 24
Peak memory 250480 kb
Host smart-aeb1456b-50ec-495d-a8a8-1f94311038d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130203414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.4130203414
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.472419071
Short name T516
Test name
Test status
Simulation time 2366995317 ps
CPU time 26.42 seconds
Started Jul 16 07:59:44 PM PDT 24
Finished Jul 16 08:00:12 PM PDT 24
Peak memory 224628 kb
Host smart-31a2fe89-dd32-4462-a555-d2805b64a2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472419071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
472419071
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1134957895
Short name T716
Test name
Test status
Simulation time 4636544499 ps
CPU time 19.04 seconds
Started Jul 16 07:59:47 PM PDT 24
Finished Jul 16 08:00:09 PM PDT 24
Peak memory 224608 kb
Host smart-2ee304b7-c8cd-4073-9cd1-117d05e6582c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134957895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1134957895
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.2838702946
Short name T168
Test name
Test status
Simulation time 12857891433 ps
CPU time 168.45 seconds
Started Jul 16 07:59:46 PM PDT 24
Finished Jul 16 08:02:37 PM PDT 24
Peak memory 262688 kb
Host smart-88e7f119-f417-482c-a24c-d2b938ecbe6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838702946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.2838702946
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3993859167
Short name T465
Test name
Test status
Simulation time 7456907860 ps
CPU time 8.45 seconds
Started Jul 16 07:59:46 PM PDT 24
Finished Jul 16 07:59:57 PM PDT 24
Peak memory 224528 kb
Host smart-1cb59617-1313-4682-b9ba-955d465975da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993859167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3993859167
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3871201993
Short name T743
Test name
Test status
Simulation time 140582885 ps
CPU time 2.53 seconds
Started Jul 16 07:59:46 PM PDT 24
Finished Jul 16 07:59:51 PM PDT 24
Peak memory 232304 kb
Host smart-349e8ed5-0ddb-40dd-b3ae-f4f9f2d6c516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871201993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3871201993
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1112757684
Short name T400
Test name
Test status
Simulation time 92221231 ps
CPU time 2.21 seconds
Started Jul 16 07:59:49 PM PDT 24
Finished Jul 16 07:59:54 PM PDT 24
Peak memory 224100 kb
Host smart-5b77e7e4-be94-4ae6-aaca-4003c91e9480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112757684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1112757684
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.639276177
Short name T638
Test name
Test status
Simulation time 375756032 ps
CPU time 3.24 seconds
Started Jul 16 07:59:45 PM PDT 24
Finished Jul 16 07:59:50 PM PDT 24
Peak memory 232640 kb
Host smart-ccb27a4c-cd4d-4661-8d53-78c9c2c0db76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639276177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.639276177
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.260722080
Short name T877
Test name
Test status
Simulation time 368365992 ps
CPU time 6.61 seconds
Started Jul 16 07:59:44 PM PDT 24
Finished Jul 16 07:59:53 PM PDT 24
Peak memory 219308 kb
Host smart-fd39bb55-7148-45c9-9ef0-66127a1f7985
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=260722080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.260722080
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2182607395
Short name T470
Test name
Test status
Simulation time 8306658579 ps
CPU time 96.09 seconds
Started Jul 16 07:59:43 PM PDT 24
Finished Jul 16 08:01:20 PM PDT 24
Peak memory 265596 kb
Host smart-33c6ce58-8324-444a-bf70-c9398fc6f744
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182607395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2182607395
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2393011150
Short name T938
Test name
Test status
Simulation time 283356886 ps
CPU time 0.72 seconds
Started Jul 16 07:59:40 PM PDT 24
Finished Jul 16 07:59:42 PM PDT 24
Peak memory 205756 kb
Host smart-2ab0b052-f11b-4166-aab1-4d5d96bd8bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393011150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2393011150
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2772706406
Short name T300
Test name
Test status
Simulation time 37585059 ps
CPU time 0.74 seconds
Started Jul 16 07:59:48 PM PDT 24
Finished Jul 16 07:59:52 PM PDT 24
Peak memory 205880 kb
Host smart-a206b562-8ce0-4583-92e3-5411b98ade16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772706406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2772706406
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3854736983
Short name T9
Test name
Test status
Simulation time 262578921 ps
CPU time 1.91 seconds
Started Jul 16 07:59:48 PM PDT 24
Finished Jul 16 07:59:53 PM PDT 24
Peak memory 216312 kb
Host smart-8a61ccad-e88e-4281-b5d0-cc17ec912a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854736983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3854736983
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.64094481
Short name T530
Test name
Test status
Simulation time 66986643 ps
CPU time 0.87 seconds
Started Jul 16 07:59:42 PM PDT 24
Finished Jul 16 07:59:43 PM PDT 24
Peak memory 205936 kb
Host smart-6e91971f-c742-4888-81cf-07c70f1e2e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64094481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.64094481
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2980284644
Short name T577
Test name
Test status
Simulation time 574122218 ps
CPU time 4.79 seconds
Started Jul 16 07:59:47 PM PDT 24
Finished Jul 16 07:59:54 PM PDT 24
Peak memory 232696 kb
Host smart-636a7f1d-aca0-4dee-8d7f-d573702f80fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980284644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2980284644
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.63661818
Short name T744
Test name
Test status
Simulation time 59027053 ps
CPU time 0.73 seconds
Started Jul 16 07:59:58 PM PDT 24
Finished Jul 16 08:00:00 PM PDT 24
Peak memory 204948 kb
Host smart-7dc0b280-4974-4131-83cb-f9164993d630
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63661818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.63661818
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2738707918
Short name T990
Test name
Test status
Simulation time 774144602 ps
CPU time 8.94 seconds
Started Jul 16 07:59:59 PM PDT 24
Finished Jul 16 08:00:11 PM PDT 24
Peak memory 224428 kb
Host smart-244774f0-7f4f-4a7a-9efe-c5bbc170290b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738707918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2738707918
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1783914205
Short name T297
Test name
Test status
Simulation time 141243800 ps
CPU time 0.81 seconds
Started Jul 16 07:59:42 PM PDT 24
Finished Jul 16 07:59:44 PM PDT 24
Peak memory 206916 kb
Host smart-05f4b283-6c30-4264-97e6-d272bffcf310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783914205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1783914205
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1860930321
Short name T198
Test name
Test status
Simulation time 10899893100 ps
CPU time 77.56 seconds
Started Jul 16 07:59:56 PM PDT 24
Finished Jul 16 08:01:15 PM PDT 24
Peak memory 249176 kb
Host smart-6cce39ef-b9b9-49dd-bc59-a4b5a7b81df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860930321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1860930321
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.168594901
Short name T567
Test name
Test status
Simulation time 4461104151 ps
CPU time 109.75 seconds
Started Jul 16 07:59:57 PM PDT 24
Finished Jul 16 08:01:49 PM PDT 24
Peak memory 263372 kb
Host smart-49ff5887-868a-4ec3-93d8-b5d98bed56f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168594901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.168594901
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1850680537
Short name T408
Test name
Test status
Simulation time 25085176225 ps
CPU time 165.91 seconds
Started Jul 16 08:00:01 PM PDT 24
Finished Jul 16 08:02:52 PM PDT 24
Peak memory 251312 kb
Host smart-6217027a-6170-4986-8ba7-b218ffb50647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850680537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1850680537
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2985343967
Short name T755
Test name
Test status
Simulation time 417452938 ps
CPU time 5.04 seconds
Started Jul 16 08:00:02 PM PDT 24
Finished Jul 16 08:00:12 PM PDT 24
Peak memory 224524 kb
Host smart-9a63a997-99f2-4772-a7f9-01b66aa52b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985343967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2985343967
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.2685153036
Short name T782
Test name
Test status
Simulation time 6686083363 ps
CPU time 68.74 seconds
Started Jul 16 07:59:57 PM PDT 24
Finished Jul 16 08:01:08 PM PDT 24
Peak memory 250320 kb
Host smart-28c39593-095d-4f93-a50c-be718cab5293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685153036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.2685153036
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2490496047
Short name T596
Test name
Test status
Simulation time 416062388 ps
CPU time 5.19 seconds
Started Jul 16 07:59:56 PM PDT 24
Finished Jul 16 08:00:02 PM PDT 24
Peak memory 224484 kb
Host smart-a80a78f9-0c56-4693-900e-be1650aedacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490496047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2490496047
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2251520217
Short name T760
Test name
Test status
Simulation time 1876405708 ps
CPU time 13.07 seconds
Started Jul 16 07:59:59 PM PDT 24
Finished Jul 16 08:00:14 PM PDT 24
Peak memory 224592 kb
Host smart-5b12043c-147d-4810-af75-577d6000cd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251520217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2251520217
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2512900530
Short name T500
Test name
Test status
Simulation time 4192262258 ps
CPU time 8.72 seconds
Started Jul 16 08:00:01 PM PDT 24
Finished Jul 16 08:00:14 PM PDT 24
Peak memory 224544 kb
Host smart-83c5e1e5-9b9f-4444-9f14-083b99231cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512900530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2512900530
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2094065782
Short name T501
Test name
Test status
Simulation time 459741696 ps
CPU time 5.04 seconds
Started Jul 16 07:59:57 PM PDT 24
Finished Jul 16 08:00:05 PM PDT 24
Peak memory 232708 kb
Host smart-77076789-771c-4171-b951-a5e4ebac11ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094065782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2094065782
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.156006852
Short name T968
Test name
Test status
Simulation time 1354287207 ps
CPU time 8.33 seconds
Started Jul 16 07:59:57 PM PDT 24
Finished Jul 16 08:00:08 PM PDT 24
Peak memory 222600 kb
Host smart-d6c3fb2d-d4f4-4311-9f74-d9083ee888f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=156006852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.156006852
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.535743818
Short name T956
Test name
Test status
Simulation time 294549512229 ps
CPU time 521.89 seconds
Started Jul 16 08:00:00 PM PDT 24
Finished Jul 16 08:08:45 PM PDT 24
Peak memory 267020 kb
Host smart-6942f2cc-ca3c-4b58-a445-df80d99e5abd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535743818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.535743818
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2210108813
Short name T802
Test name
Test status
Simulation time 26376987724 ps
CPU time 38.18 seconds
Started Jul 16 08:00:00 PM PDT 24
Finished Jul 16 08:00:42 PM PDT 24
Peak memory 216352 kb
Host smart-4c2b4808-4806-4658-bc5c-76e52a988128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210108813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2210108813
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3863567066
Short name T555
Test name
Test status
Simulation time 2713871393 ps
CPU time 12.35 seconds
Started Jul 16 07:59:58 PM PDT 24
Finished Jul 16 08:00:13 PM PDT 24
Peak memory 216328 kb
Host smart-6c2ac3f5-97dc-47dd-ba5c-a873e31cf297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863567066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3863567066
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1859596707
Short name T315
Test name
Test status
Simulation time 32095737 ps
CPU time 1.15 seconds
Started Jul 16 08:00:00 PM PDT 24
Finished Jul 16 08:00:04 PM PDT 24
Peak memory 216136 kb
Host smart-f1158aab-37ef-4606-84dc-d69e9efe64bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859596707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1859596707
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1441969942
Short name T568
Test name
Test status
Simulation time 20150675 ps
CPU time 0.77 seconds
Started Jul 16 07:59:57 PM PDT 24
Finished Jul 16 07:59:59 PM PDT 24
Peak memory 205964 kb
Host smart-27bfc287-4a8f-47b6-ae74-1f64315d5ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441969942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1441969942
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2804986709
Short name T453
Test name
Test status
Simulation time 1175807931 ps
CPU time 9.32 seconds
Started Jul 16 07:59:59 PM PDT 24
Finished Jul 16 08:00:12 PM PDT 24
Peak memory 232660 kb
Host smart-a1fd6e57-7ac0-4062-a1da-6018e6aa341f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804986709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2804986709
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3248306940
Short name T571
Test name
Test status
Simulation time 20953506 ps
CPU time 0.75 seconds
Started Jul 16 08:00:02 PM PDT 24
Finished Jul 16 08:00:07 PM PDT 24
Peak memory 205548 kb
Host smart-71c76919-abbb-4f6f-8649-3f7f294cddbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248306940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
248306940
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3818957552
Short name T847
Test name
Test status
Simulation time 64665005 ps
CPU time 2.94 seconds
Started Jul 16 08:00:02 PM PDT 24
Finished Jul 16 08:00:10 PM PDT 24
Peak memory 232628 kb
Host smart-3056ff4d-242a-46d2-8cc5-19d970622400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818957552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3818957552
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.4109950135
Short name T2
Test name
Test status
Simulation time 82415677 ps
CPU time 0.84 seconds
Started Jul 16 07:59:59 PM PDT 24
Finished Jul 16 08:00:03 PM PDT 24
Peak memory 205572 kb
Host smart-cc3df47c-000d-4eec-be53-e1d2dcc22f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109950135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.4109950135
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2087571539
Short name T737
Test name
Test status
Simulation time 17334970 ps
CPU time 0.78 seconds
Started Jul 16 08:00:00 PM PDT 24
Finished Jul 16 08:00:05 PM PDT 24
Peak memory 215800 kb
Host smart-1a1130ed-4094-44e0-978f-fdd348fbc7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087571539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2087571539
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3098108432
Short name T788
Test name
Test status
Simulation time 117898749246 ps
CPU time 98.97 seconds
Started Jul 16 07:59:59 PM PDT 24
Finished Jul 16 08:01:42 PM PDT 24
Peak memory 241092 kb
Host smart-90f431cb-8fde-41ed-b4cc-79c357be278f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098108432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3098108432
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1941966140
Short name T740
Test name
Test status
Simulation time 167766163 ps
CPU time 3.84 seconds
Started Jul 16 08:00:00 PM PDT 24
Finished Jul 16 08:00:08 PM PDT 24
Peak memory 232712 kb
Host smart-91f6cd2e-ed90-45d3-a26f-ba76491eb308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941966140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1941966140
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.1670816736
Short name T876
Test name
Test status
Simulation time 6498715063 ps
CPU time 52.31 seconds
Started Jul 16 07:59:59 PM PDT 24
Finished Jul 16 08:00:54 PM PDT 24
Peak memory 250708 kb
Host smart-4dc11d99-eb82-4c81-8a52-5d48e580247b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670816736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.1670816736
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1374068470
Short name T459
Test name
Test status
Simulation time 3852686127 ps
CPU time 11.68 seconds
Started Jul 16 07:59:59 PM PDT 24
Finished Jul 16 08:00:14 PM PDT 24
Peak memory 232768 kb
Host smart-7ee87194-8990-49a6-83a5-f654dbf9906e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374068470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1374068470
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3925365352
Short name T835
Test name
Test status
Simulation time 2742575154 ps
CPU time 27.78 seconds
Started Jul 16 07:59:59 PM PDT 24
Finished Jul 16 08:00:29 PM PDT 24
Peak memory 232776 kb
Host smart-99eda3b2-2ad4-4cc0-aefc-b8afe619fb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925365352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3925365352
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1946901645
Short name T926
Test name
Test status
Simulation time 1982418711 ps
CPU time 3.88 seconds
Started Jul 16 08:00:03 PM PDT 24
Finished Jul 16 08:00:12 PM PDT 24
Peak memory 224252 kb
Host smart-4b57c633-a342-4fda-996c-a37e9eed2cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946901645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1946901645
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.490480281
Short name T664
Test name
Test status
Simulation time 1336583371 ps
CPU time 5.84 seconds
Started Jul 16 07:59:58 PM PDT 24
Finished Jul 16 08:00:06 PM PDT 24
Peak memory 240584 kb
Host smart-e06241ae-96be-40d7-b42a-11fc51f7325c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490480281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.490480281
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2191131930
Short name T466
Test name
Test status
Simulation time 10426833204 ps
CPU time 7.07 seconds
Started Jul 16 07:59:59 PM PDT 24
Finished Jul 16 08:00:09 PM PDT 24
Peak memory 219828 kb
Host smart-87df486f-bbd4-4c5f-91ad-57cc2b6aff4c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2191131930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2191131930
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.981045310
Short name T283
Test name
Test status
Simulation time 4250488215 ps
CPU time 46.69 seconds
Started Jul 16 08:00:02 PM PDT 24
Finished Jul 16 08:00:53 PM PDT 24
Peak memory 235552 kb
Host smart-98bd77e7-68b7-492d-863a-1d3ab52741cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981045310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.981045310
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.91784961
Short name T669
Test name
Test status
Simulation time 4231486230 ps
CPU time 21.77 seconds
Started Jul 16 07:59:56 PM PDT 24
Finished Jul 16 08:00:19 PM PDT 24
Peak memory 220380 kb
Host smart-eebcf86b-09b2-4a9e-a7d0-0d4b5a083f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91784961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.91784961
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.658427470
Short name T54
Test name
Test status
Simulation time 43376120 ps
CPU time 0.74 seconds
Started Jul 16 08:00:03 PM PDT 24
Finished Jul 16 08:00:09 PM PDT 24
Peak memory 205480 kb
Host smart-69377650-1802-4b70-acb8-918f47332b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658427470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.658427470
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3344150911
Short name T319
Test name
Test status
Simulation time 259538500 ps
CPU time 1.45 seconds
Started Jul 16 08:00:03 PM PDT 24
Finished Jul 16 08:00:09 PM PDT 24
Peak memory 208044 kb
Host smart-cb02ebb1-2321-45f4-94a2-df3a6617416c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344150911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3344150911
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1279170678
Short name T381
Test name
Test status
Simulation time 293381341 ps
CPU time 0.95 seconds
Started Jul 16 07:59:57 PM PDT 24
Finished Jul 16 07:59:59 PM PDT 24
Peak memory 205972 kb
Host smart-2ad932e1-3e78-4d16-880a-2f5b04a60cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279170678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1279170678
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2393070301
Short name T606
Test name
Test status
Simulation time 235543291 ps
CPU time 2.49 seconds
Started Jul 16 07:59:56 PM PDT 24
Finished Jul 16 08:00:00 PM PDT 24
Peak memory 224520 kb
Host smart-db4c52af-414b-432c-8ebe-3f6a49bb5e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393070301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2393070301
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.841064768
Short name T771
Test name
Test status
Simulation time 31335643 ps
CPU time 0.71 seconds
Started Jul 16 08:00:01 PM PDT 24
Finished Jul 16 08:00:06 PM PDT 24
Peak memory 205448 kb
Host smart-24b9fa96-3265-4df7-a80f-c20b8359ab40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841064768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.841064768
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2246265629
Short name T228
Test name
Test status
Simulation time 186003289 ps
CPU time 3.67 seconds
Started Jul 16 08:00:02 PM PDT 24
Finished Jul 16 08:00:11 PM PDT 24
Peak memory 224488 kb
Host smart-ca1e78e7-3c51-406c-8b78-6f2e30dbbddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246265629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2246265629
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3735106522
Short name T994
Test name
Test status
Simulation time 12554203 ps
CPU time 0.75 seconds
Started Jul 16 07:59:57 PM PDT 24
Finished Jul 16 07:59:59 PM PDT 24
Peak memory 205684 kb
Host smart-aa599158-a5eb-4ed1-af1c-d42e4db3ad7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735106522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3735106522
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1294903640
Short name T818
Test name
Test status
Simulation time 32929167046 ps
CPU time 58.18 seconds
Started Jul 16 08:00:02 PM PDT 24
Finished Jul 16 08:01:05 PM PDT 24
Peak memory 239712 kb
Host smart-d36e9ada-b446-49b1-9c6c-27a68ae7e36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294903640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1294903640
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3357454298
Short name T200
Test name
Test status
Simulation time 41450715353 ps
CPU time 105.96 seconds
Started Jul 16 08:00:01 PM PDT 24
Finished Jul 16 08:01:52 PM PDT 24
Peak memory 236832 kb
Host smart-8c7f8004-136a-4c50-8505-100057f59a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357454298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3357454298
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2262764698
Short name T197
Test name
Test status
Simulation time 43693857168 ps
CPU time 205.32 seconds
Started Jul 16 08:00:02 PM PDT 24
Finished Jul 16 08:03:32 PM PDT 24
Peak memory 251408 kb
Host smart-d78f212a-5767-4163-9260-13fb0f808e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262764698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2262764698
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.643554423
Short name T369
Test name
Test status
Simulation time 95902300 ps
CPU time 2.93 seconds
Started Jul 16 08:00:01 PM PDT 24
Finished Jul 16 08:00:08 PM PDT 24
Peak memory 232680 kb
Host smart-adf5dfe0-7ed7-45c5-80a7-b8d7c239cf94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643554423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.643554423
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.3531126685
Short name T244
Test name
Test status
Simulation time 9621262145 ps
CPU time 68.27 seconds
Started Jul 16 08:00:01 PM PDT 24
Finished Jul 16 08:01:14 PM PDT 24
Peak memory 257392 kb
Host smart-b18b326f-ab2c-48b0-9139-443e0d3f3731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531126685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.3531126685
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1218991188
Short name T528
Test name
Test status
Simulation time 652996880 ps
CPU time 4.12 seconds
Started Jul 16 07:59:59 PM PDT 24
Finished Jul 16 08:00:06 PM PDT 24
Peak memory 224432 kb
Host smart-c515af29-7976-49d2-ab1b-b5fb59080a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218991188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1218991188
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.253295933
Short name T618
Test name
Test status
Simulation time 7804930832 ps
CPU time 35.25 seconds
Started Jul 16 08:00:01 PM PDT 24
Finished Jul 16 08:00:41 PM PDT 24
Peak memory 232848 kb
Host smart-aee62390-33d3-4e68-9f2b-17b461688a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253295933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.253295933
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.4200012696
Short name T689
Test name
Test status
Simulation time 515340882 ps
CPU time 3.54 seconds
Started Jul 16 07:59:57 PM PDT 24
Finished Jul 16 08:00:03 PM PDT 24
Peak memory 232696 kb
Host smart-f4e4458b-5fe5-481c-b13a-7197b6391d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200012696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.4200012696
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.181770925
Short name T575
Test name
Test status
Simulation time 478306543 ps
CPU time 7.48 seconds
Started Jul 16 08:00:01 PM PDT 24
Finished Jul 16 08:00:13 PM PDT 24
Peak memory 240472 kb
Host smart-6c93742e-137d-4890-803f-2e19c31264dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181770925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.181770925
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.300779103
Short name T39
Test name
Test status
Simulation time 1172981767 ps
CPU time 15.24 seconds
Started Jul 16 08:00:00 PM PDT 24
Finished Jul 16 08:00:20 PM PDT 24
Peak memory 221564 kb
Host smart-fbf0204a-da44-4b9a-bf0f-90847a3f8d9d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=300779103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.300779103
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2979277892
Short name T552
Test name
Test status
Simulation time 36903454 ps
CPU time 0.71 seconds
Started Jul 16 08:00:02 PM PDT 24
Finished Jul 16 08:00:07 PM PDT 24
Peak memory 205720 kb
Host smart-7970b4d1-78d5-414e-8c0b-f0ff6d19cad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979277892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2979277892
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.4094048250
Short name T735
Test name
Test status
Simulation time 692336751 ps
CPU time 1.83 seconds
Started Jul 16 07:59:58 PM PDT 24
Finished Jul 16 08:00:02 PM PDT 24
Peak memory 207896 kb
Host smart-098c31fa-00f3-477f-9356-bd831eae6fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094048250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.4094048250
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3899470126
Short name T379
Test name
Test status
Simulation time 96940906 ps
CPU time 0.89 seconds
Started Jul 16 08:00:01 PM PDT 24
Finished Jul 16 08:00:07 PM PDT 24
Peak memory 206688 kb
Host smart-b7b870eb-baf3-4c76-9063-64d711c19b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899470126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3899470126
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2605138452
Short name T545
Test name
Test status
Simulation time 24142536 ps
CPU time 0.79 seconds
Started Jul 16 07:59:59 PM PDT 24
Finished Jul 16 08:00:03 PM PDT 24
Peak memory 205988 kb
Host smart-3447cb5b-bbb1-41f2-8b6e-499e4818fca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605138452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2605138452
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2594793086
Short name T837
Test name
Test status
Simulation time 521829995 ps
CPU time 2.75 seconds
Started Jul 16 08:00:02 PM PDT 24
Finished Jul 16 08:00:10 PM PDT 24
Peak memory 224276 kb
Host smart-ca84d47c-0bbb-4818-b264-97fc6a5c6277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594793086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2594793086
Directory /workspace/9.spi_device_upload/latest
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