Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2514715	1			T1	1737		T2	4451		T3	115
all_values[1]	2514715	1			T1	1737		T2	4451		T3	115
all_values[2]	2514715	1			T1	1737		T2	4451		T3	115
all_values[3]	2514715	1			T1	1737		T2	4451		T3	115
all_values[4]	2514715	1			T1	1737		T2	4451		T3	115
all_values[5]	2514715	1			T1	1737		T2	4451		T3	115
all_values[6]	2514715	1			T1	1737		T2	4451		T3	115
all_values[7]	2514715	1			T1	1737		T2	4451		T3	115

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19811033

1

T1

13896

T2

35608

T3

920

auto[1]

306687

1

T14

91

T16

15823

T17

8909

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20091906

1

T1

13896

T2

35608

T3

920

auto[1]

25814

1

T5

6

T12

92

T14

168

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2449218	1			T1	1737		T2	4451		T3	115
all_values[0]	auto[0]	auto[1]	12625	1			T5	6		T12	46		T14	71
all_values[0]	auto[1]	auto[0]	52635	1			T14	5		T16	4		T17	2
all_values[0]	auto[1]	auto[1]	237	1			T14	3		T16	2		T17	3
all_values[1]	auto[0]	auto[0]	2451694	1			T1	1737		T2	4451		T3	115
all_values[1]	auto[0]	auto[1]	7784	1			T12	46		T14	31		T15	254
all_values[1]	auto[1]	auto[0]	54920	1			T14	10		T16	1		T17	2
all_values[1]	auto[1]	auto[1]	317	1			T14	6		T16	2		T17	1
all_values[2]	auto[0]	auto[0]	2487995	1			T1	1737		T2	4451		T3	115
all_values[2]	auto[0]	auto[1]	2747	1			T14	4		T15	30		T16	3
all_values[2]	auto[1]	auto[0]	23766	1			T14	4		T16	4		T18	11
all_values[2]	auto[1]	auto[1]	207	1			T14	8		T16	3		T17	3
all_values[3]	auto[0]	auto[0]	2499917	1			T1	1737		T2	4451		T3	115
all_values[3]	auto[0]	auto[1]	219	1			T14	5		T16	1		T17	3
all_values[3]	auto[1]	auto[0]	14398	1			T14	4		T16	5261		T17	8876
all_values[3]	auto[1]	auto[1]	181	1			T14	3		T16	4		T17	5
all_values[4]	auto[0]	auto[0]	2499053	1			T1	1737		T2	4451		T3	115
all_values[4]	auto[0]	auto[1]	190	1			T14	4		T16	2		T17	6
all_values[4]	auto[1]	auto[0]	15301	1			T14	9		T16	2		T18	7
all_values[4]	auto[1]	auto[1]	171	1			T14	2		T16	4		T17	2
all_values[5]	auto[0]	auto[0]	2468193	1			T1	1737		T2	4451		T3	115
all_values[5]	auto[0]	auto[1]	165	1			T14	1		T16	1		T17	2
all_values[5]	auto[1]	auto[0]	46177	1			T14	7		T16	2		T17	1
all_values[5]	auto[1]	auto[1]	180	1			T14	8		T16	4		T17	4
all_values[6]	auto[0]	auto[0]	2485290	1			T1	1737		T2	4451		T3	115
all_values[6]	auto[0]	auto[1]	201	1			T14	8		T17	3		T18	5
all_values[6]	auto[1]	auto[0]	29032	1			T14	8		T16	5263		T17	3
all_values[6]	auto[1]	auto[1]	192	1			T14	3		T16	2		T17	2
all_values[7]	auto[0]	auto[0]	2445543	1			T1	1737		T2	4451		T3	115
all_values[7]	auto[0]	auto[1]	199	1			T14	7		T16	3		T17	2
all_values[7]	auto[1]	auto[0]	68774	1			T14	7		T16	5261		T17	4
all_values[7]	auto[1]	auto[1]	199	1			T14	4		T16	4		T17	1