Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	36763	1			T2	92		T5	175		T6	10
auto[SpiFlashAddrCfg]	7710	1			T2	56		T4	2		T5	39
auto[SpiFlashAddr3b]	9588	1			T2	61		T4	2		T5	42
auto[SpiFlashAddr4b]	7882	1			T2	51		T4	2		T5	38

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35679

1

T2

141

T4

6

T5

215

auto[1]

26264

1

T2

119

T5

79

T7

9

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31895

1

T2

137

T4

6

T5

104

auto[1]

30048

1

T2

123

T5

190

T7

8

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	41478	1			T2	114		T5	203		T6	10
values[1]	1127	1			T2	5		T5	4		T10	6
values[2]	1498	1			T2	15		T4	2		T5	6
values[3]	1464	1			T2	5		T5	8		T7	1
values[4]	1564	1			T2	13		T5	6		T7	1
values[5]	1542	1			T2	10		T4	2		T5	8
values[6]	1603	1			T2	16		T5	6		T7	3
values[7]	1482	1			T2	12		T5	7		T8	2
values[8]	10185	1			T2	70		T4	2		T5	46

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30190

1

T2

260

T4

6

T5

294

auto[1]

31753

1

T10

373

T13

3

T14

48

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

58612

1

T2

250

T4

6

T5

279

write

3331

1

T2

10

T5

15

T7

1

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20018

1

T2

133

T4

4

T5

95

valids[0x1]

41925

1

T2

127

T4

2

T5

199

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1613	1			T2	13		T5	6		T7	2
internal_process_ops[0x5a]	1631	1			T2	17		T5	4		T8	1
internal_process_ops[0x05]	22316	1			T2	6		T5	120		T7	1
internal_process_ops[0x35]	1673	1			T2	15		T5	7		T8	2
internal_process_ops[0x15]	1600	1			T2	6		T5	3		T8	6
internal_process_ops[0x03]	1058	1			T2	13		T4	2		T5	6
internal_process_ops[0x0b]	1135	1			T2	9		T5	8		T7	1
internal_process_ops[0x3b]	1123	1			T2	13		T4	2		T5	6
internal_process_ops[0x6b]	1078	1			T2	11		T5	8		T7	1
internal_process_ops[0xbb]	1103	1			T2	7		T5	8		T8	1
internal_process_ops[0xeb]	1077	1			T2	10		T4	2		T5	6

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60382

1

T2

252

T4

6

T5

288

auto[1]

1561

1

T2

8

T5

6

T8

4

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59498

1

T2

252

T4

6

T5

287

auto[1]

2445

1

T2

8

T5

7

T7

1

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10184

1

T2

55

T5

158

T6

10

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5700

1

T2

32

T5

14

T7

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2060

1

T2

29

T4

2

T5

11

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1874

1

T2

26

T5

17

T7

1

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2526

1

T2

26

T4

2

T5

19

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2298

1

T2

33

T5

22

T8

3

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2098

1

T2

26

T4

2

T5

18

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1936

1

T2

23

T5

20

T7

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

110

1

T54

2

T51

2

T182

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

66

1

T2

2

T5

1

T12

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

88

1

T5

2

T7

1

T43

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

117

1

T2

3

T43

1

T23

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

113

1

T5

4

T159

2

T182

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

96

1

T2

1

T5

3

T25

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

71

1

T5

3

T12

1

T43

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

91

1

T5

1

T23

2

T92

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

120

1

T2

1

T43

1

T25

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

92

1

T2

1

T5

1

T12

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

88

1

T8

1

T43

2

T16

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

78

1

T51

1

T16

3

T92

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

113

1

T8

2

T44

4

T25

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

66

1

T8

2

T43

2

T25

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

88

1

T2

1

T8

3

T43

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

117

1

T2

1

T8

2

T43

4

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11884

1

T10

80

T14

15

T49

6

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8157

1

T10

165

T14

8

T49

29

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1593

1

T10

23

T13

3

T14

2

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1345

1

T10

14

T14

8

T49

2

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2084

1

T10

20

T14

4

T37

7

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1871

1

T10

12

T14

8

T15

31

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1564

1

T10

13

T14

1

T15

20

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1438

1

T10

21

T14

1

T49

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

120

1

T10

2

T15

1

T16

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

113

1

T10

2

T45

1

T18

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

123

1

T15

4

T63

1

T45

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

101

1

T10

1

T15

4

T63

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

128

1

T15

5

T63

1

T136

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

108

1

T49

2

T15

5

T45

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

115

1

T10

2

T15

1

T45

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

116

1

T10

1

T15

6

T45

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

114

1

T10

2

T15

1

T45

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

102

1

T10

2

T14

1

T15

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

134

1

T10

2

T15

5

T16

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

81

1

T18

3

T21

2

T87

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

124

1

T10

2

T63

3

T45

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

101

1

T10

3

T63

2

T45

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

121

1

T10

1

T15

1

T136

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

116

1

T10

5

T63

1

T16

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4003	1			T2	45		T5	35		T6	10
auto[0]	values[0]	valids[0x1]	14731	1			T2	69		T5	168		T7	6
auto[0]	values[1]	valids[0x1]	556	1			T2	5		T5	4		T12	5
auto[0]	values[2]	valids[0x0]	575	1			T2	4		T4	2		T5	5
auto[0]	values[2]	valids[0x1]	282	1			T2	11		T5	1		T12	1
auto[0]	values[3]	valids[0x0]	521	1			T2	2		T5	6		T7	1
auto[0]	values[3]	valids[0x1]	329	1			T2	3		T5	2		T8	2
auto[0]	values[4]	valids[0x0]	573	1			T2	10		T5	5		T8	2
auto[0]	values[4]	valids[0x1]	293	1			T2	3		T5	1		T7	1
auto[0]	values[5]	valids[0x0]	574	1			T2	8		T4	2		T5	8
auto[0]	values[5]	valids[0x1]	271	1			T2	2		T7	1		T12	2
auto[0]	values[6]	valids[0x0]	612	1			T2	13		T5	2		T7	1
auto[0]	values[6]	valids[0x1]	314	1			T2	3		T5	4		T7	2
auto[0]	values[7]	valids[0x0]	538	1			T2	8		T5	4		T8	1
auto[0]	values[7]	valids[0x1]	300	1			T2	4		T5	3		T8	1
auto[0]	values[8]	valids[0x0]	3616	1			T2	43		T5	30		T7	4
auto[0]	values[8]	valids[0x1]	2102	1			T2	27		T4	2		T5	16
auto[1]	values[0]	valids[0x0]	4096	1			T10	43		T14	8		T49	4
auto[1]	values[0]	valids[0x1]	18648	1			T10	239		T14	17		T37	8
auto[1]	values[1]	valids[0x1]	571	1			T10	6		T14	1		T49	3
auto[1]	values[2]	valids[0x0]	396	1			T10	4		T37	2		T15	3
auto[1]	values[2]	valids[0x1]	245	1			T10	3		T15	10		T63	1
auto[1]	values[3]	valids[0x0]	339	1			T10	6		T14	2		T15	4
auto[1]	values[3]	valids[0x1]	275	1			T10	4		T15	3		T45	4
auto[1]	values[4]	valids[0x0]	411	1			T10	4		T15	4		T63	6
auto[1]	values[4]	valids[0x1]	287	1			T10	5		T14	1		T15	4
auto[1]	values[5]	valids[0x0]	435	1			T14	1		T15	13		T45	7
auto[1]	values[5]	valids[0x1]	262	1			T10	2		T15	5		T63	1
auto[1]	values[6]	valids[0x0]	430	1			T10	4		T49	1		T15	6
auto[1]	values[6]	valids[0x1]	247	1			T10	3		T63	1		T45	5
auto[1]	values[7]	valids[0x0]	378	1			T10	2		T49	1		T15	7
auto[1]	values[7]	valids[0x1]	266	1			T10	2		T14	1		T15	5
auto[1]	values[8]	valids[0x0]	2521	1			T10	31		T13	2		T14	8
auto[1]	values[8]	valids[0x1]	1946	1			T10	15		T13	1		T14	9