Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3388310

1

T2

16825

T4

1257

T5

7846

auto[1]

33172

1

T2

27

T5

114

T7

1

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

827443

1

T2

585

T4

1257

T5

48

auto[1]

2594039

1

T2

16267

T5

7912

T7

1

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	634183	1			T2	37		T4	348		T5	144
auto[524288:1048575]	401501	1			T2	219		T5	265		T6	3717
auto[1048576:1572863]	396892	1			T2	59		T4	196		T5	2
auto[1572864:2097151]	409884	1			T2	1336		T4	222		T5	556
auto[2097152:2621439]	397703	1			T2	5135		T4	139		T5	2696
auto[2621440:3145727]	386868	1			T2	3936		T4	1		T5	809
auto[3145728:3670015]	451433	1			T2	6094		T4	306		T5	257
auto[3670016:4194303]	343018	1			T2	36		T4	45		T5	3231

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2629006

1

T2

16845

T4

24

T5

7957

auto[1]

792476

1

T2

7

T4

1233

T5

3

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2921498

1

T2

16223

T4

1257

T5

7273

auto[1]

499984

1

T2

629

T5

687

T7

1

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	162144	1			T2	20		T4	348		T5	6
auto[0]	auto[0]	auto[0:524287]	auto[1]	397355	1			T2	5		T5	129		T12	1
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	100562	1			T2	84		T5	4		T6	3717
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	240692	1			T2	128		T5	260		T10	4490
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	117059	1			T2	21		T4	196		T5	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	224972	1			T2	4		T8	151		T10	764
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	91850	1			T2	18		T4	222		T5	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	264349	1			T2	770		T5	385		T8	256
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	71033	1			T2	124		T4	139		T5	9
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	247018	1			T2	4999		T5	2642		T8	3115
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	94409	1			T2	51		T4	1		T5	4
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	240683	1			T2	3865		T5	772		T7	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	102404	1			T2	101		T4	306		T5	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	279472	1			T2	5978		T8	256		T10	2629
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	76211	1			T2	28		T4	45		T5	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	183837	1			T5	2971		T10	256		T12	1
auto[0]	auto[1]	auto[0:524287]	auto[0]	1017	1			T2	12		T10	2		T43	6
auto[0]	auto[1]	auto[0:524287]	auto[1]	68245	1			T10	131		T14	256		T15	5
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1302	1			T2	4		T5	1		T10	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	55568	1			T25	512		T15	319		T63	1025
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1479	1			T2	18		T10	4		T12	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	48866	1			T2	4		T10	112		T12	256
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	465	1			T2	36		T5	2		T10	4
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	50020	1			T2	512		T5	128		T10	3000
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	997	1			T2	6		T5	5		T10	4
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	76079	1			T5	6		T10	129		T12	256
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1033	1			T2	18		T7	1		T12	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	46143	1			T2	2		T25	512		T15	85
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	812	1			T2	9		T8	10		T12	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	63976	1			T5	256		T8	128		T10	5
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	746	1			T2	8		T5	2		T10	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	77512	1			T5	256		T25	2965		T15	598
auto[1]	auto[0]	auto[0:524287]	auto[0]	492	1			T5	1		T12	1		T44	4
auto[1]	auto[0]	auto[0:524287]	auto[1]	4090	1			T5	8		T12	46		T44	24
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	357	1			T2	3		T10	3		T43	8
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2591	1			T10	70		T51	4		T15	5
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	424	1			T2	12		T10	3		T14	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	3407	1			T10	24		T43	47		T63	19
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	384	1			T5	1		T14	3		T25	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2184	1			T5	37		T14	2		T25	11
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	414	1			T2	6		T5	1		T8	4
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1533	1			T5	2		T51	122		T49	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	336	1			T5	2		T7	1		T10	4
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	3376	1			T5	31		T10	40		T12	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	426	1			T2	6		T10	2		T12	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	3914	1			T10	6		T12	38		T49	24
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	348	1			T8	8		T12	1		T14	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	3172	1			T12	1		T14	1		T25	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	81	1			T45	1		T19	5		T101	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	759	1			T45	18		T19	70		T98	203
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	83	1			T15	1		T63	1		T45	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	346	1			T15	2		T63	36		T45	10
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	80	1			T63	1		T19	2		T239	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	605	1			T63	30		T19	10		T239	26
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	94	1			T10	2		T15	3		T18	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	538	1			T10	16		T15	3		T18	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	91	1			T5	2		T10	1		T18	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	538	1			T5	29		T10	2		T18	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	104	1			T63	1		T45	2		T192	11
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	784	1			T63	20		T45	19		T19	48
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	119	1			T43	6		T15	1		T45	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	310	1			T45	59		T19	13		T204	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	87	1			T17	1		T19	2		T207	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	1105	1			T17	1		T19	6		T207	4

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2104766	1			T2	16196		T4	24		T5	7189
auto[0]	auto[0]	auto[1]	789284	1			T4	1233		T5	1		T6	10208
auto[0]	auto[1]	auto[0]	491754	1			T2	629		T5	656		T7	1
auto[0]	auto[1]	auto[1]	2506	1			T10	3		T95	309		T63	1
auto[1]	auto[0]	auto[0]	26909	1			T2	20		T5	81		T7	1
auto[1]	auto[0]	auto[1]	539	1			T2	7		T5	2		T8	2
auto[1]	auto[1]	auto[0]	5577	1			T5	31		T10	19		T43	4
auto[1]	auto[1]	auto[1]	147	1			T10	2		T43	2		T63	1