Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2514715	1			T1	1737		T2	4451		T3	115
all_pins[1]	2514715	1			T1	1737		T2	4451		T3	115
all_pins[2]	2514715	1			T1	1737		T2	4451		T3	115
all_pins[3]	2514715	1			T1	1737		T2	4451		T3	115
all_pins[4]	2514715	1			T1	1737		T2	4451		T3	115
all_pins[5]	2514715	1			T1	1737		T2	4451		T3	115
all_pins[6]	2514715	1			T1	1737		T2	4451		T3	115
all_pins[7]	2514715	1			T1	1737		T2	4451		T3	115

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20091790	1			T1	13896		T2	35608		T3	920
values[0x1]	25930	1			T14	37		T16	25		T17	21
transitions[0x0=>0x1]	25299	1			T14	29		T16	14		T17	17
transitions[0x1=>0x0]	25316	1			T14	29		T16	14		T17	17

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2514461	1			T1	1737		T2	4451		T3	115
all_pins[0]	values[0x1]	254	1			T14	3		T16	2		T17	3
all_pins[0]	transitions[0x0=>0x1]	127	1			T14	3		T16	2		T17	3
all_pins[0]	transitions[0x1=>0x0]	210	1			T14	6		T16	2		T17	1
all_pins[1]	values[0x0]	2514378	1			T1	1737		T2	4451		T3	115
all_pins[1]	values[0x1]	337	1			T14	6		T16	2		T17	1
all_pins[1]	transitions[0x0=>0x1]	263	1			T14	4		T16	1		T18	3
all_pins[1]	transitions[0x1=>0x0]	140	1			T14	6		T16	2		T17	2
all_pins[2]	values[0x0]	2514501	1			T1	1737		T2	4451		T3	115
all_pins[2]	values[0x1]	214	1			T14	8		T16	3		T17	3
all_pins[2]	transitions[0x0=>0x1]	156	1			T14	6		T16	1		T17	2
all_pins[2]	transitions[0x1=>0x0]	123	1			T14	1		T16	2		T17	4
all_pins[3]	values[0x0]	2514534	1			T1	1737		T2	4451		T3	115
all_pins[3]	values[0x1]	181	1			T14	3		T16	4		T17	5
all_pins[3]	transitions[0x0=>0x1]	138	1			T14	3		T16	2		T17	5
all_pins[3]	transitions[0x1=>0x0]	128	1			T14	2		T16	2		T17	2
all_pins[4]	values[0x0]	2514544	1			T1	1737		T2	4451		T3	115
all_pins[4]	values[0x1]	171	1			T14	2		T16	4		T17	2
all_pins[4]	transitions[0x0=>0x1]	129	1			T14	1		T16	1		T17	1
all_pins[4]	transitions[0x1=>0x0]	895	1			T14	7		T16	1		T17	3
all_pins[5]	values[0x0]	2513778	1			T1	1737		T2	4451		T3	115
all_pins[5]	values[0x1]	937	1			T14	8		T16	4		T17	4
all_pins[5]	transitions[0x0=>0x1]	750	1			T14	6		T16	4		T17	3
all_pins[5]	transitions[0x1=>0x0]	23450	1			T14	1		T16	2		T17	1
all_pins[6]	values[0x0]	2491078	1			T1	1737		T2	4451		T3	115
all_pins[6]	values[0x1]	23637	1			T14	3		T16	2		T17	2
all_pins[6]	transitions[0x0=>0x1]	23588	1			T14	3		T17	2		T18	3
all_pins[6]	transitions[0x1=>0x0]	150	1			T14	4		T16	2		T17	1
all_pins[7]	values[0x0]	2514516	1			T1	1737		T2	4451		T3	115
all_pins[7]	values[0x1]	199	1			T14	4		T16	4		T17	1
all_pins[7]	transitions[0x0=>0x1]	148	1			T14	3		T16	3		T17	1
all_pins[7]	transitions[0x1=>0x0]	220	1			T14	2		T16	1		T17	3