Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17644

1

T2

141

T4

6

T5

215

auto[1]

12546

1

T2

119

T5

79

T7

9

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3858	1			T2	60		T12	149		T43	20
values[1]	3893	1			T2	40		T5	58		T12	42
values[2]	3980	1			T2	20		T5	51		T8	20
values[3]	3632	1			T2	40		T5	53		T8	20
values[4]	3522	1			T2	20		T5	43		T11	8
values[5]	3321	1			T2	20		T6	10		T8	20
values[6]	3812	1			T2	40		T4	6		T5	69
values[7]	4172	1			T2	20		T5	20		T12	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3263	1			T2	20		T8	20		T43	40
values[1]	3928	1			T2	20		T5	78		T12	60
values[2]	3782	1			T2	20		T5	49		T12	20
values[3]	4038	1			T2	80		T4	6		T5	20
values[4]	3894	1			T2	20		T43	20		T158	8
values[5]	3313	1			T2	20		T5	74		T8	20
values[6]	4560	1			T2	40		T5	73		T12	107
values[7]	3412	1			T2	40		T6	10		T8	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	173	1			T25	12		T192	12		T198	10
auto[0]	values[0]	values[1]	303	1			T2	17		T21	9		T35	33
auto[0]	values[0]	values[2]	216	1			T43	7		T51	15		T16	8
auto[0]	values[0]	values[3]	266	1			T2	19		T12	24		T240	4
auto[0]	values[0]	values[4]	267	1			T16	13		T92	7		T17	8
auto[0]	values[0]	values[5]	153	1			T21	12		T212	12		T241	9
auto[0]	values[0]	values[6]	603	1			T12	104		T51	17		T225	15
auto[0]	values[0]	values[7]	324	1			T231	12		T224	13		T84	8
auto[0]	values[1]	values[0]	203	1			T43	9		T21	15		T98	24
auto[0]	values[1]	values[1]	261	1			T5	48		T12	11		T43	5
auto[0]	values[1]	values[2]	291	1			T198	11		T35	24		T210	13
auto[0]	values[1]	values[3]	226	1			T12	15		T92	12		T17	8
auto[0]	values[1]	values[4]	314	1			T43	10		T158	8		T182	84
auto[0]	values[1]	values[5]	198	1			T2	9		T43	13		T156	8
auto[0]	values[1]	values[6]	253	1			T43	6		T205	10		T242	8
auto[0]	values[1]	values[7]	265	1			T2	12		T17	8		T192	9
auto[0]	values[2]	values[0]	232	1			T2	13		T8	9		T230	16
auto[0]	values[2]	values[1]	220	1			T35	16		T226	25		T243	9
auto[0]	values[2]	values[2]	418	1			T92	12		T198	17		T35	15
auto[0]	values[2]	values[3]	335	1			T43	23		T25	9		T92	14
auto[0]	values[2]	values[4]	257	1			T143	16		T35	15		T233	13
auto[0]	values[2]	values[5]	314	1			T5	42		T51	11		T96	26
auto[0]	values[2]	values[6]	374	1			T43	16		T227	8		T244	14
auto[0]	values[2]	values[7]	165	1			T139	14		T241	26		T245	18
auto[0]	values[3]	values[0]	259	1			T191	7		T224	9		T246	16
auto[0]	values[3]	values[1]	247	1			T43	10		T25	3		T92	12
auto[0]	values[3]	values[2]	330	1			T2	10		T25	9		T19	12
auto[0]	values[3]	values[3]	387	1			T25	10		T224	90		T198	13
auto[0]	values[3]	values[4]	159	1			T2	10		T247	41		T248	10
auto[0]	values[3]	values[5]	318	1			T19	12		T209	13		T219	12
auto[0]	values[3]	values[6]	352	1			T5	47		T249	4		T92	16
auto[0]	values[3]	values[7]	318	1			T8	13		T238	10		T16	13
auto[0]	values[4]	values[0]	210	1			T17	15		T207	8		T98	8
auto[0]	values[4]	values[1]	359	1			T19	15		T250	10		T251	16
auto[0]	values[4]	values[2]	144	1			T181	8		T252	10		T253	20
auto[0]	values[4]	values[3]	234	1			T2	20		T5	12		T11	8
auto[0]	values[4]	values[4]	365	1			T227	9		T78	8		T21	12
auto[0]	values[4]	values[5]	259	1			T5	11		T43	12		T121	4
auto[0]	values[4]	values[6]	482	1			T16	18		T192	12		T21	14
auto[0]	values[4]	values[7]	181	1			T21	17		T211	10		T218	9
auto[0]	values[5]	values[0]	170	1			T43	11		T192	11		T19	11
auto[0]	values[5]	values[1]	356	1			T12	11		T39	2		T25	25
auto[0]	values[5]	values[2]	171	1			T25	12		T97	22		T254	14
auto[0]	values[5]	values[3]	169	1			T51	11		T192	10		T21	8
auto[0]	values[5]	values[4]	358	1			T192	20		T255	16		T227	9
auto[0]	values[5]	values[5]	133	1			T8	13		T19	24		T181	6
auto[0]	values[5]	values[6]	182	1			T2	8		T256	12		T19	10
auto[0]	values[5]	values[7]	194	1			T6	10		T44	48		T51	15
auto[0]	values[6]	values[0]	229	1			T106	18		T224	14		T207	15
auto[0]	values[6]	values[1]	398	1			T5	13		T12	10		T25	10
auto[0]	values[6]	values[2]	372	1			T5	24		T92	11		T203	58
auto[0]	values[6]	values[3]	314	1			T2	12		T4	6		T7	12
auto[0]	values[6]	values[4]	344	1			T16	9		T257	18		T35	39
auto[0]	values[6]	values[5]	195	1			T51	11		T159	8		T17	10
auto[0]	values[6]	values[6]	271	1			T2	6		T5	4		T157	6
auto[0]	values[6]	values[7]	88	1			T224	12		T35	10		T218	10
auto[0]	values[7]	values[0]	285	1			T16	10		T17	26		T19	14
auto[0]	values[7]	values[1]	257	1			T43	11		T25	7		T177	14
auto[0]	values[7]	values[2]	279	1			T5	14		T12	9		T258	22
auto[0]	values[7]	values[3]	444	1			T43	8		T192	12		T21	5
auto[0]	values[7]	values[4]	215	1			T192	10		T82	6		T210	7
auto[0]	values[7]	values[5]	333	1			T207	14		T21	25		T198	11
auto[0]	values[7]	values[6]	327	1			T51	14		T95	4		T92	14
auto[0]	values[7]	values[7]	325	1			T2	5		T192	16		T259	10
auto[1]	values[0]	values[0]	132	1			T25	8		T192	8		T198	10
auto[1]	values[0]	values[1]	148	1			T2	3		T21	11		T35	7
auto[1]	values[0]	values[2]	157	1			T43	13		T51	5		T16	13
auto[1]	values[0]	values[3]	134	1			T2	21		T12	18		T216	9
auto[1]	values[0]	values[4]	370	1			T16	7		T92	13		T17	12
auto[1]	values[0]	values[5]	164	1			T21	8		T212	19		T241	27
auto[1]	values[0]	values[6]	306	1			T12	3		T51	3		T225	5
auto[1]	values[0]	values[7]	142	1			T53	24		T224	14		T198	8
auto[1]	values[1]	values[0]	173	1			T43	11		T102	18		T21	11
auto[1]	values[1]	values[1]	225	1			T5	10		T12	9		T43	15
auto[1]	values[1]	values[2]	232	1			T198	9		T35	11		T210	7
auto[1]	values[1]	values[3]	327	1			T12	7		T92	9		T17	12
auto[1]	values[1]	values[4]	168	1			T43	10		T98	8		T198	8
auto[1]	values[1]	values[5]	233	1			T2	11		T43	7		T19	9
auto[1]	values[1]	values[6]	233	1			T43	14		T205	11		T181	9
auto[1]	values[1]	values[7]	291	1			T2	8		T17	30		T192	11
auto[1]	values[2]	values[0]	307	1			T2	7		T8	11		T50	26
auto[1]	values[2]	values[1]	210	1			T35	10		T226	3		T243	11
auto[1]	values[2]	values[2]	159	1			T92	8		T198	3		T35	11
auto[1]	values[2]	values[3]	323	1			T43	17		T25	11		T92	13
auto[1]	values[2]	values[4]	222	1			T35	8		T233	7		T202	61
auto[1]	values[2]	values[5]	164	1			T5	9		T51	9		T98	7
auto[1]	values[2]	values[6]	162	1			T43	4		T227	12		T211	28
auto[1]	values[2]	values[7]	118	1			T241	6		T260	5		T261	77
auto[1]	values[3]	values[0]	161	1			T191	13		T224	11		T234	12
auto[1]	values[3]	values[1]	183	1			T43	10		T25	19		T92	8
auto[1]	values[3]	values[2]	188	1			T2	10		T25	11		T19	9
auto[1]	values[3]	values[3]	164	1			T25	10		T224	6		T198	7
auto[1]	values[3]	values[4]	106	1			T2	10		T262	10		T263	11
auto[1]	values[3]	values[5]	140	1			T19	8		T209	42		T219	8
auto[1]	values[3]	values[6]	136	1			T5	6		T92	4		T21	9
auto[1]	values[3]	values[7]	184	1			T8	7		T16	15		T17	15
auto[1]	values[4]	values[0]	137	1			T17	8		T207	46		T98	12
auto[1]	values[4]	values[1]	167	1			T19	8		T264	13		T265	19
auto[1]	values[4]	values[2]	142	1			T181	18		T252	12		T266	28
auto[1]	values[4]	values[3]	132	1			T5	8		T211	5		T222	22
auto[1]	values[4]	values[4]	143	1			T227	11		T21	8		T234	7
auto[1]	values[4]	values[5]	194	1			T5	12		T43	8		T19	18
auto[1]	values[4]	values[6]	182	1			T16	7		T192	8		T21	24
auto[1]	values[4]	values[7]	191	1			T21	31		T211	34		T218	23
auto[1]	values[5]	values[0]	155	1			T43	9		T192	9		T267	8
auto[1]	values[5]	values[1]	298	1			T12	9		T25	15		T51	12
auto[1]	values[5]	values[2]	117	1			T25	21		T205	13		T212	7
auto[1]	values[5]	values[3]	235	1			T51	9		T192	10		T21	12
auto[1]	values[5]	values[4]	229	1			T192	20		T227	11		T21	9
auto[1]	values[5]	values[5]	177	1			T8	7		T19	9		T181	31
auto[1]	values[5]	values[6]	169	1			T2	12		T19	10		T224	5
auto[1]	values[5]	values[7]	208	1			T51	5		T207	14		T198	8
auto[1]	values[6]	values[0]	184	1			T224	6		T207	10		T233	12
auto[1]	values[6]	values[1]	140	1			T5	7		T12	10		T25	10
auto[1]	values[6]	values[2]	351	1			T5	5		T92	9		T230	12
auto[1]	values[6]	values[3]	120	1			T2	8		T7	9		T92	12
auto[1]	values[6]	values[4]	261	1			T16	12		T35	4		T216	11
auto[1]	values[6]	values[5]	174	1			T51	9		T17	15		T191	13
auto[1]	values[6]	values[6]	217	1			T2	14		T5	16		T16	14
auto[1]	values[6]	values[7]	154	1			T224	8		T35	10		T218	10
auto[1]	values[7]	values[0]	253	1			T16	10		T17	10		T19	9
auto[1]	values[7]	values[1]	156	1			T43	9		T25	13		T35	9
auto[1]	values[7]	values[2]	215	1			T5	6		T12	11		T23	24
auto[1]	values[7]	values[3]	228	1			T43	12		T192	8		T21	27
auto[1]	values[7]	values[4]	116	1			T192	10		T210	13		T181	9
auto[1]	values[7]	values[5]	164	1			T207	6		T21	15		T198	9
auto[1]	values[7]	values[6]	311	1			T51	6		T92	8		T19	9
auto[1]	values[7]	values[7]	264	1			T2	15		T38	18		T192	4