Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	66	0	66	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	64	0	64	100.00	100	1	1	64

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15106

1

T2

160

T4

3

T5

174

auto[1]

46837

1

T2

100

T4

3

T5

120

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	64	0	64	100.00

Automatically Generated Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	1310	1			T2	13		T4	2		T5	6
auto[4:7]	25566	1			T2	24		T5	131		T7	2
auto[8:11]	1409	1			T2	10		T5	9		T7	1
auto[12:15]	335	1			T2	1		T8	2		T25	4
auto[16:19]	317	1			T43	3		T14	3		T15	3
auto[20:23]	1824	1			T2	6		T5	3		T8	8
auto[24:27]	332	1			T5	2		T51	5		T15	1
auto[28:31]	289	1			T2	1		T5	4		T10	1
auto[32:35]	339	1			T2	4		T5	1		T10	1
auto[36:39]	316	1			T2	2		T5	1		T43	5
auto[40:43]	362	1			T2	1		T10	2		T43	3
auto[44:47]	385	1			T2	2		T8	7		T10	6
auto[48:51]	348	1			T2	5		T5	2		T10	2
auto[52:55]	1963	1			T2	16		T5	9		T8	5
auto[56:59]	1363	1			T2	14		T4	2		T5	6
auto[60:63]	324	1			T2	1		T5	2		T12	1
auto[64:67]	385	1			T5	2		T10	5		T43	3
auto[68:71]	326	1			T2	1		T10	1		T12	1
auto[72:75]	311	1			T2	3		T5	7		T10	1
auto[76:79]	318	1			T2	2		T5	1		T10	1
auto[80:83]	328	1			T2	2		T10	2		T12	1
auto[84:87]	346	1			T2	4		T10	1		T12	2
auto[88:91]	1873	1			T2	17		T5	4		T8	1
auto[92:95]	353	1			T2	1		T10	3		T43	1
auto[96:99]	349	1			T5	6		T10	1		T25	1
auto[100:103]	336	1			T2	1		T10	2		T43	1
auto[104:107]	1356	1			T2	11		T5	8		T7	1
auto[108:111]	340	1			T2	2		T5	1		T10	2
auto[112:115]	318	1			T2	1		T10	2		T12	2
auto[116:119]	333	1			T2	3		T5	1		T7	1
auto[120:123]	370	1			T5	4		T10	3		T12	3
auto[124:127]	335	1			T2	1		T5	2		T10	1
auto[128:131]	309	1			T2	2		T12	1		T43	1
auto[132:135]	374	1			T5	2		T10	1		T12	2
auto[136:139]	330	1			T2	4		T8	1		T10	4
auto[140:143]	298	1			T5	4		T10	4		T12	3
auto[144:147]	311	1			T7	2		T10	5		T157	2
auto[148:151]	316	1			T2	4		T5	2		T8	1
auto[152:155]	334	1			T2	3		T5	1		T7	1
auto[156:159]	1827	1			T2	13		T5	6		T7	2
auto[160:163]	275	1			T2	3		T10	2		T12	1
auto[164:167]	303	1			T2	1		T8	1		T12	2
auto[168:171]	342	1			T2	4		T5	2		T10	1
auto[172:175]	382	1			T8	3		T10	1		T12	9
auto[176:179]	305	1			T5	5		T12	3		T43	6
auto[180:183]	1860	1			T2	12		T5	9		T6	8
auto[184:187]	1341	1			T2	8		T5	9		T8	1
auto[188:191]	342	1			T2	5		T5	1		T7	1
auto[192:195]	343	1			T2	1		T5	3		T7	1
auto[196:199]	357	1			T2	8		T10	2		T12	1
auto[200:203]	338	1			T2	1		T5	5		T10	4
auto[204:207]	327	1			T2	4		T7	2		T10	7
auto[208:211]	295	1			T2	2		T5	2		T43	3
auto[212:215]	322	1			T2	1		T12	1		T43	1
auto[216:219]	339	1			T2	4		T5	4		T10	3
auto[220:223]	370	1			T2	2		T5	1		T10	3
auto[224:227]	334	1			T5	3		T12	2		T43	4
auto[228:231]	310	1			T2	4		T8	1		T10	1
auto[232:235]	2895	1			T2	19		T4	2		T5	15
auto[236:239]	345	1			T2	1		T43	4		T14	1
auto[240:243]	332	1			T2	2		T5	1		T8	1
auto[244:247]	361	1			T2	2		T5	5		T10	1
auto[248:251]	295	1			T2	1		T5	2		T10	1
auto[252:255]	372	1			T43	2		T14	1		T50	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	auto[0]	433	1			T2	10		T4	1		T5	6
auto[0:3]	auto[1]	877	1			T2	3		T4	1		T8	2
auto[4:7]	auto[0]	5439	1			T2	20		T5	87		T8	5
auto[4:7]	auto[1]	20127	1			T2	4		T5	44		T7	2
auto[8:11]	auto[0]	492	1			T2	4		T5	6		T12	4
auto[8:11]	auto[1]	917	1			T2	6		T5	3		T7	1
auto[12:15]	auto[0]	55	1			T8	2		T25	1		T35	1
auto[12:15]	auto[1]	280	1			T2	1		T25	3		T51	1
auto[16:19]	auto[0]	71	1			T43	3		T192	1		T191	1
auto[16:19]	auto[1]	246	1			T14	3		T15	3		T63	1
auto[20:23]	auto[0]	458	1			T2	4		T5	2		T8	2
auto[20:23]	auto[1]	1366	1			T2	2		T5	1		T8	6
auto[24:27]	auto[0]	80	1			T51	3		T19	4		T224	4
auto[24:27]	auto[1]	252	1			T5	2		T51	2		T15	1
auto[28:31]	auto[0]	60	1			T2	1		T5	2		T25	2
auto[28:31]	auto[1]	229	1			T5	2		T10	1		T12	1
auto[32:35]	auto[0]	66	1			T2	3		T25	1		T51	2
auto[32:35]	auto[1]	273	1			T2	1		T5	1		T10	1
auto[36:39]	auto[0]	76	1			T25	1		T53	6		T16	1
auto[36:39]	auto[1]	240	1			T2	2		T5	1		T43	5
auto[40:43]	auto[0]	79	1			T2	1		T43	1		T25	1
auto[40:43]	auto[1]	283	1			T10	2		T43	2		T15	1
auto[44:47]	auto[0]	100	1			T2	1		T8	2		T12	1
auto[44:47]	auto[1]	285	1			T2	1		T8	5		T10	6
auto[48:51]	auto[0]	97	1			T2	4		T5	2		T43	1
auto[48:51]	auto[1]	251	1			T2	1		T10	2		T12	3
auto[52:55]	auto[0]	505	1			T2	9		T5	5		T8	4
auto[52:55]	auto[1]	1458	1			T2	7		T5	4		T8	1
auto[56:59]	auto[0]	498	1			T2	10		T4	1		T5	2
auto[56:59]	auto[1]	865	1			T2	4		T4	1		T5	4
auto[60:63]	auto[0]	83	1			T5	2		T12	1		T25	1
auto[60:63]	auto[1]	241	1			T2	1		T25	2		T51	1
auto[64:67]	auto[0]	114	1			T5	2		T43	1		T25	2
auto[64:67]	auto[1]	271	1			T10	5		T43	2		T14	1
auto[68:71]	auto[0]	63	1			T2	1		T12	1		T21	3
auto[68:71]	auto[1]	263	1			T10	1		T25	2		T51	1
auto[72:75]	auto[0]	71	1			T2	3		T16	1		T192	1
auto[72:75]	auto[1]	240	1			T5	7		T10	1		T43	2
auto[76:79]	auto[0]	72	1			T5	1		T51	1		T16	3
auto[76:79]	auto[1]	246	1			T2	2		T10	1		T43	1
auto[80:83]	auto[0]	98	1			T12	1		T23	1		T182	1
auto[80:83]	auto[1]	230	1			T2	2		T10	2		T23	1
auto[84:87]	auto[0]	86	1			T12	1		T25	1		T92	4
auto[84:87]	auto[1]	260	1			T2	4		T10	1		T12	1
auto[88:91]	auto[0]	434	1			T2	10		T5	3		T12	7
auto[88:91]	auto[1]	1439	1			T2	7		T5	1		T8	1
auto[92:95]	auto[0]	64	1			T2	1		T43	1		T51	1
auto[92:95]	auto[1]	289	1			T10	3		T25	1		T45	1
auto[96:99]	auto[0]	94	1			T5	4		T51	6		T16	1
auto[96:99]	auto[1]	255	1			T5	2		T10	1		T25	1
auto[100:103]	auto[0]	79	1			T43	1		T25	1		T16	1
auto[100:103]	auto[1]	257	1			T2	1		T10	2		T25	1
auto[104:107]	auto[0]	466	1			T2	4		T7	1		T12	3
auto[104:107]	auto[1]	890	1			T2	7		T5	8		T8	2
auto[108:111]	auto[0]	68	1			T2	2		T43	2		T25	3
auto[108:111]	auto[1]	272	1			T5	1		T10	2		T43	1
auto[112:115]	auto[0]	86	1			T12	2		T25	1		T50	1
auto[112:115]	auto[1]	232	1			T2	1		T10	2		T43	2
auto[116:119]	auto[0]	58	1			T2	3		T43	2		T192	1
auto[116:119]	auto[1]	275	1			T5	1		T7	1		T8	1
auto[120:123]	auto[0]	77	1			T5	4		T12	2		T23	1
auto[120:123]	auto[1]	293	1			T10	3		T12	1		T43	1
auto[124:127]	auto[0]	75	1			T5	2		T12	2		T19	1
auto[124:127]	auto[1]	260	1			T2	1		T10	1		T43	2
auto[128:131]	auto[0]	63	1			T12	1		T43	1		T51	1
auto[128:131]	auto[1]	246	1			T2	2		T25	1		T51	1
auto[132:135]	auto[0]	97	1			T5	1		T12	1		T25	1
auto[132:135]	auto[1]	277	1			T5	1		T10	1		T12	1
auto[136:139]	auto[0]	86	1			T2	2		T43	2		T51	2
auto[136:139]	auto[1]	244	1			T2	2		T8	1		T10	4
auto[140:143]	auto[0]	78	1			T5	1		T12	2		T16	1
auto[140:143]	auto[1]	220	1			T5	3		T10	4		T12	1
auto[144:147]	auto[0]	79	1			T7	2		T157	1		T51	2
auto[144:147]	auto[1]	232	1			T10	5		T157	1		T49	1
auto[148:151]	auto[0]	87	1			T2	3		T5	2		T8	1
auto[148:151]	auto[1]	229	1			T2	1		T10	3		T25	1
auto[152:155]	auto[0]	83	1			T12	1		T52	1		T92	3
auto[152:155]	auto[1]	251	1			T2	3		T5	1		T7	1
auto[156:159]	auto[0]	444	1			T2	10		T5	4		T8	3
auto[156:159]	auto[1]	1383	1			T2	3		T5	2		T7	2
auto[160:163]	auto[0]	74	1			T2	2		T51	1		T177	1
auto[160:163]	auto[1]	201	1			T2	1		T10	2		T12	1
auto[164:167]	auto[0]	75	1			T2	1		T43	1		T23	1
auto[164:167]	auto[1]	228	1			T8	1		T12	2		T14	1
auto[168:171]	auto[0]	97	1			T2	4		T5	1		T12	1
auto[168:171]	auto[1]	245	1			T5	1		T10	1		T43	3
auto[172:175]	auto[0]	90	1			T8	3		T12	4		T25	1
auto[172:175]	auto[1]	292	1			T10	1		T12	5		T43	2
auto[176:179]	auto[0]	84	1			T5	1		T12	1		T43	2
auto[176:179]	auto[1]	221	1			T5	4		T12	2		T43	4
auto[180:183]	auto[0]	476	1			T2	7		T5	7		T6	4
auto[180:183]	auto[1]	1384	1			T2	5		T5	2		T6	4
auto[184:187]	auto[0]	463	1			T2	4		T5	5		T8	1
auto[184:187]	auto[1]	878	1			T2	4		T5	4		T10	4
auto[188:191]	auto[0]	103	1			T2	1		T5	1		T7	1
auto[188:191]	auto[1]	239	1			T2	4		T10	3		T14	1
auto[192:195]	auto[0]	68	1			T5	3		T7	1		T43	1
auto[192:195]	auto[1]	275	1			T2	1		T10	1		T15	4
auto[196:199]	auto[0]	104	1			T2	4		T12	1		T43	1
auto[196:199]	auto[1]	253	1			T2	4		T10	2		T43	1
auto[200:203]	auto[0]	79	1			T5	3		T43	4		T44	1
auto[200:203]	auto[1]	259	1			T2	1		T5	2		T10	4
auto[204:207]	auto[0]	60	1			T2	3		T12	2		T192	1
auto[204:207]	auto[1]	267	1			T2	1		T7	2		T10	7
auto[208:211]	auto[0]	67	1			T5	1		T43	3		T92	1
auto[208:211]	auto[1]	228	1			T2	2		T5	1		T15	2
auto[212:215]	auto[0]	76	1			T12	1		T16	1		T92	1
auto[212:215]	auto[1]	246	1			T2	1		T43	1		T25	2
auto[216:219]	auto[0]	87	1			T2	4		T5	3		T43	1
auto[216:219]	auto[1]	252	1			T5	1		T10	3		T43	2
auto[220:223]	auto[0]	73	1			T2	1		T43	1		T25	1
auto[220:223]	auto[1]	297	1			T2	1		T5	1		T10	3
auto[224:227]	auto[0]	81	1			T12	2		T43	4		T44	2
auto[224:227]	auto[1]	253	1			T5	3		T44	2		T14	1
auto[228:231]	auto[0]	71	1			T2	4		T8	1		T25	1
auto[228:231]	auto[1]	239	1			T10	1		T51	1		T15	1
auto[232:235]	auto[0]	870	1			T2	16		T4	1		T5	10
auto[232:235]	auto[1]	2025	1			T2	3		T4	1		T5	5
auto[236:239]	auto[0]	70	1			T2	1		T43	2		T51	1
auto[236:239]	auto[1]	275	1			T43	2		T14	1		T15	4
auto[240:243]	auto[0]	72	1			T2	2		T8	1		T43	1
auto[240:243]	auto[1]	260	1			T5	1		T10	2		T43	2
auto[244:247]	auto[0]	84	1			T44	2		T25	2		T16	1
auto[244:247]	auto[1]	277	1			T2	2		T5	5		T10	1
auto[248:251]	auto[0]	81	1			T5	1		T44	1		T16	1
auto[248:251]	auto[1]	214	1			T2	1		T5	1		T10	1
auto[252:255]	auto[0]	87	1			T43	1		T50	2		T182	1
auto[252:255]	auto[1]	285	1			T43	1		T14	1		T50	2