Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	408	1			T2	10		T8	1		T12	3
auto[ReadAddrCrossIntoMailbox]	287	1			T2	6		T5	2		T12	3
auto[ReadAddrCrossOutOfMailbox]	327	1			T2	1		T5	1		T8	1
auto[ReadAddrCrossAllMailbox]	198	1			T2	8		T4	2		T8	1
auto[ReadAddrOutsideMailbox]	3721	1			T2	38		T4	4		T5	39

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2414

1

T2

39

T4

3

T5

22

auto[1]

2527

1

T2

24

T4

3

T5

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	774	1			T2	13		T4	2		T5	6
read_ops[0x0b]	844	1			T2	9		T5	8		T7	1
read_ops[0x3b]	862	1			T2	13		T4	2		T5	6
read_ops[0x6b]	816	1			T2	11		T5	8		T7	1
read_ops[0xbb]	831	1			T2	7		T5	8		T8	1
read_ops[0xeb]	814	1			T2	10		T4	2		T5	6

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T25	1		T192	1		T191	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T12	1		T43	1		T17	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T2	1		T5	1		T25	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T12	1		T16	1		T192	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T25	1		T51	1		T192	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T192	2		T254	1		T211	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T2	1		T4	1		T98	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T4	1		T43	1		T51	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	261	1			T2	8		T5	5		T7	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	321	1			T2	3		T8	2		T12	5
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T2	1		T12	1		T156	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T2	1		T156	2		T19	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T12	1		T19	1		T84	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T51	1		T84	1		T98	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	36	1			T192	1		T19	2		T224	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T192	1		T98	1		T213	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T2	1		T25	1		T210	3
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T25	1		T51	1		T230	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	310	1			T2	2		T5	6		T12	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	322	1			T2	4		T5	2		T7	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T2	1		T12	1		T25	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T8	1		T156	1		T160	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T2	1		T19	1		T21	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T43	1		T17	1		T198	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	36	1			T2	1		T25	2		T16	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	42	1			T5	1		T8	1		T51	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T2	2		T21	1		T225	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T8	1		T21	1		T181	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	338	1			T2	4		T4	1		T5	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	291	1			T2	4		T4	1		T5	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T51	3		T192	1		T21	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T2	2		T25	2		T92	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T12	1		T191	1		T19	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T2	1		T92	1		T192	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T92	1		T17	1		T191	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T192	1		T191	1		T35	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T2	1		T21	1		T225	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T2	1		T19	1		T211	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	286	1			T2	3		T7	1		T12	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	338	1			T2	3		T5	8		T8	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T121	1		T25	3		T16	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T2	1		T121	1		T17	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T2	1		T5	1		T43	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T92	2		T192	1		T35	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T43	1		T16	1		T92	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T192	1		T35	1		T233	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T25	1		T16	1		T254	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T2	2		T43	1		T192	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	299	1			T2	2		T5	3		T8	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	333	1			T2	1		T5	4		T43	13
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T2	4		T191	1		T19	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T224	1		T84	1		T198	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T2	2		T19	2		T21	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T16	1		T191	1		T35	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T21	2		T205	1		T211	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T25	1		T224	1		T21	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	9	1			T212	2		T230	1		T211	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T25	1		T207	1		T198	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	311	1			T2	3		T4	1		T5	4
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	311	1			T2	1		T4	1		T5	2