Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3831	1			T2	100		T5	58		T12	20
values[1]	4208	1			T4	6		T8	20		T12	20
values[2]	3601	1			T5	53		T8	20		T12	22
values[3]	4400	1			T2	80		T12	20		T43	20
values[4]	3769	1			T5	69		T6	10		T156	8
values[5]	3357	1			T2	20		T5	20		T7	21
values[6]	3198	1			T2	40		T5	20		T8	20
values[7]	3826	1			T2	20		T5	74		T12	127

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3317	1			T2	20		T6	10		T8	20
values[1]	3675	1			T2	80		T5	20		T43	20
values[2]	3713	1			T8	20		T12	22		T43	40
values[3]	4570	1			T2	60		T5	29		T8	20
values[4]	3246	1			T43	60		T54	99		T157	6
values[5]	3967	1			T2	40		T5	91		T12	127
values[6]	3666	1			T2	60		T5	43		T43	60
values[7]	4036	1			T4	6		T5	111		T7	21

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29467

1

T2

252

T4

6

T5

288

auto[1]

723

1

T2

8

T5

6

T8

4

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	545	1			T2	19		T51	18		T210	19
auto[0]	values[0]	values[1]	353	1			T2	37		T43	18		T16	23
auto[0]	values[0]	values[2]	479	1			T209	20		T216	22		T212	20
auto[0]	values[0]	values[3]	534	1			T2	19		T25	20		T51	20
auto[0]	values[0]	values[4]	449	1			T267	6		T19	18		T268	2
auto[0]	values[0]	values[5]	468	1			T12	20		T43	19		T192	19
auto[0]	values[0]	values[6]	384	1			T2	19		T43	20		T247	41
auto[0]	values[0]	values[7]	515	1			T5	58		T19	31		T207	24
auto[0]	values[1]	values[0]	459	1			T43	20		T19	21		T224	20
auto[0]	values[1]	values[1]	326	1			T21	47		T201	19		T269	45
auto[0]	values[1]	values[2]	654	1			T51	20		T92	20		T198	20
auto[0]	values[1]	values[3]	699	1			T8	20		T12	19		T96	26
auto[0]	values[1]	values[4]	353	1			T17	48		T198	19		T233	29
auto[0]	values[1]	values[5]	548	1			T192	20		T19	18		T21	20
auto[0]	values[1]	values[6]	550	1			T95	4		T192	20		T19	20
auto[0]	values[1]	values[7]	552	1			T4	6		T43	20		T21	19
auto[0]	values[2]	values[0]	393	1			T8	18		T25	20		T192	19
auto[0]	values[2]	values[1]	527	1			T35	20		T212	19		T181	21
auto[0]	values[2]	values[2]	407	1			T43	19		T25	21		T17	37
auto[0]	values[2]	values[3]	482	1			T12	21		T43	20		T25	19
auto[0]	values[2]	values[4]	345	1			T210	20		T212	20		T201	23
auto[0]	values[2]	values[5]	482	1			T16	25		T19	20		T207	25
auto[0]	values[2]	values[6]	335	1			T43	16		T38	18		T192	20
auto[0]	values[2]	values[7]	538	1			T5	51		T23	20		T224	20
auto[0]	values[3]	values[0]	640	1			T51	36		T50	26		T19	20
auto[0]	values[3]	values[1]	379	1			T2	20		T44	48		T92	19
auto[0]	values[3]	values[2]	539	1			T25	33		T225	27		T181	21
auto[0]	values[3]	values[3]	530	1			T2	39		T182	84		T92	21
auto[0]	values[3]	values[4]	340	1			T192	20		T191	20		T78	8
auto[0]	values[3]	values[5]	491	1			T121	4		T25	20		T51	19
auto[0]	values[3]	values[6]	622	1			T2	20		T43	20		T25	20
auto[0]	values[3]	values[7]	751	1			T12	20		T192	20		T224	93
auto[0]	values[4]	values[0]	225	1			T6	10		T231	12		T198	20
auto[0]	values[4]	values[1]	518	1			T5	19		T156	8		T143	16
auto[0]	values[4]	values[2]	415	1			T249	4		T92	20		T233	20
auto[0]	values[4]	values[3]	906	1			T5	29		T16	20		T141	18
auto[0]	values[4]	values[4]	434	1			T246	16		T226	84		T270	12
auto[0]	values[4]	values[5]	298	1			T5	20		T98	20		T181	22
auto[0]	values[4]	values[6]	469	1			T16	44		T92	23		T142	8
auto[0]	values[4]	values[7]	406	1			T220	18		T83	31		T35	26
auto[0]	values[5]	values[0]	311	1			T12	20		T192	19		T19	22
auto[0]	values[5]	values[1]	386	1			T2	20		T82	6		T21	32
auto[0]	values[5]	values[2]	473	1			T43	20		T35	40		T216	19
auto[0]	values[5]	values[3]	470	1			T106	18		T159	8		T53	20
auto[0]	values[5]	values[4]	340	1			T43	20		T224	52		T35	68
auto[0]	values[5]	values[5]	364	1			T5	20		T97	22		T17	20
auto[0]	values[5]	values[6]	413	1			T25	19		T238	10		T16	21
auto[0]	values[5]	values[7]	501	1			T7	21		T11	8		T25	20
auto[0]	values[6]	values[0]	358	1			T92	27		T17	25		T192	20
auto[0]	values[6]	values[1]	333	1			T160	2		T230	18		T271	16
auto[0]	values[6]	values[2]	360	1			T8	18		T12	22		T39	2
auto[0]	values[6]	values[3]	457	1			T25	18		T256	12		T21	19
auto[0]	values[6]	values[4]	265	1			T157	6		T35	28		T210	16
auto[0]	values[6]	values[5]	597	1			T2	20		T43	20		T16	20
auto[0]	values[6]	values[6]	409	1			T2	20		T5	18		T17	33
auto[0]	values[6]	values[7]	339	1			T216	34		T272	2		T273	14
auto[0]	values[7]	values[0]	302	1			T198	18		T205	25		T230	45
auto[0]	values[7]	values[1]	744	1			T158	8		T102	18		T191	20
auto[0]	values[7]	values[2]	302	1			T191	20		T224	20		T181	20
auto[0]	values[7]	values[3]	402	1			T12	20		T51	20		T21	46
auto[0]	values[7]	values[4]	645	1			T43	40		T54	99		T98	20
auto[0]	values[7]	values[5]	629	1			T2	19		T5	50		T12	104
auto[0]	values[7]	values[6]	388	1			T5	23		T225	20		T212	44
auto[0]	values[7]	values[7]	339	1			T51	20		T255	16		T227	19
auto[1]	values[0]	values[0]	15	1			T2	1		T51	2		T210	1
auto[1]	values[0]	values[1]	11	1			T2	3		T43	2		T212	2
auto[1]	values[0]	values[2]	10	1			T222	1		T265	3		T274	2
auto[1]	values[0]	values[3]	14	1			T2	1		T198	4		T216	2
auto[1]	values[0]	values[4]	15	1			T267	2		T19	2		T212	2
auto[1]	values[0]	values[5]	12	1			T43	1		T192	1		T234	3
auto[1]	values[0]	values[6]	11	1			T2	1		T92	2		T192	1
auto[1]	values[0]	values[7]	16	1			T19	2		T207	1		T275	4
auto[1]	values[1]	values[0]	5	1			T230	2		T276	1		T277	2
auto[1]	values[1]	values[1]	11	1			T21	2		T201	1		T269	2
auto[1]	values[1]	values[2]	12	1			T213	1		T202	2		T252	1
auto[1]	values[1]	values[3]	8	1			T12	1		T211	1		T278	2
auto[1]	values[1]	values[4]	7	1			T198	1		T233	2		T279	1
auto[1]	values[1]	values[5]	11	1			T19	2		T219	2		T57	1
auto[1]	values[1]	values[6]	6	1			T280	2		T199	1		T172	1
auto[1]	values[1]	values[7]	7	1			T21	1		T201	2		T281	1
auto[1]	values[2]	values[0]	14	1			T8	2		T192	1		T198	2
auto[1]	values[2]	values[1]	25	1			T212	1		T241	1		T213	2
auto[1]	values[2]	values[2]	7	1			T43	1		T25	1		T17	1
auto[1]	values[2]	values[3]	8	1			T12	1		T25	1		T92	2
auto[1]	values[2]	values[4]	5	1			T210	1		T201	1		T41	1
auto[1]	values[2]	values[5]	11	1			T207	1		T21	2		T202	1
auto[1]	values[2]	values[6]	11	1			T43	4		T35	1		T222	1
auto[1]	values[2]	values[7]	11	1			T5	2		T23	4		T252	1
auto[1]	values[3]	values[0]	20	1			T51	4		T35	3		T212	2
auto[1]	values[3]	values[1]	10	1			T92	1		T19	3		T98	1
auto[1]	values[3]	values[2]	15	1			T225	1		T181	1		T230	2
auto[1]	values[3]	values[3]	11	1			T2	1		T92	1		T19	3
auto[1]	values[3]	values[4]	8	1			T211	1		T282	4		T199	2
auto[1]	values[3]	values[5]	11	1			T51	1		T98	1		T210	3
auto[1]	values[3]	values[6]	11	1			T92	1		T237	2		T283	1
auto[1]	values[3]	values[7]	22	1			T224	3		T207	3		T284	2
auto[1]	values[4]	values[0]	2	1			T206	1		T285	1		-	-
auto[1]	values[4]	values[1]	21	1			T5	1		T207	2		T209	2
auto[1]	values[4]	values[2]	8	1			T222	1		T213	3		T286	2
auto[1]	values[4]	values[3]	20	1			T192	1		T19	2		T98	4
auto[1]	values[4]	values[4]	13	1			T226	2		T284	2		T266	3
auto[1]	values[4]	values[5]	4	1			T252	1		T287	2		T60	1
auto[1]	values[4]	values[6]	21	1			T16	4		T92	2		T191	1
auto[1]	values[4]	values[7]	9	1			T83	1		T279	1		T265	3
auto[1]	values[5]	values[0]	9	1			T192	1		T19	1		T198	1
auto[1]	values[5]	values[1]	8	1			T35	3		T288	2		T289	2
auto[1]	values[5]	values[2]	10	1			T216	1		T234	2		T41	1
auto[1]	values[5]	values[3]	18	1			T53	4		T225	1		T212	3
auto[1]	values[5]	values[4]	11	1			T35	7		T290	2		T281	2
auto[1]	values[5]	values[5]	13	1			T269	1		T291	2		T292	4
auto[1]	values[5]	values[6]	11	1			T25	1		T211	1		T264	5
auto[1]	values[5]	values[7]	19	1			T52	8		T207	2		T219	1
auto[1]	values[6]	values[0]	7	1			T17	1		T191	2		T21	1
auto[1]	values[6]	values[1]	12	1			T230	2		T202	2		T293	4
auto[1]	values[6]	values[2]	12	1			T8	2		T35	1		T205	2
auto[1]	values[6]	values[3]	7	1			T25	2		T21	1		T269	1
auto[1]	values[6]	values[4]	11	1			T35	2		T210	4		T211	1
auto[1]	values[6]	values[5]	9	1			T16	1		T211	2		T202	1
auto[1]	values[6]	values[6]	17	1			T5	2		T17	3		T211	2
auto[1]	values[6]	values[7]	5	1			T252	1		T243	1		T294	1
auto[1]	values[7]	values[0]	12	1			T198	2		T252	5		T265	1
auto[1]	values[7]	values[1]	11	1			T212	2		T211	3		T218	2
auto[1]	values[7]	values[2]	10	1			T252	3		T295	1		T296	3
auto[1]	values[7]	values[3]	4	1			T202	1		T276	3		-	-
auto[1]	values[7]	values[4]	5	1			T198	1		T233	2		T146	1
auto[1]	values[7]	values[5]	19	1			T2	1		T5	1		T12	3
auto[1]	values[7]	values[6]	8	1			T212	1		T218	2		T219	1
auto[1]	values[7]	values[7]	6	1			T227	1		T297	2		T61	1