Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	795	1			T14	17		T16	10		T17	10
all_values[1]	795	1			T14	17		T16	10		T17	10
all_values[2]	795	1			T14	17		T16	10		T17	10
all_values[3]	795	1			T14	17		T16	10		T17	10
all_values[4]	795	1			T14	17		T16	10		T17	10
all_values[5]	795	1			T14	17		T16	10		T17	10
all_values[6]	795	1			T14	17		T16	10		T17	10
all_values[7]	795	1			T14	17		T16	10		T17	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3349

1

T14

74

T16

38

T17

41

auto[1]

3011

1

T14

62

T16

42

T17

39

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2459

1

T14

47

T16

31

T17

22

auto[1]

3901

1

T14

89

T16

49

T17

58

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3599

1

T14

69

T16

42

T17

41

auto[1]

2761

1

T14

67

T16

38

T17

39

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	167	1			T14	5		T16	2		T17	1
all_values[0]	auto[0]	auto[0]	auto[1]	85	1			T14	2		T16	1		T17	1
all_values[0]	auto[0]	auto[1]	auto[0]	153	1			T14	4		T16	4		T17	1
all_values[0]	auto[0]	auto[1]	auto[1]	89	1			T18	1		T180	1		T181	1
all_values[0]	auto[1]	auto[0]	auto[1]	165	1			T14	4		T16	1		T17	4
all_values[0]	auto[1]	auto[1]	auto[1]	136	1			T14	2		T16	2		T17	3
all_values[1]	auto[0]	auto[0]	auto[0]	133	1			T14	3		T16	3		T17	3
all_values[1]	auto[0]	auto[0]	auto[1]	80	1			T16	1		T17	1		T18	4
all_values[1]	auto[0]	auto[1]	auto[0]	135	1			T14	4		T17	1		T18	4
all_values[1]	auto[0]	auto[1]	auto[1]	83	1			T14	3		T16	1		T19	1
all_values[1]	auto[1]	auto[0]	auto[1]	198	1			T14	1		T16	3		T17	3
all_values[1]	auto[1]	auto[1]	auto[1]	166	1			T14	6		T16	2		T17	2
all_values[2]	auto[0]	auto[0]	auto[0]	146	1			T14	1		T16	1		T35	3
all_values[2]	auto[0]	auto[0]	auto[1]	83	1			T14	2		T16	1		T17	2
all_values[2]	auto[0]	auto[1]	auto[0]	126	1			T14	1		T16	2		T18	4
all_values[2]	auto[0]	auto[1]	auto[1]	89	1			T14	3		T17	2		T18	2
all_values[2]	auto[1]	auto[0]	auto[1]	186	1			T14	5		T16	2		T17	4
all_values[2]	auto[1]	auto[1]	auto[1]	165	1			T14	5		T16	4		T17	2
all_values[3]	auto[0]	auto[0]	auto[0]	148	1			T14	3		T18	1		T180	1
all_values[3]	auto[0]	auto[0]	auto[1]	83	1			T14	2		T16	2		T17	1
all_values[3]	auto[0]	auto[1]	auto[0]	132	1			T14	2		T16	3		T17	2
all_values[3]	auto[0]	auto[1]	auto[1]	69	1			T17	3		T18	1		T35	1
all_values[3]	auto[1]	auto[0]	auto[1]	208	1			T14	7		T16	4		T17	1
all_values[3]	auto[1]	auto[1]	auto[1]	155	1			T14	3		T16	1		T17	3
all_values[4]	auto[0]	auto[0]	auto[0]	193	1			T14	4		T16	1		T17	1
all_values[4]	auto[0]	auto[0]	auto[1]	68	1			T14	2		T16	1		T17	3
all_values[4]	auto[0]	auto[1]	auto[0]	119	1			T14	4		T16	1		T18	3
all_values[4]	auto[0]	auto[1]	auto[1]	78	1			T17	2		T35	2		T181	1
all_values[4]	auto[1]	auto[0]	auto[1]	182	1			T14	5		T16	2		T17	3
all_values[4]	auto[1]	auto[1]	auto[1]	155	1			T14	2		T16	5		T17	1
all_values[5]	auto[0]	auto[0]	auto[0]	231	1			T14	4		T16	4		T17	3
all_values[5]	auto[0]	auto[1]	auto[0]	219	1			T14	4		T16	1		T17	1
all_values[5]	auto[1]	auto[0]	auto[1]	185	1			T14	2		T16	2		T17	2
all_values[5]	auto[1]	auto[1]	auto[1]	160	1			T14	7		T16	3		T17	4
all_values[6]	auto[0]	auto[0]	auto[0]	152	1			T14	1		T16	5		T17	2
all_values[6]	auto[0]	auto[0]	auto[1]	85	1			T14	3		T17	1		T18	2
all_values[6]	auto[0]	auto[1]	auto[0]	138	1			T14	4		T16	2		T17	2
all_values[6]	auto[0]	auto[1]	auto[1]	83	1			T16	1		T17	1		T18	1
all_values[6]	auto[1]	auto[0]	auto[1]	163	1			T14	6		T17	1		T18	5
all_values[6]	auto[1]	auto[1]	auto[1]	174	1			T14	3		T16	2		T17	3
all_values[7]	auto[0]	auto[0]	auto[0]	124	1			T17	2		T18	1		T19	2
all_values[7]	auto[0]	auto[0]	auto[1]	90	1			T14	4		T17	1		T18	4
all_values[7]	auto[0]	auto[1]	auto[0]	143	1			T14	3		T16	2		T17	3
all_values[7]	auto[0]	auto[1]	auto[1]	75	1			T14	1		T16	3		T17	1
all_values[7]	auto[1]	auto[0]	auto[1]	194	1			T14	8		T16	2		T17	1
all_values[7]	auto[1]	auto[1]	auto[1]	169	1			T14	1		T16	3		T17	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal