Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1780

1

T3

1

T5

4

T7

1

auto[1]

1770

1

T5

3

T7

1

T12

2

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1845

1

T3

1

T5

6

T7

2

auto[1]

1705

1

T5

1

T29

1

T33

12

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2815

1

T3

1

T5

6

T7

1

auto[1]

735

1

T5

1

T7

1

T12

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	693	1			T3	1		T5	2		T12	1
valid[1]	710	1			T5	2		T29	1		T30	4
valid[2]	711	1			T12	2		T30	5		T33	5
valid[3]	744	1			T12	2		T29	1		T30	3
valid[4]	692	1			T5	3		T7	2		T12	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	108	1			T3	1		T30	2		T15	2
auto[0]	auto[0]	valid[0]	auto[1]	163	1			T34	1		T65	1		T94	3
auto[0]	auto[0]	valid[1]	auto[0]	110	1			T5	1		T25	2		T64	1
auto[0]	auto[0]	valid[1]	auto[1]	158	1			T33	1		T34	4		T24	2
auto[0]	auto[0]	valid[2]	auto[0]	111	1			T30	2		T25	2		T15	2
auto[0]	auto[0]	valid[2]	auto[1]	175	1			T33	4		T34	7		T24	4
auto[0]	auto[0]	valid[3]	auto[0]	123	1			T12	1		T30	1		T25	1
auto[0]	auto[0]	valid[3]	auto[1]	179	1			T33	2		T34	2		T24	1
auto[0]	auto[0]	valid[4]	auto[0]	98	1			T5	1		T12	2		T25	1
auto[0]	auto[0]	valid[4]	auto[1]	179	1			T5	1		T34	1		T24	2
auto[0]	auto[1]	valid[0]	auto[0]	126	1			T5	1		T12	1		T25	1
auto[0]	auto[1]	valid[0]	auto[1]	166	1			T33	2		T34	1		T24	2
auto[0]	auto[1]	valid[1]	auto[0]	116	1			T5	1		T29	1		T30	2
auto[0]	auto[1]	valid[1]	auto[1]	177	1			T33	1		T24	5		T64	1
auto[0]	auto[1]	valid[2]	auto[0]	106	1			T12	1		T14	1		T25	1
auto[0]	auto[1]	valid[2]	auto[1]	160	1			T33	1		T34	7		T93	1
auto[0]	auto[1]	valid[3]	auto[0]	113	1			T30	1		T92	1		T19	3
auto[0]	auto[1]	valid[3]	auto[1]	179	1			T29	1		T34	3		T24	4
auto[0]	auto[1]	valid[4]	auto[0]	99	1			T5	1		T7	1		T25	2
auto[0]	auto[1]	valid[4]	auto[1]	169	1			T33	1		T34	3		T93	1
auto[1]	auto[0]	valid[0]	auto[0]	66	1			T5	1		T14	1		T64	1
auto[1]	auto[0]	valid[1]	auto[0]	71	1			T22	1		T92	2		T178	1
auto[1]	auto[0]	valid[2]	auto[0]	88	1			T12	1		T30	3		T15	1
auto[1]	auto[0]	valid[3]	auto[0]	72	1			T12	1		T15	2		T64	1
auto[1]	auto[0]	valid[4]	auto[0]	79	1			T7	1		T30	2		T15	1
auto[1]	auto[1]	valid[0]	auto[0]	64	1			T15	1		T64	1		T16	1
auto[1]	auto[1]	valid[1]	auto[0]	78	1			T30	2		T15	1		T92	1
auto[1]	auto[1]	valid[2]	auto[0]	71	1			T25	1		T178	1		T19	1
auto[1]	auto[1]	valid[3]	auto[0]	78	1			T30	1		T25	4		T15	1
auto[1]	auto[1]	valid[4]	auto[0]	68	1			T25	1		T64	1		T178	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal