Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45747

1

T1

6

T3

9

T5

66

auto[1]

17060

1

T5

12

T29

15

T33

12

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45626

1

T1

2

T3

7

T5

50

auto[1]

17181

1

T1

4

T3

2

T5

28

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32262	1			T1	2		T3	3		T5	42
others[1]	5464	1			T5	8		T7	13		T12	5
others[2]	5253	1			T3	1		T5	3		T7	8
others[3]	5965	1			T1	2		T3	3		T5	5
interest[1]	3420	1			T5	6		T7	2		T12	11
interest[4]	21154	1			T1	1		T3	2		T5	21
interest[64]	10443	1			T1	2		T3	2		T5	14

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14533	1			T1	1		T3	3		T5	24
auto[0]	auto[0]	others[1]	2448	1			T5	3		T7	9		T12	2
auto[0]	auto[0]	others[2]	2376	1			T7	7		T12	7		T29	1
auto[0]	auto[0]	others[3]	2820	1			T1	1		T3	2		T5	4
auto[0]	auto[0]	interest[1]	1612	1			T5	3		T7	2		T12	10
auto[0]	auto[0]	interest[4]	9457	1			T3	2		T5	11		T7	20
auto[0]	auto[0]	interest[64]	4777	1			T3	2		T5	4		T7	15
auto[0]	auto[1]	others[0]	8939	1			T5	4		T29	11		T33	12
auto[0]	auto[1]	others[1]	1513	1			T5	1		T34	33		T24	24
auto[0]	auto[1]	others[2]	1439	1			T5	2		T29	2		T34	32
auto[0]	auto[1]	others[3]	1574	1			T34	26		T24	16		T62	1
auto[0]	auto[1]	interest[1]	884	1			T29	1		T34	16		T24	15
auto[0]	auto[1]	interest[4]	6000	1			T5	2		T29	9		T33	12
auto[0]	auto[1]	interest[64]	2711	1			T5	5		T29	1		T34	47
auto[1]	auto[0]	others[0]	8790	1			T1	1		T5	14		T7	14
auto[1]	auto[0]	others[1]	1503	1			T5	4		T7	4		T12	3
auto[1]	auto[0]	others[2]	1438	1			T3	1		T5	1		T7	1
auto[1]	auto[0]	others[3]	1571	1			T1	1		T3	1		T5	1
auto[1]	auto[0]	interest[1]	924	1			T5	3		T12	1		T29	1
auto[1]	auto[0]	interest[4]	5697	1			T1	1		T5	8		T7	9
auto[1]	auto[0]	interest[64]	2955	1			T1	2		T5	5		T7	10

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal