Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1131
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T1030 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2190338068 Jul 17 07:18:55 PM PDT 24 Jul 17 07:19:09 PM PDT 24 23826877 ps
T183 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2194147 Jul 17 07:19:00 PM PDT 24 Jul 17 07:19:29 PM PDT 24 1079453943 ps
T1031 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3100975775 Jul 17 07:18:57 PM PDT 24 Jul 17 07:19:19 PM PDT 24 181824973 ps
T1032 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.4284170567 Jul 17 07:18:56 PM PDT 24 Jul 17 07:19:11 PM PDT 24 12847023 ps
T164 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3264460217 Jul 17 07:19:05 PM PDT 24 Jul 17 07:19:32 PM PDT 24 105160586 ps
T1033 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.412785144 Jul 17 07:19:01 PM PDT 24 Jul 17 07:19:26 PM PDT 24 1607167313 ps
T165 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2827046062 Jul 17 07:19:06 PM PDT 24 Jul 17 07:19:33 PM PDT 24 296936361 ps
T1034 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.379452582 Jul 17 07:18:58 PM PDT 24 Jul 17 07:19:22 PM PDT 24 940370838 ps
T1035 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3428381225 Jul 17 07:18:56 PM PDT 24 Jul 17 07:19:10 PM PDT 24 24306432 ps
T1036 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.4101762447 Jul 17 07:19:01 PM PDT 24 Jul 17 07:19:23 PM PDT 24 44859345 ps
T116 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3421055030 Jul 17 07:19:06 PM PDT 24 Jul 17 07:19:33 PM PDT 24 44987940 ps
T1037 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2065358464 Jul 17 07:19:02 PM PDT 24 Jul 17 07:19:27 PM PDT 24 51101465 ps
T115 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1105463424 Jul 17 07:19:05 PM PDT 24 Jul 17 07:19:33 PM PDT 24 151663186 ps
T1038 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3163560713 Jul 17 07:19:01 PM PDT 24 Jul 17 07:19:26 PM PDT 24 19599631 ps
T1039 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2072059116 Jul 17 07:18:56 PM PDT 24 Jul 17 07:19:11 PM PDT 24 13281120 ps
T128 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.180566176 Jul 17 07:18:58 PM PDT 24 Jul 17 07:19:26 PM PDT 24 109084203 ps
T110 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2914187920 Jul 17 07:19:09 PM PDT 24 Jul 17 07:19:34 PM PDT 24 971364975 ps
T111 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2718680151 Jul 17 07:19:00 PM PDT 24 Jul 17 07:19:26 PM PDT 24 180792805 ps
T1040 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1200371680 Jul 17 07:19:02 PM PDT 24 Jul 17 07:19:26 PM PDT 24 20844781 ps
T1041 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1543605029 Jul 17 07:18:57 PM PDT 24 Jul 17 07:19:18 PM PDT 24 20405575 ps
T1042 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2977282545 Jul 17 07:18:56 PM PDT 24 Jul 17 07:19:22 PM PDT 24 681472209 ps
T1043 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2876788132 Jul 17 07:19:06 PM PDT 24 Jul 17 07:19:34 PM PDT 24 470240168 ps
T1044 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3200036168 Jul 17 07:18:58 PM PDT 24 Jul 17 07:19:18 PM PDT 24 10435703 ps
T1045 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2218339084 Jul 17 07:19:08 PM PDT 24 Jul 17 07:19:32 PM PDT 24 39806973 ps
T129 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2577514313 Jul 17 07:19:01 PM PDT 24 Jul 17 07:19:24 PM PDT 24 140667874 ps
T166 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3255199667 Jul 17 07:19:01 PM PDT 24 Jul 17 07:19:45 PM PDT 24 6548208245 ps
T1046 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3926460679 Jul 17 07:19:01 PM PDT 24 Jul 17 07:19:23 PM PDT 24 26229668 ps
T1047 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.474426412 Jul 17 07:19:01 PM PDT 24 Jul 17 07:19:27 PM PDT 24 50838116 ps
T130 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2100282858 Jul 17 07:18:57 PM PDT 24 Jul 17 07:19:20 PM PDT 24 64161356 ps
T1048 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1646155717 Jul 17 07:19:01 PM PDT 24 Jul 17 07:19:26 PM PDT 24 24473431 ps
T1049 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3969750423 Jul 17 07:19:06 PM PDT 24 Jul 17 07:19:31 PM PDT 24 32616061 ps
T184 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1869000456 Jul 17 07:19:07 PM PDT 24 Jul 17 07:19:49 PM PDT 24 290565263 ps
T1050 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2296588045 Jul 17 07:19:09 PM PDT 24 Jul 17 07:19:36 PM PDT 24 194226162 ps
T113 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1965218139 Jul 17 07:18:58 PM PDT 24 Jul 17 07:19:20 PM PDT 24 54923025 ps
T1051 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3610293672 Jul 17 07:18:54 PM PDT 24 Jul 17 07:19:04 PM PDT 24 35828857 ps
T185 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2049318579 Jul 17 07:19:09 PM PDT 24 Jul 17 07:19:39 PM PDT 24 115475321 ps
T1052 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.438510034 Jul 17 07:19:07 PM PDT 24 Jul 17 07:19:32 PM PDT 24 47665421 ps
T1053 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.962516731 Jul 17 07:18:57 PM PDT 24 Jul 17 07:19:11 PM PDT 24 13917119 ps
T131 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.496479768 Jul 17 07:19:06 PM PDT 24 Jul 17 07:19:32 PM PDT 24 159959365 ps
T132 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3639693314 Jul 17 07:18:57 PM PDT 24 Jul 17 07:19:16 PM PDT 24 76075873 ps
T1054 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2112852200 Jul 17 07:19:07 PM PDT 24 Jul 17 07:19:32 PM PDT 24 14445673 ps
T1055 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2354467758 Jul 17 07:18:57 PM PDT 24 Jul 17 07:19:14 PM PDT 24 14207082 ps
T167 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.539466461 Jul 17 07:18:53 PM PDT 24 Jul 17 07:19:01 PM PDT 24 220825596 ps
T1056 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3607665809 Jul 17 07:18:57 PM PDT 24 Jul 17 07:19:13 PM PDT 24 29046942 ps
T133 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3189518287 Jul 17 07:19:05 PM PDT 24 Jul 17 07:20:03 PM PDT 24 1111370062 ps
T1057 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1829815074 Jul 17 07:18:58 PM PDT 24 Jul 17 07:19:19 PM PDT 24 47631661 ps
T168 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3721497742 Jul 17 07:18:50 PM PDT 24 Jul 17 07:18:54 PM PDT 24 377504535 ps
T1058 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.620914746 Jul 17 07:19:17 PM PDT 24 Jul 17 07:19:39 PM PDT 24 215936147 ps
T179 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1990410085 Jul 17 07:19:02 PM PDT 24 Jul 17 07:19:28 PM PDT 24 125453922 ps
T1059 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1743253168 Jul 17 07:19:05 PM PDT 24 Jul 17 07:19:30 PM PDT 24 16134332 ps
T1060 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2248443201 Jul 17 07:19:06 PM PDT 24 Jul 17 07:19:32 PM PDT 24 26490209 ps
T1061 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3565881098 Jul 17 07:18:56 PM PDT 24 Jul 17 07:19:11 PM PDT 24 26590787 ps
T1062 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.168459518 Jul 17 07:19:06 PM PDT 24 Jul 17 07:19:32 PM PDT 24 41570132 ps
T1063 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1191992658 Jul 17 07:18:57 PM PDT 24 Jul 17 07:19:33 PM PDT 24 2529512826 ps
T1064 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.4162241693 Jul 17 07:18:56 PM PDT 24 Jul 17 07:19:10 PM PDT 24 103687001 ps
T1065 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3081159303 Jul 17 07:18:57 PM PDT 24 Jul 17 07:19:15 PM PDT 24 33077105 ps
T1066 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3574498043 Jul 17 07:18:57 PM PDT 24 Jul 17 07:19:24 PM PDT 24 3151352896 ps
T1067 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1428793076 Jul 17 07:18:56 PM PDT 24 Jul 17 07:19:17 PM PDT 24 371574865 ps
T1068 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.40231851 Jul 17 07:19:03 PM PDT 24 Jul 17 07:19:28 PM PDT 24 29041188 ps
T1069 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1539286094 Jul 17 07:18:56 PM PDT 24 Jul 17 07:19:13 PM PDT 24 219915408 ps
T1070 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2505708737 Jul 17 07:19:02 PM PDT 24 Jul 17 07:19:40 PM PDT 24 2835993066 ps
T1071 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2789600186 Jul 17 07:18:58 PM PDT 24 Jul 17 07:19:20 PM PDT 24 247591168 ps
T189 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1533023568 Jul 17 07:18:57 PM PDT 24 Jul 17 07:19:36 PM PDT 24 4107810080 ps
T1072 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3592098780 Jul 17 07:19:01 PM PDT 24 Jul 17 07:19:26 PM PDT 24 31011136 ps
T190 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2769761379 Jul 17 07:18:55 PM PDT 24 Jul 17 07:19:18 PM PDT 24 423715731 ps
T1073 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.734073488 Jul 17 07:19:00 PM PDT 24 Jul 17 07:19:24 PM PDT 24 1270382805 ps
T1074 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.16668825 Jul 17 07:19:02 PM PDT 24 Jul 17 07:19:26 PM PDT 24 14676516 ps
T1075 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2896844754 Jul 17 07:19:00 PM PDT 24 Jul 17 07:19:24 PM PDT 24 157342304 ps
T187 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3629029780 Jul 17 07:19:05 PM PDT 24 Jul 17 07:19:49 PM PDT 24 1219610594 ps
T1076 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3416943021 Jul 17 07:19:01 PM PDT 24 Jul 17 07:19:23 PM PDT 24 13488063 ps
T134 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.4094208589 Jul 17 07:18:56 PM PDT 24 Jul 17 07:19:31 PM PDT 24 15031896961 ps
T1077 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3882813873 Jul 17 07:19:06 PM PDT 24 Jul 17 07:19:33 PM PDT 24 200520065 ps
T1078 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3553347630 Jul 17 07:18:56 PM PDT 24 Jul 17 07:19:13 PM PDT 24 309207700 ps
T135 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.54596108 Jul 17 07:18:57 PM PDT 24 Jul 17 07:19:52 PM PDT 24 1879995504 ps
T1079 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.760471978 Jul 17 07:20:45 PM PDT 24 Jul 17 07:20:57 PM PDT 24 11107012 ps
T1080 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3084767455 Jul 17 07:18:57 PM PDT 24 Jul 17 07:19:20 PM PDT 24 65572125 ps
T1081 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3563515953 Jul 17 07:18:57 PM PDT 24 Jul 17 07:19:15 PM PDT 24 99421269 ps
T1082 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.58628844 Jul 17 07:18:57 PM PDT 24 Jul 17 07:19:16 PM PDT 24 97519741 ps
T1083 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3557126937 Jul 17 07:20:44 PM PDT 24 Jul 17 07:20:53 PM PDT 24 34370664 ps
T1084 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3871604824 Jul 17 07:19:00 PM PDT 24 Jul 17 07:19:22 PM PDT 24 12399096 ps
T1085 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.551141194 Jul 17 07:19:08 PM PDT 24 Jul 17 07:19:32 PM PDT 24 13689518 ps
T1086 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3240626429 Jul 17 07:18:57 PM PDT 24 Jul 17 07:19:14 PM PDT 24 12750005 ps
T1087 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.534815896 Jul 17 07:19:07 PM PDT 24 Jul 17 07:19:32 PM PDT 24 30561089 ps
T1088 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2276911991 Jul 17 07:19:08 PM PDT 24 Jul 17 07:19:32 PM PDT 24 14839723 ps
T1089 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2668208149 Jul 17 07:19:07 PM PDT 24 Jul 17 07:19:34 PM PDT 24 502840075 ps
T1090 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2219468827 Jul 17 07:19:06 PM PDT 24 Jul 17 07:19:32 PM PDT 24 66871228 ps
T1091 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2497948884 Jul 17 07:18:57 PM PDT 24 Jul 17 07:19:19 PM PDT 24 214345246 ps
T1092 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1647246336 Jul 17 07:18:55 PM PDT 24 Jul 17 07:19:10 PM PDT 24 168717182 ps
T1093 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1810605921 Jul 17 07:19:02 PM PDT 24 Jul 17 07:19:28 PM PDT 24 74696952 ps
T1094 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3888492757 Jul 17 07:18:56 PM PDT 24 Jul 17 07:19:11 PM PDT 24 15958517 ps
T90 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1774840492 Jul 17 07:18:58 PM PDT 24 Jul 17 07:19:19 PM PDT 24 22730956 ps
T188 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2580601234 Jul 17 07:19:02 PM PDT 24 Jul 17 07:19:44 PM PDT 24 3185619295 ps
T1095 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.753849516 Jul 17 07:18:56 PM PDT 24 Jul 17 07:19:14 PM PDT 24 250070093 ps
T1096 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1579443950 Jul 17 07:18:56 PM PDT 24 Jul 17 07:19:17 PM PDT 24 295072357 ps
T1097 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1641721362 Jul 17 07:19:06 PM PDT 24 Jul 17 07:19:31 PM PDT 24 15561077 ps
T1098 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2625155725 Jul 17 07:18:57 PM PDT 24 Jul 17 07:19:29 PM PDT 24 1345148250 ps
T1099 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.625512696 Jul 17 07:19:06 PM PDT 24 Jul 17 07:19:35 PM PDT 24 268813501 ps
T1100 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3602578918 Jul 17 07:18:57 PM PDT 24 Jul 17 07:19:18 PM PDT 24 80651330 ps
T1101 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.999199518 Jul 17 07:18:58 PM PDT 24 Jul 17 07:19:20 PM PDT 24 44800208 ps
T1102 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.152540043 Jul 17 07:18:48 PM PDT 24 Jul 17 07:19:30 PM PDT 24 5401402941 ps
T1103 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1549334501 Jul 17 07:18:57 PM PDT 24 Jul 17 07:19:13 PM PDT 24 23960681 ps
T1104 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3314999569 Jul 17 07:19:06 PM PDT 24 Jul 17 07:19:31 PM PDT 24 15773542 ps
T1105 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3217020126 Jul 17 07:20:38 PM PDT 24 Jul 17 07:20:40 PM PDT 24 52788192 ps
T1106 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1738634141 Jul 17 07:18:57 PM PDT 24 Jul 17 07:19:17 PM PDT 24 312038086 ps
T1107 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3067860058 Jul 17 07:18:57 PM PDT 24 Jul 17 07:19:14 PM PDT 24 13739298 ps
T1108 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3109009084 Jul 17 07:18:57 PM PDT 24 Jul 17 07:19:19 PM PDT 24 39199218 ps
T1109 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2883109632 Jul 17 07:18:56 PM PDT 24 Jul 17 07:19:11 PM PDT 24 227966776 ps
T1110 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4178340568 Jul 17 07:18:58 PM PDT 24 Jul 17 07:19:22 PM PDT 24 155428985 ps
T1111 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1059991261 Jul 17 07:18:54 PM PDT 24 Jul 17 07:19:01 PM PDT 24 16608982 ps
T1112 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.4037650398 Jul 17 07:19:00 PM PDT 24 Jul 17 07:19:25 PM PDT 24 40532467 ps
T1113 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.4082692249 Jul 17 07:18:55 PM PDT 24 Jul 17 07:19:13 PM PDT 24 673780798 ps
T1114 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2675834866 Jul 17 07:19:00 PM PDT 24 Jul 17 07:19:42 PM PDT 24 1649792826 ps
T1115 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1553622618 Jul 17 07:19:06 PM PDT 24 Jul 17 07:19:33 PM PDT 24 82257807 ps
T1116 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2832005798 Jul 17 07:20:37 PM PDT 24 Jul 17 07:20:38 PM PDT 24 58548006 ps
T91 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.960364998 Jul 17 07:18:56 PM PDT 24 Jul 17 07:19:10 PM PDT 24 39571777 ps
T1117 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.375043758 Jul 17 07:18:56 PM PDT 24 Jul 17 07:19:10 PM PDT 24 50958168 ps
T1118 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1052449730 Jul 17 07:19:00 PM PDT 24 Jul 17 07:19:37 PM PDT 24 2615903780 ps
T1119 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2314610827 Jul 17 07:18:56 PM PDT 24 Jul 17 07:19:13 PM PDT 24 232212559 ps
T186 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1225454362 Jul 17 07:18:58 PM PDT 24 Jul 17 07:19:34 PM PDT 24 294995580 ps
T1120 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1404593125 Jul 17 07:19:00 PM PDT 24 Jul 17 07:19:23 PM PDT 24 29914229 ps
T1121 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3679080515 Jul 17 07:19:07 PM PDT 24 Jul 17 07:19:32 PM PDT 24 29921573 ps
T1122 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1577619700 Jul 17 07:18:57 PM PDT 24 Jul 17 07:19:12 PM PDT 24 159977674 ps
T1123 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.46778640 Jul 17 07:19:00 PM PDT 24 Jul 17 07:19:23 PM PDT 24 79193645 ps
T1124 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1371758800 Jul 17 07:19:08 PM PDT 24 Jul 17 07:19:34 PM PDT 24 154431183 ps
T1125 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1893991583 Jul 17 07:18:57 PM PDT 24 Jul 17 07:19:18 PM PDT 24 12160402 ps
T1126 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3560703377 Jul 17 07:18:53 PM PDT 24 Jul 17 07:19:01 PM PDT 24 37085975 ps
T1127 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.4136966844 Jul 17 07:18:56 PM PDT 24 Jul 17 07:19:11 PM PDT 24 16956456 ps
T1128 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.700645861 Jul 17 07:18:53 PM PDT 24 Jul 17 07:18:56 PM PDT 24 21724568 ps
T1129 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2660840240 Jul 17 07:19:06 PM PDT 24 Jul 17 07:19:31 PM PDT 24 21836351 ps
T1130 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3299037222 Jul 17 07:18:58 PM PDT 24 Jul 17 07:19:26 PM PDT 24 1001256652 ps
T1131 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1006258690 Jul 17 07:18:57 PM PDT 24 Jul 17 07:19:19 PM PDT 24 70281455 ps

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2230726191
Short name T5
Test name
Test status
Simulation time 7692467754 ps
CPU time 74.95 seconds
Started Jul 17 07:51:47 PM PDT 24
Finished Jul 17 07:53:07 PM PDT 24
Peak memory 260460 kb
Host smart-1f9d38d6-fb98-4d40-84e9-0471eb00c29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230726191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2230726191
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.7229537
Short name T14
Test name
Test status
Simulation time 101424982322 ps
CPU time 76.81 seconds
Started Jul 17 07:50:55 PM PDT 24
Finished Jul 17 07:52:14 PM PDT 24
Peak memory 224672 kb
Host smart-cd10db22-fad9-4401-8b09-a81354fe7eed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7229537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stress_
all.7229537
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1676199497
Short name T19
Test name
Test status
Simulation time 54040580805 ps
CPU time 664.69 seconds
Started Jul 17 07:51:42 PM PDT 24
Finished Jul 17 08:02:48 PM PDT 24
Peak memory 305008 kb
Host smart-389e31c0-31f2-4e87-a32e-bf6bdbcb4980
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676199497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1676199497
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1101012114
Short name T118
Test name
Test status
Simulation time 218834251 ps
CPU time 2.93 seconds
Started Jul 17 07:18:55 PM PDT 24
Finished Jul 17 07:19:10 PM PDT 24
Peak memory 218644 kb
Host smart-e9f6db61-6f2d-4a53-b213-32740e754ce0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101012114 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1101012114
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3620096238
Short name T25
Test name
Test status
Simulation time 40813575438 ps
CPU time 240.97 seconds
Started Jul 17 07:49:48 PM PDT 24
Finished Jul 17 07:53:52 PM PDT 24
Peak memory 252340 kb
Host smart-505f557d-2452-4e57-b5ed-100a4e9a8282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620096238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3620096238
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1340403413
Short name T17
Test name
Test status
Simulation time 65251761431 ps
CPU time 129.66 seconds
Started Jul 17 07:50:16 PM PDT 24
Finished Jul 17 07:52:27 PM PDT 24
Peak memory 251736 kb
Host smart-b8df9cce-aebd-46b3-bb8f-9242e53a6f57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340403413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1340403413
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.2065041279
Short name T2
Test name
Test status
Simulation time 131597665201 ps
CPU time 297.45 seconds
Started Jul 17 07:48:36 PM PDT 24
Finished Jul 17 07:53:34 PM PDT 24
Peak memory 253284 kb
Host smart-5e6e53bf-c333-46cd-812a-9af16e81ebf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065041279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.2065041279
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3399071504
Short name T73
Test name
Test status
Simulation time 35696795 ps
CPU time 0.73 seconds
Started Jul 17 07:47:52 PM PDT 24
Finished Jul 17 07:47:53 PM PDT 24
Peak memory 216084 kb
Host smart-f048fd81-7e17-49cf-8da9-3774195a6766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399071504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3399071504
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.4250456757
Short name T35
Test name
Test status
Simulation time 86838780305 ps
CPU time 556.57 seconds
Started Jul 17 07:48:39 PM PDT 24
Finished Jul 17 07:57:59 PM PDT 24
Peak memory 287464 kb
Host smart-7579bbe6-240c-40de-8a02-23056469dbac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250456757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.4250456757
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1203495794
Short name T20
Test name
Test status
Simulation time 55766893 ps
CPU time 1.06 seconds
Started Jul 17 07:47:51 PM PDT 24
Finished Jul 17 07:47:53 PM PDT 24
Peak memory 236616 kb
Host smart-79180fb6-d847-4a45-8065-ee27e98d8cc2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203495794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1203495794
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.883476539
Short name T21
Test name
Test status
Simulation time 68139673023 ps
CPU time 622.27 seconds
Started Jul 17 07:51:45 PM PDT 24
Finished Jul 17 08:02:12 PM PDT 24
Peak memory 287124 kb
Host smart-c7f59962-d587-4132-bac7-1e6bafa9f271
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883476539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.883476539
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.973835290
Short name T15
Test name
Test status
Simulation time 381699199893 ps
CPU time 408.04 seconds
Started Jul 17 07:51:21 PM PDT 24
Finished Jul 17 07:58:12 PM PDT 24
Peak memory 255840 kb
Host smart-2b7aa804-6fff-4630-91d5-9bd6cc77a2d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973835290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.973835290
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3091530335
Short name T152
Test name
Test status
Simulation time 17083689876 ps
CPU time 33.88 seconds
Started Jul 17 07:51:19 PM PDT 24
Finished Jul 17 07:51:55 PM PDT 24
Peak memory 224596 kb
Host smart-5f148f34-ecb6-47b5-b9a7-9b18acc1b58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091530335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3091530335
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3255199667
Short name T166
Test name
Test status
Simulation time 6548208245 ps
CPU time 22.86 seconds
Started Jul 17 07:19:01 PM PDT 24
Finished Jul 17 07:19:45 PM PDT 24
Peak memory 216388 kb
Host smart-1c87a907-05c2-4ff0-8f4c-79c49e7a3628
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255199667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3255199667
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3024956863
Short name T211
Test name
Test status
Simulation time 604949970524 ps
CPU time 1176.78 seconds
Started Jul 17 07:51:18 PM PDT 24
Finished Jul 17 08:10:56 PM PDT 24
Peak memory 269332 kb
Host smart-a5c07d0d-c414-418d-ab69-7e53783c9dcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024956863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3024956863
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3484559136
Short name T103
Test name
Test status
Simulation time 234987304 ps
CPU time 2.95 seconds
Started Jul 17 07:19:09 PM PDT 24
Finished Jul 17 07:19:35 PM PDT 24
Peak memory 216144 kb
Host smart-fd907bc3-b3f6-4f3b-a565-55d6b54068dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484559136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3484559136
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.4108387770
Short name T252
Test name
Test status
Simulation time 384752876222 ps
CPU time 879.15 seconds
Started Jul 17 07:48:38 PM PDT 24
Finished Jul 17 08:03:21 PM PDT 24
Peak memory 265712 kb
Host smart-3218766b-ef0b-4d76-80e6-26ed885deb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108387770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.4108387770
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.4170002233
Short name T123
Test name
Test status
Simulation time 83543946 ps
CPU time 2.23 seconds
Started Jul 17 07:18:59 PM PDT 24
Finished Jul 17 07:19:21 PM PDT 24
Peak memory 215916 kb
Host smart-25c6fdbd-5525-4e7c-abff-04f9d255ca8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170002233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
4170002233
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1927041611
Short name T233
Test name
Test status
Simulation time 11647270362 ps
CPU time 184.96 seconds
Started Jul 17 07:50:38 PM PDT 24
Finished Jul 17 07:53:45 PM PDT 24
Peak memory 256580 kb
Host smart-0954a2cc-e6a0-44ea-89f9-3b02143333af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927041611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1927041611
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.4264300436
Short name T212
Test name
Test status
Simulation time 1497570214598 ps
CPU time 538.23 seconds
Started Jul 17 07:49:59 PM PDT 24
Finished Jul 17 07:59:03 PM PDT 24
Peak memory 265720 kb
Host smart-b82cb10c-dbfe-4486-a7ec-4a60e3cec028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264300436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.4264300436
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.3904065440
Short name T217
Test name
Test status
Simulation time 117143970958 ps
CPU time 224.39 seconds
Started Jul 17 07:50:09 PM PDT 24
Finished Jul 17 07:53:54 PM PDT 24
Peak memory 249208 kb
Host smart-c6a29008-78d4-45c4-b9f7-1343f3bbb78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904065440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.3904065440
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1865594139
Short name T284
Test name
Test status
Simulation time 478576846513 ps
CPU time 290.06 seconds
Started Jul 17 07:48:36 PM PDT 24
Finished Jul 17 07:53:27 PM PDT 24
Peak memory 252128 kb
Host smart-54e2b2c3-4634-4d8d-b744-3de3031e1cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865594139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1865594139
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1397467703
Short name T18
Test name
Test status
Simulation time 10044539607 ps
CPU time 103.14 seconds
Started Jul 17 07:49:52 PM PDT 24
Finished Jul 17 07:51:38 PM PDT 24
Peak memory 256992 kb
Host smart-a5e816ee-56f6-4701-ba44-26258ce8afcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397467703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1397467703
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1217155901
Short name T68
Test name
Test status
Simulation time 40452368 ps
CPU time 0.7 seconds
Started Jul 17 07:49:16 PM PDT 24
Finished Jul 17 07:49:20 PM PDT 24
Peak memory 205548 kb
Host smart-f503accc-a1a0-4fdb-9ef4-2a1e8aebb061
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217155901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1217155901
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.117437276
Short name T1007
Test name
Test status
Simulation time 12354549857 ps
CPU time 182.1 seconds
Started Jul 17 07:49:22 PM PDT 24
Finished Jul 17 07:52:28 PM PDT 24
Peak memory 285504 kb
Host smart-292feaa4-9531-45d7-b689-2b9aac8fcc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117437276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.117437276
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1710722561
Short name T230
Test name
Test status
Simulation time 18193159224 ps
CPU time 150.58 seconds
Started Jul 17 07:49:53 PM PDT 24
Finished Jul 17 07:52:28 PM PDT 24
Peak memory 254372 kb
Host smart-9fb10a4e-b7c3-4366-bbcd-141f43409734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710722561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1710722561
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2529182616
Short name T210
Test name
Test status
Simulation time 6298253153 ps
CPU time 94.55 seconds
Started Jul 17 07:50:33 PM PDT 24
Finished Jul 17 07:52:08 PM PDT 24
Peak memory 252540 kb
Host smart-b7a96e11-e808-49b4-bb8f-c188b02a1175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529182616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2529182616
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.776878190
Short name T206
Test name
Test status
Simulation time 80001087952 ps
CPU time 630.33 seconds
Started Jul 17 07:50:55 PM PDT 24
Finished Jul 17 08:01:28 PM PDT 24
Peak memory 265608 kb
Host smart-c2e0dbd9-8d6d-4798-87bd-dd8719a2059b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776878190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.776878190
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.724762454
Short name T92
Test name
Test status
Simulation time 230931606777 ps
CPU time 535.83 seconds
Started Jul 17 07:49:17 PM PDT 24
Finished Jul 17 07:58:16 PM PDT 24
Peak memory 265644 kb
Host smart-6a8d8deb-1a6b-4824-b4fe-d09e01142099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724762454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.724762454
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3629029780
Short name T187
Test name
Test status
Simulation time 1219610594 ps
CPU time 18.72 seconds
Started Jul 17 07:19:05 PM PDT 24
Finished Jul 17 07:19:49 PM PDT 24
Peak memory 216012 kb
Host smart-4b72a4be-e8ee-4dca-b9da-4d8136de4cae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629029780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3629029780
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.4217254952
Short name T12
Test name
Test status
Simulation time 6508999653 ps
CPU time 97.91 seconds
Started Jul 17 07:49:17 PM PDT 24
Finished Jul 17 07:50:58 PM PDT 24
Peak memory 249340 kb
Host smart-147fb55b-68b0-47cf-ac4a-be53aef7474c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217254952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.4217254952
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1698810114
Short name T222
Test name
Test status
Simulation time 72369574490 ps
CPU time 104.8 seconds
Started Jul 17 07:49:49 PM PDT 24
Finished Jul 17 07:51:37 PM PDT 24
Peak memory 273836 kb
Host smart-23133e26-58d0-4439-aecb-9c95eb04f550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698810114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1698810114
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.295080937
Short name T153
Test name
Test status
Simulation time 167619009 ps
CPU time 8.27 seconds
Started Jul 17 07:51:44 PM PDT 24
Finished Jul 17 07:51:56 PM PDT 24
Peak memory 235944 kb
Host smart-40251eb0-fa7c-4ae8-a67e-ad799e0143fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295080937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.295080937
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3278738229
Short name T70
Test name
Test status
Simulation time 2377149301 ps
CPU time 3.39 seconds
Started Jul 17 07:19:05 PM PDT 24
Finished Jul 17 07:19:33 PM PDT 24
Peak memory 216168 kb
Host smart-d8cb35da-b643-4a0e-ad87-2b1f03a5a57b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278738229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3278738229
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1843141102
Short name T216
Test name
Test status
Simulation time 59381458734 ps
CPU time 91.68 seconds
Started Jul 17 07:50:15 PM PDT 24
Finished Jul 17 07:51:49 PM PDT 24
Peak memory 255836 kb
Host smart-a4dc38b2-2c64-4845-86fb-535c3cedc5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843141102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1843141102
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2832324905
Short name T100
Test name
Test status
Simulation time 830919221 ps
CPU time 6.06 seconds
Started Jul 17 07:50:44 PM PDT 24
Finished Jul 17 07:50:51 PM PDT 24
Peak memory 232664 kb
Host smart-5b4bc748-7594-48ad-a686-c061888fd034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832324905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2832324905
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1127206006
Short name T52
Test name
Test status
Simulation time 1632404510 ps
CPU time 13.45 seconds
Started Jul 17 07:49:15 PM PDT 24
Finished Jul 17 07:49:31 PM PDT 24
Peak memory 250928 kb
Host smart-2dfb16cd-a310-4067-b945-a548e78345fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127206006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1127206006
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1056976601
Short name T13
Test name
Test status
Simulation time 160886228 ps
CPU time 5.43 seconds
Started Jul 17 07:49:18 PM PDT 24
Finished Jul 17 07:49:28 PM PDT 24
Peak memory 224420 kb
Host smart-cccc76b6-c497-4cf2-bf8c-bb4ec313b6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056976601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1056976601
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.128458022
Short name T276
Test name
Test status
Simulation time 7875445619 ps
CPU time 173.69 seconds
Started Jul 17 07:48:09 PM PDT 24
Finished Jul 17 07:51:04 PM PDT 24
Peak memory 263780 kb
Host smart-96df1d2e-c81b-4592-bcbb-a5c9d76df62e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128458022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.128458022
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2049318579
Short name T185
Test name
Test status
Simulation time 115475321 ps
CPU time 6.61 seconds
Started Jul 17 07:19:09 PM PDT 24
Finished Jul 17 07:19:39 PM PDT 24
Peak memory 215984 kb
Host smart-7f30aa65-a2c3-47e3-8e50-16426513b912
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049318579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2049318579
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1724677231
Short name T914
Test name
Test status
Simulation time 12320060006 ps
CPU time 100.12 seconds
Started Jul 17 07:47:46 PM PDT 24
Finished Jul 17 07:49:28 PM PDT 24
Peak memory 250348 kb
Host smart-49e1a7bc-954f-45b3-a4d4-ad1d1747b5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724677231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1724677231
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1656327216
Short name T701
Test name
Test status
Simulation time 1000970890 ps
CPU time 5.28 seconds
Started Jul 17 07:49:18 PM PDT 24
Finished Jul 17 07:49:27 PM PDT 24
Peak memory 235616 kb
Host smart-243fcfb2-36c6-43f5-91a2-4e38256258b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656327216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1656327216
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3645900838
Short name T305
Test name
Test status
Simulation time 901907850 ps
CPU time 9.6 seconds
Started Jul 17 07:49:47 PM PDT 24
Finished Jul 17 07:50:00 PM PDT 24
Peak memory 232700 kb
Host smart-1c0e7a46-ddfe-4ec5-959a-84d5b17b489b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645900838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3645900838
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_upload.3391986075
Short name T200
Test name
Test status
Simulation time 13635349314 ps
CPU time 11.22 seconds
Started Jul 17 07:49:59 PM PDT 24
Finished Jul 17 07:50:16 PM PDT 24
Peak memory 232796 kb
Host smart-184c4067-9f3a-4f43-86a6-e4f3b0938f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391986075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3391986075
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.261331182
Short name T307
Test name
Test status
Simulation time 1696173924 ps
CPU time 15.16 seconds
Started Jul 17 07:50:33 PM PDT 24
Finished Jul 17 07:50:49 PM PDT 24
Peak memory 232652 kb
Host smart-e98b5a9c-c295-4538-8a31-25d312bd28df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261331182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.261331182
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.713681664
Short name T89
Test name
Test status
Simulation time 34043935 ps
CPU time 1.13 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:19 PM PDT 24
Peak memory 207628 kb
Host smart-954500b3-b5d5-443c-8b94-6b5290d965b7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713681664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.713681664
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2718680151
Short name T111
Test name
Test status
Simulation time 180792805 ps
CPU time 4.39 seconds
Started Jul 17 07:19:00 PM PDT 24
Finished Jul 17 07:19:26 PM PDT 24
Peak memory 216216 kb
Host smart-2597db52-24b3-4f61-a6bc-4cda4b98a3d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718680151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2718680151
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.4094208589
Short name T134
Test name
Test status
Simulation time 15031896961 ps
CPU time 21.91 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:31 PM PDT 24
Peak memory 215836 kb
Host smart-26606904-10f6-43c8-94e1-c7c21539f918
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094208589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.4094208589
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.152540043
Short name T1102
Test name
Test status
Simulation time 5401402941 ps
CPU time 40.76 seconds
Started Jul 17 07:18:48 PM PDT 24
Finished Jul 17 07:19:30 PM PDT 24
Peak memory 207804 kb
Host smart-7f37657c-b563-4be4-909d-e2cc24744c1b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152540043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.152540043
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.379452582
Short name T1034
Test name
Test status
Simulation time 940370838 ps
CPU time 3.57 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:22 PM PDT 24
Peak memory 218928 kb
Host smart-775ecba0-a0cc-438d-9453-1f6bd839e66f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379452582 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.379452582
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2823009173
Short name T126
Test name
Test status
Simulation time 127596846 ps
CPU time 2.7 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:16 PM PDT 24
Peak memory 215920 kb
Host smart-cfa4a3d4-785c-424a-ad6e-9f6535f49286
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823009173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
823009173
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1059991261
Short name T1111
Test name
Test status
Simulation time 16608982 ps
CPU time 0.77 seconds
Started Jul 17 07:18:54 PM PDT 24
Finished Jul 17 07:19:01 PM PDT 24
Peak memory 204412 kb
Host smart-aa1ce09c-0e4f-4de7-b3ce-a207cf57c620
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059991261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
059991261
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2100282858
Short name T130
Test name
Test status
Simulation time 64161356 ps
CPU time 2.17 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:20 PM PDT 24
Peak memory 216056 kb
Host smart-df48f26c-4955-4ab8-9ce5-1c0ed5951f65
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100282858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2100282858
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1543605029
Short name T1041
Test name
Test status
Simulation time 20405575 ps
CPU time 0.68 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:18 PM PDT 24
Peak memory 204280 kb
Host smart-c1795713-8a57-4e40-9d36-b29f50022f08
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543605029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1543605029
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3190623377
Short name T1028
Test name
Test status
Simulation time 100630821 ps
CPU time 1.87 seconds
Started Jul 17 07:18:53 PM PDT 24
Finished Jul 17 07:18:59 PM PDT 24
Peak memory 207748 kb
Host smart-fb0d2c03-aaa9-4a9e-b7ef-b1b50699325c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190623377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3190623377
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2914187920
Short name T110
Test name
Test status
Simulation time 971364975 ps
CPU time 1.85 seconds
Started Jul 17 07:19:09 PM PDT 24
Finished Jul 17 07:19:34 PM PDT 24
Peak memory 216256 kb
Host smart-34f6257a-32e4-49f1-bcad-b989260c3c33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914187920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
914187920
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1869000456
Short name T184
Test name
Test status
Simulation time 290565263 ps
CPU time 17.96 seconds
Started Jul 17 07:19:07 PM PDT 24
Finished Jul 17 07:19:49 PM PDT 24
Peak memory 215964 kb
Host smart-735f4fb4-cc62-4787-9668-c28162178a8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869000456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1869000456
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3299037222
Short name T1130
Test name
Test status
Simulation time 1001256652 ps
CPU time 8.32 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:26 PM PDT 24
Peak memory 207684 kb
Host smart-a329d3b4-872e-43d2-a142-dda8f8e8df95
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299037222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3299037222
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.54596108
Short name T135
Test name
Test status
Simulation time 1879995504 ps
CPU time 35.05 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:52 PM PDT 24
Peak memory 207724 kb
Host smart-c0f6ae29-0195-47e5-88bf-fb241da99b61
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54596108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_
bit_bash.54596108
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.960364998
Short name T91
Test name
Test status
Simulation time 39571777 ps
CPU time 1.35 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:10 PM PDT 24
Peak memory 207724 kb
Host smart-3ed2a5ad-801f-4193-9f82-0a4c0e4be879
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960364998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.960364998
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1719993588
Short name T114
Test name
Test status
Simulation time 143506329 ps
CPU time 2.65 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:21 PM PDT 24
Peak memory 217056 kb
Host smart-edba759b-cc07-4a8b-9ba0-812fbe5eec43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719993588 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1719993588
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3639693314
Short name T132
Test name
Test status
Simulation time 76075873 ps
CPU time 2.56 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:16 PM PDT 24
Peak memory 207804 kb
Host smart-ebd266df-326a-4a1a-b033-4e95c3d3ab3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639693314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
639693314
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.962516731
Short name T1053
Test name
Test status
Simulation time 13917119 ps
CPU time 0.72 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:11 PM PDT 24
Peak memory 204736 kb
Host smart-2d459cb2-f965-45e4-b50a-7a89af9313df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962516731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.962516731
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1577619700
Short name T1122
Test name
Test status
Simulation time 159977674 ps
CPU time 1.23 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:12 PM PDT 24
Peak memory 216064 kb
Host smart-139578c3-3a17-4eb2-884a-bd1b7163c63d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577619700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1577619700
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3067860058
Short name T1107
Test name
Test status
Simulation time 13739298 ps
CPU time 0.66 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:14 PM PDT 24
Peak memory 204236 kb
Host smart-aa9dc1dc-5efc-4263-aa9a-ea9c7c3ff3c1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067860058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3067860058
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3116260058
Short name T1024
Test name
Test status
Simulation time 114784376 ps
CPU time 3.06 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:12 PM PDT 24
Peak memory 215892 kb
Host smart-f9852e75-9741-48aa-b262-578b7c02ef6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116260058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3116260058
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3553347630
Short name T1078
Test name
Test status
Simulation time 309207700 ps
CPU time 4.68 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:13 PM PDT 24
Peak memory 216096 kb
Host smart-c5528205-5c96-441a-a177-cc994d09c078
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553347630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
553347630
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1428793076
Short name T1067
Test name
Test status
Simulation time 371574865 ps
CPU time 8.43 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:17 PM PDT 24
Peak memory 215952 kb
Host smart-bfe40f65-b904-4acc-89b7-67da303ffb30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428793076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1428793076
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.618399127
Short name T120
Test name
Test status
Simulation time 61789769 ps
CPU time 4.02 seconds
Started Jul 17 07:18:59 PM PDT 24
Finished Jul 17 07:19:24 PM PDT 24
Peak memory 218900 kb
Host smart-f8e929bd-3b9e-41c0-9930-a5d90dcc48bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618399127 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.618399127
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2219468827
Short name T1090
Test name
Test status
Simulation time 66871228 ps
CPU time 1.34 seconds
Started Jul 17 07:19:06 PM PDT 24
Finished Jul 17 07:19:32 PM PDT 24
Peak memory 207684 kb
Host smart-08f013ba-1e93-47e3-b65e-991e453259db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219468827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2219468827
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.529567090
Short name T1026
Test name
Test status
Simulation time 25606309 ps
CPU time 0.73 seconds
Started Jul 17 07:19:01 PM PDT 24
Finished Jul 17 07:19:23 PM PDT 24
Peak memory 204412 kb
Host smart-e641d4e3-0f35-453e-9814-aad192a4e7d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529567090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.529567090
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3511511388
Short name T162
Test name
Test status
Simulation time 246866060 ps
CPU time 4.16 seconds
Started Jul 17 07:19:02 PM PDT 24
Finished Jul 17 07:19:29 PM PDT 24
Peak memory 216020 kb
Host smart-7e09db0a-bcdd-4981-8c7b-f328078a5282
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511511388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3511511388
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3084767455
Short name T1080
Test name
Test status
Simulation time 65572125 ps
CPU time 2.26 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:20 PM PDT 24
Peak memory 216220 kb
Host smart-fd7b433b-a6f8-4f32-b152-01ef5417ce72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084767455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3084767455
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2675834866
Short name T1114
Test name
Test status
Simulation time 1649792826 ps
CPU time 20.25 seconds
Started Jul 17 07:19:00 PM PDT 24
Finished Jul 17 07:19:42 PM PDT 24
Peak memory 216340 kb
Host smart-9a62befc-d5da-43be-a9a8-f15dd0cfbb02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675834866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2675834866
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.412785144
Short name T1033
Test name
Test status
Simulation time 1607167313 ps
CPU time 3.51 seconds
Started Jul 17 07:19:01 PM PDT 24
Finished Jul 17 07:19:26 PM PDT 24
Peak memory 218540 kb
Host smart-576f94fd-8cb8-4a0e-8a6d-168beabec902
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412785144 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.412785144
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1646155717
Short name T1048
Test name
Test status
Simulation time 24473431 ps
CPU time 1.26 seconds
Started Jul 17 07:19:01 PM PDT 24
Finished Jul 17 07:19:26 PM PDT 24
Peak memory 219520 kb
Host smart-6bc128ec-18e2-4e56-b379-8672708c2716
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646155717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1646155717
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1404593125
Short name T1120
Test name
Test status
Simulation time 29914229 ps
CPU time 0.77 seconds
Started Jul 17 07:19:00 PM PDT 24
Finished Jul 17 07:19:23 PM PDT 24
Peak memory 204724 kb
Host smart-13dbe8c5-5783-4c0e-816d-cf4c27625c78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404593125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1404593125
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2827046062
Short name T165
Test name
Test status
Simulation time 296936361 ps
CPU time 2.05 seconds
Started Jul 17 07:19:06 PM PDT 24
Finished Jul 17 07:19:33 PM PDT 24
Peak memory 216580 kb
Host smart-4b0cf7ca-b274-4c64-93d5-f3390651fa74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827046062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2827046062
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2505708737
Short name T1070
Test name
Test status
Simulation time 2835993066 ps
CPU time 15.12 seconds
Started Jul 17 07:19:02 PM PDT 24
Finished Jul 17 07:19:40 PM PDT 24
Peak memory 216060 kb
Host smart-353ee818-811b-4fe0-82b5-f8b8a12ea9e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505708737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2505708737
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2296588045
Short name T1050
Test name
Test status
Simulation time 194226162 ps
CPU time 3.45 seconds
Started Jul 17 07:19:09 PM PDT 24
Finished Jul 17 07:19:36 PM PDT 24
Peak memory 219060 kb
Host smart-4c00576d-8563-473b-92d8-aab54ab1de9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296588045 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2296588045
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2668208149
Short name T1089
Test name
Test status
Simulation time 502840075 ps
CPU time 2.91 seconds
Started Jul 17 07:19:07 PM PDT 24
Finished Jul 17 07:19:34 PM PDT 24
Peak memory 215940 kb
Host smart-0cd7eff8-7b43-4486-8ecd-6729f48652ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668208149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2668208149
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2218339084
Short name T1045
Test name
Test status
Simulation time 39806973 ps
CPU time 0.7 seconds
Started Jul 17 07:19:08 PM PDT 24
Finished Jul 17 07:19:32 PM PDT 24
Peak memory 204452 kb
Host smart-19389223-4150-479f-9a2e-64646c21d616
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218339084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2218339084
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1006258690
Short name T1131
Test name
Test status
Simulation time 70281455 ps
CPU time 1.73 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:19 PM PDT 24
Peak memory 216020 kb
Host smart-644fe836-3a01-46fc-94aa-503314b305b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006258690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1006258690
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3882813873
Short name T1077
Test name
Test status
Simulation time 200520065 ps
CPU time 2.79 seconds
Started Jul 17 07:19:06 PM PDT 24
Finished Jul 17 07:19:33 PM PDT 24
Peak memory 216236 kb
Host smart-3a00acfc-f804-4d2c-9d13-f663994cf3be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882813873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3882813873
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1371758800
Short name T1124
Test name
Test status
Simulation time 154431183 ps
CPU time 2.46 seconds
Started Jul 17 07:19:08 PM PDT 24
Finished Jul 17 07:19:34 PM PDT 24
Peak memory 218112 kb
Host smart-431dad70-8122-4156-bc87-884b36b1d599
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371758800 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1371758800
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1553622618
Short name T1115
Test name
Test status
Simulation time 82257807 ps
CPU time 2.33 seconds
Started Jul 17 07:19:06 PM PDT 24
Finished Jul 17 07:19:33 PM PDT 24
Peak memory 215936 kb
Host smart-df453161-16f1-4347-9b19-a1527d5cc3db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553622618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1553622618
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3969750423
Short name T1049
Test name
Test status
Simulation time 32616061 ps
CPU time 0.68 seconds
Started Jul 17 07:19:06 PM PDT 24
Finished Jul 17 07:19:31 PM PDT 24
Peak memory 204420 kb
Host smart-dbb1912c-2287-4af7-82c3-7d3dfba05d03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969750423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3969750423
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.594971893
Short name T161
Test name
Test status
Simulation time 720977739 ps
CPU time 3.98 seconds
Started Jul 17 07:19:07 PM PDT 24
Finished Jul 17 07:19:35 PM PDT 24
Peak memory 215856 kb
Host smart-f24158a6-5b8d-4729-92d2-548d37b46b94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594971893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.594971893
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3100975775
Short name T1031
Test name
Test status
Simulation time 181824973 ps
CPU time 1.64 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:19 PM PDT 24
Peak memory 217104 kb
Host smart-aa97b7bb-f59f-49aa-8491-0740cc04c1ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100975775 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3100975775
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.496479768
Short name T131
Test name
Test status
Simulation time 159959365 ps
CPU time 1.3 seconds
Started Jul 17 07:19:06 PM PDT 24
Finished Jul 17 07:19:32 PM PDT 24
Peak memory 207608 kb
Host smart-990677c0-8a4a-463d-a5bb-eae9d445a194
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496479768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.496479768
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3607665809
Short name T1056
Test name
Test status
Simulation time 29046942 ps
CPU time 0.66 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:13 PM PDT 24
Peak memory 204432 kb
Host smart-40ed72bc-d06e-448a-a97b-36a618e293b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607665809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3607665809
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.4162241693
Short name T1064
Test name
Test status
Simulation time 103687001 ps
CPU time 1.69 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:10 PM PDT 24
Peak memory 215896 kb
Host smart-9f53bbbe-6602-4eda-98ef-0647e5ea93d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162241693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.4162241693
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3563515953
Short name T1081
Test name
Test status
Simulation time 99421269 ps
CPU time 1.81 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:15 PM PDT 24
Peak memory 216216 kb
Host smart-bd9e39dd-94db-4d48-bb8d-de5d84e141b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563515953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3563515953
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3574498043
Short name T1066
Test name
Test status
Simulation time 3151352896 ps
CPU time 7.24 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:24 PM PDT 24
Peak memory 216616 kb
Host smart-f642262c-2372-428a-945e-6ca6dc7b95b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574498043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3574498043
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1539286094
Short name T1069
Test name
Test status
Simulation time 219915408 ps
CPU time 3.41 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:13 PM PDT 24
Peak memory 217484 kb
Host smart-49a6e21e-c093-430a-8478-f98eeb527b09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539286094 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1539286094
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3112717245
Short name T1020
Test name
Test status
Simulation time 95585133 ps
CPU time 2.7 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:15 PM PDT 24
Peak memory 207688 kb
Host smart-bbd76cfe-3624-4782-a6c1-73c6c4998edf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112717245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3112717245
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.16668825
Short name T1074
Test name
Test status
Simulation time 14676516 ps
CPU time 0.73 seconds
Started Jul 17 07:19:02 PM PDT 24
Finished Jul 17 07:19:26 PM PDT 24
Peak memory 204756 kb
Host smart-3cce077f-01f4-4e6c-a17b-ac133e683024
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16668825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.16668825
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.753849516
Short name T1095
Test name
Test status
Simulation time 250070093 ps
CPU time 3.66 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:14 PM PDT 24
Peak memory 216144 kb
Host smart-c505d320-78b8-42f4-b41a-0fce27d16f11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753849516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.753849516
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.625512696
Short name T1099
Test name
Test status
Simulation time 268813501 ps
CPU time 4.35 seconds
Started Jul 17 07:19:06 PM PDT 24
Finished Jul 17 07:19:35 PM PDT 24
Peak memory 215948 kb
Host smart-b13bf8f4-cad1-4564-a0e4-511c039eb516
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625512696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.625512696
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2683125343
Short name T72
Test name
Test status
Simulation time 384243651 ps
CPU time 11.55 seconds
Started Jul 17 07:19:07 PM PDT 24
Finished Jul 17 07:19:43 PM PDT 24
Peak memory 215616 kb
Host smart-afa2bf26-3799-4c8d-a7a1-81d68ab656ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683125343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2683125343
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3415661028
Short name T117
Test name
Test status
Simulation time 497104853 ps
CPU time 3.51 seconds
Started Jul 17 07:18:59 PM PDT 24
Finished Jul 17 07:19:22 PM PDT 24
Peak memory 219068 kb
Host smart-9a84e22b-6851-4b25-b97d-1c9eba7c6f99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415661028 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3415661028
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2883109632
Short name T1109
Test name
Test status
Simulation time 227966776 ps
CPU time 2.53 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:11 PM PDT 24
Peak memory 207612 kb
Host smart-672861eb-83d8-47f5-9807-1e629451357c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883109632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2883109632
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.541964918
Short name T1018
Test name
Test status
Simulation time 111877073 ps
CPU time 0.76 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:14 PM PDT 24
Peak memory 204728 kb
Host smart-a032da59-2cbf-4705-939a-2c5e33eb308b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541964918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.541964918
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2314610827
Short name T1119
Test name
Test status
Simulation time 232212559 ps
CPU time 1.95 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:13 PM PDT 24
Peak memory 215860 kb
Host smart-d141c819-6d7e-4e8a-945c-6cda274b097a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314610827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2314610827
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3428381225
Short name T1035
Test name
Test status
Simulation time 24306432 ps
CPU time 1.29 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:10 PM PDT 24
Peak memory 216332 kb
Host smart-9d4fa5bf-c88b-4ff5-9ffc-baeaa2094e30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428381225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3428381225
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1533023568
Short name T189
Test name
Test status
Simulation time 4107810080 ps
CPU time 22.62 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:36 PM PDT 24
Peak memory 216024 kb
Host smart-dd318bc3-1b47-4843-af40-c3bbfd3b411b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533023568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1533023568
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2065358464
Short name T1037
Test name
Test status
Simulation time 51101465 ps
CPU time 2.07 seconds
Started Jul 17 07:19:02 PM PDT 24
Finished Jul 17 07:19:27 PM PDT 24
Peak memory 217060 kb
Host smart-1048bdfb-5ce7-4c61-b107-21a86bfa996f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065358464 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2065358464
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.4101762447
Short name T1036
Test name
Test status
Simulation time 44859345 ps
CPU time 0.75 seconds
Started Jul 17 07:19:01 PM PDT 24
Finished Jul 17 07:19:23 PM PDT 24
Peak memory 204748 kb
Host smart-3d21c0d1-0669-491f-a1b6-be0dfffcc3dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101762447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
4101762447
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1411125219
Short name T163
Test name
Test status
Simulation time 566436617 ps
CPU time 1.93 seconds
Started Jul 17 07:19:02 PM PDT 24
Finished Jul 17 07:19:27 PM PDT 24
Peak memory 216004 kb
Host smart-a92aa2cc-cc66-45d7-aaff-822930dc870c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411125219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1411125219
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1829815074
Short name T1057
Test name
Test status
Simulation time 47631661 ps
CPU time 1.56 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:19 PM PDT 24
Peak memory 216256 kb
Host smart-59e674be-88ba-4f78-99a2-006e6ba0d845
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829815074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1829815074
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1052449730
Short name T1118
Test name
Test status
Simulation time 2615903780 ps
CPU time 15.61 seconds
Started Jul 17 07:19:00 PM PDT 24
Finished Jul 17 07:19:37 PM PDT 24
Peak memory 215980 kb
Host smart-8a281753-edbe-43d8-ae7a-0a8d52af6cc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052449730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1052449730
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.271361882
Short name T119
Test name
Test status
Simulation time 80964583 ps
CPU time 1.54 seconds
Started Jul 17 07:19:01 PM PDT 24
Finished Jul 17 07:19:24 PM PDT 24
Peak memory 216092 kb
Host smart-cb3bf98b-dd86-49e9-8f82-1f21745099fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271361882 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.271361882
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3109284540
Short name T124
Test name
Test status
Simulation time 29462410 ps
CPU time 1.94 seconds
Started Jul 17 07:19:00 PM PDT 24
Finished Jul 17 07:19:23 PM PDT 24
Peak memory 215928 kb
Host smart-a6ecad6d-8365-4ec1-bec2-8d17116ad26e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109284540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3109284540
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3871604824
Short name T1084
Test name
Test status
Simulation time 12399096 ps
CPU time 0.73 seconds
Started Jul 17 07:19:00 PM PDT 24
Finished Jul 17 07:19:22 PM PDT 24
Peak memory 204428 kb
Host smart-f6521843-b1f7-4062-9575-a495de0d4e97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871604824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3871604824
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4178340568
Short name T1110
Test name
Test status
Simulation time 155428985 ps
CPU time 3.75 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:22 PM PDT 24
Peak memory 216108 kb
Host smart-9fa16e93-a99e-4aea-ac2e-d491ca179cd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178340568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.4178340568
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.4269528019
Short name T105
Test name
Test status
Simulation time 212920469 ps
CPU time 11.41 seconds
Started Jul 17 07:19:01 PM PDT 24
Finished Jul 17 07:19:36 PM PDT 24
Peak memory 215968 kb
Host smart-3446a074-b535-4215-ab59-d4fba023535f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269528019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.4269528019
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1810605921
Short name T1093
Test name
Test status
Simulation time 74696952 ps
CPU time 2.46 seconds
Started Jul 17 07:19:02 PM PDT 24
Finished Jul 17 07:19:28 PM PDT 24
Peak memory 218516 kb
Host smart-e468efe7-2ce7-4fa5-823a-8b0e224b659e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810605921 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1810605921
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.168459518
Short name T1062
Test name
Test status
Simulation time 41570132 ps
CPU time 1.41 seconds
Started Jul 17 07:19:06 PM PDT 24
Finished Jul 17 07:19:32 PM PDT 24
Peak memory 207752 kb
Host smart-a22da20c-9f1b-4866-b270-95fd05341768
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168459518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.168459518
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1670399352
Short name T1013
Test name
Test status
Simulation time 27622921 ps
CPU time 0.73 seconds
Started Jul 17 07:19:00 PM PDT 24
Finished Jul 17 07:19:22 PM PDT 24
Peak memory 204468 kb
Host smart-bcd567f3-990a-4747-b239-bd505a7dcd3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670399352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1670399352
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.816470682
Short name T1023
Test name
Test status
Simulation time 66215381 ps
CPU time 1.8 seconds
Started Jul 17 07:19:02 PM PDT 24
Finished Jul 17 07:19:27 PM PDT 24
Peak memory 215984 kb
Host smart-55e133f8-d5a3-4f46-b725-7e2e42564b8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816470682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.816470682
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3421055030
Short name T116
Test name
Test status
Simulation time 44987940 ps
CPU time 2.82 seconds
Started Jul 17 07:19:06 PM PDT 24
Finished Jul 17 07:19:33 PM PDT 24
Peak memory 216216 kb
Host smart-324b7bb2-dddb-4ac8-8976-4497e1064283
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421055030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3421055030
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2580601234
Short name T188
Test name
Test status
Simulation time 3185619295 ps
CPU time 19.52 seconds
Started Jul 17 07:19:02 PM PDT 24
Finished Jul 17 07:19:44 PM PDT 24
Peak memory 216456 kb
Host smart-459f8374-62ae-4afd-aaa5-879e727c7ae4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580601234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2580601234
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3324553170
Short name T127
Test name
Test status
Simulation time 747623841 ps
CPU time 13.72 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:32 PM PDT 24
Peak memory 215924 kb
Host smart-22cdc138-95e9-4202-b347-7343dacecf16
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324553170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3324553170
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2977282545
Short name T1042
Test name
Test status
Simulation time 681472209 ps
CPU time 12.8 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:22 PM PDT 24
Peak memory 207628 kb
Host smart-8c16e485-fecc-4acf-9a22-f0b2d3c319f6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977282545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2977282545
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3602578918
Short name T1100
Test name
Test status
Simulation time 80651330 ps
CPU time 1.33 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:18 PM PDT 24
Peak memory 207720 kb
Host smart-3d89376d-b9a7-4067-89d1-8abba6f08775
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602578918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3602578918
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2190338068
Short name T1030
Test name
Test status
Simulation time 23826877 ps
CPU time 1.53 seconds
Started Jul 17 07:18:55 PM PDT 24
Finished Jul 17 07:19:09 PM PDT 24
Peak memory 216128 kb
Host smart-8f185613-f793-4c19-a6dd-1fe0093ce318
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190338068 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2190338068
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.58628844
Short name T1082
Test name
Test status
Simulation time 97519741 ps
CPU time 2.46 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:16 PM PDT 24
Peak memory 216056 kb
Host smart-8492cac4-5c24-4dab-af09-d9e5af3a8a0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58628844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.58628844
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3610293672
Short name T1051
Test name
Test status
Simulation time 35828857 ps
CPU time 0.76 seconds
Started Jul 17 07:18:54 PM PDT 24
Finished Jul 17 07:19:04 PM PDT 24
Peak memory 204444 kb
Host smart-b5248ba7-b970-4d7f-b6c9-456ddbe10ebc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610293672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
610293672
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3560703377
Short name T1126
Test name
Test status
Simulation time 37085975 ps
CPU time 1.6 seconds
Started Jul 17 07:18:53 PM PDT 24
Finished Jul 17 07:19:01 PM PDT 24
Peak memory 215996 kb
Host smart-b3951ace-f8db-42ce-beb5-d0489863b0f5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560703377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3560703377
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.655621906
Short name T1017
Test name
Test status
Simulation time 11476628 ps
CPU time 0.65 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:11 PM PDT 24
Peak memory 204616 kb
Host smart-c92993b8-fc05-49ad-904b-f151ef5f47a2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655621906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.655621906
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3080158998
Short name T1016
Test name
Test status
Simulation time 210911629 ps
CPU time 2.56 seconds
Started Jul 17 07:18:55 PM PDT 24
Finished Jul 17 07:19:08 PM PDT 24
Peak memory 215916 kb
Host smart-73b014cd-e21c-4623-9605-7add544eef72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080158998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3080158998
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.34533078
Short name T109
Test name
Test status
Simulation time 227936642 ps
CPU time 4.16 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:22 PM PDT 24
Peak memory 216160 kb
Host smart-71a660b0-f21b-4178-91d3-881653e0e26b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34533078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.34533078
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2834856350
Short name T104
Test name
Test status
Simulation time 109434253 ps
CPU time 6.05 seconds
Started Jul 17 07:18:55 PM PDT 24
Finished Jul 17 07:19:13 PM PDT 24
Peak memory 216464 kb
Host smart-47de3d4f-57e8-4c00-8b37-b006963bf89a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834856350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2834856350
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.40231851
Short name T1068
Test name
Test status
Simulation time 29041188 ps
CPU time 0.74 seconds
Started Jul 17 07:19:03 PM PDT 24
Finished Jul 17 07:19:28 PM PDT 24
Peak memory 204740 kb
Host smart-67f6e665-7d1d-4df6-9fc8-fc3bbe0814c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40231851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.40231851
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3372945880
Short name T1015
Test name
Test status
Simulation time 15184837 ps
CPU time 0.71 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:09 PM PDT 24
Peak memory 204412 kb
Host smart-ce435147-fab8-4204-af14-a80c9ea24c23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372945880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3372945880
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3416943021
Short name T1076
Test name
Test status
Simulation time 13488063 ps
CPU time 0.71 seconds
Started Jul 17 07:19:01 PM PDT 24
Finished Jul 17 07:19:23 PM PDT 24
Peak memory 204424 kb
Host smart-e8558a83-d014-40d0-83d7-c34ed85d1d8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416943021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3416943021
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1743253168
Short name T1059
Test name
Test status
Simulation time 16134332 ps
CPU time 0.68 seconds
Started Jul 17 07:19:05 PM PDT 24
Finished Jul 17 07:19:30 PM PDT 24
Peak memory 204828 kb
Host smart-acb01f9f-39ae-46f5-a0a4-439d688c665f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743253168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1743253168
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1641721362
Short name T1097
Test name
Test status
Simulation time 15561077 ps
CPU time 0.73 seconds
Started Jul 17 07:19:06 PM PDT 24
Finished Jul 17 07:19:31 PM PDT 24
Peak memory 204496 kb
Host smart-d22bfa9a-aeff-4c2d-b259-aff3c55c084a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641721362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1641721362
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3163560713
Short name T1038
Test name
Test status
Simulation time 19599631 ps
CPU time 0.73 seconds
Started Jul 17 07:19:01 PM PDT 24
Finished Jul 17 07:19:26 PM PDT 24
Peak memory 204396 kb
Host smart-23259c5f-66b0-42b6-abd0-7e974df4d37a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163560713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3163560713
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.4284170567
Short name T1032
Test name
Test status
Simulation time 12847023 ps
CPU time 0.71 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:11 PM PDT 24
Peak memory 204440 kb
Host smart-e009b42a-8544-42d2-9931-e9a1483b28d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284170567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
4284170567
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3314999569
Short name T1104
Test name
Test status
Simulation time 15773542 ps
CPU time 0.75 seconds
Started Jul 17 07:19:06 PM PDT 24
Finished Jul 17 07:19:31 PM PDT 24
Peak memory 204448 kb
Host smart-648b1985-9d74-423f-81fd-872ff004ddf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314999569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3314999569
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.4138832997
Short name T1025
Test name
Test status
Simulation time 36873614 ps
CPU time 0.78 seconds
Started Jul 17 07:19:09 PM PDT 24
Finished Jul 17 07:19:33 PM PDT 24
Peak memory 204452 kb
Host smart-cadf827f-b1be-434f-9be7-c0351c93a600
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138832997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
4138832997
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2072059116
Short name T1039
Test name
Test status
Simulation time 13281120 ps
CPU time 0.71 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:11 PM PDT 24
Peak memory 204412 kb
Host smart-847e1870-eace-4af8-9b27-90d90bc34cb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072059116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2072059116
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.180566176
Short name T128
Test name
Test status
Simulation time 109084203 ps
CPU time 8 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:26 PM PDT 24
Peak memory 207616 kb
Host smart-3ace3623-6baf-4da0-a5c8-b03b116c5291
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180566176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.180566176
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3525454306
Short name T1027
Test name
Test status
Simulation time 2464020623 ps
CPU time 25.26 seconds
Started Jul 17 07:19:00 PM PDT 24
Finished Jul 17 07:19:47 PM PDT 24
Peak memory 207664 kb
Host smart-4f3d1549-f276-4f8f-945b-fbe1c48a2173
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525454306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3525454306
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1774840492
Short name T90
Test name
Test status
Simulation time 22730956 ps
CPU time 0.97 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:19 PM PDT 24
Peak memory 207452 kb
Host smart-ea8cd033-b303-4530-9e5a-540080bf6eb4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774840492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1774840492
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.734073488
Short name T1073
Test name
Test status
Simulation time 1270382805 ps
CPU time 1.97 seconds
Started Jul 17 07:19:00 PM PDT 24
Finished Jul 17 07:19:24 PM PDT 24
Peak memory 217124 kb
Host smart-db50ff0e-1af2-4a0c-96ec-237513cd0cf2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734073488 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.734073488
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1942059143
Short name T122
Test name
Test status
Simulation time 89948523 ps
CPU time 1.58 seconds
Started Jul 17 07:19:01 PM PDT 24
Finished Jul 17 07:19:26 PM PDT 24
Peak memory 216020 kb
Host smart-014fcc82-5ec3-4fa4-8579-7e0c013a01a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942059143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
942059143
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3512677988
Short name T1029
Test name
Test status
Simulation time 16402883 ps
CPU time 0.78 seconds
Started Jul 17 07:18:59 PM PDT 24
Finished Jul 17 07:19:19 PM PDT 24
Peak memory 204456 kb
Host smart-8e18eecb-9d02-43be-84cd-e0659caeef3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512677988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
512677988
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2577514313
Short name T129
Test name
Test status
Simulation time 140667874 ps
CPU time 2.18 seconds
Started Jul 17 07:19:01 PM PDT 24
Finished Jul 17 07:19:24 PM PDT 24
Peak memory 216060 kb
Host smart-011f6513-bfda-4c8d-b340-5278c1357446
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577514313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2577514313
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3200036168
Short name T1044
Test name
Test status
Simulation time 10435703 ps
CPU time 0.7 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:18 PM PDT 24
Peak memory 204644 kb
Host smart-2dd07754-67b8-4162-905c-ce3ba50ba131
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200036168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3200036168
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2896844754
Short name T1075
Test name
Test status
Simulation time 157342304 ps
CPU time 2.78 seconds
Started Jul 17 07:19:00 PM PDT 24
Finished Jul 17 07:19:24 PM PDT 24
Peak memory 215948 kb
Host smart-2fb0b454-d57b-4a67-819c-5202c16fd108
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896844754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2896844754
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1647246336
Short name T1092
Test name
Test status
Simulation time 168717182 ps
CPU time 2.63 seconds
Started Jul 17 07:18:55 PM PDT 24
Finished Jul 17 07:19:10 PM PDT 24
Peak memory 216084 kb
Host smart-6cd38404-d065-451e-b368-cefd7525dcc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647246336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
647246336
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2769761379
Short name T190
Test name
Test status
Simulation time 423715731 ps
CPU time 13.07 seconds
Started Jul 17 07:18:55 PM PDT 24
Finished Jul 17 07:19:18 PM PDT 24
Peak memory 217352 kb
Host smart-485d7e72-0e92-47da-b7e8-c453b41a96ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769761379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2769761379
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2276911991
Short name T1088
Test name
Test status
Simulation time 14839723 ps
CPU time 0.68 seconds
Started Jul 17 07:19:08 PM PDT 24
Finished Jul 17 07:19:32 PM PDT 24
Peak memory 204448 kb
Host smart-81060b81-4ff6-4500-a23d-fedf778ea945
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276911991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2276911991
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3679080515
Short name T1121
Test name
Test status
Simulation time 29921573 ps
CPU time 0.65 seconds
Started Jul 17 07:19:07 PM PDT 24
Finished Jul 17 07:19:32 PM PDT 24
Peak memory 204452 kb
Host smart-ce359c15-6d9e-4243-9e42-592a59f55da0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679080515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3679080515
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2860573443
Short name T1022
Test name
Test status
Simulation time 14901347 ps
CPU time 0.71 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:18 PM PDT 24
Peak memory 204732 kb
Host smart-65b68ab2-326c-4ab8-9248-496ceafb1ac6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860573443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2860573443
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.551141194
Short name T1085
Test name
Test status
Simulation time 13689518 ps
CPU time 0.71 seconds
Started Jul 17 07:19:08 PM PDT 24
Finished Jul 17 07:19:32 PM PDT 24
Peak memory 204432 kb
Host smart-0a7c703a-f851-4fcf-85b5-4171d1547365
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551141194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.551141194
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2112852200
Short name T1054
Test name
Test status
Simulation time 14445673 ps
CPU time 0.74 seconds
Started Jul 17 07:19:07 PM PDT 24
Finished Jul 17 07:19:32 PM PDT 24
Peak memory 204724 kb
Host smart-6bd2dbad-535c-4a05-84fd-bd5736c9277e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112852200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2112852200
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3592098780
Short name T1072
Test name
Test status
Simulation time 31011136 ps
CPU time 0.76 seconds
Started Jul 17 07:19:01 PM PDT 24
Finished Jul 17 07:19:26 PM PDT 24
Peak memory 204404 kb
Host smart-f5406e33-5fa7-4f47-8298-40f3a8a7a6b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592098780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3592098780
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.438510034
Short name T1052
Test name
Test status
Simulation time 47665421 ps
CPU time 0.7 seconds
Started Jul 17 07:19:07 PM PDT 24
Finished Jul 17 07:19:32 PM PDT 24
Peak memory 204080 kb
Host smart-5ec31896-de97-4bba-8147-3501d213e42c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438510034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.438510034
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2660840240
Short name T1129
Test name
Test status
Simulation time 21836351 ps
CPU time 0.73 seconds
Started Jul 17 07:19:06 PM PDT 24
Finished Jul 17 07:19:31 PM PDT 24
Peak memory 204404 kb
Host smart-f0555b26-15ad-43fa-9532-7cb460f9d636
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660840240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2660840240
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1776938034
Short name T1021
Test name
Test status
Simulation time 24780397 ps
CPU time 0.69 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:14 PM PDT 24
Peak memory 204440 kb
Host smart-1f0dac43-e239-4146-8e60-c0813df84d56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776938034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1776938034
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1893991583
Short name T1125
Test name
Test status
Simulation time 12160402 ps
CPU time 0.68 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:18 PM PDT 24
Peak memory 204420 kb
Host smart-1cb092c1-34aa-4475-b17d-aa270a64dddf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893991583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1893991583
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1191992658
Short name T1063
Test name
Test status
Simulation time 2529512826 ps
CPU time 15.8 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:33 PM PDT 24
Peak memory 207692 kb
Host smart-3cd2a491-6405-442a-b503-af6a2e939e68
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191992658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1191992658
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3189518287
Short name T133
Test name
Test status
Simulation time 1111370062 ps
CPU time 33.09 seconds
Started Jul 17 07:19:05 PM PDT 24
Finished Jul 17 07:20:03 PM PDT 24
Peak memory 207700 kb
Host smart-3e161c0a-8be4-48bc-afbf-b5088e440556
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189518287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3189518287
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1502071132
Short name T88
Test name
Test status
Simulation time 53289275 ps
CPU time 0.91 seconds
Started Jul 17 07:18:51 PM PDT 24
Finished Jul 17 07:18:55 PM PDT 24
Peak memory 207408 kb
Host smart-2a7a2d5c-6a44-40ab-b925-0830caca1b2b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502071132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1502071132
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3264460217
Short name T164
Test name
Test status
Simulation time 105160586 ps
CPU time 2.81 seconds
Started Jul 17 07:19:05 PM PDT 24
Finished Jul 17 07:19:32 PM PDT 24
Peak memory 218424 kb
Host smart-6357c0b7-1edc-4a87-a484-8770b5416aba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264460217 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3264460217
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2427520921
Short name T125
Test name
Test status
Simulation time 365915610 ps
CPU time 2.02 seconds
Started Jul 17 07:19:01 PM PDT 24
Finished Jul 17 07:19:27 PM PDT 24
Peak memory 215932 kb
Host smart-f85092dc-d45a-473c-958e-119bab1b342d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427520921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
427520921
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3926460679
Short name T1046
Test name
Test status
Simulation time 26229668 ps
CPU time 0.69 seconds
Started Jul 17 07:19:01 PM PDT 24
Finished Jul 17 07:19:23 PM PDT 24
Peak memory 204412 kb
Host smart-a0f1157b-7ae7-4e77-9dd6-55c2e3d40119
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926460679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
926460679
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.46778640
Short name T1123
Test name
Test status
Simulation time 79193645 ps
CPU time 1.67 seconds
Started Jul 17 07:19:00 PM PDT 24
Finished Jul 17 07:19:23 PM PDT 24
Peak memory 215996 kb
Host smart-9a8d3a79-d242-49ce-8d00-15efa13c6552
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46778640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi
_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_d
evice_mem_partial_access.46778640
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1200371680
Short name T1040
Test name
Test status
Simulation time 20844781 ps
CPU time 0.67 seconds
Started Jul 17 07:19:02 PM PDT 24
Finished Jul 17 07:19:26 PM PDT 24
Peak memory 204300 kb
Host smart-c3f89bb9-169f-45ca-945d-e8b91a3908c2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200371680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1200371680
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1990410085
Short name T179
Test name
Test status
Simulation time 125453922 ps
CPU time 2.48 seconds
Started Jul 17 07:19:02 PM PDT 24
Finished Jul 17 07:19:28 PM PDT 24
Peak memory 215984 kb
Host smart-91c52c56-bc4f-4664-9267-2ad3470ab5e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990410085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1990410085
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1105463424
Short name T115
Test name
Test status
Simulation time 151663186 ps
CPU time 4.27 seconds
Started Jul 17 07:19:05 PM PDT 24
Finished Jul 17 07:19:33 PM PDT 24
Peak memory 216264 kb
Host smart-88e00f96-cb31-4e5e-bf73-141ea6ac09e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105463424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
105463424
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2194147
Short name T183
Test name
Test status
Simulation time 1079453943 ps
CPU time 7.31 seconds
Started Jul 17 07:19:00 PM PDT 24
Finished Jul 17 07:19:29 PM PDT 24
Peak memory 215892 kb
Host smart-6c0abb6a-f861-49b9-aea5-d9b2f5033f44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl
_intg_err.2194147
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2248443201
Short name T1060
Test name
Test status
Simulation time 26490209 ps
CPU time 0.71 seconds
Started Jul 17 07:19:06 PM PDT 24
Finished Jul 17 07:19:32 PM PDT 24
Peak memory 204324 kb
Host smart-de7667f6-f04e-4680-b072-0529a496225b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248443201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2248443201
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.534815896
Short name T1087
Test name
Test status
Simulation time 30561089 ps
CPU time 0.71 seconds
Started Jul 17 07:19:07 PM PDT 24
Finished Jul 17 07:19:32 PM PDT 24
Peak memory 204324 kb
Host smart-c3fdf76c-e136-478e-b6cb-a9e453650b46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534815896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.534815896
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3565881098
Short name T1061
Test name
Test status
Simulation time 26590787 ps
CPU time 0.7 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:11 PM PDT 24
Peak memory 204396 kb
Host smart-ec3c5e35-5bf9-4881-aba8-6c05937dda1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565881098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3565881098
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2354467758
Short name T1055
Test name
Test status
Simulation time 14207082 ps
CPU time 0.74 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:14 PM PDT 24
Peak memory 204420 kb
Host smart-cd54d49a-7bcf-4da5-9edb-01ed56fb21a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354467758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2354467758
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1381221799
Short name T1014
Test name
Test status
Simulation time 45368592 ps
CPU time 0.74 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:09 PM PDT 24
Peak memory 204388 kb
Host smart-9491cc28-8794-4f48-9b0b-40dc7e947a12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381221799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1381221799
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.4136966844
Short name T1127
Test name
Test status
Simulation time 16956456 ps
CPU time 0.7 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:11 PM PDT 24
Peak memory 204548 kb
Host smart-e2e5b178-3bc0-4bde-bbd8-0c43cdddcc46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136966844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
4136966844
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.760471978
Short name T1079
Test name
Test status
Simulation time 11107012 ps
CPU time 0.66 seconds
Started Jul 17 07:20:45 PM PDT 24
Finished Jul 17 07:20:57 PM PDT 24
Peak memory 204432 kb
Host smart-e7e94a94-9445-4de6-944e-8ad1bd4302c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760471978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.760471978
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3217020126
Short name T1105
Test name
Test status
Simulation time 52788192 ps
CPU time 0.76 seconds
Started Jul 17 07:20:38 PM PDT 24
Finished Jul 17 07:20:40 PM PDT 24
Peak memory 204404 kb
Host smart-bc9a9c5a-f878-4f7a-880d-ce30fe47e596
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217020126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3217020126
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2832005798
Short name T1116
Test name
Test status
Simulation time 58548006 ps
CPU time 0.67 seconds
Started Jul 17 07:20:37 PM PDT 24
Finished Jul 17 07:20:38 PM PDT 24
Peak memory 204408 kb
Host smart-22ee02f5-637c-4622-b547-2b39c1a4face
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832005798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2832005798
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3557126937
Short name T1083
Test name
Test status
Simulation time 34370664 ps
CPU time 0.68 seconds
Started Jul 17 07:20:44 PM PDT 24
Finished Jul 17 07:20:53 PM PDT 24
Peak memory 204400 kb
Host smart-da36b99e-c8b7-4b92-9bd1-253f104cdd69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557126937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3557126937
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3109009084
Short name T1108
Test name
Test status
Simulation time 39199218 ps
CPU time 2.23 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:19 PM PDT 24
Peak memory 207648 kb
Host smart-952e48a6-0175-43bb-8bc5-e861bf0becdf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109009084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
109009084
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.700645861
Short name T1128
Test name
Test status
Simulation time 21724568 ps
CPU time 0.76 seconds
Started Jul 17 07:18:53 PM PDT 24
Finished Jul 17 07:18:56 PM PDT 24
Peak memory 204404 kb
Host smart-614cd020-05f8-43a0-8e9c-d21a7439db34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700645861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.700645861
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2876788132
Short name T1043
Test name
Test status
Simulation time 470240168 ps
CPU time 3.1 seconds
Started Jul 17 07:19:06 PM PDT 24
Finished Jul 17 07:19:34 PM PDT 24
Peak memory 215928 kb
Host smart-a18c9ba9-989d-4a28-b5d2-54911e7165b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876788132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2876788132
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3094962290
Short name T71
Test name
Test status
Simulation time 193863864 ps
CPU time 3.1 seconds
Started Jul 17 07:19:05 PM PDT 24
Finished Jul 17 07:19:32 PM PDT 24
Peak memory 216032 kb
Host smart-a1cbeb5d-e0ca-4942-95d5-76cdb743ec97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094962290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
094962290
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1579443950
Short name T1096
Test name
Test status
Simulation time 295072357 ps
CPU time 8.07 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:17 PM PDT 24
Peak memory 224140 kb
Host smart-5f9d6423-4c3f-48fe-b2a6-50d78817c5ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579443950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1579443950
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3301915971
Short name T1019
Test name
Test status
Simulation time 58923466 ps
CPU time 1.82 seconds
Started Jul 17 07:18:55 PM PDT 24
Finished Jul 17 07:19:09 PM PDT 24
Peak memory 216060 kb
Host smart-a2f41dce-601f-4829-9b78-36f525fbca0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301915971 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3301915971
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3721497742
Short name T168
Test name
Test status
Simulation time 377504535 ps
CPU time 2.45 seconds
Started Jul 17 07:18:50 PM PDT 24
Finished Jul 17 07:18:54 PM PDT 24
Peak memory 215944 kb
Host smart-151317a2-a3e5-46ab-8cd3-338dd18eb026
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721497742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
721497742
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3888492757
Short name T1094
Test name
Test status
Simulation time 15958517 ps
CPU time 0.73 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:11 PM PDT 24
Peak memory 204700 kb
Host smart-bb342005-cd76-46ac-952e-40c2ab994f49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888492757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
888492757
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.539466461
Short name T167
Test name
Test status
Simulation time 220825596 ps
CPU time 4.5 seconds
Started Jul 17 07:18:53 PM PDT 24
Finished Jul 17 07:19:01 PM PDT 24
Peak memory 215972 kb
Host smart-7681e050-34a2-4f36-8fc6-8b84d412f87b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539466461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.539466461
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2497948884
Short name T1091
Test name
Test status
Simulation time 214345246 ps
CPU time 5.31 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:19 PM PDT 24
Peak memory 216080 kb
Host smart-20050412-47b1-4e21-9518-7bebcf745e83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497948884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
497948884
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1225454362
Short name T186
Test name
Test status
Simulation time 294995580 ps
CPU time 16.46 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:34 PM PDT 24
Peak memory 215996 kb
Host smart-d420f6ad-4dea-4680-8b71-16bb10467d31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225454362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1225454362
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2757470708
Short name T112
Test name
Test status
Simulation time 113158326 ps
CPU time 1.54 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:10 PM PDT 24
Peak memory 216028 kb
Host smart-21a96f7c-432d-4961-85c1-cdcd8e2f2174
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757470708 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2757470708
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.375043758
Short name T1117
Test name
Test status
Simulation time 50958168 ps
CPU time 1.35 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:10 PM PDT 24
Peak memory 207880 kb
Host smart-88059585-a299-4443-bd74-d081a5d69f78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375043758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.375043758
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3240626429
Short name T1086
Test name
Test status
Simulation time 12750005 ps
CPU time 0.74 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:14 PM PDT 24
Peak memory 204448 kb
Host smart-053c94db-5334-438e-8c97-d34e165cbfde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240626429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
240626429
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1738634141
Short name T1106
Test name
Test status
Simulation time 312038086 ps
CPU time 4.06 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:17 PM PDT 24
Peak memory 215900 kb
Host smart-96e120e0-3b04-4ff3-8464-ca9aa6ea0744
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738634141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1738634141
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2380449087
Short name T107
Test name
Test status
Simulation time 132840629 ps
CPU time 4.32 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:14 PM PDT 24
Peak memory 216176 kb
Host smart-a4d1bb3a-d8ca-4230-8065-88a849a09b44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380449087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
380449087
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.4082692249
Short name T1113
Test name
Test status
Simulation time 673780798 ps
CPU time 7.55 seconds
Started Jul 17 07:18:55 PM PDT 24
Finished Jul 17 07:19:13 PM PDT 24
Peak memory 216600 kb
Host smart-11c12e96-4264-4b73-aac7-4fd96b45e53f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082692249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.4082692249
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.620914746
Short name T1058
Test name
Test status
Simulation time 215936147 ps
CPU time 3.63 seconds
Started Jul 17 07:19:17 PM PDT 24
Finished Jul 17 07:19:39 PM PDT 24
Peak memory 218096 kb
Host smart-fcf129e8-d315-49ab-a71a-7c99fcc1e701
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620914746 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.620914746
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3081159303
Short name T1065
Test name
Test status
Simulation time 33077105 ps
CPU time 2.03 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:15 PM PDT 24
Peak memory 215908 kb
Host smart-16853a2d-3b8f-42bc-bae5-7a62bc79e425
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081159303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
081159303
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1549334501
Short name T1103
Test name
Test status
Simulation time 23960681 ps
CPU time 0.71 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:13 PM PDT 24
Peak memory 204456 kb
Host smart-2f255fc9-6c6b-4604-9b2e-3f6fd2f87628
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549334501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
549334501
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.999199518
Short name T1101
Test name
Test status
Simulation time 44800208 ps
CPU time 2.85 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:20 PM PDT 24
Peak memory 215996 kb
Host smart-ab50aaad-c67a-48b1-8829-9d3b31da87dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999199518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.999199518
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3757349510
Short name T108
Test name
Test status
Simulation time 131433085 ps
CPU time 3.99 seconds
Started Jul 17 07:18:56 PM PDT 24
Finished Jul 17 07:19:13 PM PDT 24
Peak memory 216060 kb
Host smart-9e10c00a-85fd-49ea-adbb-7025e2e59e15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757349510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
757349510
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2625155725
Short name T1098
Test name
Test status
Simulation time 1345148250 ps
CPU time 16.14 seconds
Started Jul 17 07:18:57 PM PDT 24
Finished Jul 17 07:19:29 PM PDT 24
Peak memory 216404 kb
Host smart-b140d694-f48e-405a-bbf8-832d36ed3f3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625155725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2625155725
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.4037650398
Short name T1112
Test name
Test status
Simulation time 40532467 ps
CPU time 2.67 seconds
Started Jul 17 07:19:00 PM PDT 24
Finished Jul 17 07:19:25 PM PDT 24
Peak memory 217592 kb
Host smart-4ea30593-f392-4591-ba54-1e74613f8bd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037650398 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.4037650398
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2789600186
Short name T1071
Test name
Test status
Simulation time 247591168 ps
CPU time 2.21 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:20 PM PDT 24
Peak memory 215840 kb
Host smart-d7ede9f6-24f0-4b5e-a48e-7ae37030d035
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789600186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
789600186
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2679991709
Short name T1012
Test name
Test status
Simulation time 56210445 ps
CPU time 0.75 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:19 PM PDT 24
Peak memory 204440 kb
Host smart-2241cb71-a5cd-4eef-84b0-5134f90438a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679991709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
679991709
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.474426412
Short name T1047
Test name
Test status
Simulation time 50838116 ps
CPU time 1.73 seconds
Started Jul 17 07:19:01 PM PDT 24
Finished Jul 17 07:19:27 PM PDT 24
Peak memory 215940 kb
Host smart-a514c85a-6435-4fac-815d-2f25d4f75c5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474426412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.474426412
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1965218139
Short name T113
Test name
Test status
Simulation time 54923025 ps
CPU time 3.24 seconds
Started Jul 17 07:18:58 PM PDT 24
Finished Jul 17 07:19:20 PM PDT 24
Peak memory 216116 kb
Host smart-7f21e456-e7a8-4967-af82-5bf810939961
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965218139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
965218139
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3602133364
Short name T728
Test name
Test status
Simulation time 31751130 ps
CPU time 0.73 seconds
Started Jul 17 07:47:48 PM PDT 24
Finished Jul 17 07:47:50 PM PDT 24
Peak memory 204548 kb
Host smart-ef9f941d-b796-40a4-9b83-bb57ce4271a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602133364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
602133364
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1488011380
Short name T97
Test name
Test status
Simulation time 785791831 ps
CPU time 11.91 seconds
Started Jul 17 07:47:51 PM PDT 24
Finished Jul 17 07:48:04 PM PDT 24
Peak memory 224428 kb
Host smart-77762070-59cc-421c-a48d-d27c5b849432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488011380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1488011380
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.538583995
Short name T1008
Test name
Test status
Simulation time 12466744 ps
CPU time 0.74 seconds
Started Jul 17 07:47:47 PM PDT 24
Finished Jul 17 07:47:49 PM PDT 24
Peak memory 205580 kb
Host smart-c4498864-7680-486a-ae1d-8a7986dc975d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538583995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.538583995
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.428356812
Short name T978
Test name
Test status
Simulation time 5830688926 ps
CPU time 106.96 seconds
Started Jul 17 07:47:48 PM PDT 24
Finished Jul 17 07:49:37 PM PDT 24
Peak memory 256668 kb
Host smart-e6763f8a-80db-4100-931d-441321195433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428356812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.428356812
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.511877564
Short name T195
Test name
Test status
Simulation time 2830104351 ps
CPU time 34.12 seconds
Started Jul 17 07:47:48 PM PDT 24
Finished Jul 17 07:48:24 PM PDT 24
Peak memory 231152 kb
Host smart-512df2bb-a678-4dc7-9ef6-e40c459755ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511877564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
511877564
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1910181812
Short name T576
Test name
Test status
Simulation time 736457794 ps
CPU time 8.34 seconds
Started Jul 17 07:47:45 PM PDT 24
Finished Jul 17 07:47:53 PM PDT 24
Peak memory 224448 kb
Host smart-1425e68e-5a04-4695-b995-53a937ea80b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910181812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1910181812
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.3237058938
Short name T673
Test name
Test status
Simulation time 1691425434 ps
CPU time 6.97 seconds
Started Jul 17 07:47:49 PM PDT 24
Finished Jul 17 07:47:58 PM PDT 24
Peak memory 224496 kb
Host smart-fac7ac87-1556-45b9-a800-1ddd51f6c5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237058938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.3237058938
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3844796719
Short name T244
Test name
Test status
Simulation time 14111415434 ps
CPU time 36.43 seconds
Started Jul 17 07:47:47 PM PDT 24
Finished Jul 17 07:48:25 PM PDT 24
Peak memory 232760 kb
Host smart-02e37aa4-b0c6-4d84-86fb-c0bdd5db69fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844796719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3844796719
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2132983818
Short name T381
Test name
Test status
Simulation time 1174601849 ps
CPU time 12.22 seconds
Started Jul 17 07:47:49 PM PDT 24
Finished Jul 17 07:48:03 PM PDT 24
Peak memory 232700 kb
Host smart-57739d75-420e-4dde-8d58-0467a9c4a9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132983818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2132983818
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1506077872
Short name T1009
Test name
Test status
Simulation time 21240055666 ps
CPU time 10.1 seconds
Started Jul 17 07:47:46 PM PDT 24
Finished Jul 17 07:47:56 PM PDT 24
Peak memory 224564 kb
Host smart-77ed3d5e-f0fc-48de-93a5-113a745beb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506077872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1506077872
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3970575320
Short name T795
Test name
Test status
Simulation time 9011323479 ps
CPU time 26.21 seconds
Started Jul 17 07:47:46 PM PDT 24
Finished Jul 17 07:48:14 PM PDT 24
Peak memory 232812 kb
Host smart-ff874cf7-98c0-4473-ae28-80e9d1ad6093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970575320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3970575320
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3977582624
Short name T464
Test name
Test status
Simulation time 346736148 ps
CPU time 6.19 seconds
Started Jul 17 07:47:50 PM PDT 24
Finished Jul 17 07:47:58 PM PDT 24
Peak memory 219360 kb
Host smart-19a4dea0-17c8-43c0-bec4-bcd76bf80ae6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3977582624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3977582624
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1212799355
Short name T77
Test name
Test status
Simulation time 117674230 ps
CPU time 1.12 seconds
Started Jul 17 07:47:51 PM PDT 24
Finished Jul 17 07:47:53 PM PDT 24
Peak memory 236624 kb
Host smart-5d283c6c-be9d-4e2f-9fdc-e66a629ed1f5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212799355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1212799355
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2819288634
Short name T173
Test name
Test status
Simulation time 104868949828 ps
CPU time 316.12 seconds
Started Jul 17 07:47:46 PM PDT 24
Finished Jul 17 07:53:03 PM PDT 24
Peak memory 256632 kb
Host smart-2f51f35b-5bda-4088-ac36-c8afe72dd8f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819288634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2819288634
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.660737002
Short name T875
Test name
Test status
Simulation time 27028048 ps
CPU time 0.87 seconds
Started Jul 17 07:47:46 PM PDT 24
Finished Jul 17 07:47:47 PM PDT 24
Peak memory 205728 kb
Host smart-5506707a-1647-43cc-b26e-cf1bfd9b656a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660737002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.660737002
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1144318826
Short name T474
Test name
Test status
Simulation time 13687377687 ps
CPU time 19.55 seconds
Started Jul 17 07:47:46 PM PDT 24
Finished Jul 17 07:48:07 PM PDT 24
Peak memory 216296 kb
Host smart-428d6938-e5e7-467e-95fe-69e81fbb657d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144318826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1144318826
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.927405611
Short name T436
Test name
Test status
Simulation time 87208650 ps
CPU time 1.6 seconds
Started Jul 17 07:47:46 PM PDT 24
Finished Jul 17 07:47:49 PM PDT 24
Peak memory 216240 kb
Host smart-64d529b5-0862-4e30-803a-5e2e805a7a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927405611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.927405611
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1859821333
Short name T682
Test name
Test status
Simulation time 27800691 ps
CPU time 0.78 seconds
Started Jul 17 07:47:48 PM PDT 24
Finished Jul 17 07:47:50 PM PDT 24
Peak memory 205596 kb
Host smart-8019481a-b2bc-40b6-8b0f-3f89b933c4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859821333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1859821333
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3985606566
Short name T404
Test name
Test status
Simulation time 609889646 ps
CPU time 5.99 seconds
Started Jul 17 07:47:49 PM PDT 24
Finished Jul 17 07:47:57 PM PDT 24
Peak memory 224512 kb
Host smart-3414b4a4-9659-45ba-b221-1aee6fe57a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985606566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3985606566
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3987221525
Short name T857
Test name
Test status
Simulation time 11486881 ps
CPU time 0.68 seconds
Started Jul 17 07:47:51 PM PDT 24
Finished Jul 17 07:47:53 PM PDT 24
Peak memory 204956 kb
Host smart-228eb61c-d7d8-4dc5-b9a0-d2341f530716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987221525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
987221525
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2910897205
Short name T85
Test name
Test status
Simulation time 119771568 ps
CPU time 3.84 seconds
Started Jul 17 07:47:46 PM PDT 24
Finished Jul 17 07:47:50 PM PDT 24
Peak memory 232812 kb
Host smart-2c2fc5a5-9b66-4121-a33b-0c8625c8d5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910897205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2910897205
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1016385336
Short name T586
Test name
Test status
Simulation time 14415290 ps
CPU time 0.77 seconds
Started Jul 17 07:47:50 PM PDT 24
Finished Jul 17 07:47:52 PM PDT 24
Peak memory 205592 kb
Host smart-79923ef7-fbad-415a-adcb-b3a8b3360eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016385336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1016385336
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2154926911
Short name T720
Test name
Test status
Simulation time 8632730377 ps
CPU time 78.61 seconds
Started Jul 17 07:47:55 PM PDT 24
Finished Jul 17 07:49:15 PM PDT 24
Peak memory 249140 kb
Host smart-453848f1-1524-46ae-9d27-ef3d5b82e2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154926911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2154926911
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.333117594
Short name T764
Test name
Test status
Simulation time 4522870088 ps
CPU time 74.47 seconds
Started Jul 17 07:47:55 PM PDT 24
Finished Jul 17 07:49:10 PM PDT 24
Peak memory 255620 kb
Host smart-b43a552c-acec-49b2-838d-0a5e67de645d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333117594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.333117594
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1201548440
Short name T401
Test name
Test status
Simulation time 3027403505 ps
CPU time 9.65 seconds
Started Jul 17 07:47:52 PM PDT 24
Finished Jul 17 07:48:03 PM PDT 24
Peak memory 219288 kb
Host smart-da22fad8-b078-424c-b7e6-8d2c5efc3c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201548440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1201548440
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1082211148
Short name T473
Test name
Test status
Simulation time 6205864398 ps
CPU time 21.3 seconds
Started Jul 17 07:47:51 PM PDT 24
Finished Jul 17 07:48:13 PM PDT 24
Peak memory 224580 kb
Host smart-a7d29806-5d7f-46e6-941b-e91c3cd6adea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082211148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1082211148
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.1422666649
Short name T970
Test name
Test status
Simulation time 82255277473 ps
CPU time 292.94 seconds
Started Jul 17 07:47:49 PM PDT 24
Finished Jul 17 07:52:44 PM PDT 24
Peak memory 250212 kb
Host smart-850bc1c5-236e-4412-8372-9e5b15c19d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422666649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.1422666649
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.874958433
Short name T1003
Test name
Test status
Simulation time 40438452719 ps
CPU time 25.28 seconds
Started Jul 17 07:47:49 PM PDT 24
Finished Jul 17 07:48:16 PM PDT 24
Peak memory 224528 kb
Host smart-c1fdfd90-25c1-47e0-85be-25f347070d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874958433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.874958433
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.308052290
Short name T441
Test name
Test status
Simulation time 163037177 ps
CPU time 2.54 seconds
Started Jul 17 07:47:47 PM PDT 24
Finished Jul 17 07:47:51 PM PDT 24
Peak memory 232632 kb
Host smart-697d145e-19ad-47d6-8ac0-2e8c8f0ed67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308052290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.308052290
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3779557415
Short name T440
Test name
Test status
Simulation time 432087213 ps
CPU time 3.97 seconds
Started Jul 17 07:47:48 PM PDT 24
Finished Jul 17 07:47:54 PM PDT 24
Peak memory 232620 kb
Host smart-a504e1e8-4506-45d3-bda2-140b7e497a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779557415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3779557415
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.4064585419
Short name T626
Test name
Test status
Simulation time 29532863 ps
CPU time 2.12 seconds
Started Jul 17 07:47:47 PM PDT 24
Finished Jul 17 07:47:50 PM PDT 24
Peak memory 222996 kb
Host smart-c1686198-d4ad-41ab-8b8e-4a97648f048e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064585419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.4064585419
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.4163164201
Short name T461
Test name
Test status
Simulation time 271194898 ps
CPU time 3.08 seconds
Started Jul 17 07:47:49 PM PDT 24
Finished Jul 17 07:47:54 PM PDT 24
Peak memory 220276 kb
Host smart-ee012924-c376-4859-86a7-a1ae2a08a863
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4163164201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.4163164201
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1439950260
Short name T291
Test name
Test status
Simulation time 8990568200 ps
CPU time 106.65 seconds
Started Jul 17 07:47:48 PM PDT 24
Finished Jul 17 07:49:36 PM PDT 24
Peak memory 250372 kb
Host smart-a22f324d-fc47-4b55-9d65-c236229a7541
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439950260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1439950260
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2711188740
Short name T603
Test name
Test status
Simulation time 1624510983 ps
CPU time 18.96 seconds
Started Jul 17 07:47:51 PM PDT 24
Finished Jul 17 07:48:11 PM PDT 24
Peak memory 216240 kb
Host smart-b83a4348-9f9c-4a7d-a304-223e65db6e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711188740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2711188740
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.993913738
Short name T605
Test name
Test status
Simulation time 465886912 ps
CPU time 1.07 seconds
Started Jul 17 07:47:46 PM PDT 24
Finished Jul 17 07:47:48 PM PDT 24
Peak memory 207792 kb
Host smart-defae6a3-89ec-458d-94b0-f91b6f24eff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993913738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.993913738
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2075311565
Short name T598
Test name
Test status
Simulation time 13987278 ps
CPU time 0.72 seconds
Started Jul 17 07:47:51 PM PDT 24
Finished Jul 17 07:47:53 PM PDT 24
Peak memory 205660 kb
Host smart-b04a7ae2-e36d-4ba3-938d-d5f8d31c93c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075311565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2075311565
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1990911881
Short name T684
Test name
Test status
Simulation time 65597986 ps
CPU time 0.76 seconds
Started Jul 17 07:47:47 PM PDT 24
Finished Jul 17 07:47:49 PM PDT 24
Peak memory 205964 kb
Host smart-a1920a94-9014-4a78-aa59-d0949f91a2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990911881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1990911881
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.202765144
Short name T989
Test name
Test status
Simulation time 59686038 ps
CPU time 2.49 seconds
Started Jul 17 07:47:48 PM PDT 24
Finished Jul 17 07:47:52 PM PDT 24
Peak memory 224416 kb
Host smart-470a5976-8173-4558-872f-7af7b4d5065b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202765144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.202765144
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1597980653
Short name T369
Test name
Test status
Simulation time 10805179 ps
CPU time 0.69 seconds
Started Jul 17 07:49:14 PM PDT 24
Finished Jul 17 07:49:17 PM PDT 24
Peak memory 204980 kb
Host smart-3cb613b6-4402-499c-a3e7-ed3d0e661f85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597980653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1597980653
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1162080911
Short name T501
Test name
Test status
Simulation time 1975930616 ps
CPU time 3.57 seconds
Started Jul 17 07:49:15 PM PDT 24
Finished Jul 17 07:49:21 PM PDT 24
Peak memory 224432 kb
Host smart-53e0e656-85a2-45ed-a111-3c88d0072dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162080911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1162080911
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.943521356
Short name T506
Test name
Test status
Simulation time 112894285 ps
CPU time 0.74 seconds
Started Jul 17 07:48:41 PM PDT 24
Finished Jul 17 07:48:45 PM PDT 24
Peak memory 205596 kb
Host smart-710925dc-f369-4d1b-a492-031bd486d225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943521356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.943521356
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1436845054
Short name T223
Test name
Test status
Simulation time 4673220675 ps
CPU time 55.73 seconds
Started Jul 17 07:49:14 PM PDT 24
Finished Jul 17 07:50:12 PM PDT 24
Peak memory 254812 kb
Host smart-e89d32a9-52f6-4d12-aff6-cee8a599f853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436845054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1436845054
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3331890149
Short name T802
Test name
Test status
Simulation time 7136365866 ps
CPU time 65.31 seconds
Started Jul 17 07:49:18 PM PDT 24
Finished Jul 17 07:50:27 PM PDT 24
Peak memory 257000 kb
Host smart-4ffc172f-854e-4672-aae5-382c5d2734bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331890149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3331890149
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.584275163
Short name T311
Test name
Test status
Simulation time 20019232848 ps
CPU time 39.14 seconds
Started Jul 17 07:49:15 PM PDT 24
Finished Jul 17 07:49:56 PM PDT 24
Peak memory 217680 kb
Host smart-08c2d5f2-ff70-4313-bb19-15be704fec56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584275163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.584275163
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1931426940
Short name T303
Test name
Test status
Simulation time 775884575 ps
CPU time 11.95 seconds
Started Jul 17 07:49:16 PM PDT 24
Finished Jul 17 07:49:30 PM PDT 24
Peak memory 232664 kb
Host smart-dd7be347-c084-4517-a891-3d6eb33082df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931426940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1931426940
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.3374596551
Short name T991
Test name
Test status
Simulation time 5978604970 ps
CPU time 77.05 seconds
Started Jul 17 07:49:16 PM PDT 24
Finished Jul 17 07:50:35 PM PDT 24
Peak memory 236488 kb
Host smart-f78e938a-9573-4c07-9e53-7f0a178eca6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374596551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.3374596551
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3679664556
Short name T268
Test name
Test status
Simulation time 32633300 ps
CPU time 2.28 seconds
Started Jul 17 07:48:40 PM PDT 24
Finished Jul 17 07:48:46 PM PDT 24
Peak memory 232572 kb
Host smart-8c098fde-0e03-49a3-9926-09405445665f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679664556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3679664556
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2005360708
Short name T946
Test name
Test status
Simulation time 113581389 ps
CPU time 2.27 seconds
Started Jul 17 07:48:39 PM PDT 24
Finished Jul 17 07:48:45 PM PDT 24
Peak memory 232404 kb
Host smart-cd1fbb9b-a84f-4ec7-806d-81fe8d489612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005360708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2005360708
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3067535077
Short name T293
Test name
Test status
Simulation time 2987280824 ps
CPU time 12.39 seconds
Started Jul 17 07:48:40 PM PDT 24
Finished Jul 17 07:48:56 PM PDT 24
Peak memory 250076 kb
Host smart-c99c2cd4-fc40-46af-89e6-7fb77ca1520f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067535077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3067535077
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1242244305
Short name T845
Test name
Test status
Simulation time 33403073505 ps
CPU time 21.82 seconds
Started Jul 17 07:48:40 PM PDT 24
Finished Jul 17 07:49:06 PM PDT 24
Peak memory 252660 kb
Host smart-a44a9657-a83d-4348-8d5b-1bf9e1208850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242244305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1242244305
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2354764481
Short name T48
Test name
Test status
Simulation time 128771959 ps
CPU time 4.4 seconds
Started Jul 17 07:49:13 PM PDT 24
Finished Jul 17 07:49:19 PM PDT 24
Peak memory 223100 kb
Host smart-d844bd60-9d75-4b0e-952a-3f961b85f7aa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2354764481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2354764481
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1718569812
Short name T574
Test name
Test status
Simulation time 239491145 ps
CPU time 1.06 seconds
Started Jul 17 07:49:20 PM PDT 24
Finished Jul 17 07:49:25 PM PDT 24
Peak memory 207016 kb
Host smart-61902ae1-4b6d-4d0c-9d72-21fb9bd6f364
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718569812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1718569812
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.62867082
Short name T312
Test name
Test status
Simulation time 3940062555 ps
CPU time 11.64 seconds
Started Jul 17 07:48:40 PM PDT 24
Finished Jul 17 07:48:55 PM PDT 24
Peak memory 220100 kb
Host smart-d03d759f-d1aa-460d-8be7-94dbcddc4a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62867082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.62867082
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.721989819
Short name T384
Test name
Test status
Simulation time 6766491039 ps
CPU time 8.23 seconds
Started Jul 17 07:48:41 PM PDT 24
Finished Jul 17 07:48:52 PM PDT 24
Peak memory 216324 kb
Host smart-05344d23-1b9d-4567-a415-ffefae35a44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721989819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.721989819
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1710792125
Short name T996
Test name
Test status
Simulation time 37657658 ps
CPU time 0.75 seconds
Started Jul 17 07:48:40 PM PDT 24
Finished Jul 17 07:48:45 PM PDT 24
Peak memory 205996 kb
Host smart-505ca6c5-4f93-42a3-80c3-64bf2d7e14e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710792125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1710792125
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1976034943
Short name T925
Test name
Test status
Simulation time 44700637 ps
CPU time 0.86 seconds
Started Jul 17 07:48:40 PM PDT 24
Finished Jul 17 07:48:45 PM PDT 24
Peak memory 206344 kb
Host smart-dbd75c60-b606-491b-8a33-71a9c39e4242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976034943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1976034943
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.4074126791
Short name T961
Test name
Test status
Simulation time 741150907 ps
CPU time 4.93 seconds
Started Jul 17 07:48:39 PM PDT 24
Finished Jul 17 07:48:47 PM PDT 24
Peak memory 224476 kb
Host smart-8af46624-d423-4bf2-a336-69f87d0e0f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074126791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.4074126791
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1436057522
Short name T444
Test name
Test status
Simulation time 34953023 ps
CPU time 0.71 seconds
Started Jul 17 07:49:14 PM PDT 24
Finished Jul 17 07:49:16 PM PDT 24
Peak memory 205936 kb
Host smart-cede3a28-1b09-4739-a715-c3ff782510a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436057522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1436057522
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.525740528
Short name T390
Test name
Test status
Simulation time 527321074 ps
CPU time 7.93 seconds
Started Jul 17 07:49:15 PM PDT 24
Finished Jul 17 07:49:25 PM PDT 24
Peak memory 233688 kb
Host smart-03e5b44f-7a77-49e3-880a-df06aa31bbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525740528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.525740528
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1773793360
Short name T870
Test name
Test status
Simulation time 66295862 ps
CPU time 0.78 seconds
Started Jul 17 07:49:13 PM PDT 24
Finished Jul 17 07:49:15 PM PDT 24
Peak memory 206864 kb
Host smart-5f77e841-b01d-4eb6-b78a-ac88430f3ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773793360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1773793360
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1141397445
Short name T226
Test name
Test status
Simulation time 17847136461 ps
CPU time 160.57 seconds
Started Jul 17 07:49:17 PM PDT 24
Finished Jul 17 07:52:00 PM PDT 24
Peak memory 252592 kb
Host smart-6368befa-23bd-4bba-8ca1-e8234b903fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141397445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1141397445
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2031834891
Short name T286
Test name
Test status
Simulation time 13196096238 ps
CPU time 76.99 seconds
Started Jul 17 07:49:15 PM PDT 24
Finished Jul 17 07:50:35 PM PDT 24
Peak memory 270568 kb
Host smart-cd3ad689-acfe-4ba3-9aaf-7ea4e56a0bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031834891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2031834891
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3186537165
Short name T308
Test name
Test status
Simulation time 1648043132 ps
CPU time 29.64 seconds
Started Jul 17 07:49:14 PM PDT 24
Finished Jul 17 07:49:46 PM PDT 24
Peak memory 224608 kb
Host smart-391531a9-5cbc-4a6c-89a0-6c02fd7f890a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186537165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3186537165
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.4190388263
Short name T824
Test name
Test status
Simulation time 127661767 ps
CPU time 3.92 seconds
Started Jul 17 07:49:16 PM PDT 24
Finished Jul 17 07:49:24 PM PDT 24
Peak memory 232652 kb
Host smart-12703eb4-a7bc-4f37-bb78-2c65d469ca08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190388263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.4190388263
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.1536437972
Short name T697
Test name
Test status
Simulation time 50730543544 ps
CPU time 120.97 seconds
Started Jul 17 07:49:14 PM PDT 24
Finished Jul 17 07:51:16 PM PDT 24
Peak memory 256572 kb
Host smart-8b6cbf85-fa4c-41b6-b952-efcfcd2f6c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536437972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.1536437972
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.421385160
Short name T271
Test name
Test status
Simulation time 10045663612 ps
CPU time 22.23 seconds
Started Jul 17 07:49:19 PM PDT 24
Finished Jul 17 07:49:44 PM PDT 24
Peak memory 232836 kb
Host smart-25ab93f8-c779-42a7-b59b-b587a1ca2f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421385160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.421385160
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2962982604
Short name T584
Test name
Test status
Simulation time 3097130334 ps
CPU time 27.99 seconds
Started Jul 17 07:49:18 PM PDT 24
Finished Jul 17 07:49:49 PM PDT 24
Peak memory 240936 kb
Host smart-9721ad30-2e1d-4e42-9dbe-6a39ef89b27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962982604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2962982604
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1157622605
Short name T708
Test name
Test status
Simulation time 5819488244 ps
CPU time 18.21 seconds
Started Jul 17 07:49:18 PM PDT 24
Finished Jul 17 07:49:40 PM PDT 24
Peak memory 240948 kb
Host smart-a12a39a0-a163-43c7-bb60-959e1dacd9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157622605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1157622605
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1263848690
Short name T767
Test name
Test status
Simulation time 65092152 ps
CPU time 3.61 seconds
Started Jul 17 07:49:18 PM PDT 24
Finished Jul 17 07:49:25 PM PDT 24
Peak memory 223152 kb
Host smart-c115ed43-f2c3-419f-bd6c-c079e792ad25
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1263848690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1263848690
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1474994995
Short name T261
Test name
Test status
Simulation time 1334490020 ps
CPU time 32.71 seconds
Started Jul 17 07:49:16 PM PDT 24
Finished Jul 17 07:49:52 PM PDT 24
Peak memory 250832 kb
Host smart-c3247c2d-5dc8-43ca-82b8-f5eeeca5586f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474994995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1474994995
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1399396003
Short name T549
Test name
Test status
Simulation time 7819355295 ps
CPU time 45.09 seconds
Started Jul 17 07:49:13 PM PDT 24
Finished Jul 17 07:49:59 PM PDT 24
Peak memory 216312 kb
Host smart-c8df5e3b-afcd-4665-8af4-f76e3d1c0280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399396003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1399396003
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.634289024
Short name T813
Test name
Test status
Simulation time 69143810758 ps
CPU time 17.2 seconds
Started Jul 17 07:49:13 PM PDT 24
Finished Jul 17 07:49:31 PM PDT 24
Peak memory 216416 kb
Host smart-e3964006-9d0b-483d-ad9b-195b9fe4bb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634289024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.634289024
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3973230883
Short name T553
Test name
Test status
Simulation time 131217131 ps
CPU time 2.74 seconds
Started Jul 17 07:49:15 PM PDT 24
Finished Jul 17 07:49:21 PM PDT 24
Peak memory 216156 kb
Host smart-e18be298-28ba-47eb-8bfc-6ef8bc489a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973230883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3973230883
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2683805417
Short name T617
Test name
Test status
Simulation time 51365136 ps
CPU time 0.85 seconds
Started Jul 17 07:49:14 PM PDT 24
Finished Jul 17 07:49:17 PM PDT 24
Peak memory 205976 kb
Host smart-3c25099f-50b3-4e23-b80e-905e9891c444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683805417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2683805417
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2905684191
Short name T582
Test name
Test status
Simulation time 2529063665 ps
CPU time 5.92 seconds
Started Jul 17 07:49:13 PM PDT 24
Finished Jul 17 07:49:21 PM PDT 24
Peak memory 224604 kb
Host smart-15c0b100-bbda-4e6d-814c-90db2d0cbada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905684191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2905684191
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.599917389
Short name T990
Test name
Test status
Simulation time 12349811 ps
CPU time 0.72 seconds
Started Jul 17 07:49:15 PM PDT 24
Finished Jul 17 07:49:19 PM PDT 24
Peak memory 205516 kb
Host smart-79e6cbe9-d6b5-4351-bb34-2c24a3fb8742
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599917389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.599917389
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2994591821
Short name T757
Test name
Test status
Simulation time 117877389 ps
CPU time 2.77 seconds
Started Jul 17 07:49:15 PM PDT 24
Finished Jul 17 07:49:20 PM PDT 24
Peak memory 224440 kb
Host smart-00dff257-8eae-47a7-89af-484b9c4b42df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994591821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2994591821
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.807051864
Short name T835
Test name
Test status
Simulation time 33860063 ps
CPU time 0.77 seconds
Started Jul 17 07:49:16 PM PDT 24
Finished Jul 17 07:49:20 PM PDT 24
Peak memory 206924 kb
Host smart-8015f3b4-4328-4cb4-b269-4bdcb73fc110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807051864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.807051864
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3856565098
Short name T593
Test name
Test status
Simulation time 15554201449 ps
CPU time 133.57 seconds
Started Jul 17 07:49:14 PM PDT 24
Finished Jul 17 07:51:29 PM PDT 24
Peak memory 256608 kb
Host smart-36f60081-6d4c-4f81-bb96-69803c32a41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856565098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3856565098
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1823276228
Short name T533
Test name
Test status
Simulation time 48045033527 ps
CPU time 112.76 seconds
Started Jul 17 07:49:18 PM PDT 24
Finished Jul 17 07:51:14 PM PDT 24
Peak memory 254352 kb
Host smart-98563df5-18e9-47d6-a60d-262c4e27eb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823276228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1823276228
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1193367420
Short name T449
Test name
Test status
Simulation time 2228131637 ps
CPU time 14.33 seconds
Started Jul 17 07:49:16 PM PDT 24
Finished Jul 17 07:49:33 PM PDT 24
Peak memory 217628 kb
Host smart-4062b3be-166d-4b74-831f-bef10919918b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193367420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1193367420
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.523545080
Short name T581
Test name
Test status
Simulation time 148240562 ps
CPU time 2.94 seconds
Started Jul 17 07:49:15 PM PDT 24
Finished Jul 17 07:49:20 PM PDT 24
Peak memory 232676 kb
Host smart-415be55f-6d4a-4072-ad90-ca45e1c39493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523545080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.523545080
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.1540113538
Short name T8
Test name
Test status
Simulation time 1505120610 ps
CPU time 20.56 seconds
Started Jul 17 07:49:16 PM PDT 24
Finished Jul 17 07:49:40 PM PDT 24
Peak memory 250080 kb
Host smart-322057d7-4a93-4560-a77b-92a042775d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540113538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.1540113538
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3569169431
Short name T721
Test name
Test status
Simulation time 1324586196 ps
CPU time 8.53 seconds
Started Jul 17 07:49:15 PM PDT 24
Finished Jul 17 07:49:25 PM PDT 24
Peak memory 224456 kb
Host smart-9a78d3b6-930c-40a8-a6a4-ad836d2080cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569169431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3569169431
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2647975488
Short name T442
Test name
Test status
Simulation time 2043217049 ps
CPU time 8.82 seconds
Started Jul 17 07:49:19 PM PDT 24
Finished Jul 17 07:49:31 PM PDT 24
Peak memory 232656 kb
Host smart-2ef993cd-cf3d-4e17-a7b9-cefcce2d51b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647975488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2647975488
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.397808520
Short name T497
Test name
Test status
Simulation time 1509133075 ps
CPU time 9.4 seconds
Started Jul 17 07:49:13 PM PDT 24
Finished Jul 17 07:49:24 PM PDT 24
Peak memory 240676 kb
Host smart-84e65c3f-a44c-4477-b7e8-0fda5dababa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397808520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.397808520
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.686179755
Short name T372
Test name
Test status
Simulation time 4779467272 ps
CPU time 9.22 seconds
Started Jul 17 07:49:15 PM PDT 24
Finished Jul 17 07:49:27 PM PDT 24
Peak memory 222696 kb
Host smart-42f7fdfc-e06a-489f-90f7-9500cc2f6e78
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=686179755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.686179755
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3618035654
Short name T838
Test name
Test status
Simulation time 63131900 ps
CPU time 1.13 seconds
Started Jul 17 07:49:18 PM PDT 24
Finished Jul 17 07:49:23 PM PDT 24
Peak memory 215184 kb
Host smart-f0a74c0c-3d50-4511-b5d7-f5a9d7f17fc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618035654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3618035654
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3528698717
Short name T447
Test name
Test status
Simulation time 5431542900 ps
CPU time 16.38 seconds
Started Jul 17 07:49:12 PM PDT 24
Finished Jul 17 07:49:30 PM PDT 24
Peak memory 216372 kb
Host smart-98fb4721-2082-469e-8627-afe8a1ee2ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528698717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3528698717
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.278637287
Short name T981
Test name
Test status
Simulation time 5452868170 ps
CPU time 17.85 seconds
Started Jul 17 07:49:16 PM PDT 24
Finished Jul 17 07:49:36 PM PDT 24
Peak memory 216308 kb
Host smart-57875940-07bf-4344-a460-18533688c46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278637287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.278637287
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1697601684
Short name T323
Test name
Test status
Simulation time 46129746 ps
CPU time 0.76 seconds
Started Jul 17 07:49:12 PM PDT 24
Finished Jul 17 07:49:13 PM PDT 24
Peak memory 205996 kb
Host smart-18b60f4a-8559-48d0-b56f-1b74cfc5ae75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697601684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1697601684
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.649279102
Short name T325
Test name
Test status
Simulation time 109233532 ps
CPU time 0.78 seconds
Started Jul 17 07:49:16 PM PDT 24
Finished Jul 17 07:49:20 PM PDT 24
Peak memory 205992 kb
Host smart-c500312d-f10c-41c9-b001-30209496b1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649279102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.649279102
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2077378532
Short name T256
Test name
Test status
Simulation time 652982303 ps
CPU time 5.09 seconds
Started Jul 17 07:49:17 PM PDT 24
Finished Jul 17 07:49:26 PM PDT 24
Peak memory 232648 kb
Host smart-8a814c9c-af68-4fb7-a1f9-3f57ecff8a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077378532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2077378532
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.69094091
Short name T470
Test name
Test status
Simulation time 175372450 ps
CPU time 0.71 seconds
Started Jul 17 07:49:22 PM PDT 24
Finished Jul 17 07:49:26 PM PDT 24
Peak memory 205544 kb
Host smart-0ef42dc1-3385-4171-b8ed-b1564a0bf8ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69094091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.69094091
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3325926395
Short name T196
Test name
Test status
Simulation time 443524701 ps
CPU time 2.47 seconds
Started Jul 17 07:49:18 PM PDT 24
Finished Jul 17 07:49:25 PM PDT 24
Peak memory 224400 kb
Host smart-27be91af-b079-4033-b469-cac81c601862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325926395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3325926395
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1838302621
Short name T9
Test name
Test status
Simulation time 44959537 ps
CPU time 0.72 seconds
Started Jul 17 07:49:16 PM PDT 24
Finished Jul 17 07:49:20 PM PDT 24
Peak memory 205860 kb
Host smart-14d823a3-2d4b-498c-b3f1-351c9b0cd38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838302621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1838302621
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.994890333
Short name T504
Test name
Test status
Simulation time 18080521557 ps
CPU time 29.74 seconds
Started Jul 17 07:49:23 PM PDT 24
Finished Jul 17 07:49:56 PM PDT 24
Peak memory 250244 kb
Host smart-507b4b12-b591-482e-8661-0e0dc61b4613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994890333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.994890333
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1746177053
Short name T514
Test name
Test status
Simulation time 2172584083 ps
CPU time 22.33 seconds
Started Jul 17 07:49:24 PM PDT 24
Finished Jul 17 07:49:49 PM PDT 24
Peak memory 224624 kb
Host smart-556e657d-36e5-4f6a-b688-c04841d129cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746177053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1746177053
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3977441717
Short name T696
Test name
Test status
Simulation time 133586958 ps
CPU time 2.75 seconds
Started Jul 17 07:49:19 PM PDT 24
Finished Jul 17 07:49:25 PM PDT 24
Peak memory 224472 kb
Host smart-bad33dc5-8c65-47bf-8a82-f15ad73ff7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977441717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3977441717
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.470479078
Short name T922
Test name
Test status
Simulation time 36496360861 ps
CPU time 67.49 seconds
Started Jul 17 07:49:20 PM PDT 24
Finished Jul 17 07:50:31 PM PDT 24
Peak memory 241020 kb
Host smart-1c5476fd-d34d-4015-bf84-a7e01b9f8038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470479078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds
.470479078
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3547732703
Short name T736
Test name
Test status
Simulation time 3435166991 ps
CPU time 29.14 seconds
Started Jul 17 07:49:19 PM PDT 24
Finished Jul 17 07:49:52 PM PDT 24
Peak memory 232784 kb
Host smart-11f0ea97-8705-431e-b766-0efe7f277ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547732703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3547732703
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2675648027
Short name T700
Test name
Test status
Simulation time 1656507265 ps
CPU time 3.95 seconds
Started Jul 17 07:49:17 PM PDT 24
Finished Jul 17 07:49:25 PM PDT 24
Peak memory 224520 kb
Host smart-922c4622-f22e-48f9-ae72-36bdf67b3ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675648027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2675648027
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2101206551
Short name T102
Test name
Test status
Simulation time 1118588181 ps
CPU time 9.7 seconds
Started Jul 17 07:49:21 PM PDT 24
Finished Jul 17 07:49:34 PM PDT 24
Peak memory 224492 kb
Host smart-dd72ae3a-c923-4149-90b0-b8bfa00b3f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101206551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2101206551
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1307401712
Short name T726
Test name
Test status
Simulation time 530044449 ps
CPU time 2.79 seconds
Started Jul 17 07:49:18 PM PDT 24
Finished Jul 17 07:49:25 PM PDT 24
Peak memory 224492 kb
Host smart-3b35895b-e574-46fd-8144-fd9b4beeaf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307401712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1307401712
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2549496128
Short name T137
Test name
Test status
Simulation time 1250276195 ps
CPU time 14.63 seconds
Started Jul 17 07:49:20 PM PDT 24
Finished Jul 17 07:49:38 PM PDT 24
Peak memory 222040 kb
Host smart-392d84ac-b150-4794-b955-8f1729dd4cc8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2549496128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2549496128
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2262810488
Short name T799
Test name
Test status
Simulation time 57514091 ps
CPU time 1.09 seconds
Started Jul 17 07:49:23 PM PDT 24
Finished Jul 17 07:49:27 PM PDT 24
Peak memory 206868 kb
Host smart-4447927f-1e69-4e06-8587-318809b19a09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262810488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2262810488
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.14908292
Short name T983
Test name
Test status
Simulation time 880233227 ps
CPU time 5.43 seconds
Started Jul 17 07:49:17 PM PDT 24
Finished Jul 17 07:49:27 PM PDT 24
Peak memory 216256 kb
Host smart-2b52f49a-2661-46bb-bc6f-58b09b0b6d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14908292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.14908292
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3568346430
Short name T646
Test name
Test status
Simulation time 453734688 ps
CPU time 2.23 seconds
Started Jul 17 07:49:15 PM PDT 24
Finished Jul 17 07:49:20 PM PDT 24
Peak memory 216224 kb
Host smart-f1630ee3-8ba7-43a2-ad1c-98f6bf78f05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568346430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3568346430
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2583252761
Short name T454
Test name
Test status
Simulation time 147480094 ps
CPU time 2.59 seconds
Started Jul 17 07:49:19 PM PDT 24
Finished Jul 17 07:49:25 PM PDT 24
Peak memory 216208 kb
Host smart-04ef6ea2-ba64-4981-a322-6ddcf2c1dcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583252761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2583252761
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3233632419
Short name T680
Test name
Test status
Simulation time 59293293 ps
CPU time 0.81 seconds
Started Jul 17 07:51:09 PM PDT 24
Finished Jul 17 07:51:11 PM PDT 24
Peak memory 205988 kb
Host smart-9b39b29b-2b01-4053-b7d5-2cf2ab7defd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233632419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3233632419
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.617920705
Short name T774
Test name
Test status
Simulation time 3726639011 ps
CPU time 10.9 seconds
Started Jul 17 07:49:22 PM PDT 24
Finished Jul 17 07:49:36 PM PDT 24
Peak memory 240924 kb
Host smart-018c2e02-e7ee-4e79-bcf3-0c15b3c6446f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617920705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.617920705
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.633788340
Short name T998
Test name
Test status
Simulation time 473414623 ps
CPU time 4.61 seconds
Started Jul 17 07:49:19 PM PDT 24
Finished Jul 17 07:49:27 PM PDT 24
Peak memory 224516 kb
Host smart-8ec20685-5481-47c8-825a-b9427310a98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633788340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.633788340
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.136162038
Short name T901
Test name
Test status
Simulation time 48287473 ps
CPU time 0.75 seconds
Started Jul 17 07:49:24 PM PDT 24
Finished Jul 17 07:49:27 PM PDT 24
Peak memory 206592 kb
Host smart-123afd38-f6ea-4a27-a040-71d7362f493c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136162038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.136162038
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3185596544
Short name T622
Test name
Test status
Simulation time 29651914531 ps
CPU time 114.73 seconds
Started Jul 17 07:49:20 PM PDT 24
Finished Jul 17 07:51:18 PM PDT 24
Peak memory 264440 kb
Host smart-528c5581-ea69-4291-b860-9edbdc971ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185596544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3185596544
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1220639123
Short name T676
Test name
Test status
Simulation time 3858371269 ps
CPU time 82.38 seconds
Started Jul 17 07:49:16 PM PDT 24
Finished Jul 17 07:50:41 PM PDT 24
Peak memory 273496 kb
Host smart-3d4a1a54-5920-4829-bf92-725ba0eb7ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220639123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1220639123
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3207599909
Short name T301
Test name
Test status
Simulation time 7301925490 ps
CPU time 42.71 seconds
Started Jul 17 07:49:19 PM PDT 24
Finished Jul 17 07:50:06 PM PDT 24
Peak memory 249976 kb
Host smart-57f4c51d-542d-4241-b250-d5a47b971a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207599909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3207599909
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.2726217747
Short name T587
Test name
Test status
Simulation time 70258024674 ps
CPU time 154.68 seconds
Started Jul 17 07:49:22 PM PDT 24
Finished Jul 17 07:52:00 PM PDT 24
Peak memory 256020 kb
Host smart-336b6d01-3ce3-4666-8c75-e8c975137664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726217747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.2726217747
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.290761346
Short name T421
Test name
Test status
Simulation time 33483017 ps
CPU time 2.44 seconds
Started Jul 17 07:49:19 PM PDT 24
Finished Jul 17 07:49:25 PM PDT 24
Peak memory 232328 kb
Host smart-1d1fa6c9-ae53-4746-895f-a19434543216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290761346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.290761346
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2066861567
Short name T861
Test name
Test status
Simulation time 19624999202 ps
CPU time 86.21 seconds
Started Jul 17 07:49:24 PM PDT 24
Finished Jul 17 07:50:52 PM PDT 24
Peak memory 232764 kb
Host smart-30822ca4-249b-4490-9973-11acd2b9e754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066861567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2066861567
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2473753994
Short name T542
Test name
Test status
Simulation time 3916596226 ps
CPU time 13.35 seconds
Started Jul 17 07:49:24 PM PDT 24
Finished Jul 17 07:49:40 PM PDT 24
Peak memory 232696 kb
Host smart-f0ca0dab-9721-4676-8868-576e7064026a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473753994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2473753994
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.4133934310
Short name T902
Test name
Test status
Simulation time 5380944491 ps
CPU time 12.72 seconds
Started Jul 17 07:49:25 PM PDT 24
Finished Jul 17 07:49:40 PM PDT 24
Peak memory 232836 kb
Host smart-588b5bab-b0fa-4547-8ba7-e17ee7c98c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133934310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.4133934310
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.336294070
Short name T742
Test name
Test status
Simulation time 716937488 ps
CPU time 11.7 seconds
Started Jul 17 07:49:17 PM PDT 24
Finished Jul 17 07:49:32 PM PDT 24
Peak memory 219484 kb
Host smart-89104f78-69fb-459f-8c40-131670d81297
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=336294070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.336294070
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.258793875
Short name T841
Test name
Test status
Simulation time 58164842 ps
CPU time 1.1 seconds
Started Jul 17 07:49:16 PM PDT 24
Finished Jul 17 07:49:21 PM PDT 24
Peak memory 207096 kb
Host smart-ee290f69-1dbe-4e1b-9a4c-00027a1d9b42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258793875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.258793875
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1502866248
Short name T962
Test name
Test status
Simulation time 868912342 ps
CPU time 11.86 seconds
Started Jul 17 07:49:24 PM PDT 24
Finished Jul 17 07:49:39 PM PDT 24
Peak memory 216192 kb
Host smart-07717ff6-cc42-4d10-8036-75f071f61f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502866248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1502866248
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.4006546359
Short name T827
Test name
Test status
Simulation time 1567013988 ps
CPU time 1.97 seconds
Started Jul 17 07:49:24 PM PDT 24
Finished Jul 17 07:49:28 PM PDT 24
Peak memory 207896 kb
Host smart-0504f338-ff63-47b7-a538-8867a7d444ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006546359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.4006546359
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1492852952
Short name T703
Test name
Test status
Simulation time 57275036 ps
CPU time 2.77 seconds
Started Jul 17 07:49:24 PM PDT 24
Finished Jul 17 07:49:29 PM PDT 24
Peak memory 216204 kb
Host smart-88dc0125-93d1-4e05-86ec-057b20b4faa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492852952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1492852952
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1175321021
Short name T868
Test name
Test status
Simulation time 129705345 ps
CPU time 0.9 seconds
Started Jul 17 07:49:21 PM PDT 24
Finished Jul 17 07:49:25 PM PDT 24
Peak memory 207000 kb
Host smart-9b331a82-037e-433e-9805-df58b215d533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175321021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1175321021
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2694755246
Short name T157
Test name
Test status
Simulation time 2538333209 ps
CPU time 4.82 seconds
Started Jul 17 07:49:24 PM PDT 24
Finished Jul 17 07:49:31 PM PDT 24
Peak memory 232748 kb
Host smart-a4f66c3b-7c4c-4cff-946b-f52723ff34a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694755246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2694755246
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.368980600
Short name T900
Test name
Test status
Simulation time 13814078 ps
CPU time 0.77 seconds
Started Jul 17 07:49:23 PM PDT 24
Finished Jul 17 07:49:27 PM PDT 24
Peak memory 205872 kb
Host smart-7dbcf366-54f2-48bc-892f-5fabfd5be1f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368980600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.368980600
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.285644318
Short name T405
Test name
Test status
Simulation time 6139145542 ps
CPU time 25.35 seconds
Started Jul 17 07:49:17 PM PDT 24
Finished Jul 17 07:49:46 PM PDT 24
Peak memory 232748 kb
Host smart-8916d0fb-26ba-431d-ab9c-6d8aac80a44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285644318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.285644318
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3515418584
Short name T66
Test name
Test status
Simulation time 20575740 ps
CPU time 0.78 seconds
Started Jul 17 07:49:13 PM PDT 24
Finished Jul 17 07:49:14 PM PDT 24
Peak memory 206676 kb
Host smart-0775cdb5-3e3c-43b6-9906-4ae2f87e0a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515418584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3515418584
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3187432920
Short name T643
Test name
Test status
Simulation time 19953781031 ps
CPU time 172.87 seconds
Started Jul 17 07:49:17 PM PDT 24
Finished Jul 17 07:52:14 PM PDT 24
Peak memory 255556 kb
Host smart-4a5e87e2-103a-4ed1-9398-39938912e60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187432920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3187432920
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3342135926
Short name T859
Test name
Test status
Simulation time 1402100691 ps
CPU time 20.03 seconds
Started Jul 17 07:49:19 PM PDT 24
Finished Jul 17 07:49:43 PM PDT 24
Peak memory 236956 kb
Host smart-b8aa733b-faf2-4103-a6fb-a144b3bf39e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342135926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3342135926
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.2914354391
Short name T976
Test name
Test status
Simulation time 13202081627 ps
CPU time 80.16 seconds
Started Jul 17 07:49:17 PM PDT 24
Finished Jul 17 07:50:40 PM PDT 24
Peak memory 249204 kb
Host smart-16b27ce7-c3c8-4e89-8b7e-6f80cf5eb79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914354391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.2914354391
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1403133951
Short name T231
Test name
Test status
Simulation time 174792395 ps
CPU time 3.91 seconds
Started Jul 17 07:49:22 PM PDT 24
Finished Jul 17 07:49:29 PM PDT 24
Peak memory 224436 kb
Host smart-8b7a018d-da85-45da-8c39-c04edc513523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403133951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1403133951
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1546033492
Short name T633
Test name
Test status
Simulation time 3399897411 ps
CPU time 26.18 seconds
Started Jul 17 07:49:20 PM PDT 24
Finished Jul 17 07:49:49 PM PDT 24
Peak memory 232712 kb
Host smart-5c02e482-ab97-46ea-a659-b67325f1f2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546033492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1546033492
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.471322791
Short name T557
Test name
Test status
Simulation time 7970783923 ps
CPU time 8.55 seconds
Started Jul 17 07:49:16 PM PDT 24
Finished Jul 17 07:49:28 PM PDT 24
Peak memory 224564 kb
Host smart-a9be15dc-4803-497e-8d54-3214720b4612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471322791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.471322791
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1109861498
Short name T804
Test name
Test status
Simulation time 4686923775 ps
CPU time 11.58 seconds
Started Jul 17 07:49:15 PM PDT 24
Finished Jul 17 07:49:30 PM PDT 24
Peak memory 232784 kb
Host smart-83fe08e9-006f-4dff-9a1e-c865f3579d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109861498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1109861498
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1279432942
Short name T80
Test name
Test status
Simulation time 2452557410 ps
CPU time 5.02 seconds
Started Jul 17 07:49:21 PM PDT 24
Finished Jul 17 07:49:29 PM PDT 24
Peak memory 219500 kb
Host smart-dc670135-dfa2-4579-8aee-a5c667d0bb65
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1279432942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1279432942
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.715956731
Short name T60
Test name
Test status
Simulation time 778447846188 ps
CPU time 652.02 seconds
Started Jul 17 07:49:20 PM PDT 24
Finished Jul 17 08:00:16 PM PDT 24
Peak memory 282936 kb
Host smart-e50cb528-3428-40d7-b17d-d49061315701
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715956731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.715956731
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2027382431
Short name T653
Test name
Test status
Simulation time 4677581993 ps
CPU time 12.89 seconds
Started Jul 17 07:49:15 PM PDT 24
Finished Jul 17 07:49:29 PM PDT 24
Peak memory 216216 kb
Host smart-3c394516-ea8d-444c-85b9-2e9566aa1373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027382431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2027382431
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1872676161
Short name T335
Test name
Test status
Simulation time 9908949014 ps
CPU time 4.51 seconds
Started Jul 17 07:49:16 PM PDT 24
Finished Jul 17 07:49:23 PM PDT 24
Peak memory 216316 kb
Host smart-a3572316-7e54-49ae-b594-6329fde16394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872676161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1872676161
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.666062481
Short name T409
Test name
Test status
Simulation time 280262761 ps
CPU time 1.53 seconds
Started Jul 17 07:49:13 PM PDT 24
Finished Jul 17 07:49:16 PM PDT 24
Peak memory 216288 kb
Host smart-17a949fe-b1c3-4cb0-bb2f-fecd18ce9440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666062481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.666062481
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.233908735
Short name T632
Test name
Test status
Simulation time 77185670 ps
CPU time 0.85 seconds
Started Jul 17 07:49:19 PM PDT 24
Finished Jul 17 07:49:23 PM PDT 24
Peak memory 205968 kb
Host smart-620be0ee-f295-4ddd-89b4-94ebbd59f088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233908735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.233908735
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1531750005
Short name T460
Test name
Test status
Simulation time 1489022559 ps
CPU time 8.55 seconds
Started Jul 17 07:49:17 PM PDT 24
Finished Jul 17 07:49:30 PM PDT 24
Peak memory 224496 kb
Host smart-0eb3b5d5-5866-4983-a881-64f4f19ac977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531750005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1531750005
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.236768310
Short name T406
Test name
Test status
Simulation time 26735067 ps
CPU time 0.71 seconds
Started Jul 17 07:49:46 PM PDT 24
Finished Jul 17 07:49:48 PM PDT 24
Peak memory 205548 kb
Host smart-2e7b1135-3210-47ec-97c8-ad53d94f4370
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236768310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.236768310
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.362041304
Short name T259
Test name
Test status
Simulation time 185065681 ps
CPU time 4.73 seconds
Started Jul 17 07:49:13 PM PDT 24
Finished Jul 17 07:49:19 PM PDT 24
Peak memory 232652 kb
Host smart-64c363cb-5f45-49b7-b803-966950aa7df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362041304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.362041304
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2779265638
Short name T796
Test name
Test status
Simulation time 26108139 ps
CPU time 0.76 seconds
Started Jul 17 07:49:22 PM PDT 24
Finished Jul 17 07:49:26 PM PDT 24
Peak memory 205904 kb
Host smart-6c33864f-d2bc-4ce5-8296-d59b9d91dbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779265638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2779265638
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3493405190
Short name T274
Test name
Test status
Simulation time 21141997512 ps
CPU time 52.46 seconds
Started Jul 17 07:49:45 PM PDT 24
Finished Jul 17 07:50:38 PM PDT 24
Peak memory 240980 kb
Host smart-9b56af90-46c7-41af-9ecb-66c21580ccfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493405190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3493405190
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3666072899
Short name T315
Test name
Test status
Simulation time 3967356750 ps
CPU time 5.66 seconds
Started Jul 17 07:49:45 PM PDT 24
Finished Jul 17 07:49:52 PM PDT 24
Peak memory 217672 kb
Host smart-ebac5782-b160-4358-9c17-81e0ee9ecc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666072899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3666072899
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2463923908
Short name T887
Test name
Test status
Simulation time 77470599454 ps
CPU time 219.84 seconds
Started Jul 17 07:49:45 PM PDT 24
Finished Jul 17 07:53:26 PM PDT 24
Peak memory 265668 kb
Host smart-bce34e62-14df-48bd-aff4-3254dce351ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463923908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2463923908
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.3858143406
Short name T923
Test name
Test status
Simulation time 5305428477 ps
CPU time 58.2 seconds
Started Jul 17 07:49:45 PM PDT 24
Finished Jul 17 07:50:45 PM PDT 24
Peak memory 252608 kb
Host smart-dfc101f7-1375-4fe4-b7da-0d44185070b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858143406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.3858143406
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.4268390703
Short name T578
Test name
Test status
Simulation time 889425282 ps
CPU time 5.89 seconds
Started Jul 17 07:49:17 PM PDT 24
Finished Jul 17 07:49:26 PM PDT 24
Peak memory 224388 kb
Host smart-cc63b6bf-10f1-4eb4-b580-178947718b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268390703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.4268390703
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2644846186
Short name T1001
Test name
Test status
Simulation time 2490222784 ps
CPU time 7.91 seconds
Started Jul 17 07:49:15 PM PDT 24
Finished Jul 17 07:49:25 PM PDT 24
Peak memory 233504 kb
Host smart-cefaa9c1-718c-49aa-b402-787a923004f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644846186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2644846186
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2464197764
Short name T232
Test name
Test status
Simulation time 886634261 ps
CPU time 3.13 seconds
Started Jul 17 07:49:17 PM PDT 24
Finished Jul 17 07:49:23 PM PDT 24
Peak memory 232596 kb
Host smart-99a95d8c-ef76-44c2-8f81-bdc19693f0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464197764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2464197764
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1790313779
Short name T544
Test name
Test status
Simulation time 21647284395 ps
CPU time 6.4 seconds
Started Jul 17 07:49:19 PM PDT 24
Finished Jul 17 07:49:29 PM PDT 24
Peak memory 218956 kb
Host smart-21d47c50-f109-4025-82ef-53548433e64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790313779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1790313779
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1577426904
Short name T338
Test name
Test status
Simulation time 1362555800 ps
CPU time 8.6 seconds
Started Jul 17 07:49:47 PM PDT 24
Finished Jul 17 07:49:58 PM PDT 24
Peak memory 220876 kb
Host smart-db602b3a-a7a9-4996-ada8-3b131c415bdb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1577426904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1577426904
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1558048831
Short name T678
Test name
Test status
Simulation time 6917997451 ps
CPU time 38.98 seconds
Started Jul 17 07:49:46 PM PDT 24
Finished Jul 17 07:50:27 PM PDT 24
Peak memory 250300 kb
Host smart-68b2ee8a-fa6d-4fee-a46d-414a5ca38ff6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558048831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1558048831
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2286676227
Short name T415
Test name
Test status
Simulation time 4193035446 ps
CPU time 4.11 seconds
Started Jul 17 07:49:22 PM PDT 24
Finished Jul 17 07:49:29 PM PDT 24
Peak memory 216320 kb
Host smart-0fc3baa9-7008-40b8-8fb1-63c2bc85df49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286676227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2286676227
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1862175391
Short name T320
Test name
Test status
Simulation time 3167685594 ps
CPU time 10.24 seconds
Started Jul 17 07:49:23 PM PDT 24
Finished Jul 17 07:49:36 PM PDT 24
Peak memory 216336 kb
Host smart-218af6e3-a7ff-4a6b-b0a1-3267d4c3b3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862175391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1862175391
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2902041239
Short name T898
Test name
Test status
Simulation time 393016932 ps
CPU time 7.38 seconds
Started Jul 17 07:49:24 PM PDT 24
Finished Jul 17 07:49:34 PM PDT 24
Peak memory 216180 kb
Host smart-172d128f-662a-4bd6-a17d-db467867ffb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902041239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2902041239
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.610158311
Short name T735
Test name
Test status
Simulation time 29288726 ps
CPU time 0.88 seconds
Started Jul 17 07:49:27 PM PDT 24
Finished Jul 17 07:49:29 PM PDT 24
Peak memory 205980 kb
Host smart-a25202fe-6ac1-41a0-a422-bf17bfa8858b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610158311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.610158311
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2317091444
Short name T555
Test name
Test status
Simulation time 108813270 ps
CPU time 2.96 seconds
Started Jul 17 07:49:15 PM PDT 24
Finished Jul 17 07:49:20 PM PDT 24
Peak memory 232648 kb
Host smart-3881d7fa-e709-4158-a050-d521b77f17d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317091444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2317091444
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.922358283
Short name T640
Test name
Test status
Simulation time 35762399 ps
CPU time 0.76 seconds
Started Jul 17 07:49:46 PM PDT 24
Finished Jul 17 07:49:49 PM PDT 24
Peak memory 205544 kb
Host smart-a2aab292-3ba4-4dd4-9b8c-d0a951ec26f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922358283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.922358283
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3105969615
Short name T327
Test name
Test status
Simulation time 179643378 ps
CPU time 2.82 seconds
Started Jul 17 07:49:46 PM PDT 24
Finished Jul 17 07:49:50 PM PDT 24
Peak memory 232640 kb
Host smart-c8371293-e481-4fa8-b663-bb865b0a6b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105969615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3105969615
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3229116467
Short name T977
Test name
Test status
Simulation time 51761965 ps
CPU time 0.76 seconds
Started Jul 17 07:49:45 PM PDT 24
Finished Jul 17 07:49:46 PM PDT 24
Peak memory 205912 kb
Host smart-651840df-2f66-4f1d-b042-3ecb2e022428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229116467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3229116467
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.134251149
Short name T531
Test name
Test status
Simulation time 6325210865 ps
CPU time 23.79 seconds
Started Jul 17 07:49:47 PM PDT 24
Finished Jul 17 07:50:13 PM PDT 24
Peak memory 240952 kb
Host smart-980524c0-f659-4d10-acb2-228361712c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134251149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.134251149
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2521802597
Short name T536
Test name
Test status
Simulation time 148084577528 ps
CPU time 357.51 seconds
Started Jul 17 07:49:45 PM PDT 24
Finished Jul 17 07:55:44 PM PDT 24
Peak memory 254872 kb
Host smart-1ddc758f-a3cb-4ebc-941b-e04a9331eec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521802597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2521802597
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3204935931
Short name T374
Test name
Test status
Simulation time 1554358027 ps
CPU time 5.47 seconds
Started Jul 17 07:49:46 PM PDT 24
Finished Jul 17 07:49:54 PM PDT 24
Peak memory 232700 kb
Host smart-487e639f-bcf8-426f-b0d9-9ff59d9dc3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204935931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3204935931
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.2142390287
Short name T229
Test name
Test status
Simulation time 53024461889 ps
CPU time 89.08 seconds
Started Jul 17 07:49:57 PM PDT 24
Finished Jul 17 07:51:32 PM PDT 24
Peak memory 252048 kb
Host smart-04236dd5-6228-4c53-bfd6-8e5c6ad117bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142390287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.2142390287
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.613642815
Short name T486
Test name
Test status
Simulation time 1096518060 ps
CPU time 2.99 seconds
Started Jul 17 07:49:49 PM PDT 24
Finished Jul 17 07:49:55 PM PDT 24
Peak memory 224464 kb
Host smart-1d331004-ebe8-49b4-8e28-3f74de0012e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613642815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.613642815
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1374582663
Short name T860
Test name
Test status
Simulation time 43939357 ps
CPU time 2.87 seconds
Started Jul 17 07:49:45 PM PDT 24
Finished Jul 17 07:49:49 PM PDT 24
Peak memory 232708 kb
Host smart-0f20ba54-07dd-44bb-9f6a-88b0ad15a61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374582663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1374582663
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2733126967
Short name T562
Test name
Test status
Simulation time 3586083908 ps
CPU time 11.26 seconds
Started Jul 17 07:49:46 PM PDT 24
Finished Jul 17 07:49:59 PM PDT 24
Peak memory 224568 kb
Host smart-9201e2b2-54d0-4148-bdbd-443d297a69c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733126967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2733126967
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3709222331
Short name T855
Test name
Test status
Simulation time 7517765978 ps
CPU time 4.34 seconds
Started Jul 17 07:49:47 PM PDT 24
Finished Jul 17 07:49:54 PM PDT 24
Peak memory 218788 kb
Host smart-ccb218f1-97f4-4a1f-b71b-dcac6f90b38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709222331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3709222331
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3038988966
Short name T150
Test name
Test status
Simulation time 370430888 ps
CPU time 4.13 seconds
Started Jul 17 07:49:48 PM PDT 24
Finished Jul 17 07:49:55 PM PDT 24
Peak memory 222576 kb
Host smart-eba5be00-cc3a-478f-83bc-2ffa1e579db5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3038988966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3038988966
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.194363666
Short name T916
Test name
Test status
Simulation time 24979894144 ps
CPU time 283.4 seconds
Started Jul 17 07:49:46 PM PDT 24
Finished Jul 17 07:54:31 PM PDT 24
Peak memory 265120 kb
Host smart-ae205f25-79a1-4231-b25b-d4557e756c3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194363666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.194363666
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1769184396
Short name T968
Test name
Test status
Simulation time 2277908716 ps
CPU time 8.15 seconds
Started Jul 17 07:49:48 PM PDT 24
Finished Jul 17 07:49:59 PM PDT 24
Peak memory 216316 kb
Host smart-bce96c5d-3742-4f93-b617-05b30d8c800d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769184396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1769184396
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3095245366
Short name T658
Test name
Test status
Simulation time 1431437953 ps
CPU time 1.34 seconds
Started Jul 17 07:49:48 PM PDT 24
Finished Jul 17 07:49:53 PM PDT 24
Peak memory 207904 kb
Host smart-983d65df-1918-4e60-9b8b-89cb82b8f9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095245366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3095245366
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.4086435240
Short name T592
Test name
Test status
Simulation time 51684066 ps
CPU time 1.3 seconds
Started Jul 17 07:49:49 PM PDT 24
Finished Jul 17 07:49:53 PM PDT 24
Peak memory 216260 kb
Host smart-649f3cd5-9063-48e3-a812-d8a3d9559cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086435240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.4086435240
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.4036499582
Short name T924
Test name
Test status
Simulation time 22656860 ps
CPU time 0.67 seconds
Started Jul 17 07:49:48 PM PDT 24
Finished Jul 17 07:49:52 PM PDT 24
Peak memory 205648 kb
Host smart-990fabeb-7f32-4884-a2c1-6059b0a045f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036499582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.4036499582
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.902733451
Short name T947
Test name
Test status
Simulation time 760001727 ps
CPU time 6.11 seconds
Started Jul 17 07:49:46 PM PDT 24
Finished Jul 17 07:49:54 PM PDT 24
Peak memory 224600 kb
Host smart-c9f06a35-6624-43aa-9e4c-e028c6263ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902733451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.902733451
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1341854573
Short name T733
Test name
Test status
Simulation time 36664080 ps
CPU time 0.71 seconds
Started Jul 17 07:49:55 PM PDT 24
Finished Jul 17 07:50:01 PM PDT 24
Peak memory 205876 kb
Host smart-e6b0cd8e-d01f-404a-aa65-409ff9288577
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341854573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1341854573
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3512503347
Short name T964
Test name
Test status
Simulation time 117203232 ps
CPU time 4.08 seconds
Started Jul 17 07:49:55 PM PDT 24
Finished Jul 17 07:50:04 PM PDT 24
Peak memory 232628 kb
Host smart-2bde4147-d530-40a8-bbdc-0f96261fdad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512503347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3512503347
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3874874715
Short name T370
Test name
Test status
Simulation time 24599416 ps
CPU time 0.79 seconds
Started Jul 17 07:49:55 PM PDT 24
Finished Jul 17 07:50:01 PM PDT 24
Peak memory 206528 kb
Host smart-445eeaf0-3f1c-4230-b400-90c5f95bd0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874874715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3874874715
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1804944396
Short name T492
Test name
Test status
Simulation time 13887373880 ps
CPU time 71.46 seconds
Started Jul 17 07:49:53 PM PDT 24
Finished Jul 17 07:51:08 PM PDT 24
Peak memory 260712 kb
Host smart-b8c0fb5b-700b-4c8c-9752-6346f733a710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804944396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1804944396
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3584974609
Short name T645
Test name
Test status
Simulation time 46221039866 ps
CPU time 97.05 seconds
Started Jul 17 07:49:55 PM PDT 24
Finished Jul 17 07:51:37 PM PDT 24
Peak memory 241080 kb
Host smart-73853d02-576d-488d-afc4-46d15b627b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584974609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3584974609
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.61254015
Short name T747
Test name
Test status
Simulation time 6720463786 ps
CPU time 20.66 seconds
Started Jul 17 07:49:49 PM PDT 24
Finished Jul 17 07:50:13 PM PDT 24
Peak memory 240996 kb
Host smart-585f6fda-38f5-4f49-9350-5e46b1b24ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61254015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.61254015
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.2452897877
Short name T882
Test name
Test status
Simulation time 72485323 ps
CPU time 0.81 seconds
Started Jul 17 07:49:55 PM PDT 24
Finished Jul 17 07:50:01 PM PDT 24
Peak memory 215936 kb
Host smart-ece584a1-2aa0-4554-976f-6366f019f2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452897877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.2452897877
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1872296896
Short name T476
Test name
Test status
Simulation time 179886109 ps
CPU time 2.19 seconds
Started Jul 17 07:49:50 PM PDT 24
Finished Jul 17 07:49:55 PM PDT 24
Peak memory 222692 kb
Host smart-2516ef3e-638a-42ad-95ee-8b6f7a76fcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872296896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1872296896
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2312861860
Short name T711
Test name
Test status
Simulation time 1694786026 ps
CPU time 3.91 seconds
Started Jul 17 07:49:49 PM PDT 24
Finished Jul 17 07:49:56 PM PDT 24
Peak memory 218848 kb
Host smart-e31da012-c160-4d08-ab8e-beb676fc21b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312861860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2312861860
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3584476327
Short name T885
Test name
Test status
Simulation time 5287579299 ps
CPU time 16.64 seconds
Started Jul 17 07:49:49 PM PDT 24
Finished Jul 17 07:50:09 PM PDT 24
Peak memory 232840 kb
Host smart-4414e194-5d22-4e5f-b6f0-a5c90c635e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584476327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3584476327
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2697958075
Short name T139
Test name
Test status
Simulation time 18868392720 ps
CPU time 11.43 seconds
Started Jul 17 07:49:48 PM PDT 24
Finished Jul 17 07:50:02 PM PDT 24
Peak memory 224664 kb
Host smart-3cc087a3-5959-4642-85bf-edece5cb4e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697958075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2697958075
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2428162761
Short name T478
Test name
Test status
Simulation time 1652199777 ps
CPU time 10.5 seconds
Started Jul 17 07:49:52 PM PDT 24
Finished Jul 17 07:50:06 PM PDT 24
Peak memory 219168 kb
Host smart-6a796628-32bf-47f4-b424-934540ec16de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2428162761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2428162761
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1600134060
Short name T398
Test name
Test status
Simulation time 46010350 ps
CPU time 0.91 seconds
Started Jul 17 07:49:50 PM PDT 24
Finished Jul 17 07:49:54 PM PDT 24
Peak memory 206620 kb
Host smart-07733fb2-1943-4b11-8b00-316e34186b38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600134060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1600134060
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1387609662
Short name T641
Test name
Test status
Simulation time 61252202321 ps
CPU time 33.6 seconds
Started Jul 17 07:49:48 PM PDT 24
Finished Jul 17 07:50:25 PM PDT 24
Peak memory 216380 kb
Host smart-ba5e4ec7-46cd-4c54-96e7-7140bb8256d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387609662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1387609662
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3066408230
Short name T800
Test name
Test status
Simulation time 2358308989 ps
CPU time 7.78 seconds
Started Jul 17 07:49:54 PM PDT 24
Finished Jul 17 07:50:07 PM PDT 24
Peak memory 215872 kb
Host smart-ee038728-2d0e-49be-9db9-5c0b2a2f87fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066408230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3066408230
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.4103959802
Short name T439
Test name
Test status
Simulation time 248849143 ps
CPU time 4.09 seconds
Started Jul 17 07:49:48 PM PDT 24
Finished Jul 17 07:49:55 PM PDT 24
Peak memory 216420 kb
Host smart-e67dea99-d06a-48a7-9578-12644618da3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103959802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.4103959802
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.296922139
Short name T912
Test name
Test status
Simulation time 658828785 ps
CPU time 0.85 seconds
Started Jul 17 07:49:48 PM PDT 24
Finished Jul 17 07:49:52 PM PDT 24
Peak memory 205904 kb
Host smart-9fb87bd6-56eb-42d2-8ae4-f807d0fab379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296922139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.296922139
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3670191502
Short name T273
Test name
Test status
Simulation time 14885333605 ps
CPU time 43.02 seconds
Started Jul 17 07:49:55 PM PDT 24
Finished Jul 17 07:50:43 PM PDT 24
Peak memory 240776 kb
Host smart-95a93d01-ddc9-4f49-87c1-74c009b968d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670191502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3670191502
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.4044725404
Short name T698
Test name
Test status
Simulation time 21555076 ps
CPU time 0.76 seconds
Started Jul 17 07:50:01 PM PDT 24
Finished Jul 17 07:50:06 PM PDT 24
Peak memory 205548 kb
Host smart-afd55568-9083-42c9-9d3c-009809d13069
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044725404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
4044725404
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.528529511
Short name T246
Test name
Test status
Simulation time 236136947 ps
CPU time 4.1 seconds
Started Jul 17 07:49:58 PM PDT 24
Finished Jul 17 07:50:08 PM PDT 24
Peak memory 232680 kb
Host smart-f0453db4-4d1d-4fd0-90cd-c4f65de9b883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528529511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.528529511
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2527646029
Short name T322
Test name
Test status
Simulation time 44951282 ps
CPU time 0.77 seconds
Started Jul 17 07:49:57 PM PDT 24
Finished Jul 17 07:50:04 PM PDT 24
Peak memory 206912 kb
Host smart-5772b11e-4061-4df2-ba46-d7b513951555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527646029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2527646029
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.4188701843
Short name T500
Test name
Test status
Simulation time 121539474 ps
CPU time 1.05 seconds
Started Jul 17 07:50:01 PM PDT 24
Finished Jul 17 07:50:07 PM PDT 24
Peak memory 215936 kb
Host smart-c6cd066a-b7f9-480d-832b-66bc08eb0184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188701843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.4188701843
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.4188670170
Short name T61
Test name
Test status
Simulation time 18257382381 ps
CPU time 144.23 seconds
Started Jul 17 07:49:58 PM PDT 24
Finished Jul 17 07:52:28 PM PDT 24
Peak memory 254396 kb
Host smart-d18e7361-5694-410c-ac41-400904763c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188670170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.4188670170
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3767197435
Short name T207
Test name
Test status
Simulation time 4755241442 ps
CPU time 94.42 seconds
Started Jul 17 07:49:50 PM PDT 24
Finished Jul 17 07:51:28 PM PDT 24
Peak memory 257456 kb
Host smart-a2d086c5-1a55-432b-a621-6bf256969e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767197435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3767197435
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.4260468318
Short name T298
Test name
Test status
Simulation time 497597184 ps
CPU time 5.82 seconds
Started Jul 17 07:49:57 PM PDT 24
Finished Jul 17 07:50:09 PM PDT 24
Peak memory 224440 kb
Host smart-ee840ec9-814e-45d4-b261-ff4fa05d6a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260468318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.4260468318
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.7590979
Short name T710
Test name
Test status
Simulation time 33346374593 ps
CPU time 208.61 seconds
Started Jul 17 07:49:58 PM PDT 24
Finished Jul 17 07:53:32 PM PDT 24
Peak memory 249196 kb
Host smart-c292312c-4ac9-4499-b219-58d6eebba653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7590979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds.7590979
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2302381031
Short name T160
Test name
Test status
Simulation time 560585001 ps
CPU time 3.98 seconds
Started Jul 17 07:49:58 PM PDT 24
Finished Jul 17 07:50:08 PM PDT 24
Peak memory 232704 kb
Host smart-2535e85d-f73f-4901-b88f-007249cd43a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302381031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2302381031
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2658652306
Short name T4
Test name
Test status
Simulation time 362830477 ps
CPU time 10.75 seconds
Started Jul 17 07:49:57 PM PDT 24
Finished Jul 17 07:50:14 PM PDT 24
Peak memory 240584 kb
Host smart-3b36e9f3-38da-4061-9201-06e3c2e031b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658652306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2658652306
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.4261173997
Short name T665
Test name
Test status
Simulation time 2004929779 ps
CPU time 5.1 seconds
Started Jul 17 07:49:57 PM PDT 24
Finished Jul 17 07:50:08 PM PDT 24
Peak memory 232712 kb
Host smart-0e771781-3bc7-403f-8aa5-c571472b9531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261173997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.4261173997
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2742179194
Short name T573
Test name
Test status
Simulation time 411984296 ps
CPU time 4.9 seconds
Started Jul 17 07:49:57 PM PDT 24
Finished Jul 17 07:50:08 PM PDT 24
Peak memory 232652 kb
Host smart-aadedd85-4f4a-4308-8176-cb611665ba07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742179194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2742179194
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.966728932
Short name T541
Test name
Test status
Simulation time 506556604 ps
CPU time 5.57 seconds
Started Jul 17 07:49:59 PM PDT 24
Finished Jul 17 07:50:10 PM PDT 24
Peak memory 220524 kb
Host smart-2c0f0cc0-2a25-4105-8912-63eb74d3165d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=966728932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.966728932
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.792228246
Short name T41
Test name
Test status
Simulation time 199912831226 ps
CPU time 396.23 seconds
Started Jul 17 07:50:01 PM PDT 24
Finished Jul 17 07:56:42 PM PDT 24
Peak memory 257400 kb
Host smart-e0a4aea3-56a9-4a5f-ab6c-bd6028ba96a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792228246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.792228246
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.235362658
Short name T30
Test name
Test status
Simulation time 5901316528 ps
CPU time 31.3 seconds
Started Jul 17 07:49:56 PM PDT 24
Finished Jul 17 07:50:33 PM PDT 24
Peak memory 216328 kb
Host smart-f6a80c15-d2ba-4d06-a223-245fa29823d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235362658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.235362658
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3045957290
Short name T634
Test name
Test status
Simulation time 696693861 ps
CPU time 2.93 seconds
Started Jul 17 07:49:57 PM PDT 24
Finished Jul 17 07:50:06 PM PDT 24
Peak memory 216096 kb
Host smart-c4b22659-e557-4464-b793-6f77241afd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045957290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3045957290
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.844426901
Short name T391
Test name
Test status
Simulation time 88188627 ps
CPU time 2.96 seconds
Started Jul 17 07:49:56 PM PDT 24
Finished Jul 17 07:50:05 PM PDT 24
Peak memory 216176 kb
Host smart-611653c7-086e-485f-8d1c-7e081fcef87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844426901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.844426901
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3048279804
Short name T672
Test name
Test status
Simulation time 92121402 ps
CPU time 0.92 seconds
Started Jul 17 07:49:57 PM PDT 24
Finished Jul 17 07:50:04 PM PDT 24
Peak memory 205976 kb
Host smart-c86117d7-82ec-4cde-a500-41469fe8218d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048279804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3048279804
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.730979920
Short name T730
Test name
Test status
Simulation time 88917705 ps
CPU time 0.7 seconds
Started Jul 17 07:48:11 PM PDT 24
Finished Jul 17 07:48:15 PM PDT 24
Peak memory 204964 kb
Host smart-284db5ae-0bb4-40e3-bd62-2b3530828c2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730979920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.730979920
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1007014420
Short name T95
Test name
Test status
Simulation time 3386729532 ps
CPU time 8.85 seconds
Started Jul 17 07:48:12 PM PDT 24
Finished Jul 17 07:48:24 PM PDT 24
Peak memory 224584 kb
Host smart-cef70efd-9bcf-404b-8a55-39f902d4f86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007014420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1007014420
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1264710600
Short name T537
Test name
Test status
Simulation time 69099100 ps
CPU time 0.73 seconds
Started Jul 17 07:47:46 PM PDT 24
Finished Jul 17 07:47:48 PM PDT 24
Peak memory 205888 kb
Host smart-8df51155-d952-46c2-87bd-c34a6285c820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264710600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1264710600
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2002728242
Short name T10
Test name
Test status
Simulation time 17921708272 ps
CPU time 149.51 seconds
Started Jul 17 07:48:10 PM PDT 24
Finished Jul 17 07:50:41 PM PDT 24
Peak memory 252160 kb
Host smart-43fa484f-0c9b-40e7-8447-a3bd4ab4ec39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002728242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2002728242
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3423216551
Short name T260
Test name
Test status
Simulation time 36528126596 ps
CPU time 244.5 seconds
Started Jul 17 07:48:24 PM PDT 24
Finished Jul 17 07:52:29 PM PDT 24
Peak memory 248928 kb
Host smart-873dd48d-a4cb-41e0-9a7a-1f1fda8feaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423216551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3423216551
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1548447435
Short name T942
Test name
Test status
Simulation time 72305537241 ps
CPU time 332.39 seconds
Started Jul 17 07:48:09 PM PDT 24
Finished Jul 17 07:53:43 PM PDT 24
Peak memory 257420 kb
Host smart-89dd980b-7d26-4884-982a-02b59b7d17f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548447435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1548447435
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2769047272
Short name T420
Test name
Test status
Simulation time 213372265 ps
CPU time 4 seconds
Started Jul 17 07:48:11 PM PDT 24
Finished Jul 17 07:48:17 PM PDT 24
Peak memory 240748 kb
Host smart-8fa29f21-1e84-474b-842d-ee42486c9adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769047272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2769047272
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.3146696889
Short name T450
Test name
Test status
Simulation time 1184551825 ps
CPU time 10.42 seconds
Started Jul 17 07:48:11 PM PDT 24
Finished Jul 17 07:48:25 PM PDT 24
Peak memory 224412 kb
Host smart-dc8abfaf-17af-45b4-96e1-edcc90d6c735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146696889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.3146696889
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1157589249
Short name T1000
Test name
Test status
Simulation time 9004560558 ps
CPU time 18.44 seconds
Started Jul 17 07:48:11 PM PDT 24
Finished Jul 17 07:48:33 PM PDT 24
Peak memory 224544 kb
Host smart-b9403733-8bb7-4879-b9df-267dcd975807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157589249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1157589249
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1601309213
Short name T997
Test name
Test status
Simulation time 7301346383 ps
CPU time 67.72 seconds
Started Jul 17 07:48:09 PM PDT 24
Finished Jul 17 07:49:19 PM PDT 24
Peak memory 232744 kb
Host smart-87ba8ffb-6ca7-4291-b9f4-59d3f654a1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601309213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1601309213
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.763768557
Short name T414
Test name
Test status
Simulation time 73470987399 ps
CPU time 26.92 seconds
Started Jul 17 07:48:11 PM PDT 24
Finished Jul 17 07:48:42 PM PDT 24
Peak memory 241984 kb
Host smart-41c19d29-c52d-4aa2-a1e0-2aa2c5a433a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763768557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
763768557
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.4080636570
Short name T528
Test name
Test status
Simulation time 56700197897 ps
CPU time 23.84 seconds
Started Jul 17 07:48:10 PM PDT 24
Finished Jul 17 07:48:36 PM PDT 24
Peak memory 239804 kb
Host smart-5f776655-5215-4e95-b84f-20318eaaa147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080636570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.4080636570
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.68834796
Short name T373
Test name
Test status
Simulation time 282094789 ps
CPU time 3.94 seconds
Started Jul 17 07:48:08 PM PDT 24
Finished Jul 17 07:48:13 PM PDT 24
Peak memory 222500 kb
Host smart-d1c045e6-a15e-41a3-a8c7-ceb329eff726
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=68834796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direct
.68834796
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1893306403
Short name T75
Test name
Test status
Simulation time 501609008 ps
CPU time 1.27 seconds
Started Jul 17 07:48:11 PM PDT 24
Finished Jul 17 07:48:16 PM PDT 24
Peak memory 236608 kb
Host smart-f0e7b0e8-efdd-4510-a199-964114ee9bc7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893306403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1893306403
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3906237701
Short name T505
Test name
Test status
Simulation time 40499784 ps
CPU time 1.01 seconds
Started Jul 17 07:48:09 PM PDT 24
Finished Jul 17 07:48:12 PM PDT 24
Peak memory 206960 kb
Host smart-ecd66345-d598-4235-ab06-6f52ab3ea8c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906237701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3906237701
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2692337593
Short name T1002
Test name
Test status
Simulation time 33853700359 ps
CPU time 35.19 seconds
Started Jul 17 07:47:48 PM PDT 24
Finished Jul 17 07:48:26 PM PDT 24
Peak memory 216504 kb
Host smart-bc7d2c0b-5a39-4eb8-ab0c-f17943b4bbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692337593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2692337593
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.308293480
Short name T538
Test name
Test status
Simulation time 6997973782 ps
CPU time 2.2 seconds
Started Jul 17 07:47:50 PM PDT 24
Finished Jul 17 07:47:54 PM PDT 24
Peak memory 208004 kb
Host smart-22fe1999-7d80-4a1c-918b-92aa423d29c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308293480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.308293480
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2852765253
Short name T1
Test name
Test status
Simulation time 210220527 ps
CPU time 3.07 seconds
Started Jul 17 07:48:07 PM PDT 24
Finished Jul 17 07:48:11 PM PDT 24
Peak memory 216268 kb
Host smart-1646a6df-4d7f-44a2-83ea-91422a556c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852765253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2852765253
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3772017106
Short name T33
Test name
Test status
Simulation time 187835041 ps
CPU time 1.03 seconds
Started Jul 17 07:48:10 PM PDT 24
Finished Jul 17 07:48:15 PM PDT 24
Peak memory 206228 kb
Host smart-1496d5f8-ac52-4d42-a52c-08ce9d5cedd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772017106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3772017106
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1241863805
Short name T44
Test name
Test status
Simulation time 5142108790 ps
CPU time 14.69 seconds
Started Jul 17 07:48:09 PM PDT 24
Finished Jul 17 07:48:26 PM PDT 24
Peak memory 224612 kb
Host smart-5656a0dd-6e7f-4cef-8a19-6210b4471313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241863805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1241863805
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2114084651
Short name T659
Test name
Test status
Simulation time 42696431 ps
CPU time 0.71 seconds
Started Jul 17 07:49:49 PM PDT 24
Finished Jul 17 07:49:53 PM PDT 24
Peak memory 205468 kb
Host smart-b3ddd51d-042c-440e-9cad-365a38077e1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114084651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2114084651
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1027478767
Short name T345
Test name
Test status
Simulation time 84130592 ps
CPU time 3.52 seconds
Started Jul 17 07:49:50 PM PDT 24
Finished Jul 17 07:49:56 PM PDT 24
Peak memory 232668 kb
Host smart-7cc57aac-c516-4d51-8d65-bbe2fc49ba12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027478767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1027478767
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2384209426
Short name T903
Test name
Test status
Simulation time 15181467 ps
CPU time 0.74 seconds
Started Jul 17 07:49:54 PM PDT 24
Finished Jul 17 07:49:59 PM PDT 24
Peak memory 205584 kb
Host smart-fc045faf-906e-421a-b584-9ee4d26f7680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384209426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2384209426
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.145583616
Short name T614
Test name
Test status
Simulation time 32385333 ps
CPU time 0.78 seconds
Started Jul 17 07:49:50 PM PDT 24
Finished Jul 17 07:49:53 PM PDT 24
Peak memory 215704 kb
Host smart-b8bedb7d-90f0-4815-a563-0fd329cf192b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145583616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.145583616
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1526105537
Short name T204
Test name
Test status
Simulation time 107931775340 ps
CPU time 313.23 seconds
Started Jul 17 07:49:49 PM PDT 24
Finished Jul 17 07:55:05 PM PDT 24
Peak memory 263788 kb
Host smart-f92ed079-6a0b-4a38-a870-23f6ed5f0bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526105537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1526105537
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2990531544
Short name T670
Test name
Test status
Simulation time 370225809 ps
CPU time 5.38 seconds
Started Jul 17 07:49:47 PM PDT 24
Finished Jul 17 07:49:55 PM PDT 24
Peak memory 224700 kb
Host smart-52271887-9a63-44f6-a57d-2ba2b8c950ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990531544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2990531544
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.2716732025
Short name T965
Test name
Test status
Simulation time 83954595141 ps
CPU time 162.83 seconds
Started Jul 17 07:49:49 PM PDT 24
Finished Jul 17 07:52:35 PM PDT 24
Peak memory 249564 kb
Host smart-3037a155-1575-460b-affc-eda845f2f940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716732025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.2716732025
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1541124216
Short name T612
Test name
Test status
Simulation time 1051893795 ps
CPU time 3.95 seconds
Started Jul 17 07:49:47 PM PDT 24
Finished Jul 17 07:49:53 PM PDT 24
Peak memory 227836 kb
Host smart-aa67d17a-1434-4c0a-80fa-9178d25ea19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541124216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1541124216
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.534029862
Short name T879
Test name
Test status
Simulation time 4387262032 ps
CPU time 45.13 seconds
Started Jul 17 07:49:49 PM PDT 24
Finished Jul 17 07:50:38 PM PDT 24
Peak memory 238776 kb
Host smart-db9d1248-e344-4c5b-923d-bdcdefd4f500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534029862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.534029862
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1104963432
Short name T527
Test name
Test status
Simulation time 416074642 ps
CPU time 5.42 seconds
Started Jul 17 07:49:47 PM PDT 24
Finished Jul 17 07:49:55 PM PDT 24
Peak memory 232536 kb
Host smart-be85c998-f94a-4d84-9d56-a01a96273850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104963432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1104963432
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3280046774
Short name T539
Test name
Test status
Simulation time 7684771321 ps
CPU time 22.1 seconds
Started Jul 17 07:49:46 PM PDT 24
Finished Jul 17 07:50:10 PM PDT 24
Peak memory 238616 kb
Host smart-24dcf743-4198-44b9-ae72-41a829c93fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280046774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3280046774
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.878956679
Short name T745
Test name
Test status
Simulation time 329429828 ps
CPU time 3.52 seconds
Started Jul 17 07:49:48 PM PDT 24
Finished Jul 17 07:49:54 PM PDT 24
Peak memory 220316 kb
Host smart-a3f502a9-651a-4e58-94f0-4278c56921f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=878956679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.878956679
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.723236215
Short name T623
Test name
Test status
Simulation time 1622673016 ps
CPU time 33.94 seconds
Started Jul 17 07:49:53 PM PDT 24
Finished Jul 17 07:50:30 PM PDT 24
Peak memory 250584 kb
Host smart-041148f8-857e-4fdf-8db8-07dd8500b528
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723236215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stres
s_all.723236215
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.310264770
Short name T724
Test name
Test status
Simulation time 20492165628 ps
CPU time 21.95 seconds
Started Jul 17 07:49:53 PM PDT 24
Finished Jul 17 07:50:18 PM PDT 24
Peak memory 216576 kb
Host smart-45e53eff-07e1-4ab5-b66c-5107b57c2db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310264770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.310264770
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.4181719833
Short name T794
Test name
Test status
Simulation time 19321934161 ps
CPU time 14.89 seconds
Started Jul 17 07:49:47 PM PDT 24
Finished Jul 17 07:50:04 PM PDT 24
Peak memory 216364 kb
Host smart-fef59f46-35b9-4931-8ff7-2cef8f6f4f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181719833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.4181719833
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.4206218211
Short name T985
Test name
Test status
Simulation time 24462959 ps
CPU time 1.47 seconds
Started Jul 17 07:49:45 PM PDT 24
Finished Jul 17 07:49:48 PM PDT 24
Peak memory 216244 kb
Host smart-e28c81ad-107b-4a79-b728-07d23dba615f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206218211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.4206218211
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.553860240
Short name T348
Test name
Test status
Simulation time 100162065 ps
CPU time 0.91 seconds
Started Jul 17 07:49:48 PM PDT 24
Finished Jul 17 07:49:52 PM PDT 24
Peak memory 206372 kb
Host smart-d50cfca6-6d81-4d0f-96d4-8f440eed9066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553860240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.553860240
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.532444302
Short name T821
Test name
Test status
Simulation time 665517663 ps
CPU time 4.24 seconds
Started Jul 17 07:49:51 PM PDT 24
Finished Jul 17 07:49:58 PM PDT 24
Peak memory 232636 kb
Host smart-a299c73b-0136-4e93-8464-27f51dc11b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532444302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.532444302
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2881854118
Short name T69
Test name
Test status
Simulation time 131677755 ps
CPU time 0.72 seconds
Started Jul 17 07:49:58 PM PDT 24
Finished Jul 17 07:50:05 PM PDT 24
Peak memory 204964 kb
Host smart-9d6a8690-6c2b-4425-b6d6-3a2cef7f3f73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881854118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2881854118
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2163717849
Short name T483
Test name
Test status
Simulation time 180163645 ps
CPU time 2.07 seconds
Started Jul 17 07:49:56 PM PDT 24
Finished Jul 17 07:50:04 PM PDT 24
Peak memory 232360 kb
Host smart-d9d2982c-aedd-4280-8e0c-718be219f359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163717849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2163717849
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2156607449
Short name T396
Test name
Test status
Simulation time 25441046 ps
CPU time 0.78 seconds
Started Jul 17 07:49:55 PM PDT 24
Finished Jul 17 07:50:01 PM PDT 24
Peak memory 206600 kb
Host smart-9f904f64-9db4-47c4-a92b-110a0ab1b591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156607449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2156607449
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1169591007
Short name T732
Test name
Test status
Simulation time 5972938171 ps
CPU time 42.29 seconds
Started Jul 17 07:49:57 PM PDT 24
Finished Jul 17 07:50:45 PM PDT 24
Peak memory 221960 kb
Host smart-d98934ab-9ae9-48c9-811a-09288057b2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169591007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1169591007
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2661000223
Short name T948
Test name
Test status
Simulation time 28868619142 ps
CPU time 73.62 seconds
Started Jul 17 07:49:57 PM PDT 24
Finished Jul 17 07:51:16 PM PDT 24
Peak memory 249260 kb
Host smart-569b514b-2437-49d1-8dbd-b66f6cceb6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661000223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2661000223
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.831465796
Short name T496
Test name
Test status
Simulation time 2259947898 ps
CPU time 17.76 seconds
Started Jul 17 07:49:57 PM PDT 24
Finished Jul 17 07:50:21 PM PDT 24
Peak memory 224516 kb
Host smart-20808588-0094-43f0-8c77-a9e594785f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831465796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.831465796
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.1426374480
Short name T43
Test name
Test status
Simulation time 53922118162 ps
CPU time 386.17 seconds
Started Jul 17 07:49:56 PM PDT 24
Finished Jul 17 07:56:28 PM PDT 24
Peak memory 265060 kb
Host smart-a261f6db-7ae2-4bcd-8660-faa15903fd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426374480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.1426374480
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2233228949
Short name T1011
Test name
Test status
Simulation time 311805735 ps
CPU time 6.11 seconds
Started Jul 17 07:49:55 PM PDT 24
Finished Jul 17 07:50:07 PM PDT 24
Peak memory 232716 kb
Host smart-d4abf15f-14fb-4648-8e7c-5681190118e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233228949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2233228949
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.4206206741
Short name T686
Test name
Test status
Simulation time 840747953 ps
CPU time 14.94 seconds
Started Jul 17 07:49:53 PM PDT 24
Finished Jul 17 07:50:12 PM PDT 24
Peak memory 235184 kb
Host smart-20fb8a17-f270-439e-953f-1ffddedf6178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206206741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.4206206741
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1600175485
Short name T535
Test name
Test status
Simulation time 4649759069 ps
CPU time 9.09 seconds
Started Jul 17 07:49:53 PM PDT 24
Finished Jul 17 07:50:06 PM PDT 24
Peak memory 234812 kb
Host smart-745aca7d-fc57-45df-9235-701259f0cc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600175485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1600175485
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.4188834181
Short name T39
Test name
Test status
Simulation time 436121638 ps
CPU time 3.27 seconds
Started Jul 17 07:49:52 PM PDT 24
Finished Jul 17 07:49:58 PM PDT 24
Peak memory 224472 kb
Host smart-3ac4d1f3-838e-46f7-8473-9ca0b986902c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188834181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.4188834181
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1836569705
Short name T864
Test name
Test status
Simulation time 535044050 ps
CPU time 4.22 seconds
Started Jul 17 07:49:56 PM PDT 24
Finished Jul 17 07:50:06 PM PDT 24
Peak memory 223080 kb
Host smart-fe29a627-4b30-4ff4-b494-b82a6c362278
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1836569705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1836569705
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.55112710
Short name T219
Test name
Test status
Simulation time 8152971004 ps
CPU time 158.08 seconds
Started Jul 17 07:49:58 PM PDT 24
Finished Jul 17 07:52:43 PM PDT 24
Peak memory 290204 kb
Host smart-bb3e8b68-f911-4d15-9063-bee19cc17704
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55112710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stress
_all.55112710
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.4004519811
Short name T869
Test name
Test status
Simulation time 4543209226 ps
CPU time 12.39 seconds
Started Jul 17 07:49:54 PM PDT 24
Finished Jul 17 07:50:12 PM PDT 24
Peak memory 216692 kb
Host smart-bd1bd05b-4ee8-4317-9f30-9dc98ccd4eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004519811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.4004519811
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2289705230
Short name T893
Test name
Test status
Simulation time 2700516670 ps
CPU time 8.33 seconds
Started Jul 17 07:49:56 PM PDT 24
Finished Jul 17 07:50:10 PM PDT 24
Peak memory 216336 kb
Host smart-2d0aa00d-6ef4-40d7-bb88-041678903cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289705230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2289705230
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.813055758
Short name T849
Test name
Test status
Simulation time 29580884 ps
CPU time 1.51 seconds
Started Jul 17 07:49:55 PM PDT 24
Finished Jul 17 07:50:02 PM PDT 24
Peak memory 216208 kb
Host smart-a6e5af22-d54f-4fdb-a65e-7078f556ec12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813055758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.813055758
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.541639682
Short name T836
Test name
Test status
Simulation time 100247847 ps
CPU time 0.89 seconds
Started Jul 17 07:49:53 PM PDT 24
Finished Jul 17 07:49:57 PM PDT 24
Peak memory 206492 kb
Host smart-05eb8ebf-62a9-4c7c-b0ff-a25657095fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541639682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.541639682
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3099242252
Short name T465
Test name
Test status
Simulation time 4489233951 ps
CPU time 3.07 seconds
Started Jul 17 07:49:55 PM PDT 24
Finished Jul 17 07:50:03 PM PDT 24
Peak memory 224572 kb
Host smart-7be854f3-d8c2-4069-b8af-08c734a6883b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099242252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3099242252
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1051375009
Short name T324
Test name
Test status
Simulation time 29578480 ps
CPU time 0.72 seconds
Started Jul 17 07:49:53 PM PDT 24
Finished Jul 17 07:49:56 PM PDT 24
Peak memory 205484 kb
Host smart-4242335f-4e5f-456d-91f8-65564c2f6681
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051375009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1051375009
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2645852642
Short name T466
Test name
Test status
Simulation time 5267740600 ps
CPU time 12 seconds
Started Jul 17 07:49:55 PM PDT 24
Finished Jul 17 07:50:12 PM PDT 24
Peak memory 232764 kb
Host smart-a28bc93c-d89d-4d3d-ac5b-b028bc55f31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645852642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2645852642
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.4294117254
Short name T328
Test name
Test status
Simulation time 18332270 ps
CPU time 0.75 seconds
Started Jul 17 07:49:57 PM PDT 24
Finished Jul 17 07:50:04 PM PDT 24
Peak memory 206580 kb
Host smart-68c715e0-5f47-4e76-9493-8f2d0de36b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294117254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.4294117254
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.237544295
Short name T499
Test name
Test status
Simulation time 85743370092 ps
CPU time 70.5 seconds
Started Jul 17 07:49:46 PM PDT 24
Finished Jul 17 07:50:58 PM PDT 24
Peak memory 250228 kb
Host smart-e7f8d58e-94b2-4c2e-b769-f38c9fee4dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237544295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.237544295
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2177451666
Short name T820
Test name
Test status
Simulation time 81595474785 ps
CPU time 278.93 seconds
Started Jul 17 07:49:56 PM PDT 24
Finished Jul 17 07:54:41 PM PDT 24
Peak memory 265652 kb
Host smart-7031ac61-f2e7-40f5-961a-6767e691d795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177451666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2177451666
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1781546574
Short name T706
Test name
Test status
Simulation time 2505008973 ps
CPU time 36.01 seconds
Started Jul 17 07:49:47 PM PDT 24
Finished Jul 17 07:50:25 PM PDT 24
Peak memory 239792 kb
Host smart-2e9b4929-6c87-4265-9ff0-d7514c3bbdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781546574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1781546574
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.225692608
Short name T811
Test name
Test status
Simulation time 574976760 ps
CPU time 4.55 seconds
Started Jul 17 07:49:54 PM PDT 24
Finished Jul 17 07:50:04 PM PDT 24
Peak memory 232724 kb
Host smart-cd04c4e8-2c27-40e6-b1df-d617c889506f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225692608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.225692608
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.3713792098
Short name T101
Test name
Test status
Simulation time 1667389886 ps
CPU time 35.26 seconds
Started Jul 17 07:49:56 PM PDT 24
Finished Jul 17 07:50:37 PM PDT 24
Peak memory 249080 kb
Host smart-2ab5e24e-aa92-4a63-83f8-f08c7b9f3d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713792098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.3713792098
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.471533163
Short name T607
Test name
Test status
Simulation time 2010026911 ps
CPU time 18.23 seconds
Started Jul 17 07:49:58 PM PDT 24
Finished Jul 17 07:50:23 PM PDT 24
Peak memory 224484 kb
Host smart-4fa27cff-0f68-4078-a47b-802e50537ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471533163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.471533163
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3646506783
Short name T762
Test name
Test status
Simulation time 1232108720 ps
CPU time 11.97 seconds
Started Jul 17 07:49:49 PM PDT 24
Finished Jul 17 07:50:03 PM PDT 24
Peak memory 232636 kb
Host smart-0fe77251-24f2-47dd-b23a-bbc533623474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646506783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3646506783
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1149350576
Short name T275
Test name
Test status
Simulation time 14860804482 ps
CPU time 15.08 seconds
Started Jul 17 07:49:58 PM PDT 24
Finished Jul 17 07:50:19 PM PDT 24
Peak memory 249168 kb
Host smart-5cd8b0be-7b67-4310-bf5b-0911f77cbbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149350576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1149350576
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3059615690
Short name T471
Test name
Test status
Simulation time 1022193388 ps
CPU time 3.08 seconds
Started Jul 17 07:49:59 PM PDT 24
Finished Jul 17 07:50:08 PM PDT 24
Peak memory 224520 kb
Host smart-1165ddf2-f7b3-4772-a849-fc85d6679ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059615690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3059615690
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3147963512
Short name T740
Test name
Test status
Simulation time 1008237555 ps
CPU time 11.9 seconds
Started Jul 17 07:49:48 PM PDT 24
Finished Jul 17 07:50:03 PM PDT 24
Peak memory 222956 kb
Host smart-8fae0a01-1c77-42d0-b8d4-63b574994c2f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3147963512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3147963512
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.993105464
Short name T784
Test name
Test status
Simulation time 10976306222 ps
CPU time 15.63 seconds
Started Jul 17 07:50:01 PM PDT 24
Finished Jul 17 07:50:21 PM PDT 24
Peak memory 216320 kb
Host smart-51ea1d5f-03b4-41f7-b53d-186dda811946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993105464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.993105464
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3430724742
Short name T727
Test name
Test status
Simulation time 411326550 ps
CPU time 2.73 seconds
Started Jul 17 07:50:01 PM PDT 24
Finished Jul 17 07:50:08 PM PDT 24
Peak memory 216324 kb
Host smart-44dc7f12-ff57-42fa-9d17-97d02119e3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430724742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3430724742
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.4093037244
Short name T933
Test name
Test status
Simulation time 209823862 ps
CPU time 2.11 seconds
Started Jul 17 07:50:01 PM PDT 24
Finished Jul 17 07:50:08 PM PDT 24
Peak memory 216260 kb
Host smart-8c75956b-e7ee-4260-ad93-b8dc064820ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093037244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.4093037244
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.794393762
Short name T798
Test name
Test status
Simulation time 27042524 ps
CPU time 0.78 seconds
Started Jul 17 07:50:01 PM PDT 24
Finished Jul 17 07:50:06 PM PDT 24
Peak memory 205884 kb
Host smart-40e1c2f2-a95d-4b04-82a6-f781e2709df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794393762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.794393762
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.218235256
Short name T963
Test name
Test status
Simulation time 2082283763 ps
CPU time 11.38 seconds
Started Jul 17 07:49:48 PM PDT 24
Finished Jul 17 07:50:02 PM PDT 24
Peak memory 240772 kb
Host smart-dd83c8da-3dd8-490a-966f-d144c854c4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218235256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.218235256
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1902066079
Short name T517
Test name
Test status
Simulation time 53329733 ps
CPU time 0.71 seconds
Started Jul 17 07:50:14 PM PDT 24
Finished Jul 17 07:50:16 PM PDT 24
Peak memory 205516 kb
Host smart-dcafac3b-05ef-42c2-83a0-04dcc9373886
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902066079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1902066079
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2614149237
Short name T337
Test name
Test status
Simulation time 152223340 ps
CPU time 4 seconds
Started Jul 17 07:50:07 PM PDT 24
Finished Jul 17 07:50:11 PM PDT 24
Peak memory 224508 kb
Host smart-b4abc45c-047c-45b1-a41e-bdc17c23108f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614149237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2614149237
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1795280483
Short name T416
Test name
Test status
Simulation time 109544157 ps
CPU time 0.75 seconds
Started Jul 17 07:49:53 PM PDT 24
Finished Jul 17 07:49:58 PM PDT 24
Peak memory 205588 kb
Host smart-c204bdb2-d51f-4e97-99b6-17016e268535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795280483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1795280483
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.853915235
Short name T969
Test name
Test status
Simulation time 502257697 ps
CPU time 3.96 seconds
Started Jul 17 07:50:09 PM PDT 24
Finished Jul 17 07:50:14 PM PDT 24
Peak memory 234872 kb
Host smart-b2d9e6d9-b5ec-4975-abb3-54980e7aab44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853915235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.853915235
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3437293994
Short name T79
Test name
Test status
Simulation time 13450755237 ps
CPU time 113.6 seconds
Started Jul 17 07:50:12 PM PDT 24
Finished Jul 17 07:52:06 PM PDT 24
Peak memory 256916 kb
Host smart-55677232-0f72-4428-9a27-105b68162066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437293994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3437293994
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.580787554
Short name T854
Test name
Test status
Simulation time 1822466681 ps
CPU time 5.11 seconds
Started Jul 17 07:50:07 PM PDT 24
Finished Jul 17 07:50:13 PM PDT 24
Peak memory 224452 kb
Host smart-76b93b92-466d-4954-acdc-f0f6cfb46638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580787554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.580787554
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3179434950
Short name T193
Test name
Test status
Simulation time 10568125089 ps
CPU time 48.05 seconds
Started Jul 17 07:50:06 PM PDT 24
Finished Jul 17 07:50:55 PM PDT 24
Peak memory 257388 kb
Host smart-6b30b0f5-6872-4705-90e0-29adb06e8ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179434950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3179434950
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2968495173
Short name T994
Test name
Test status
Simulation time 2178625199 ps
CPU time 5.02 seconds
Started Jul 17 07:50:12 PM PDT 24
Finished Jul 17 07:50:18 PM PDT 24
Peak memory 224460 kb
Host smart-583f8e43-60be-4bbf-9d8a-6e68b5d8407d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968495173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2968495173
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1475577374
Short name T221
Test name
Test status
Simulation time 223179784 ps
CPU time 5.13 seconds
Started Jul 17 07:50:09 PM PDT 24
Finished Jul 17 07:50:15 PM PDT 24
Peak memory 233448 kb
Host smart-37b0cca5-6b73-4130-b978-e66ebb37e984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475577374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1475577374
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3846912445
Short name T267
Test name
Test status
Simulation time 2261060025 ps
CPU time 5.2 seconds
Started Jul 17 07:49:49 PM PDT 24
Finished Jul 17 07:49:57 PM PDT 24
Peak memory 232748 kb
Host smart-73604800-65a3-4315-8c72-0d21e439e6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846912445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3846912445
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.208701071
Short name T142
Test name
Test status
Simulation time 6281958159 ps
CPU time 8.28 seconds
Started Jul 17 07:49:49 PM PDT 24
Finished Jul 17 07:50:00 PM PDT 24
Peak memory 232724 kb
Host smart-abb4cded-3620-4ca8-b7a1-818e2cd40abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208701071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.208701071
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.438991409
Short name T966
Test name
Test status
Simulation time 136965767 ps
CPU time 3.68 seconds
Started Jul 17 07:50:09 PM PDT 24
Finished Jul 17 07:50:13 PM PDT 24
Peak memory 218992 kb
Host smart-914120e1-bc32-4c57-8681-0f17aa9f871c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=438991409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.438991409
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1484209474
Short name T650
Test name
Test status
Simulation time 94127848 ps
CPU time 0.99 seconds
Started Jul 17 07:50:15 PM PDT 24
Finished Jul 17 07:50:18 PM PDT 24
Peak memory 206948 kb
Host smart-e60452fa-4079-4d4f-b299-20bb445ced49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484209474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1484209474
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1567196612
Short name T874
Test name
Test status
Simulation time 3252474433 ps
CPU time 26.32 seconds
Started Jul 17 07:49:55 PM PDT 24
Finished Jul 17 07:50:28 PM PDT 24
Peak memory 219996 kb
Host smart-dbaf5cb3-dd5a-480f-a361-8b4676f9f3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567196612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1567196612
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1742226499
Short name T911
Test name
Test status
Simulation time 13334412314 ps
CPU time 12.63 seconds
Started Jul 17 07:49:54 PM PDT 24
Finished Jul 17 07:50:11 PM PDT 24
Peak memory 215768 kb
Host smart-b2b37924-fe22-4a80-969b-4757df8bdff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742226499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1742226499
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1012037815
Short name T782
Test name
Test status
Simulation time 143372012 ps
CPU time 4.59 seconds
Started Jul 17 07:49:48 PM PDT 24
Finished Jul 17 07:49:55 PM PDT 24
Peak memory 216300 kb
Host smart-701218fe-16c5-4087-9172-5394c2c5b8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012037815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1012037815
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3001239531
Short name T652
Test name
Test status
Simulation time 69719687 ps
CPU time 0.85 seconds
Started Jul 17 07:49:52 PM PDT 24
Finished Jul 17 07:49:56 PM PDT 24
Peak memory 206320 kb
Host smart-14bcc99e-b5d1-4337-9567-a98a5100ed43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001239531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3001239531
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2848001979
Short name T54
Test name
Test status
Simulation time 1645668429 ps
CPU time 3.96 seconds
Started Jul 17 07:50:08 PM PDT 24
Finished Jul 17 07:50:13 PM PDT 24
Peak memory 232640 kb
Host smart-df8eae3d-ebdf-429d-8bce-e8a24acbe1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848001979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2848001979
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3315530073
Short name T349
Test name
Test status
Simulation time 47376347 ps
CPU time 0.74 seconds
Started Jul 17 07:50:16 PM PDT 24
Finished Jul 17 07:50:19 PM PDT 24
Peak memory 204980 kb
Host smart-e227a07e-1142-407e-8831-c70138b50510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315530073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3315530073
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2095682936
Short name T413
Test name
Test status
Simulation time 2446860429 ps
CPU time 10.46 seconds
Started Jul 17 07:50:15 PM PDT 24
Finished Jul 17 07:50:26 PM PDT 24
Peak memory 224620 kb
Host smart-dd1f3c19-8be5-4631-bb81-1aa85917cf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095682936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2095682936
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.492269261
Short name T432
Test name
Test status
Simulation time 66991595 ps
CPU time 0.83 seconds
Started Jul 17 07:50:11 PM PDT 24
Finished Jul 17 07:50:12 PM PDT 24
Peak memory 206616 kb
Host smart-72f0f280-5815-4cb0-b74b-f843d5c2ec73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492269261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.492269261
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2105929103
Short name T356
Test name
Test status
Simulation time 13992578 ps
CPU time 0.77 seconds
Started Jul 17 07:50:13 PM PDT 24
Finished Jul 17 07:50:15 PM PDT 24
Peak memory 215776 kb
Host smart-818e3a02-0c83-46a6-8c0e-e00a94ddcd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105929103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2105929103
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.61352972
Short name T199
Test name
Test status
Simulation time 26449326398 ps
CPU time 146.05 seconds
Started Jul 17 07:50:15 PM PDT 24
Finished Jul 17 07:52:42 PM PDT 24
Peak memory 253420 kb
Host smart-94357134-249c-4832-a846-581adc438396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61352972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.61352972
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.4154183214
Short name T769
Test name
Test status
Simulation time 11203600756 ps
CPU time 48.25 seconds
Started Jul 17 07:50:19 PM PDT 24
Finished Jul 17 07:51:09 PM PDT 24
Peak memory 249228 kb
Host smart-13c9d8da-84a7-4142-a0d6-97a96be7e53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154183214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.4154183214
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3098692081
Short name T302
Test name
Test status
Simulation time 4874547635 ps
CPU time 15.4 seconds
Started Jul 17 07:50:15 PM PDT 24
Finished Jul 17 07:50:32 PM PDT 24
Peak memory 224576 kb
Host smart-4561d7a0-fafc-4cfd-b579-6643cafd6206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098692081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3098692081
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.289709897
Short name T853
Test name
Test status
Simulation time 5270250942 ps
CPU time 15.45 seconds
Started Jul 17 07:50:16 PM PDT 24
Finished Jul 17 07:50:33 PM PDT 24
Peak memory 232768 kb
Host smart-9bb3742c-11c6-4321-8749-a4292bba351e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289709897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.289709897
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2403169806
Short name T554
Test name
Test status
Simulation time 1607622585 ps
CPU time 10.9 seconds
Started Jul 17 07:50:15 PM PDT 24
Finished Jul 17 07:50:27 PM PDT 24
Peak memory 232628 kb
Host smart-06dcdbd2-7993-44d2-b021-6379efa617ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403169806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2403169806
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.569965506
Short name T546
Test name
Test status
Simulation time 27162371158 ps
CPU time 16.22 seconds
Started Jul 17 07:50:08 PM PDT 24
Finished Jul 17 07:50:25 PM PDT 24
Peak memory 224596 kb
Host smart-c039cca0-508d-4030-a326-8e0b33906ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569965506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.569965506
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2126717156
Short name T253
Test name
Test status
Simulation time 261081119 ps
CPU time 4.15 seconds
Started Jul 17 07:50:08 PM PDT 24
Finished Jul 17 07:50:13 PM PDT 24
Peak memory 224504 kb
Host smart-fa89f8d8-bcd5-4311-aa4c-4a4979127b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126717156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2126717156
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2464911619
Short name T995
Test name
Test status
Simulation time 1782649021 ps
CPU time 4.16 seconds
Started Jul 17 07:50:09 PM PDT 24
Finished Jul 17 07:50:14 PM PDT 24
Peak memory 220512 kb
Host smart-75ad0d2c-17ca-48d9-b582-6c855b134f95
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2464911619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2464911619
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3516216010
Short name T172
Test name
Test status
Simulation time 24285034178 ps
CPU time 218.21 seconds
Started Jul 17 07:50:15 PM PDT 24
Finished Jul 17 07:53:55 PM PDT 24
Peak memory 252196 kb
Host smart-8b46b164-a94e-4887-ad9f-a3dfbf9d3104
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516216010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3516216010
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2955175050
Short name T852
Test name
Test status
Simulation time 23835816694 ps
CPU time 34.62 seconds
Started Jul 17 07:50:09 PM PDT 24
Finished Jul 17 07:50:45 PM PDT 24
Peak memory 216356 kb
Host smart-4718ef32-03f5-4a53-8ac6-3f3edbd72305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955175050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2955175050
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1363986582
Short name T357
Test name
Test status
Simulation time 45852434334 ps
CPU time 20.08 seconds
Started Jul 17 07:50:12 PM PDT 24
Finished Jul 17 07:50:33 PM PDT 24
Peak memory 216456 kb
Host smart-c767bbfc-36a6-49b9-982d-a5d512f26b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363986582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1363986582
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2191984687
Short name T502
Test name
Test status
Simulation time 55452624 ps
CPU time 1.33 seconds
Started Jul 17 07:50:15 PM PDT 24
Finished Jul 17 07:50:18 PM PDT 24
Peak memory 216164 kb
Host smart-1077f624-0fb1-42db-adbf-b221f84e9931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191984687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2191984687
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1220824569
Short name T1004
Test name
Test status
Simulation time 36005891 ps
CPU time 0.82 seconds
Started Jul 17 07:50:11 PM PDT 24
Finished Jul 17 07:50:12 PM PDT 24
Peak memory 205984 kb
Host smart-c9f1250a-bf0e-4de0-a160-c34991236a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220824569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1220824569
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.831416077
Short name T523
Test name
Test status
Simulation time 518132202 ps
CPU time 9.47 seconds
Started Jul 17 07:50:12 PM PDT 24
Finished Jul 17 07:50:22 PM PDT 24
Peak memory 240832 kb
Host smart-e4062a4d-696c-41e9-9039-7820f6174125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831416077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.831416077
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2404161444
Short name T386
Test name
Test status
Simulation time 19301686 ps
CPU time 0.73 seconds
Started Jul 17 07:50:09 PM PDT 24
Finished Jul 17 07:50:10 PM PDT 24
Peak memory 205540 kb
Host smart-ee1b5d13-1639-442a-a822-730cbc2266e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404161444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2404161444
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.4223940666
Short name T387
Test name
Test status
Simulation time 5775248885 ps
CPU time 14.06 seconds
Started Jul 17 07:50:16 PM PDT 24
Finished Jul 17 07:50:32 PM PDT 24
Peak memory 232712 kb
Host smart-3e521604-8522-4b50-ba4c-0306d175f590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223940666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.4223940666
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1634729835
Short name T944
Test name
Test status
Simulation time 32652622 ps
CPU time 0.75 seconds
Started Jul 17 07:50:15 PM PDT 24
Finished Jul 17 07:50:18 PM PDT 24
Peak memory 205704 kb
Host smart-d46df31a-cdf5-4bb8-9ce2-59a333a7eef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634729835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1634729835
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.249919277
Short name T45
Test name
Test status
Simulation time 3314942909 ps
CPU time 65.15 seconds
Started Jul 17 07:50:16 PM PDT 24
Finished Jul 17 07:51:23 PM PDT 24
Peak memory 255052 kb
Host smart-a02501e7-e0d6-4a07-8cca-2c626b02e988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249919277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.249919277
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.581215220
Short name T294
Test name
Test status
Simulation time 120466090537 ps
CPU time 557.82 seconds
Started Jul 17 07:50:19 PM PDT 24
Finished Jul 17 07:59:40 PM PDT 24
Peak memory 265544 kb
Host smart-403557f7-5cbf-484f-aa09-189860cdf2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581215220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.581215220
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2696907624
Short name T316
Test name
Test status
Simulation time 38055419152 ps
CPU time 38.59 seconds
Started Jul 17 07:50:16 PM PDT 24
Finished Jul 17 07:50:56 PM PDT 24
Peak memory 217724 kb
Host smart-e4286bc1-dfa5-4b5e-b935-5bfb11d897bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696907624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2696907624
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1856766814
Short name T26
Test name
Test status
Simulation time 486118484 ps
CPU time 3.63 seconds
Started Jul 17 07:50:18 PM PDT 24
Finished Jul 17 07:50:24 PM PDT 24
Peak memory 224488 kb
Host smart-f5dd166d-3f15-468b-be8f-e8d61e88877f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856766814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1856766814
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.1900545623
Short name T191
Test name
Test status
Simulation time 26991118171 ps
CPU time 184.69 seconds
Started Jul 17 07:51:41 PM PDT 24
Finished Jul 17 07:54:47 PM PDT 24
Peak memory 257256 kb
Host smart-85e273cb-88f3-4e92-a214-192b099cbfa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900545623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.1900545623
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3012101371
Short name T558
Test name
Test status
Simulation time 873484412 ps
CPU time 5.64 seconds
Started Jul 17 07:50:07 PM PDT 24
Finished Jul 17 07:50:14 PM PDT 24
Peak memory 232708 kb
Host smart-43d946b6-0893-4efb-87be-e31bb422cc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012101371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3012101371
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3278680104
Short name T842
Test name
Test status
Simulation time 139452090 ps
CPU time 3.22 seconds
Started Jul 17 07:50:14 PM PDT 24
Finished Jul 17 07:50:18 PM PDT 24
Peak memory 232652 kb
Host smart-79572891-e582-4fec-bb8d-9abb1a42f85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278680104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3278680104
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1713591778
Short name T50
Test name
Test status
Simulation time 7371669980 ps
CPU time 21.94 seconds
Started Jul 17 07:50:16 PM PDT 24
Finished Jul 17 07:50:40 PM PDT 24
Peak memory 232800 kb
Host smart-706204a1-168f-4329-9e0a-d6ca132dd69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713591778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1713591778
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.4245015823
Short name T878
Test name
Test status
Simulation time 288737864 ps
CPU time 3.94 seconds
Started Jul 17 07:50:07 PM PDT 24
Finished Jul 17 07:50:12 PM PDT 24
Peak memory 232612 kb
Host smart-1a776005-f394-415e-9822-95e8a86c4b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245015823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.4245015823
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3845314615
Short name T689
Test name
Test status
Simulation time 18296472423 ps
CPU time 12.09 seconds
Started Jul 17 07:50:17 PM PDT 24
Finished Jul 17 07:50:31 PM PDT 24
Peak memory 223224 kb
Host smart-4c77cbb0-3c2c-4977-824f-12af0e6ff192
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3845314615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3845314615
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2985619322
Short name T636
Test name
Test status
Simulation time 26728543525 ps
CPU time 272.16 seconds
Started Jul 17 07:50:18 PM PDT 24
Finished Jul 17 07:54:52 PM PDT 24
Peak memory 256600 kb
Host smart-6d393441-4efd-4b5b-a71f-4c5c6c7216dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985619322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2985619322
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3747586677
Short name T178
Test name
Test status
Simulation time 5166651463 ps
CPU time 26.53 seconds
Started Jul 17 07:50:17 PM PDT 24
Finished Jul 17 07:50:45 PM PDT 24
Peak memory 216392 kb
Host smart-c3034b82-d676-40f4-9565-1389572251eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747586677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3747586677
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2149181015
Short name T780
Test name
Test status
Simulation time 22667407290 ps
CPU time 16.94 seconds
Started Jul 17 07:50:13 PM PDT 24
Finished Jul 17 07:50:32 PM PDT 24
Peak memory 216344 kb
Host smart-5e92bd66-d0d6-4bcd-bbcd-f9a932e7052e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149181015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2149181015
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1358004147
Short name T599
Test name
Test status
Simulation time 802337046 ps
CPU time 1.98 seconds
Started Jul 17 07:50:10 PM PDT 24
Finished Jul 17 07:50:13 PM PDT 24
Peak memory 216208 kb
Host smart-44cdcd27-1c4f-4ae6-b502-30a9178d32c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358004147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1358004147
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.834770792
Short name T456
Test name
Test status
Simulation time 282509311 ps
CPU time 0.98 seconds
Started Jul 17 07:50:16 PM PDT 24
Finished Jul 17 07:50:19 PM PDT 24
Peak memory 206980 kb
Host smart-3dcd68d7-436e-4301-b4b4-0d5ff05ae615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834770792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.834770792
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1721890169
Short name T435
Test name
Test status
Simulation time 1067879967 ps
CPU time 3.85 seconds
Started Jul 17 07:50:14 PM PDT 24
Finished Jul 17 07:50:19 PM PDT 24
Peak memory 224624 kb
Host smart-7b945826-79b6-47a6-a75f-a9852a8a2d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721890169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1721890169
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1756565993
Short name T326
Test name
Test status
Simulation time 40778300 ps
CPU time 0.77 seconds
Started Jul 17 07:50:18 PM PDT 24
Finished Jul 17 07:50:21 PM PDT 24
Peak memory 204976 kb
Host smart-4967f3c9-8ec8-4e4f-ad0c-cf8838fdb382
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756565993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1756565993
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1176221922
Short name T891
Test name
Test status
Simulation time 63660191 ps
CPU time 2.53 seconds
Started Jul 17 07:50:20 PM PDT 24
Finished Jul 17 07:50:25 PM PDT 24
Peak memory 232360 kb
Host smart-83662bbf-ab98-420e-8c79-b92eb3e89af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176221922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1176221922
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1034198405
Short name T507
Test name
Test status
Simulation time 19785470 ps
CPU time 0.82 seconds
Started Jul 17 07:50:20 PM PDT 24
Finished Jul 17 07:50:23 PM PDT 24
Peak memory 206924 kb
Host smart-7a65954b-f81f-469f-9e37-833a49ccd109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034198405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1034198405
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.4214135046
Short name T202
Test name
Test status
Simulation time 13629938927 ps
CPU time 86.44 seconds
Started Jul 17 07:50:19 PM PDT 24
Finished Jul 17 07:51:48 PM PDT 24
Peak memory 257088 kb
Host smart-2efecf18-3f7e-4a76-8886-888d6ff9c2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214135046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.4214135046
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1821929893
Short name T485
Test name
Test status
Simulation time 4396705489 ps
CPU time 66.96 seconds
Started Jul 17 07:50:20 PM PDT 24
Finished Jul 17 07:51:30 PM PDT 24
Peak memory 249412 kb
Host smart-ed747495-8192-443c-a7e1-917ce5736973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821929893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1821929893
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.863679787
Short name T709
Test name
Test status
Simulation time 16024435210 ps
CPU time 161.41 seconds
Started Jul 17 07:50:19 PM PDT 24
Finished Jul 17 07:53:02 PM PDT 24
Peak memory 249264 kb
Host smart-7e2ecdf6-33fd-450a-9622-c9081f8005aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863679787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.863679787
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3970139714
Short name T591
Test name
Test status
Simulation time 828749028 ps
CPU time 9.88 seconds
Started Jul 17 07:50:18 PM PDT 24
Finished Jul 17 07:50:30 PM PDT 24
Peak memory 232716 kb
Host smart-8562b04e-40b1-4cd4-bdac-4ffade426921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970139714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3970139714
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.2112983370
Short name T292
Test name
Test status
Simulation time 30666818660 ps
CPU time 123.35 seconds
Started Jul 17 07:50:18 PM PDT 24
Finished Jul 17 07:52:23 PM PDT 24
Peak memory 257360 kb
Host smart-c12bda13-e1b2-4137-81d6-c3ccb468e07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112983370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.2112983370
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1036429984
Short name T249
Test name
Test status
Simulation time 204692045 ps
CPU time 2.84 seconds
Started Jul 17 07:50:18 PM PDT 24
Finished Jul 17 07:50:23 PM PDT 24
Peak memory 224432 kb
Host smart-71792a2e-2bdf-4ed0-a261-593a9a0d6f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036429984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1036429984
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1166038612
Short name T610
Test name
Test status
Simulation time 39698378488 ps
CPU time 93.51 seconds
Started Jul 17 07:50:18 PM PDT 24
Finished Jul 17 07:51:54 PM PDT 24
Peak memory 232832 kb
Host smart-ca9fd220-fa30-4a3f-bdbb-5ace8de1ece4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166038612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1166038612
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.4107299701
Short name T793
Test name
Test status
Simulation time 1262282806 ps
CPU time 4.66 seconds
Started Jul 17 07:50:19 PM PDT 24
Finished Jul 17 07:50:26 PM PDT 24
Peak memory 238860 kb
Host smart-86d54fe0-848e-46df-9cd5-2c071ba93f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107299701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.4107299701
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.56394747
Short name T177
Test name
Test status
Simulation time 42485361393 ps
CPU time 16.92 seconds
Started Jul 17 07:50:15 PM PDT 24
Finished Jul 17 07:50:34 PM PDT 24
Peak memory 224544 kb
Host smart-7d4b6667-bd85-4528-bb12-57e285ed0d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56394747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.56394747
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2369424089
Short name T830
Test name
Test status
Simulation time 4493729348 ps
CPU time 7.99 seconds
Started Jul 17 07:50:16 PM PDT 24
Finished Jul 17 07:50:25 PM PDT 24
Peak memory 219836 kb
Host smart-ffb587f1-0eb6-41c3-b297-350bbc53244a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2369424089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2369424089
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.607219786
Short name T744
Test name
Test status
Simulation time 3335056584 ps
CPU time 6.08 seconds
Started Jul 17 07:50:18 PM PDT 24
Finished Jul 17 07:50:26 PM PDT 24
Peak memory 216376 kb
Host smart-69ba9327-3810-4ea1-9600-e7c14364d1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607219786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.607219786
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1276842127
Short name T896
Test name
Test status
Simulation time 2871116206 ps
CPU time 3.19 seconds
Started Jul 17 07:50:14 PM PDT 24
Finished Jul 17 07:50:19 PM PDT 24
Peak memory 208024 kb
Host smart-74a74171-e03b-4e49-899b-6358159448cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276842127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1276842127
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3328884887
Short name T621
Test name
Test status
Simulation time 156082832 ps
CPU time 5.08 seconds
Started Jul 17 07:50:18 PM PDT 24
Finished Jul 17 07:50:26 PM PDT 24
Peak memory 216272 kb
Host smart-85493622-0460-4dcd-998a-e617bb96919d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328884887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3328884887
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3859114150
Short name T664
Test name
Test status
Simulation time 52831182 ps
CPU time 0.85 seconds
Started Jul 17 07:50:18 PM PDT 24
Finished Jul 17 07:50:20 PM PDT 24
Peak memory 207008 kb
Host smart-76fded90-6e1d-46b9-b350-5b2b3a5f15e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859114150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3859114150
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2801236405
Short name T807
Test name
Test status
Simulation time 132432199 ps
CPU time 2.47 seconds
Started Jul 17 07:50:16 PM PDT 24
Finished Jul 17 07:50:20 PM PDT 24
Peak memory 232748 kb
Host smart-c59182f8-0a1b-474f-9103-1ff1ff94ff09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801236405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2801236405
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.747744558
Short name T815
Test name
Test status
Simulation time 17963815 ps
CPU time 0.75 seconds
Started Jul 17 07:50:34 PM PDT 24
Finished Jul 17 07:50:37 PM PDT 24
Peak memory 205460 kb
Host smart-f44b15e4-824f-4a6c-b6e7-3a67c6650f71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747744558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.747744558
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3756886444
Short name T1006
Test name
Test status
Simulation time 99038466 ps
CPU time 2.58 seconds
Started Jul 17 07:50:35 PM PDT 24
Finished Jul 17 07:50:40 PM PDT 24
Peak memory 224420 kb
Host smart-69a5b487-0c5d-454f-9d6c-a5b663f80855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756886444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3756886444
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3007475848
Short name T31
Test name
Test status
Simulation time 39530291 ps
CPU time 0.78 seconds
Started Jul 17 07:50:19 PM PDT 24
Finished Jul 17 07:50:22 PM PDT 24
Peak memory 206676 kb
Host smart-8d8e8539-ceef-4ce8-8e74-8fe8b834899d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007475848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3007475848
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1843750303
Short name T355
Test name
Test status
Simulation time 2033464568 ps
CPU time 37.93 seconds
Started Jul 17 07:50:34 PM PDT 24
Finished Jul 17 07:51:14 PM PDT 24
Peak memory 254020 kb
Host smart-891754a1-5d2b-440b-9896-4b90228ec846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843750303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1843750303
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2337268040
Short name T269
Test name
Test status
Simulation time 72353774473 ps
CPU time 195.41 seconds
Started Jul 17 07:50:32 PM PDT 24
Finished Jul 17 07:53:48 PM PDT 24
Peak memory 256264 kb
Host smart-a00adeb6-506d-4d6f-8f84-6b379c3d1862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337268040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2337268040
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3063080122
Short name T1005
Test name
Test status
Simulation time 70713740 ps
CPU time 2.39 seconds
Started Jul 17 07:50:40 PM PDT 24
Finished Jul 17 07:50:44 PM PDT 24
Peak memory 232600 kb
Host smart-4729774a-f487-48fe-9f31-3da10a2a1132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063080122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3063080122
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.309503309
Short name T317
Test name
Test status
Simulation time 37160995 ps
CPU time 0.75 seconds
Started Jul 17 07:50:36 PM PDT 24
Finished Jul 17 07:50:39 PM PDT 24
Peak memory 215732 kb
Host smart-9bdf62d8-13a5-4c3d-9a93-f6ab91871f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309503309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds
.309503309
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3847035260
Short name T242
Test name
Test status
Simulation time 3633156422 ps
CPU time 9.54 seconds
Started Jul 17 07:50:36 PM PDT 24
Finished Jul 17 07:50:48 PM PDT 24
Peak memory 224564 kb
Host smart-8851cef5-d393-4f73-80ad-a86d8181edc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847035260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3847035260
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3874150222
Short name T952
Test name
Test status
Simulation time 1821440264 ps
CPU time 16.58 seconds
Started Jul 17 07:50:33 PM PDT 24
Finished Jul 17 07:50:51 PM PDT 24
Peak memory 232652 kb
Host smart-7f21f28b-92a2-478d-ae98-3854691e34f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874150222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3874150222
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2984894543
Short name T236
Test name
Test status
Simulation time 6666190950 ps
CPU time 9.55 seconds
Started Jul 17 07:50:33 PM PDT 24
Finished Jul 17 07:50:45 PM PDT 24
Peak memory 249116 kb
Host smart-315aee22-c1f6-4cd4-a8f3-134a16ee761b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984894543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2984894543
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1535715694
Short name T693
Test name
Test status
Simulation time 1643591565 ps
CPU time 3.36 seconds
Started Jul 17 07:50:33 PM PDT 24
Finished Jul 17 07:50:38 PM PDT 24
Peak memory 232652 kb
Host smart-b59dc798-4a64-4df1-a3be-676b616c4586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535715694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1535715694
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.252881144
Short name T330
Test name
Test status
Simulation time 2381680134 ps
CPU time 8.82 seconds
Started Jul 17 07:50:32 PM PDT 24
Finished Jul 17 07:50:42 PM PDT 24
Peak memory 220348 kb
Host smart-0d01ac4d-4ac0-40fc-be04-cb2e6f5b24de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=252881144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.252881144
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3908794388
Short name T392
Test name
Test status
Simulation time 197877116 ps
CPU time 1.05 seconds
Started Jul 17 07:50:34 PM PDT 24
Finished Jul 17 07:50:38 PM PDT 24
Peak memory 206916 kb
Host smart-62a0b5e7-7fb1-4aae-a24f-1477f1699116
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908794388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3908794388
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.764201381
Short name T895
Test name
Test status
Simulation time 1961810038 ps
CPU time 13.05 seconds
Started Jul 17 07:50:18 PM PDT 24
Finished Jul 17 07:50:33 PM PDT 24
Peak memory 216324 kb
Host smart-3159429e-b1fe-434f-a077-102292113b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764201381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.764201381
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3269455625
Short name T65
Test name
Test status
Simulation time 1094617707 ps
CPU time 6.18 seconds
Started Jul 17 07:50:17 PM PDT 24
Finished Jul 17 07:50:25 PM PDT 24
Peak memory 216160 kb
Host smart-2c0743e5-bbd1-4866-9fc9-ea8019524eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269455625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3269455625
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1126203092
Short name T353
Test name
Test status
Simulation time 22987270 ps
CPU time 1.07 seconds
Started Jul 17 07:50:30 PM PDT 24
Finished Jul 17 07:50:32 PM PDT 24
Peak memory 207016 kb
Host smart-569a0dbc-4eba-453b-8e73-50a4267cf217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126203092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1126203092
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3081666733
Short name T446
Test name
Test status
Simulation time 172232007 ps
CPU time 0.74 seconds
Started Jul 17 07:50:31 PM PDT 24
Finished Jul 17 07:50:32 PM PDT 24
Peak memory 205988 kb
Host smart-7b74a170-570c-474f-bdfd-b9b6003f5942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081666733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3081666733
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1923682746
Short name T395
Test name
Test status
Simulation time 8316370869 ps
CPU time 14.08 seconds
Started Jul 17 07:50:37 PM PDT 24
Finished Jul 17 07:50:53 PM PDT 24
Peak memory 232836 kb
Host smart-b96307a7-1806-41d1-85de-153dd8e2c2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923682746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1923682746
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1783918256
Short name T318
Test name
Test status
Simulation time 13582213 ps
CPU time 0.71 seconds
Started Jul 17 07:50:36 PM PDT 24
Finished Jul 17 07:50:39 PM PDT 24
Peak memory 205544 kb
Host smart-83e7f2a7-0af8-4a3f-b109-fc479c39f7eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783918256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1783918256
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2638584204
Short name T159
Test name
Test status
Simulation time 554579285 ps
CPU time 3.62 seconds
Started Jul 17 07:50:31 PM PDT 24
Finished Jul 17 07:50:35 PM PDT 24
Peak memory 224500 kb
Host smart-5b31a853-fd7a-4500-bc87-095e66153952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638584204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2638584204
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2759516841
Short name T423
Test name
Test status
Simulation time 47726127 ps
CPU time 0.81 seconds
Started Jul 17 07:50:35 PM PDT 24
Finished Jul 17 07:50:38 PM PDT 24
Peak memory 206616 kb
Host smart-8435da66-7f4a-4304-84f9-2e6a9aca56c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759516841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2759516841
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2375017117
Short name T239
Test name
Test status
Simulation time 4515253595 ps
CPU time 38.82 seconds
Started Jul 17 07:50:32 PM PDT 24
Finished Jul 17 07:51:12 PM PDT 24
Peak memory 249196 kb
Host smart-4ed97ad8-fe4d-4d3d-9a0f-556320703ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375017117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2375017117
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1770983772
Short name T42
Test name
Test status
Simulation time 7296974387 ps
CPU time 40.37 seconds
Started Jul 17 07:50:32 PM PDT 24
Finished Jul 17 07:51:13 PM PDT 24
Peak memory 239988 kb
Host smart-6ed77d94-98be-4abe-9279-8753077a57cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770983772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1770983772
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3729145771
Short name T57
Test name
Test status
Simulation time 18047500155 ps
CPU time 232.04 seconds
Started Jul 17 07:50:35 PM PDT 24
Finished Jul 17 07:54:29 PM PDT 24
Peak memory 256916 kb
Host smart-bfa5d85c-0f0b-4e8c-8a9e-c65dec93a30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729145771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3729145771
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.689528044
Short name T243
Test name
Test status
Simulation time 22571812255 ps
CPU time 146.69 seconds
Started Jul 17 07:50:35 PM PDT 24
Finished Jul 17 07:53:04 PM PDT 24
Peak memory 257356 kb
Host smart-934450b3-45b9-470b-967a-d2aa3379a889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689528044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds
.689528044
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.4283837456
Short name T559
Test name
Test status
Simulation time 7650959651 ps
CPU time 17.74 seconds
Started Jul 17 07:50:31 PM PDT 24
Finished Jul 17 07:50:49 PM PDT 24
Peak memory 232764 kb
Host smart-acfd39e6-5018-4c01-b575-b874c3aef701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283837456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.4283837456
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3631517643
Short name T331
Test name
Test status
Simulation time 1671869920 ps
CPU time 8.96 seconds
Started Jul 17 07:50:34 PM PDT 24
Finished Jul 17 07:50:45 PM PDT 24
Peak memory 232508 kb
Host smart-0a83003f-961c-47cf-ba3f-08935cb9fc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631517643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3631517643
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.4273663351
Short name T278
Test name
Test status
Simulation time 1461475449 ps
CPU time 4.21 seconds
Started Jul 17 07:50:34 PM PDT 24
Finished Jul 17 07:50:40 PM PDT 24
Peak memory 232672 kb
Host smart-b73ed450-8454-4feb-9109-82ce788cf5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273663351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.4273663351
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3681368361
Short name T931
Test name
Test status
Simulation time 829887057 ps
CPU time 2.76 seconds
Started Jul 17 07:50:34 PM PDT 24
Finished Jul 17 07:50:39 PM PDT 24
Peak memory 232480 kb
Host smart-48a1e15b-7b75-41fe-94f1-436705ade584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681368361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3681368361
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3891263824
Short name T352
Test name
Test status
Simulation time 2237313741 ps
CPU time 16.33 seconds
Started Jul 17 07:50:34 PM PDT 24
Finished Jul 17 07:50:52 PM PDT 24
Peak memory 219116 kb
Host smart-579a9ed2-8800-4dd0-87cc-a3a8e1df61f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3891263824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3891263824
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.492783884
Short name T16
Test name
Test status
Simulation time 81130115275 ps
CPU time 679.96 seconds
Started Jul 17 07:50:33 PM PDT 24
Finished Jul 17 08:01:55 PM PDT 24
Peak memory 252692 kb
Host smart-651ea823-e18a-4fdb-bdb6-f3dd0d9e2cf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492783884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.492783884
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2867331607
Short name T801
Test name
Test status
Simulation time 29975165074 ps
CPU time 35.6 seconds
Started Jul 17 07:50:34 PM PDT 24
Finished Jul 17 07:51:12 PM PDT 24
Peak memory 216332 kb
Host smart-4c91ed3a-6004-4a34-b489-9a9557ab5e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867331607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2867331607
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3840072783
Short name T365
Test name
Test status
Simulation time 225322884 ps
CPU time 1.7 seconds
Started Jul 17 07:50:43 PM PDT 24
Finished Jul 17 07:50:46 PM PDT 24
Peak memory 207900 kb
Host smart-5131bc21-cc80-4c66-b552-2b5f680600f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840072783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3840072783
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3336221083
Short name T32
Test name
Test status
Simulation time 150613842 ps
CPU time 2.16 seconds
Started Jul 17 07:50:33 PM PDT 24
Finished Jul 17 07:50:36 PM PDT 24
Peak memory 216184 kb
Host smart-1719f3d0-a186-479b-8219-63e3237504e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336221083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3336221083
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1132983713
Short name T362
Test name
Test status
Simulation time 52749070 ps
CPU time 0.84 seconds
Started Jul 17 07:50:32 PM PDT 24
Finished Jul 17 07:50:34 PM PDT 24
Peak memory 205964 kb
Host smart-4dc043b4-3c94-4c56-8b41-32218dabc508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132983713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1132983713
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2431030302
Short name T430
Test name
Test status
Simulation time 640990680 ps
CPU time 4.7 seconds
Started Jul 17 07:50:30 PM PDT 24
Finished Jul 17 07:50:35 PM PDT 24
Peak memory 228440 kb
Host smart-afe986a8-aa71-489e-b379-67c6e5a02b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431030302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2431030302
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1769945179
Short name T618
Test name
Test status
Simulation time 23560129 ps
CPU time 0.76 seconds
Started Jul 17 07:50:36 PM PDT 24
Finished Jul 17 07:50:39 PM PDT 24
Peak memory 205500 kb
Host smart-36581522-e2f5-4760-bc05-59f95618747e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769945179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1769945179
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.125458356
Short name T78
Test name
Test status
Simulation time 2312672009 ps
CPU time 8.81 seconds
Started Jul 17 07:50:43 PM PDT 24
Finished Jul 17 07:50:53 PM PDT 24
Peak memory 232808 kb
Host smart-636c5f93-de56-488e-b5bd-5796afb7c455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125458356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.125458356
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.94025773
Short name T467
Test name
Test status
Simulation time 62039844 ps
CPU time 0.75 seconds
Started Jul 17 07:50:39 PM PDT 24
Finished Jul 17 07:50:41 PM PDT 24
Peak memory 205904 kb
Host smart-50ce49ee-5a7f-498c-be97-ea01b1ba0c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94025773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.94025773
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2474895014
Short name T940
Test name
Test status
Simulation time 11334250542 ps
CPU time 77.98 seconds
Started Jul 17 07:50:37 PM PDT 24
Finished Jul 17 07:51:57 PM PDT 24
Peak memory 250004 kb
Host smart-abbbb19d-470e-4474-a261-f7537ad6dcbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474895014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2474895014
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3305315908
Short name T649
Test name
Test status
Simulation time 26158402387 ps
CPU time 67.3 seconds
Started Jul 17 07:50:36 PM PDT 24
Finished Jul 17 07:51:45 PM PDT 24
Peak memory 240272 kb
Host smart-4bec7cc4-e1cb-4d81-bbad-e90d995d2951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305315908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3305315908
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1364611866
Short name T55
Test name
Test status
Simulation time 111073575426 ps
CPU time 490.05 seconds
Started Jul 17 07:50:35 PM PDT 24
Finished Jul 17 07:58:47 PM PDT 24
Peak memory 252636 kb
Host smart-97bbdb19-ca5f-457a-a37f-0719da783155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364611866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1364611866
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2229078648
Short name T772
Test name
Test status
Simulation time 5094537624 ps
CPU time 22.18 seconds
Started Jul 17 07:50:34 PM PDT 24
Finished Jul 17 07:50:59 PM PDT 24
Peak memory 232812 kb
Host smart-51b22abe-4457-4d40-8dad-d3f0a7d8265b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229078648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2229078648
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2865665655
Short name T342
Test name
Test status
Simulation time 110267261 ps
CPU time 0.76 seconds
Started Jul 17 07:50:36 PM PDT 24
Finished Jul 17 07:50:39 PM PDT 24
Peak memory 215752 kb
Host smart-baaefa3b-1d86-438b-ab36-7079cf02531f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865665655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.2865665655
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.75934217
Short name T434
Test name
Test status
Simulation time 877058824 ps
CPU time 5.72 seconds
Started Jul 17 07:50:32 PM PDT 24
Finished Jul 17 07:50:39 PM PDT 24
Peak memory 232772 kb
Host smart-7e35a92a-5365-4d0c-868d-49c8fa605801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75934217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.75934217
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3332574586
Short name T601
Test name
Test status
Simulation time 3872924258 ps
CPU time 18.63 seconds
Started Jul 17 07:50:43 PM PDT 24
Finished Jul 17 07:51:03 PM PDT 24
Peak memory 240776 kb
Host smart-1dc89f32-8154-4f14-8e39-87c3c331039f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332574586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3332574586
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.4224109189
Short name T341
Test name
Test status
Simulation time 690332514 ps
CPU time 5.89 seconds
Started Jul 17 07:50:43 PM PDT 24
Finished Jul 17 07:50:51 PM PDT 24
Peak memory 232684 kb
Host smart-6410e6f9-5468-44f6-aeb5-e3595cbf2748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224109189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.4224109189
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1826833490
Short name T889
Test name
Test status
Simulation time 563661450 ps
CPU time 2.34 seconds
Started Jul 17 07:50:37 PM PDT 24
Finished Jul 17 07:50:41 PM PDT 24
Peak memory 232320 kb
Host smart-ae734ef9-a838-416c-819e-730c6314f9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826833490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1826833490
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3882127812
Short name T382
Test name
Test status
Simulation time 714707786 ps
CPU time 6.65 seconds
Started Jul 17 07:50:34 PM PDT 24
Finished Jul 17 07:50:42 PM PDT 24
Peak memory 222960 kb
Host smart-f8bec171-22fe-4753-9e37-ae0b0be872a1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3882127812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3882127812
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3992534206
Short name T145
Test name
Test status
Simulation time 28303021529 ps
CPU time 117.84 seconds
Started Jul 17 07:50:36 PM PDT 24
Finished Jul 17 07:52:36 PM PDT 24
Peak memory 249264 kb
Host smart-4f089175-e312-409d-9b49-118b4cacadcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992534206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3992534206
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1434596111
Short name T988
Test name
Test status
Simulation time 2141451785 ps
CPU time 17.64 seconds
Started Jul 17 07:50:39 PM PDT 24
Finished Jul 17 07:50:58 PM PDT 24
Peak memory 216216 kb
Host smart-0058b854-4517-4de7-80bb-86730af7b2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434596111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1434596111
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2766914761
Short name T510
Test name
Test status
Simulation time 2181686770 ps
CPU time 2.31 seconds
Started Jul 17 07:50:39 PM PDT 24
Finished Jul 17 07:50:44 PM PDT 24
Peak memory 207968 kb
Host smart-14811b49-66b0-42ab-ad8c-35c45471a709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766914761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2766914761
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2357300031
Short name T481
Test name
Test status
Simulation time 312620946 ps
CPU time 1.3 seconds
Started Jul 17 07:50:32 PM PDT 24
Finished Jul 17 07:50:35 PM PDT 24
Peak memory 216252 kb
Host smart-a252d19b-e2d4-4049-a503-bda4cac14a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357300031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2357300031
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3269271993
Short name T928
Test name
Test status
Simulation time 39066584 ps
CPU time 0.71 seconds
Started Jul 17 07:50:34 PM PDT 24
Finished Jul 17 07:50:37 PM PDT 24
Peak memory 205984 kb
Host smart-f1365736-09b5-4b28-ba2d-208efe64c2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269271993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3269271993
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.441498217
Short name T812
Test name
Test status
Simulation time 133633494 ps
CPU time 2.62 seconds
Started Jul 17 07:50:43 PM PDT 24
Finished Jul 17 07:50:47 PM PDT 24
Peak memory 224168 kb
Host smart-4f7280ef-3ba5-438f-b51b-dd48e6fb0bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441498217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.441498217
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3663457467
Short name T67
Test name
Test status
Simulation time 60604883 ps
CPU time 0.73 seconds
Started Jul 17 07:48:09 PM PDT 24
Finished Jul 17 07:48:11 PM PDT 24
Peak memory 204952 kb
Host smart-9234f649-cfc7-4241-9897-8c6ffc309d5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663457467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
663457467
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2309153132
Short name T143
Test name
Test status
Simulation time 568573827 ps
CPU time 6.95 seconds
Started Jul 17 07:48:10 PM PDT 24
Finished Jul 17 07:48:20 PM PDT 24
Peak memory 232660 kb
Host smart-a0d05163-9f77-4522-9d09-58fcf8b63d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309153132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2309153132
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1445419744
Short name T377
Test name
Test status
Simulation time 79318304 ps
CPU time 0.75 seconds
Started Jul 17 07:48:10 PM PDT 24
Finished Jul 17 07:48:14 PM PDT 24
Peak memory 205552 kb
Host smart-45ab8706-f0fe-430f-ad51-e57275031941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445419744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1445419744
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.278675345
Short name T479
Test name
Test status
Simulation time 27106424781 ps
CPU time 47.97 seconds
Started Jul 17 07:48:08 PM PDT 24
Finished Jul 17 07:48:57 PM PDT 24
Peak memory 234272 kb
Host smart-a6ce2952-a6ba-41a9-8b16-bb0f80a8fa5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278675345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.278675345
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1242368054
Short name T749
Test name
Test status
Simulation time 112844985580 ps
CPU time 251.48 seconds
Started Jul 17 07:48:08 PM PDT 24
Finished Jul 17 07:52:21 PM PDT 24
Peak memory 253460 kb
Host smart-a0ecbac0-e1fc-4eef-ac35-c4847a10a070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242368054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1242368054
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.297515738
Short name T493
Test name
Test status
Simulation time 1467322876 ps
CPU time 33.6 seconds
Started Jul 17 07:48:10 PM PDT 24
Finished Jul 17 07:48:47 PM PDT 24
Peak memory 240992 kb
Host smart-9dbdb8ee-09d7-47b6-ad1e-16e78bda9ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297515738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
297515738
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3639024405
Short name T890
Test name
Test status
Simulation time 8026315470 ps
CPU time 12.28 seconds
Started Jul 17 07:48:09 PM PDT 24
Finished Jul 17 07:48:24 PM PDT 24
Peak memory 232792 kb
Host smart-450d6875-8713-4269-91c7-693b6af5e9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639024405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3639024405
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1387318620
Short name T264
Test name
Test status
Simulation time 154660850518 ps
CPU time 223.93 seconds
Started Jul 17 07:48:11 PM PDT 24
Finished Jul 17 07:51:58 PM PDT 24
Peak memory 249204 kb
Host smart-b195aec5-2a3a-4d13-82c5-cb0394a54451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387318620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1387318620
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2233359654
Short name T509
Test name
Test status
Simulation time 2045272858 ps
CPU time 8.13 seconds
Started Jul 17 07:48:10 PM PDT 24
Finished Jul 17 07:48:22 PM PDT 24
Peak memory 232712 kb
Host smart-c25915b0-e424-43a4-a2cd-a15778b8ebaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233359654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2233359654
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2040122402
Short name T214
Test name
Test status
Simulation time 1221474720 ps
CPU time 8.02 seconds
Started Jul 17 07:48:10 PM PDT 24
Finished Jul 17 07:48:21 PM PDT 24
Peak memory 224476 kb
Host smart-032e9270-2f35-4e74-adfa-39993e0c6bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040122402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2040122402
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.737462991
Short name T388
Test name
Test status
Simulation time 4363342532 ps
CPU time 5.47 seconds
Started Jul 17 07:48:10 PM PDT 24
Finished Jul 17 07:48:19 PM PDT 24
Peak memory 224636 kb
Host smart-64d47d19-f0db-49e5-86da-5629101cf3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737462991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
737462991
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2444446637
Short name T725
Test name
Test status
Simulation time 2263573952 ps
CPU time 3.69 seconds
Started Jul 17 07:48:07 PM PDT 24
Finished Jul 17 07:48:12 PM PDT 24
Peak memory 227924 kb
Host smart-7fbb729f-acb2-4834-adbc-d29abf8b72ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444446637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2444446637
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1491936891
Short name T343
Test name
Test status
Simulation time 690761177 ps
CPU time 4.65 seconds
Started Jul 17 07:48:08 PM PDT 24
Finished Jul 17 07:48:13 PM PDT 24
Peak memory 223176 kb
Host smart-4ebc6bee-d1a1-43e4-af05-bc5f88bd7e76
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1491936891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1491936891
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2799323083
Short name T74
Test name
Test status
Simulation time 307561228 ps
CPU time 1.18 seconds
Started Jul 17 07:48:10 PM PDT 24
Finished Jul 17 07:48:14 PM PDT 24
Peak memory 236592 kb
Host smart-93744a44-c0a9-4273-84f0-3debe7627a7e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799323083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2799323083
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2258341898
Short name T62
Test name
Test status
Simulation time 1506326560 ps
CPU time 6.33 seconds
Started Jul 17 07:48:10 PM PDT 24
Finished Jul 17 07:48:18 PM PDT 24
Peak memory 218952 kb
Host smart-3133254e-f239-4bc8-b53c-e82256aa7afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258341898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2258341898
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1777030971
Short name T616
Test name
Test status
Simulation time 2474908189 ps
CPU time 2.4 seconds
Started Jul 17 07:48:12 PM PDT 24
Finished Jul 17 07:48:18 PM PDT 24
Peak memory 208032 kb
Host smart-3312ec08-c3d9-4da5-8c90-57b61def9e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777030971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1777030971
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2609146358
Short name T685
Test name
Test status
Simulation time 362630899 ps
CPU time 1.24 seconds
Started Jul 17 07:48:07 PM PDT 24
Finished Jul 17 07:48:09 PM PDT 24
Peak memory 216208 kb
Host smart-947abb7f-38f7-4a9b-904a-f850c7abc7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609146358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2609146358
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1741258395
Short name T624
Test name
Test status
Simulation time 65627167 ps
CPU time 0.74 seconds
Started Jul 17 07:48:20 PM PDT 24
Finished Jul 17 07:48:21 PM PDT 24
Peak memory 205984 kb
Host smart-89db33ff-1b60-4469-ad26-7fd8925f3fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741258395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1741258395
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3923993104
Short name T738
Test name
Test status
Simulation time 681504606 ps
CPU time 4.34 seconds
Started Jul 17 07:48:08 PM PDT 24
Finished Jul 17 07:48:13 PM PDT 24
Peak memory 224496 kb
Host smart-eea04c71-1a83-4ea6-9cce-6b0a21ca7b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923993104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3923993104
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2447470472
Short name T508
Test name
Test status
Simulation time 22810274 ps
CPU time 0.72 seconds
Started Jul 17 07:50:44 PM PDT 24
Finished Jul 17 07:50:46 PM PDT 24
Peak memory 205520 kb
Host smart-ea1b01aa-7835-4a8c-a512-e850b8f3ff10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447470472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2447470472
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.960527680
Short name T567
Test name
Test status
Simulation time 190671345 ps
CPU time 0.73 seconds
Started Jul 17 07:50:34 PM PDT 24
Finished Jul 17 07:50:37 PM PDT 24
Peak memory 205576 kb
Host smart-58642d8e-317e-472c-8426-be8902e8b6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960527680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.960527680
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1104152713
Short name T611
Test name
Test status
Simulation time 10937576025 ps
CPU time 95.48 seconds
Started Jul 17 07:50:38 PM PDT 24
Finished Jul 17 07:52:15 PM PDT 24
Peak memory 249192 kb
Host smart-010e252c-b5ef-4957-a50b-de78afa35b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104152713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1104152713
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.4270828319
Short name T359
Test name
Test status
Simulation time 26630190529 ps
CPU time 96.76 seconds
Started Jul 17 07:50:46 PM PDT 24
Finished Jul 17 07:52:23 PM PDT 24
Peak memory 240520 kb
Host smart-2e87ad4d-08ef-414f-8d70-26b7af56c7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270828319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.4270828319
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3413511310
Short name T151
Test name
Test status
Simulation time 1510211878 ps
CPU time 24.35 seconds
Started Jul 17 07:50:36 PM PDT 24
Finished Jul 17 07:51:03 PM PDT 24
Peak memory 249008 kb
Host smart-2540cfba-4582-4102-8075-2da475c48de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413511310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3413511310
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.850375002
Short name T81
Test name
Test status
Simulation time 4391707574 ps
CPU time 9.89 seconds
Started Jul 17 07:50:39 PM PDT 24
Finished Jul 17 07:50:51 PM PDT 24
Peak memory 224620 kb
Host smart-bf888f0f-cd5f-4f5a-88f8-69f2615a73af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850375002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds
.850375002
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.414464369
Short name T873
Test name
Test status
Simulation time 1607143978 ps
CPU time 13.46 seconds
Started Jul 17 07:50:35 PM PDT 24
Finished Jul 17 07:50:50 PM PDT 24
Peak memory 224460 kb
Host smart-a4136c92-a907-43bd-b931-1c94b14c362c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414464369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.414464369
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.904645766
Short name T734
Test name
Test status
Simulation time 21651894725 ps
CPU time 72.02 seconds
Started Jul 17 07:50:36 PM PDT 24
Finished Jul 17 07:51:50 PM PDT 24
Peak memory 232712 kb
Host smart-e905a529-7f21-4364-8899-b6f2afb4eb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904645766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.904645766
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.332970405
Short name T707
Test name
Test status
Simulation time 659630525 ps
CPU time 5.56 seconds
Started Jul 17 07:50:33 PM PDT 24
Finished Jul 17 07:50:40 PM PDT 24
Peak memory 232624 kb
Host smart-b5c3d043-e127-4770-8b61-6097a2943c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332970405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.332970405
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3556269770
Short name T915
Test name
Test status
Simulation time 4005420748 ps
CPU time 7.45 seconds
Started Jul 17 07:50:38 PM PDT 24
Finished Jul 17 07:50:47 PM PDT 24
Peak memory 240460 kb
Host smart-21ea2b24-324d-41cd-8f05-55e780b5fe83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556269770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3556269770
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1245168845
Short name T393
Test name
Test status
Simulation time 1348333238 ps
CPU time 6.92 seconds
Started Jul 17 07:50:43 PM PDT 24
Finished Jul 17 07:50:51 PM PDT 24
Peak memory 220136 kb
Host smart-fb8b54cb-46c8-4e49-906e-6802135fdfe4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1245168845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1245168845
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2296386537
Short name T282
Test name
Test status
Simulation time 7226987871 ps
CPU time 68.47 seconds
Started Jul 17 07:50:43 PM PDT 24
Finished Jul 17 07:51:53 PM PDT 24
Peak memory 241016 kb
Host smart-4984a396-b53c-4e39-8f46-b3d48d61556b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296386537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2296386537
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2979507912
Short name T64
Test name
Test status
Simulation time 13990617240 ps
CPU time 30.55 seconds
Started Jul 17 07:50:34 PM PDT 24
Finished Jul 17 07:51:07 PM PDT 24
Peak memory 216588 kb
Host smart-001f05d0-b349-4db0-bd3d-4087193f58a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979507912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2979507912
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3681025373
Short name T809
Test name
Test status
Simulation time 1970909862 ps
CPU time 7.28 seconds
Started Jul 17 07:50:32 PM PDT 24
Finished Jul 17 07:50:40 PM PDT 24
Peak memory 216184 kb
Host smart-e544ad5d-0ae4-4632-bcc3-19353e857396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681025373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3681025373
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.999985286
Short name T3
Test name
Test status
Simulation time 115982915 ps
CPU time 1.44 seconds
Started Jul 17 07:50:37 PM PDT 24
Finished Jul 17 07:50:41 PM PDT 24
Peak memory 216256 kb
Host smart-4b313399-a9c7-48d8-8cfd-44e2c5d5d9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999985286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.999985286
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1668109085
Short name T334
Test name
Test status
Simulation time 14991033 ps
CPU time 0.74 seconds
Started Jul 17 07:50:35 PM PDT 24
Finished Jul 17 07:50:38 PM PDT 24
Peak memory 206192 kb
Host smart-ec20d87d-607d-4174-94f3-a2c94af4df79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668109085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1668109085
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.705362309
Short name T245
Test name
Test status
Simulation time 1642373892 ps
CPU time 9.09 seconds
Started Jul 17 07:50:38 PM PDT 24
Finished Jul 17 07:50:49 PM PDT 24
Peak memory 234736 kb
Host smart-bd877b53-68fe-4118-a41d-817d69f2739d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705362309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.705362309
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2893129576
Short name T831
Test name
Test status
Simulation time 30745977 ps
CPU time 0.74 seconds
Started Jul 17 07:50:34 PM PDT 24
Finished Jul 17 07:50:37 PM PDT 24
Peak memory 205528 kb
Host smart-a4731456-adaf-4a7d-941e-04537984242b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893129576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2893129576
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2235639202
Short name T11
Test name
Test status
Simulation time 330639640 ps
CPU time 5.21 seconds
Started Jul 17 07:50:36 PM PDT 24
Finished Jul 17 07:50:43 PM PDT 24
Peak memory 232692 kb
Host smart-3ea0e36d-4a70-4fcc-9681-2cd145b12e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235639202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2235639202
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1944393572
Short name T556
Test name
Test status
Simulation time 50223945 ps
CPU time 0.73 seconds
Started Jul 17 07:50:33 PM PDT 24
Finished Jul 17 07:50:35 PM PDT 24
Peak memory 206996 kb
Host smart-31f1360f-6136-497f-b8cc-54fc5a613821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944393572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1944393572
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2497943208
Short name T351
Test name
Test status
Simulation time 1819840290 ps
CPU time 44.3 seconds
Started Jul 17 07:50:34 PM PDT 24
Finished Jul 17 07:51:21 PM PDT 24
Peak memory 250132 kb
Host smart-419fdefb-59cf-4499-80db-77870b17428f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497943208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2497943208
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2906965193
Short name T692
Test name
Test status
Simulation time 22819391903 ps
CPU time 160.08 seconds
Started Jul 17 07:50:34 PM PDT 24
Finished Jul 17 07:53:16 PM PDT 24
Peak memory 249232 kb
Host smart-e740ab7e-3699-4541-973f-aa9ab1903996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906965193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2906965193
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3256172223
Short name T205
Test name
Test status
Simulation time 72555483638 ps
CPU time 349.52 seconds
Started Jul 17 07:50:34 PM PDT 24
Finished Jul 17 07:56:26 PM PDT 24
Peak memory 249540 kb
Host smart-e800895c-5383-4d79-afc1-3050ee3c76fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256172223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3256172223
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.734857713
Short name T306
Test name
Test status
Simulation time 346397552 ps
CPU time 10.57 seconds
Started Jul 17 07:50:40 PM PDT 24
Finished Jul 17 07:50:52 PM PDT 24
Peak memory 232684 kb
Host smart-e47adb3e-0552-4a58-90a9-f3d1787fe2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734857713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.734857713
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.228194292
Short name T713
Test name
Test status
Simulation time 998144889 ps
CPU time 20.28 seconds
Started Jul 17 07:50:35 PM PDT 24
Finished Jul 17 07:50:58 PM PDT 24
Peak memory 238904 kb
Host smart-74e4687c-3c5f-4eb1-9d51-c88aa5deea4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228194292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds
.228194292
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2957794243
Short name T905
Test name
Test status
Simulation time 245197309 ps
CPU time 4.99 seconds
Started Jul 17 07:50:40 PM PDT 24
Finished Jul 17 07:50:47 PM PDT 24
Peak memory 224496 kb
Host smart-1cce7802-fc6d-4b88-a43b-41db68a49901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957794243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2957794243
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.373233657
Short name T674
Test name
Test status
Simulation time 472888013 ps
CPU time 11.35 seconds
Started Jul 17 07:50:33 PM PDT 24
Finished Jul 17 07:50:45 PM PDT 24
Peak memory 232640 kb
Host smart-be8fd7c4-7a4a-496e-bf08-6cbc85a5771a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373233657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.373233657
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.821212207
Short name T638
Test name
Test status
Simulation time 13013558245 ps
CPU time 12.58 seconds
Started Jul 17 07:50:41 PM PDT 24
Finished Jul 17 07:50:55 PM PDT 24
Peak memory 232764 kb
Host smart-becf71c3-a126-4e02-9d0f-0209d02b67dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821212207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.821212207
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.945186050
Short name T832
Test name
Test status
Simulation time 43339419890 ps
CPU time 7.94 seconds
Started Jul 17 07:50:37 PM PDT 24
Finished Jul 17 07:50:47 PM PDT 24
Peak memory 232728 kb
Host smart-93037f7a-7c9b-4587-8c30-e639166a90e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945186050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.945186050
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2608046850
Short name T376
Test name
Test status
Simulation time 918242097 ps
CPU time 11.58 seconds
Started Jul 17 07:50:43 PM PDT 24
Finished Jul 17 07:50:56 PM PDT 24
Peak memory 222136 kb
Host smart-d3125842-6c1e-48b5-9d4e-ff32107587d7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2608046850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2608046850
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2260386420
Short name T144
Test name
Test status
Simulation time 974514879524 ps
CPU time 644.34 seconds
Started Jul 17 07:50:34 PM PDT 24
Finished Jul 17 08:01:20 PM PDT 24
Peak memory 266468 kb
Host smart-1ccc6a83-1fa0-49fa-acac-71bafda0b0fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260386420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2260386420
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.455097092
Short name T606
Test name
Test status
Simulation time 3286633666 ps
CPU time 4.3 seconds
Started Jul 17 07:50:41 PM PDT 24
Finished Jul 17 07:50:47 PM PDT 24
Peak memory 220172 kb
Host smart-8e54e788-ae47-4f3e-94b7-f05c05cd6ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455097092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.455097092
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.4224029241
Short name T907
Test name
Test status
Simulation time 104478443 ps
CPU time 1.47 seconds
Started Jul 17 07:50:35 PM PDT 24
Finished Jul 17 07:50:39 PM PDT 24
Peak memory 207900 kb
Host smart-7d08ebfb-061a-4a2a-9727-231e95889b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224029241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.4224029241
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3346439118
Short name T908
Test name
Test status
Simulation time 260931772 ps
CPU time 1.95 seconds
Started Jul 17 07:50:43 PM PDT 24
Finished Jul 17 07:50:45 PM PDT 24
Peak memory 216204 kb
Host smart-cf34d61e-4862-4b32-9898-de095851167a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346439118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3346439118
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1265474502
Short name T797
Test name
Test status
Simulation time 123652018 ps
CPU time 0.86 seconds
Started Jul 17 07:50:41 PM PDT 24
Finished Jul 17 07:50:43 PM PDT 24
Peak memory 207016 kb
Host smart-523ddb27-dabb-4496-ac18-a461cdc0f9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265474502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1265474502
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2620490815
Short name T141
Test name
Test status
Simulation time 5137509035 ps
CPU time 9.44 seconds
Started Jul 17 07:50:43 PM PDT 24
Finished Jul 17 07:50:54 PM PDT 24
Peak memory 224620 kb
Host smart-b1796298-7102-4f61-abb5-26c53480090e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620490815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2620490815
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2078500602
Short name T378
Test name
Test status
Simulation time 14727720 ps
CPU time 0.71 seconds
Started Jul 17 07:50:54 PM PDT 24
Finished Jul 17 07:50:57 PM PDT 24
Peak memory 205536 kb
Host smart-d8980a38-b268-4580-b09d-bc26dc01b409
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078500602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2078500602
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.775066290
Short name T663
Test name
Test status
Simulation time 244354368 ps
CPU time 2.78 seconds
Started Jul 17 07:50:53 PM PDT 24
Finished Jul 17 07:50:58 PM PDT 24
Peak memory 232636 kb
Host smart-7fb2c65e-0171-440d-86f3-04abeb6e1f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775066290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.775066290
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.854518876
Short name T332
Test name
Test status
Simulation time 63229285 ps
CPU time 0.77 seconds
Started Jul 17 07:50:43 PM PDT 24
Finished Jul 17 07:50:46 PM PDT 24
Peak memory 205900 kb
Host smart-c1d4ca29-f4e3-4c00-b628-63c1e169a6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854518876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.854518876
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.472281871
Short name T850
Test name
Test status
Simulation time 11657253726 ps
CPU time 100.94 seconds
Started Jul 17 07:50:52 PM PDT 24
Finished Jul 17 07:52:35 PM PDT 24
Peak memory 250084 kb
Host smart-b5add6d2-ecf3-4739-b41f-cf1dd42e9c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472281871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.472281871
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1458845546
Short name T146
Test name
Test status
Simulation time 52855131807 ps
CPU time 418.27 seconds
Started Jul 17 07:50:55 PM PDT 24
Finished Jul 17 07:57:56 PM PDT 24
Peak memory 265644 kb
Host smart-b9f76f74-2aad-48d9-b016-30087721d4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458845546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1458845546
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1001082143
Short name T644
Test name
Test status
Simulation time 937713948 ps
CPU time 14.66 seconds
Started Jul 17 07:50:53 PM PDT 24
Finished Jul 17 07:51:09 PM PDT 24
Peak memory 224440 kb
Host smart-df7f6cbf-f8f6-43d8-a8c5-32919b0db805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001082143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1001082143
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.1925429107
Short name T958
Test name
Test status
Simulation time 12241044145 ps
CPU time 63.7 seconds
Started Jul 17 07:51:00 PM PDT 24
Finished Jul 17 07:52:06 PM PDT 24
Peak memory 251020 kb
Host smart-b286f75f-8f24-4ccc-8e0b-33899ff75c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925429107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.1925429107
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2236839782
Short name T488
Test name
Test status
Simulation time 15941783214 ps
CPU time 36.88 seconds
Started Jul 17 07:50:50 PM PDT 24
Finished Jul 17 07:51:28 PM PDT 24
Peak memory 232788 kb
Host smart-4ff25959-9d84-44bc-b9c1-4b77afcc40a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236839782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2236839782
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3403017936
Short name T771
Test name
Test status
Simulation time 193747028 ps
CPU time 5.3 seconds
Started Jul 17 07:50:52 PM PDT 24
Finished Jul 17 07:50:59 PM PDT 24
Peak memory 224440 kb
Host smart-efbd8485-cf22-4e23-9daa-4ed44c50c793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403017936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3403017936
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.8264107
Short name T482
Test name
Test status
Simulation time 1138456418 ps
CPU time 5.88 seconds
Started Jul 17 07:50:53 PM PDT 24
Finished Jul 17 07:51:00 PM PDT 24
Peak memory 232720 kb
Host smart-ef5ef36a-0e14-4a60-9d01-a19f20538917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8264107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap.8264107
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1540583847
Short name T694
Test name
Test status
Simulation time 381490958 ps
CPU time 4.97 seconds
Started Jul 17 07:50:53 PM PDT 24
Finished Jul 17 07:50:59 PM PDT 24
Peak memory 232572 kb
Host smart-478c9db7-3f7c-4e97-9f71-8bbe47771b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540583847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1540583847
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.72338400
Short name T491
Test name
Test status
Simulation time 650658052 ps
CPU time 7.75 seconds
Started Jul 17 07:50:52 PM PDT 24
Finished Jul 17 07:51:01 PM PDT 24
Peak memory 223172 kb
Host smart-640f8d7f-067c-4e3a-b990-fc0247cb6fac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=72338400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direc
t.72338400
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2012935715
Short name T169
Test name
Test status
Simulation time 8609419367 ps
CPU time 120.52 seconds
Started Jul 17 07:50:52 PM PDT 24
Finished Jul 17 07:52:54 PM PDT 24
Peak memory 266684 kb
Host smart-7d23dab8-fe3c-4f42-a5f5-68b1863a9d97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012935715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2012935715
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3558106521
Short name T880
Test name
Test status
Simulation time 716462179 ps
CPU time 8.82 seconds
Started Jul 17 07:50:53 PM PDT 24
Finished Jul 17 07:51:04 PM PDT 24
Peak memory 216156 kb
Host smart-01ee25f0-509f-4902-bbd7-2161577ac487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558106521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3558106521
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3205022631
Short name T862
Test name
Test status
Simulation time 279318977 ps
CPU time 1.53 seconds
Started Jul 17 07:50:34 PM PDT 24
Finished Jul 17 07:50:38 PM PDT 24
Peak memory 207648 kb
Host smart-2803d5ec-7d26-4295-9055-44b605b71a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205022631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3205022631
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1577051707
Short name T655
Test name
Test status
Simulation time 43276682 ps
CPU time 2.37 seconds
Started Jul 17 07:50:52 PM PDT 24
Finished Jul 17 07:50:55 PM PDT 24
Peak memory 216180 kb
Host smart-ed00f3bd-654c-4900-ac46-a6a5ee399ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577051707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1577051707
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.23697911
Short name T380
Test name
Test status
Simulation time 125289798 ps
CPU time 0.78 seconds
Started Jul 17 07:50:53 PM PDT 24
Finished Jul 17 07:50:56 PM PDT 24
Peak memory 205984 kb
Host smart-562653d6-b610-4e2d-a2d4-adbf87cda3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23697911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.23697911
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.51859578
Short name T722
Test name
Test status
Simulation time 290852682 ps
CPU time 3.56 seconds
Started Jul 17 07:50:55 PM PDT 24
Finished Jul 17 07:51:01 PM PDT 24
Peak memory 232652 kb
Host smart-b17eb9e9-f223-48c6-a290-191beaf2a81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51859578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.51859578
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3497089104
Short name T765
Test name
Test status
Simulation time 21510364 ps
CPU time 0.74 seconds
Started Jul 17 07:50:54 PM PDT 24
Finished Jul 17 07:50:57 PM PDT 24
Peak memory 204952 kb
Host smart-75a5bf0c-6c97-4094-adf3-247794d4770d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497089104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3497089104
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1219227690
Short name T695
Test name
Test status
Simulation time 631653457 ps
CPU time 8.09 seconds
Started Jul 17 07:50:55 PM PDT 24
Finished Jul 17 07:51:05 PM PDT 24
Peak memory 232672 kb
Host smart-e82c9b7f-d530-42e4-8aa0-117aba587d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219227690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1219227690
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1585210694
Short name T358
Test name
Test status
Simulation time 18465469 ps
CPU time 0.75 seconds
Started Jul 17 07:50:51 PM PDT 24
Finished Jul 17 07:50:53 PM PDT 24
Peak memory 205904 kb
Host smart-22c4cfc9-3abe-42e7-a37a-cfb0ff92ba0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585210694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1585210694
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3174002182
Short name T993
Test name
Test status
Simulation time 6200177051 ps
CPU time 52.57 seconds
Started Jul 17 07:50:52 PM PDT 24
Finished Jul 17 07:51:46 PM PDT 24
Peak memory 249200 kb
Host smart-fa90f146-5759-491e-9f1b-0d16ef83bf81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174002182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3174002182
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.838342653
Short name T818
Test name
Test status
Simulation time 101229525932 ps
CPU time 46.66 seconds
Started Jul 17 07:50:54 PM PDT 24
Finished Jul 17 07:51:43 PM PDT 24
Peak memory 233852 kb
Host smart-9264c725-2092-4ed2-abfd-c7bf5730a1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838342653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.838342653
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2946040986
Short name T788
Test name
Test status
Simulation time 41759912049 ps
CPU time 147.57 seconds
Started Jul 17 07:50:54 PM PDT 24
Finished Jul 17 07:53:24 PM PDT 24
Peak memory 249184 kb
Host smart-9a5f6b33-4a0c-477e-bdf7-3277b05101bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946040986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2946040986
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.224877394
Short name T754
Test name
Test status
Simulation time 281356094 ps
CPU time 3.46 seconds
Started Jul 17 07:50:57 PM PDT 24
Finished Jul 17 07:51:04 PM PDT 24
Peak memory 224448 kb
Host smart-22b815d4-238a-4f35-9867-1a2812682b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224877394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.224877394
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.713763336
Short name T662
Test name
Test status
Simulation time 4357218180 ps
CPU time 10.74 seconds
Started Jul 17 07:50:54 PM PDT 24
Finished Jul 17 07:51:06 PM PDT 24
Peak memory 233868 kb
Host smart-00e62fd0-9e67-4f5c-ac42-9652bf5134be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713763336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds
.713763336
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.4219730413
Short name T515
Test name
Test status
Simulation time 1134835939 ps
CPU time 4.63 seconds
Started Jul 17 07:50:55 PM PDT 24
Finished Jul 17 07:51:02 PM PDT 24
Peak memory 224452 kb
Host smart-89c5b109-a2ae-417e-a4b9-46a654f05eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219730413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.4219730413
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3246052644
Short name T534
Test name
Test status
Simulation time 9974433091 ps
CPU time 52.8 seconds
Started Jul 17 07:50:54 PM PDT 24
Finished Jul 17 07:51:49 PM PDT 24
Peak memory 232748 kb
Host smart-82972a03-f15a-4db9-b06a-f6eb63c61010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246052644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3246052644
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1464208530
Short name T53
Test name
Test status
Simulation time 5538081617 ps
CPU time 12.15 seconds
Started Jul 17 07:50:53 PM PDT 24
Finished Jul 17 07:51:07 PM PDT 24
Peak memory 224640 kb
Host smart-a997fa6e-e570-4aba-be21-08751ff1b239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464208530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1464208530
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.745894613
Short name T829
Test name
Test status
Simulation time 2471664464 ps
CPU time 6.01 seconds
Started Jul 17 07:50:51 PM PDT 24
Finished Jul 17 07:50:59 PM PDT 24
Peak memory 232828 kb
Host smart-fe0dae70-99a6-4dae-be73-f5ea6eeb837c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745894613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.745894613
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2652272034
Short name T366
Test name
Test status
Simulation time 21718301763 ps
CPU time 19.74 seconds
Started Jul 17 07:50:51 PM PDT 24
Finished Jul 17 07:51:11 PM PDT 24
Peak memory 223292 kb
Host smart-1c6ba63f-a4cb-4f12-aade-974b25e79b8e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2652272034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2652272034
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.138347316
Short name T863
Test name
Test status
Simulation time 2861176321 ps
CPU time 15.31 seconds
Started Jul 17 07:50:57 PM PDT 24
Finished Jul 17 07:51:15 PM PDT 24
Peak memory 216248 kb
Host smart-56532261-b4c9-4158-966e-36e6cb47af67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138347316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.138347316
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2179129828
Short name T677
Test name
Test status
Simulation time 46503690253 ps
CPU time 19.42 seconds
Started Jul 17 07:50:58 PM PDT 24
Finished Jul 17 07:51:20 PM PDT 24
Peak memory 218016 kb
Host smart-7dc1dbcf-a86e-42e9-ad20-6f0e627b4d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179129828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2179129828
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1124799395
Short name T731
Test name
Test status
Simulation time 165265055 ps
CPU time 3.51 seconds
Started Jul 17 07:50:54 PM PDT 24
Finished Jul 17 07:51:00 PM PDT 24
Peak memory 216208 kb
Host smart-b94dabe2-66e0-4f3d-9c9d-01cdee8e5557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124799395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1124799395
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.992042245
Short name T547
Test name
Test status
Simulation time 291587341 ps
CPU time 0.89 seconds
Started Jul 17 07:50:53 PM PDT 24
Finished Jul 17 07:50:56 PM PDT 24
Peak memory 205956 kb
Host smart-6de0a220-dd36-4e52-ac32-10552075430b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992042245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.992042245
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2944884954
Short name T520
Test name
Test status
Simulation time 862013745 ps
CPU time 4.73 seconds
Started Jul 17 07:50:54 PM PDT 24
Finished Jul 17 07:51:01 PM PDT 24
Peak memory 224508 kb
Host smart-210bb013-2e3d-43c2-8840-b86b2f2208d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944884954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2944884954
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3670658503
Short name T400
Test name
Test status
Simulation time 27752196 ps
CPU time 0.72 seconds
Started Jul 17 07:50:54 PM PDT 24
Finished Jul 17 07:50:57 PM PDT 24
Peak memory 205916 kb
Host smart-c583270f-e19a-4f0b-88dc-269492362455
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670658503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3670658503
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1046824102
Short name T856
Test name
Test status
Simulation time 51607295 ps
CPU time 2.54 seconds
Started Jul 17 07:50:52 PM PDT 24
Finished Jul 17 07:50:56 PM PDT 24
Peak memory 232308 kb
Host smart-b9e8ba87-f355-44fa-a692-5eb5b84d08a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046824102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1046824102
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1832294713
Short name T490
Test name
Test status
Simulation time 83089886 ps
CPU time 0.79 seconds
Started Jul 17 07:50:57 PM PDT 24
Finished Jul 17 07:51:00 PM PDT 24
Peak memory 206604 kb
Host smart-e0781484-d006-4a1b-9d35-4e94b2caa444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832294713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1832294713
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3792613667
Short name T83
Test name
Test status
Simulation time 9555800353 ps
CPU time 31.58 seconds
Started Jul 17 07:50:57 PM PDT 24
Finished Jul 17 07:51:31 PM PDT 24
Peak memory 224552 kb
Host smart-d29dffec-a65f-4850-82ec-00b0d647b10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792613667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3792613667
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3034801741
Short name T661
Test name
Test status
Simulation time 75071447330 ps
CPU time 177.67 seconds
Started Jul 17 07:50:56 PM PDT 24
Finished Jul 17 07:53:57 PM PDT 24
Peak memory 241056 kb
Host smart-6fe1bc8e-9f2e-4d87-85b9-762b6539c860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034801741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3034801741
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3689524553
Short name T313
Test name
Test status
Simulation time 13912100671 ps
CPU time 90 seconds
Started Jul 17 07:50:57 PM PDT 24
Finished Jul 17 07:52:30 PM PDT 24
Peak memory 257440 kb
Host smart-9fc4592b-6fbc-4587-bbd0-f9caad228e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689524553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3689524553
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.518132435
Short name T615
Test name
Test status
Simulation time 759289959 ps
CPU time 16.77 seconds
Started Jul 17 07:50:51 PM PDT 24
Finished Jul 17 07:51:09 PM PDT 24
Peak memory 224584 kb
Host smart-06801388-eee9-4543-a905-fce41618caad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518132435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.518132435
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.1712727441
Short name T919
Test name
Test status
Simulation time 111241543216 ps
CPU time 202.61 seconds
Started Jul 17 07:50:52 PM PDT 24
Finished Jul 17 07:54:17 PM PDT 24
Peak memory 253000 kb
Host smart-c6750642-c712-47de-b0ad-07c4b06a33d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712727441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.1712727441
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3325801459
Short name T106
Test name
Test status
Simulation time 478099198 ps
CPU time 4.45 seconds
Started Jul 17 07:50:55 PM PDT 24
Finished Jul 17 07:51:01 PM PDT 24
Peak memory 232656 kb
Host smart-d9e09541-7146-4487-a327-b7cc19ecb53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325801459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3325801459
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.123539940
Short name T897
Test name
Test status
Simulation time 6347756252 ps
CPU time 51.09 seconds
Started Jul 17 07:50:58 PM PDT 24
Finished Jul 17 07:51:51 PM PDT 24
Peak memory 239532 kb
Host smart-65b41e26-7ead-4424-a2fe-0cfa77f9fdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123539940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.123539940
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.4057687815
Short name T262
Test name
Test status
Simulation time 9096726211 ps
CPU time 9.15 seconds
Started Jul 17 07:50:53 PM PDT 24
Finished Jul 17 07:51:04 PM PDT 24
Peak memory 232816 kb
Host smart-8e74d643-17b9-4da6-9b7d-a28a8fca1026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057687815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.4057687815
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1808354062
Short name T759
Test name
Test status
Simulation time 691699101 ps
CPU time 7.32 seconds
Started Jul 17 07:50:53 PM PDT 24
Finished Jul 17 07:51:03 PM PDT 24
Peak memory 224500 kb
Host smart-9b3fbdff-6ff2-4ced-bf8d-5de35c96c1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808354062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1808354062
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3729306868
Short name T716
Test name
Test status
Simulation time 3793510435 ps
CPU time 12.09 seconds
Started Jul 17 07:50:58 PM PDT 24
Finished Jul 17 07:51:12 PM PDT 24
Peak memory 218852 kb
Host smart-2e06f1fa-6aa3-415f-8d81-74fe670583ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3729306868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3729306868
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3555554448
Short name T283
Test name
Test status
Simulation time 120812493076 ps
CPU time 493.3 seconds
Started Jul 17 07:50:57 PM PDT 24
Finished Jul 17 07:59:13 PM PDT 24
Peak memory 272912 kb
Host smart-a5508ad9-28eb-42e3-879f-960951ffc339
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555554448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3555554448
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.4119285531
Short name T513
Test name
Test status
Simulation time 894964270 ps
CPU time 9.88 seconds
Started Jul 17 07:50:52 PM PDT 24
Finished Jul 17 07:51:03 PM PDT 24
Peak memory 216288 kb
Host smart-42498b4b-acdf-4166-99a8-bfe4cc397652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119285531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.4119285531
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2336659757
Short name T569
Test name
Test status
Simulation time 816285475 ps
CPU time 1.77 seconds
Started Jul 17 07:50:54 PM PDT 24
Finished Jul 17 07:50:58 PM PDT 24
Peak memory 207892 kb
Host smart-f29fd066-331f-4317-9eb2-960d1351f92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336659757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2336659757
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.973928379
Short name T525
Test name
Test status
Simulation time 156498188 ps
CPU time 8.79 seconds
Started Jul 17 07:50:51 PM PDT 24
Finished Jul 17 07:51:01 PM PDT 24
Peak memory 216220 kb
Host smart-6d4840e1-94f5-4aa2-80ec-5a5593d64507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973928379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.973928379
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1457669968
Short name T760
Test name
Test status
Simulation time 48821341 ps
CPU time 0.75 seconds
Started Jul 17 07:50:54 PM PDT 24
Finished Jul 17 07:50:57 PM PDT 24
Peak memory 205960 kb
Host smart-54078b29-226c-4eb5-8978-c33dcb519897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457669968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1457669968
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2893483543
Short name T457
Test name
Test status
Simulation time 3889607810 ps
CPU time 4.08 seconds
Started Jul 17 07:50:55 PM PDT 24
Finished Jul 17 07:51:01 PM PDT 24
Peak memory 224632 kb
Host smart-10092d25-85e8-4e8e-ba9d-4ec5b9243c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893483543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2893483543
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2556867366
Short name T319
Test name
Test status
Simulation time 33336860 ps
CPU time 0.74 seconds
Started Jul 17 07:51:01 PM PDT 24
Finished Jul 17 07:51:04 PM PDT 24
Peak memory 204980 kb
Host smart-c834d374-aebd-405d-803c-422e01d04dc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556867366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2556867366
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2227023935
Short name T580
Test name
Test status
Simulation time 2094096790 ps
CPU time 5.46 seconds
Started Jul 17 07:50:57 PM PDT 24
Finished Jul 17 07:51:05 PM PDT 24
Peak memory 231604 kb
Host smart-fce405a2-4b66-447f-b0c4-0962eefa91f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227023935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2227023935
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.669282284
Short name T865
Test name
Test status
Simulation time 13566258 ps
CPU time 0.76 seconds
Started Jul 17 07:50:58 PM PDT 24
Finished Jul 17 07:51:01 PM PDT 24
Peak memory 205900 kb
Host smart-1c3917a5-1cba-47bd-9787-edcffabb253d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669282284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.669282284
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2776451237
Short name T49
Test name
Test status
Simulation time 6478272874 ps
CPU time 24.78 seconds
Started Jul 17 07:51:01 PM PDT 24
Finished Jul 17 07:51:28 PM PDT 24
Peak memory 235484 kb
Host smart-005d2781-0e0e-4bc3-a9d5-4c411aca5fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776451237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2776451237
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3014617764
Short name T930
Test name
Test status
Simulation time 9972108603 ps
CPU time 100.96 seconds
Started Jul 17 07:50:58 PM PDT 24
Finished Jul 17 07:52:41 PM PDT 24
Peak memory 249644 kb
Host smart-e390626f-1dbf-4730-b788-6f3f7ce51a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014617764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3014617764
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1871873375
Short name T704
Test name
Test status
Simulation time 8420530566 ps
CPU time 35.49 seconds
Started Jul 17 07:50:52 PM PDT 24
Finished Jul 17 07:51:29 PM PDT 24
Peak memory 232836 kb
Host smart-10219bd4-6a49-46c6-9f8e-90498b20a155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871873375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1871873375
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3730952106
Short name T304
Test name
Test status
Simulation time 149137586 ps
CPU time 5.25 seconds
Started Jul 17 07:51:01 PM PDT 24
Finished Jul 17 07:51:08 PM PDT 24
Peak memory 224480 kb
Host smart-250d6ac8-eb4d-496f-8dbe-ae46cc50571e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730952106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3730952106
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.2311227328
Short name T198
Test name
Test status
Simulation time 9174445589 ps
CPU time 121.51 seconds
Started Jul 17 07:51:01 PM PDT 24
Finished Jul 17 07:53:04 PM PDT 24
Peak memory 252192 kb
Host smart-2a2e4e68-b9c8-4a28-ad21-fc8b4a65758c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311227328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.2311227328
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1956490244
Short name T669
Test name
Test status
Simulation time 173602243 ps
CPU time 3.32 seconds
Started Jul 17 07:50:57 PM PDT 24
Finished Jul 17 07:51:03 PM PDT 24
Peak memory 224440 kb
Host smart-ad034381-3af7-4689-9633-282e4f8e510e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956490244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1956490244
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2838166599
Short name T639
Test name
Test status
Simulation time 851588439 ps
CPU time 4.7 seconds
Started Jul 17 07:51:00 PM PDT 24
Finished Jul 17 07:51:07 PM PDT 24
Peak memory 224416 kb
Host smart-9156c08b-7632-4a90-b3c1-4b41e7dd57b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838166599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2838166599
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.793585161
Short name T761
Test name
Test status
Simulation time 224230677 ps
CPU time 2.12 seconds
Started Jul 17 07:51:01 PM PDT 24
Finished Jul 17 07:51:05 PM PDT 24
Peak memory 222984 kb
Host smart-1e9e97a4-21fd-42e9-86e6-b53921c10684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793585161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.793585161
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3700922917
Short name T814
Test name
Test status
Simulation time 1830969687 ps
CPU time 7.19 seconds
Started Jul 17 07:50:55 PM PDT 24
Finished Jul 17 07:51:05 PM PDT 24
Peak memory 232696 kb
Host smart-95130310-765f-4869-b354-afeeeb777837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700922917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3700922917
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1120316566
Short name T47
Test name
Test status
Simulation time 322260189 ps
CPU time 5.35 seconds
Started Jul 17 07:51:01 PM PDT 24
Finished Jul 17 07:51:09 PM PDT 24
Peak memory 219360 kb
Host smart-a30678dc-f125-4940-8235-d163a8936d95
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1120316566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1120316566
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2638685943
Short name T171
Test name
Test status
Simulation time 15833188737 ps
CPU time 62 seconds
Started Jul 17 07:51:01 PM PDT 24
Finished Jul 17 07:52:05 PM PDT 24
Peak memory 249248 kb
Host smart-b1c0f2ef-a538-4623-aefa-78c0c8bfce47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638685943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2638685943
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1181051879
Short name T668
Test name
Test status
Simulation time 30122174512 ps
CPU time 38.53 seconds
Started Jul 17 07:50:56 PM PDT 24
Finished Jul 17 07:51:37 PM PDT 24
Peak memory 216308 kb
Host smart-1cfad9f5-3eab-43e2-8060-619d57d3a36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181051879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1181051879
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1833063533
Short name T953
Test name
Test status
Simulation time 5740438633 ps
CPU time 6.01 seconds
Started Jul 17 07:50:53 PM PDT 24
Finished Jul 17 07:51:01 PM PDT 24
Peak memory 216272 kb
Host smart-77645c07-3bf2-4e33-878f-bbdfe595675c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833063533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1833063533
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.720086315
Short name T321
Test name
Test status
Simulation time 325134393 ps
CPU time 1.1 seconds
Started Jul 17 07:50:55 PM PDT 24
Finished Jul 17 07:50:59 PM PDT 24
Peak memory 207892 kb
Host smart-5b3f465e-d891-4620-96b6-4c417d1b37b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720086315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.720086315
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.270663519
Short name T781
Test name
Test status
Simulation time 116201626 ps
CPU time 0.87 seconds
Started Jul 17 07:50:56 PM PDT 24
Finished Jul 17 07:50:59 PM PDT 24
Peak memory 206976 kb
Host smart-6ee40063-52b4-4f27-9aab-4434c1e75155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270663519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.270663519
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2106360362
Short name T751
Test name
Test status
Simulation time 5849766467 ps
CPU time 7.84 seconds
Started Jul 17 07:50:58 PM PDT 24
Finished Jul 17 07:51:08 PM PDT 24
Peak memory 232772 kb
Host smart-f1e53c96-7b04-4e14-bd7c-fa297ce00e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106360362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2106360362
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1927966982
Short name T717
Test name
Test status
Simulation time 68442807 ps
CPU time 0.7 seconds
Started Jul 17 07:51:20 PM PDT 24
Finished Jul 17 07:51:24 PM PDT 24
Peak memory 205064 kb
Host smart-23d86603-da99-4b05-8603-893f2e14b555
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927966982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1927966982
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3287500463
Short name T776
Test name
Test status
Simulation time 126457821 ps
CPU time 3.27 seconds
Started Jul 17 07:51:22 PM PDT 24
Finished Jul 17 07:51:28 PM PDT 24
Peak memory 224488 kb
Host smart-424f3788-79df-45e1-b14d-52761027de29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287500463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3287500463
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2919532821
Short name T600
Test name
Test status
Simulation time 46749549 ps
CPU time 0.75 seconds
Started Jul 17 07:50:53 PM PDT 24
Finished Jul 17 07:50:56 PM PDT 24
Peak memory 205892 kb
Host smart-e6b06247-3151-4c73-9c3a-1339020b1111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919532821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2919532821
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.455216533
Short name T737
Test name
Test status
Simulation time 11866431081 ps
CPU time 63.75 seconds
Started Jul 17 07:51:17 PM PDT 24
Finished Jul 17 07:52:21 PM PDT 24
Peak memory 252492 kb
Host smart-fbb09990-76df-4cb5-9d8e-9d417f886566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455216533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.455216533
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.411506382
Short name T739
Test name
Test status
Simulation time 8332935405 ps
CPU time 60.89 seconds
Started Jul 17 07:51:19 PM PDT 24
Finished Jul 17 07:52:22 PM PDT 24
Peak memory 254336 kb
Host smart-813da413-4c37-44eb-9511-5d4e3ad791ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411506382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.411506382
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1600948793
Short name T59
Test name
Test status
Simulation time 22918025728 ps
CPU time 203.09 seconds
Started Jul 17 07:51:19 PM PDT 24
Finished Jul 17 07:54:44 PM PDT 24
Peak memory 257392 kb
Host smart-a1ecc7c6-8309-4635-9348-0bee53ca0119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600948793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1600948793
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.196660700
Short name T823
Test name
Test status
Simulation time 1367130109 ps
CPU time 16.68 seconds
Started Jul 17 07:51:19 PM PDT 24
Finished Jul 17 07:51:37 PM PDT 24
Peak memory 240848 kb
Host smart-e3fcdfc0-c433-4d8a-a462-f4b8100982d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196660700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.196660700
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.1475481271
Short name T192
Test name
Test status
Simulation time 143358439418 ps
CPU time 268.8 seconds
Started Jul 17 07:51:18 PM PDT 24
Finished Jul 17 07:55:48 PM PDT 24
Peak memory 251492 kb
Host smart-8b3be1f8-7072-4234-87d8-3c4c166de0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475481271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.1475481271
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1585659852
Short name T121
Test name
Test status
Simulation time 1998380499 ps
CPU time 17.53 seconds
Started Jul 17 07:50:56 PM PDT 24
Finished Jul 17 07:51:16 PM PDT 24
Peak memory 232604 kb
Host smart-476038ed-19e9-4936-9954-a042f26b4da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585659852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1585659852
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.127831878
Short name T84
Test name
Test status
Simulation time 861142040 ps
CPU time 13.09 seconds
Started Jul 17 07:50:55 PM PDT 24
Finished Jul 17 07:51:11 PM PDT 24
Peak memory 237676 kb
Host smart-4ec728f0-aff3-4489-8043-74e44d00b706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127831878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.127831878
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.4142318358
Short name T702
Test name
Test status
Simulation time 16745042847 ps
CPU time 15.14 seconds
Started Jul 17 07:50:59 PM PDT 24
Finished Jul 17 07:51:16 PM PDT 24
Peak memory 240952 kb
Host smart-959e75e2-e8c1-4156-855e-ad89a1c646f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142318358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.4142318358
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2122478883
Short name T625
Test name
Test status
Simulation time 12744662701 ps
CPU time 31.62 seconds
Started Jul 17 07:50:55 PM PDT 24
Finished Jul 17 07:51:29 PM PDT 24
Peak memory 240932 kb
Host smart-a274eea7-3773-41e3-88a1-925edf6f3657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122478883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2122478883
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3428424599
Short name T691
Test name
Test status
Simulation time 3714467853 ps
CPU time 4.85 seconds
Started Jul 17 07:51:22 PM PDT 24
Finished Jul 17 07:51:29 PM PDT 24
Peak memory 223348 kb
Host smart-d79394db-3620-4cc3-876b-2d804d3ae55b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3428424599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3428424599
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2177428379
Short name T526
Test name
Test status
Simulation time 10058902788 ps
CPU time 17.03 seconds
Started Jul 17 07:51:01 PM PDT 24
Finished Jul 17 07:51:20 PM PDT 24
Peak memory 216428 kb
Host smart-2e76fde2-c9fc-4f80-897a-ad191c5e75be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177428379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2177428379
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.737362070
Short name T412
Test name
Test status
Simulation time 1547004073 ps
CPU time 3.97 seconds
Started Jul 17 07:50:59 PM PDT 24
Finished Jul 17 07:51:05 PM PDT 24
Peak memory 216188 kb
Host smart-ac4c41fc-8da7-4e21-892d-9145744e5718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737362070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.737362070
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2878844204
Short name T495
Test name
Test status
Simulation time 146175399 ps
CPU time 5.27 seconds
Started Jul 17 07:50:59 PM PDT 24
Finished Jul 17 07:51:06 PM PDT 24
Peak memory 216200 kb
Host smart-4d6f04ca-d69d-4227-8ed3-53536e5d7bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878844204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2878844204
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.671409663
Short name T973
Test name
Test status
Simulation time 751502224 ps
CPU time 1 seconds
Started Jul 17 07:50:56 PM PDT 24
Finished Jul 17 07:50:59 PM PDT 24
Peak memory 205988 kb
Host smart-7708b5b6-67fe-49d7-a08d-5d1e6325ebc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671409663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.671409663
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2174792354
Short name T560
Test name
Test status
Simulation time 129893092 ps
CPU time 2.4 seconds
Started Jul 17 07:50:57 PM PDT 24
Finished Jul 17 07:51:02 PM PDT 24
Peak memory 216704 kb
Host smart-3ea76095-d38c-42d4-8b41-222f2ae36c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174792354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2174792354
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3786742907
Short name T926
Test name
Test status
Simulation time 11862983 ps
CPU time 0.79 seconds
Started Jul 17 07:51:19 PM PDT 24
Finished Jul 17 07:51:21 PM PDT 24
Peak memory 205804 kb
Host smart-70fc991f-84c7-40cb-97ff-a8d58d82bb27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786742907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3786742907
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.440314835
Short name T927
Test name
Test status
Simulation time 7381074385 ps
CPU time 18.01 seconds
Started Jul 17 07:51:21 PM PDT 24
Finished Jul 17 07:51:42 PM PDT 24
Peak memory 232836 kb
Host smart-f31c8a8f-ed7d-4f54-bacd-f2689a35e41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440314835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.440314835
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3441996861
Short name T27
Test name
Test status
Simulation time 43138673 ps
CPU time 0.75 seconds
Started Jul 17 07:51:18 PM PDT 24
Finished Jul 17 07:51:19 PM PDT 24
Peak memory 205892 kb
Host smart-f386ab5b-45ed-4672-9cfa-a0f19e99ad1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441996861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3441996861
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3575834004
Short name T295
Test name
Test status
Simulation time 1615526446 ps
CPU time 17.03 seconds
Started Jul 17 07:51:18 PM PDT 24
Finished Jul 17 07:51:36 PM PDT 24
Peak memory 224416 kb
Host smart-71cb1391-3da6-4ff5-8aa6-9a47c3762608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575834004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3575834004
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1379534972
Short name T487
Test name
Test status
Simulation time 3040196933 ps
CPU time 26.34 seconds
Started Jul 17 07:51:22 PM PDT 24
Finished Jul 17 07:51:51 PM PDT 24
Peak memory 224664 kb
Host smart-0a820d68-e887-4e65-9866-8b92bf15eb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379534972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1379534972
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2382153491
Short name T999
Test name
Test status
Simulation time 34391952249 ps
CPU time 211.03 seconds
Started Jul 17 07:51:18 PM PDT 24
Finished Jul 17 07:54:50 PM PDT 24
Peak memory 256576 kb
Host smart-9f198da8-1afd-4f32-b28a-d57351b51eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382153491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2382153491
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3447241363
Short name T363
Test name
Test status
Simulation time 420561726 ps
CPU time 3.18 seconds
Started Jul 17 07:51:19 PM PDT 24
Finished Jul 17 07:51:24 PM PDT 24
Peak memory 232700 kb
Host smart-67cb8fe5-b43d-4f7a-ba26-1b498e352a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447241363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3447241363
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.3720296572
Short name T540
Test name
Test status
Simulation time 34098653356 ps
CPU time 236.01 seconds
Started Jul 17 07:51:25 PM PDT 24
Finished Jul 17 07:55:22 PM PDT 24
Peak memory 249892 kb
Host smart-7b3dacad-1aff-4c15-8687-bd67d8a3bd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720296572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.3720296572
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3426997241
Short name T972
Test name
Test status
Simulation time 11909446425 ps
CPU time 12.3 seconds
Started Jul 17 07:51:18 PM PDT 24
Finished Jul 17 07:51:31 PM PDT 24
Peak memory 224560 kb
Host smart-e46f80d7-ad4f-464f-a8f8-64050cf1575f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426997241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3426997241
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2759165119
Short name T480
Test name
Test status
Simulation time 6089638148 ps
CPU time 61.38 seconds
Started Jul 17 07:51:17 PM PDT 24
Finished Jul 17 07:52:19 PM PDT 24
Peak memory 233828 kb
Host smart-e518ddf5-337f-4b8e-bbdc-c2ffeec5dd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759165119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2759165119
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2124838239
Short name T768
Test name
Test status
Simulation time 13934593592 ps
CPU time 20.97 seconds
Started Jul 17 07:51:21 PM PDT 24
Finished Jul 17 07:51:45 PM PDT 24
Peak memory 240928 kb
Host smart-9c20386e-9eab-4af3-b61e-77cc008ae551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124838239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2124838239
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1194439735
Short name T452
Test name
Test status
Simulation time 407893343 ps
CPU time 2.26 seconds
Started Jul 17 07:51:21 PM PDT 24
Finished Jul 17 07:51:25 PM PDT 24
Peak memory 223140 kb
Host smart-f81a49c1-4dd7-486d-a6f4-451464f08f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194439735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1194439735
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3773962244
Short name T453
Test name
Test status
Simulation time 7101899997 ps
CPU time 9.57 seconds
Started Jul 17 07:51:18 PM PDT 24
Finished Jul 17 07:51:30 PM PDT 24
Peak memory 222748 kb
Host smart-4b063fa0-d2a4-4015-8754-7245076d49b8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3773962244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3773962244
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.136882996
Short name T594
Test name
Test status
Simulation time 3183043523 ps
CPU time 16.27 seconds
Started Jul 17 07:51:23 PM PDT 24
Finished Jul 17 07:51:42 PM PDT 24
Peak memory 216376 kb
Host smart-4984b711-8c22-489e-b69e-804ea3939623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136882996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.136882996
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1423941779
Short name T986
Test name
Test status
Simulation time 26193363580 ps
CPU time 19.83 seconds
Started Jul 17 07:51:19 PM PDT 24
Finished Jul 17 07:51:41 PM PDT 24
Peak memory 216308 kb
Host smart-e045c8a9-d079-4057-a38e-b91c64dc3164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423941779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1423941779
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.934654174
Short name T425
Test name
Test status
Simulation time 326453098 ps
CPU time 1.3 seconds
Started Jul 17 07:51:21 PM PDT 24
Finished Jul 17 07:51:25 PM PDT 24
Peak memory 215864 kb
Host smart-b596822e-5806-4d8d-bdae-325b8f53812f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934654174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.934654174
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.493644164
Short name T463
Test name
Test status
Simulation time 738772470 ps
CPU time 0.94 seconds
Started Jul 17 07:51:20 PM PDT 24
Finished Jul 17 07:51:24 PM PDT 24
Peak memory 207012 kb
Host smart-a524a530-1ade-40ce-810f-ce74e3d943f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493644164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.493644164
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3949162951
Short name T220
Test name
Test status
Simulation time 5601877492 ps
CPU time 18.5 seconds
Started Jul 17 07:51:22 PM PDT 24
Finished Jul 17 07:51:43 PM PDT 24
Peak memory 232824 kb
Host smart-a0040117-ec23-4a82-87aa-369f4581c30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949162951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3949162951
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2783929395
Short name T437
Test name
Test status
Simulation time 54713333 ps
CPU time 0.71 seconds
Started Jul 17 07:51:21 PM PDT 24
Finished Jul 17 07:51:24 PM PDT 24
Peak memory 205628 kb
Host smart-9ecb30da-c602-4531-bf88-a2735200eb80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783929395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2783929395
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2180705999
Short name T755
Test name
Test status
Simulation time 38209858 ps
CPU time 2.95 seconds
Started Jul 17 07:51:17 PM PDT 24
Finished Jul 17 07:51:20 PM PDT 24
Peak memory 232704 kb
Host smart-232ec673-b274-4d29-bab6-705358ffe444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180705999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2180705999
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.42861560
Short name T871
Test name
Test status
Simulation time 46806468 ps
CPU time 0.75 seconds
Started Jul 17 07:51:22 PM PDT 24
Finished Jul 17 07:51:26 PM PDT 24
Peak memory 205596 kb
Host smart-506aa9bc-99ae-4c21-abf4-353995dbd668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42861560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.42861560
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1852170472
Short name T419
Test name
Test status
Simulation time 73598088417 ps
CPU time 151.64 seconds
Started Jul 17 07:51:20 PM PDT 24
Finished Jul 17 07:53:54 PM PDT 24
Peak memory 248808 kb
Host smart-d3812a8a-48e6-4d54-9bbd-9fd9195420c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852170472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1852170472
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3308052439
Short name T289
Test name
Test status
Simulation time 26512968392 ps
CPU time 278.99 seconds
Started Jul 17 07:51:19 PM PDT 24
Finished Jul 17 07:56:00 PM PDT 24
Peak memory 265656 kb
Host smart-c85aed2c-610a-4c8e-a5c4-e4d27d52349b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308052439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3308052439
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2502025730
Short name T224
Test name
Test status
Simulation time 16837443276 ps
CPU time 177.03 seconds
Started Jul 17 07:51:20 PM PDT 24
Finished Jul 17 07:54:19 PM PDT 24
Peak memory 252892 kb
Host smart-e055cf4b-4575-45db-bb33-c54e6affa7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502025730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2502025730
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1865088852
Short name T389
Test name
Test status
Simulation time 11401386 ps
CPU time 0.79 seconds
Started Jul 17 07:51:19 PM PDT 24
Finished Jul 17 07:51:21 PM PDT 24
Peak memory 215768 kb
Host smart-ce698d85-1b78-4ef2-8c3e-d2033769ad18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865088852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1865088852
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1499434102
Short name T883
Test name
Test status
Simulation time 8192956427 ps
CPU time 18.35 seconds
Started Jul 17 07:51:25 PM PDT 24
Finished Jul 17 07:51:45 PM PDT 24
Peak memory 232776 kb
Host smart-a76a53e7-3800-4f36-bfa5-4d80098a1225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499434102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1499434102
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.4151353369
Short name T613
Test name
Test status
Simulation time 3650414900 ps
CPU time 33.76 seconds
Started Jul 17 07:51:21 PM PDT 24
Finished Jul 17 07:51:58 PM PDT 24
Peak memory 224540 kb
Host smart-4dee95ec-6698-4a0a-a63c-8ba07f405460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151353369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.4151353369
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2008001616
Short name T375
Test name
Test status
Simulation time 897234099 ps
CPU time 5.69 seconds
Started Jul 17 07:51:18 PM PDT 24
Finished Jul 17 07:51:26 PM PDT 24
Peak memory 232636 kb
Host smart-b614c0cd-e771-4fcb-a50f-880689948117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008001616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2008001616
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3628482483
Short name T368
Test name
Test status
Simulation time 41395563551 ps
CPU time 17.07 seconds
Started Jul 17 07:51:19 PM PDT 24
Finished Jul 17 07:51:38 PM PDT 24
Peak memory 232836 kb
Host smart-1653ab68-e81d-4074-99c6-9bd86d9ad1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628482483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3628482483
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2153160145
Short name T455
Test name
Test status
Simulation time 479583392 ps
CPU time 3.84 seconds
Started Jul 17 07:51:19 PM PDT 24
Finished Jul 17 07:51:25 PM PDT 24
Peak memory 220520 kb
Host smart-ee7d31a8-5fb6-4a9f-ba34-b5e29ed93151
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2153160145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2153160145
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1406458447
Short name T181
Test name
Test status
Simulation time 136830446114 ps
CPU time 335.24 seconds
Started Jul 17 07:51:19 PM PDT 24
Finished Jul 17 07:56:56 PM PDT 24
Peak memory 269372 kb
Host smart-87fd0f04-82c1-413e-8e25-ea50229209a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406458447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1406458447
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3374517799
Short name T512
Test name
Test status
Simulation time 10796679856 ps
CPU time 13.25 seconds
Started Jul 17 07:51:20 PM PDT 24
Finished Jul 17 07:51:36 PM PDT 24
Peak memory 215988 kb
Host smart-3a7ba887-cde8-415a-8b1a-ae1e42cb6f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374517799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3374517799
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.373990869
Short name T175
Test name
Test status
Simulation time 6998237491 ps
CPU time 6.37 seconds
Started Jul 17 07:51:20 PM PDT 24
Finished Jul 17 07:51:29 PM PDT 24
Peak memory 216304 kb
Host smart-610678be-5577-4616-a1b7-36786078e84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373990869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.373990869
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1177966443
Short name T361
Test name
Test status
Simulation time 64818197 ps
CPU time 0.82 seconds
Started Jul 17 07:51:21 PM PDT 24
Finished Jul 17 07:51:25 PM PDT 24
Peak memory 207188 kb
Host smart-032e9db0-10ef-4c26-bbc6-d208ba99fabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177966443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1177966443
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2019684886
Short name T917
Test name
Test status
Simulation time 44872593 ps
CPU time 0.88 seconds
Started Jul 17 07:51:17 PM PDT 24
Finished Jul 17 07:51:19 PM PDT 24
Peak memory 205988 kb
Host smart-f1002d27-c83c-4f08-9d1b-032b7163cc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019684886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2019684886
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2705734196
Short name T203
Test name
Test status
Simulation time 7398700473 ps
CPU time 7.94 seconds
Started Jul 17 07:51:22 PM PDT 24
Finished Jul 17 07:51:33 PM PDT 24
Peak memory 232836 kb
Host smart-217b2b13-de5f-4b6f-a7b4-8e100accae16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705734196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2705734196
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3726320811
Short name T690
Test name
Test status
Simulation time 16140413 ps
CPU time 0.73 seconds
Started Jul 17 07:51:24 PM PDT 24
Finished Jul 17 07:51:27 PM PDT 24
Peak memory 205292 kb
Host smart-348da6f7-4d55-4256-856b-fe97190b5c25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726320811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3726320811
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.962759788
Short name T6
Test name
Test status
Simulation time 1941527239 ps
CPU time 24.69 seconds
Started Jul 17 07:51:21 PM PDT 24
Finished Jul 17 07:51:48 PM PDT 24
Peak memory 224080 kb
Host smart-205c5610-d8e8-4cfc-a44a-bc3ab5c12d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962759788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.962759788
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2492465737
Short name T777
Test name
Test status
Simulation time 60505405 ps
CPU time 0.8 seconds
Started Jul 17 07:51:18 PM PDT 24
Finished Jul 17 07:51:20 PM PDT 24
Peak memory 205568 kb
Host smart-ce40e000-f025-48a8-aa5e-d018efaf60ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492465737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2492465737
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3369555336
Short name T974
Test name
Test status
Simulation time 458814964155 ps
CPU time 293.6 seconds
Started Jul 17 07:51:20 PM PDT 24
Finished Jul 17 07:56:16 PM PDT 24
Peak memory 273696 kb
Host smart-79c7a767-f737-4bd0-92c7-e376bd52b980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369555336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3369555336
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.772656782
Short name T266
Test name
Test status
Simulation time 10010292693 ps
CPU time 92.86 seconds
Started Jul 17 07:51:20 PM PDT 24
Finished Jul 17 07:52:55 PM PDT 24
Peak memory 249272 kb
Host smart-8b1c6a5d-f685-49c4-b2c9-f5eedf62729e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772656782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.772656782
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1127421738
Short name T148
Test name
Test status
Simulation time 10844529547 ps
CPU time 117.06 seconds
Started Jul 17 07:51:20 PM PDT 24
Finished Jul 17 07:53:19 PM PDT 24
Peak memory 253700 kb
Host smart-fa4913d0-c39f-42d2-b06c-677ad24d95f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127421738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1127421738
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1074559907
Short name T28
Test name
Test status
Simulation time 3706860054 ps
CPU time 10.48 seconds
Started Jul 17 07:51:21 PM PDT 24
Finished Jul 17 07:51:35 PM PDT 24
Peak memory 224556 kb
Host smart-331da850-f5aa-4672-b264-c16e0c3878cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074559907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1074559907
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.4291672977
Short name T237
Test name
Test status
Simulation time 40826819713 ps
CPU time 274.35 seconds
Started Jul 17 07:51:18 PM PDT 24
Finished Jul 17 07:55:53 PM PDT 24
Peak memory 250932 kb
Host smart-5f6ed57e-dbfc-41c9-8ca9-3b97286bc0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291672977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.4291672977
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3877181401
Short name T938
Test name
Test status
Simulation time 533255603 ps
CPU time 4 seconds
Started Jul 17 07:51:21 PM PDT 24
Finished Jul 17 07:51:27 PM PDT 24
Peak memory 232648 kb
Host smart-02f0379e-dc5a-44b3-ac52-a64f90aac04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877181401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3877181401
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.842887700
Short name T82
Test name
Test status
Simulation time 3332652497 ps
CPU time 34.13 seconds
Started Jul 17 07:51:21 PM PDT 24
Finished Jul 17 07:51:57 PM PDT 24
Peak memory 235948 kb
Host smart-aeda5dd3-46f4-4046-ba9d-1b0cd1a91c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842887700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.842887700
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2701373415
Short name T588
Test name
Test status
Simulation time 3005509236 ps
CPU time 3.53 seconds
Started Jul 17 07:51:19 PM PDT 24
Finished Jul 17 07:51:25 PM PDT 24
Peak memory 232696 kb
Host smart-bdd148e1-41bc-4fb9-99a5-ebf96f3e06cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701373415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2701373415
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.365036547
Short name T681
Test name
Test status
Simulation time 3572211745 ps
CPU time 14.24 seconds
Started Jul 17 07:51:24 PM PDT 24
Finished Jul 17 07:51:40 PM PDT 24
Peak memory 232580 kb
Host smart-ce1a6538-65cd-4483-9ef2-fbe8a65ea0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365036547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.365036547
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3063182792
Short name T778
Test name
Test status
Simulation time 1309454236 ps
CPU time 5.65 seconds
Started Jul 17 07:51:20 PM PDT 24
Finished Jul 17 07:51:28 PM PDT 24
Peak memory 223196 kb
Host smart-283cb59b-23e3-4678-8c33-e129c883e449
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3063182792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3063182792
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3245993473
Short name T36
Test name
Test status
Simulation time 107617356907 ps
CPU time 288.78 seconds
Started Jul 17 07:51:20 PM PDT 24
Finished Jul 17 07:56:11 PM PDT 24
Peak memory 265628 kb
Host smart-e3ad3cf2-9484-4671-aa9f-d5e3ff2ed2a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245993473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3245993473
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2488041139
Short name T688
Test name
Test status
Simulation time 74710523928 ps
CPU time 27.17 seconds
Started Jul 17 07:51:22 PM PDT 24
Finished Jul 17 07:51:51 PM PDT 24
Peak memory 216296 kb
Host smart-547edf71-ea10-4e22-a0ea-f1ce7d1a6124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488041139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2488041139
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1960223901
Short name T950
Test name
Test status
Simulation time 461251019 ps
CPU time 3.41 seconds
Started Jul 17 07:51:19 PM PDT 24
Finished Jul 17 07:51:25 PM PDT 24
Peak memory 216256 kb
Host smart-75652d6b-57f9-43d9-bad2-3abf322691ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960223901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1960223901
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.4154020397
Short name T826
Test name
Test status
Simulation time 646606852 ps
CPU time 3.11 seconds
Started Jul 17 07:51:17 PM PDT 24
Finished Jul 17 07:51:20 PM PDT 24
Peak memory 216268 kb
Host smart-4d5a9bcc-c45c-42e6-a1f6-7cdef372e101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154020397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.4154020397
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3501653056
Short name T629
Test name
Test status
Simulation time 71205451 ps
CPU time 0.84 seconds
Started Jul 17 07:51:20 PM PDT 24
Finished Jul 17 07:51:24 PM PDT 24
Peak memory 205992 kb
Host smart-74b1fdc6-6863-4979-8d45-d90cb2066f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501653056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3501653056
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.678870061
Short name T951
Test name
Test status
Simulation time 15742133122 ps
CPU time 14.22 seconds
Started Jul 17 07:51:21 PM PDT 24
Finished Jul 17 07:51:38 PM PDT 24
Peak memory 224276 kb
Host smart-808e554c-2c45-4d7f-8b24-b389b63379b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678870061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.678870061
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.615957935
Short name T174
Test name
Test status
Simulation time 27343279 ps
CPU time 0.73 seconds
Started Jul 17 07:48:11 PM PDT 24
Finished Jul 17 07:48:15 PM PDT 24
Peak memory 205524 kb
Host smart-9b7ec9f6-c86a-404c-8102-44038c7f1251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615957935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.615957935
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1415222391
Short name T936
Test name
Test status
Simulation time 54926080 ps
CPU time 2.73 seconds
Started Jul 17 07:48:11 PM PDT 24
Finished Jul 17 07:48:17 PM PDT 24
Peak memory 232692 kb
Host smart-0bfd91ab-7f66-40bb-9f4d-317f1dca8b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415222391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1415222391
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.480101097
Short name T631
Test name
Test status
Simulation time 23141240 ps
CPU time 0.81 seconds
Started Jul 17 07:48:08 PM PDT 24
Finished Jul 17 07:48:09 PM PDT 24
Peak memory 206928 kb
Host smart-77093705-cfff-4f1d-b5ca-12acaf71bf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480101097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.480101097
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.87029207
Short name T451
Test name
Test status
Simulation time 15055642137 ps
CPU time 65.55 seconds
Started Jul 17 07:48:11 PM PDT 24
Finished Jul 17 07:49:20 PM PDT 24
Peak memory 264936 kb
Host smart-bfb86c69-f2af-4f9d-bde1-eafe9a6e3c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87029207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.87029207
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.526269855
Short name T213
Test name
Test status
Simulation time 21234785939 ps
CPU time 195.71 seconds
Started Jul 17 07:48:10 PM PDT 24
Finished Jul 17 07:51:29 PM PDT 24
Peak memory 257320 kb
Host smart-20191812-a64f-40de-b38e-0a019cccb13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526269855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.526269855
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3833792619
Short name T791
Test name
Test status
Simulation time 6415719257 ps
CPU time 125.88 seconds
Started Jul 17 07:48:10 PM PDT 24
Finished Jul 17 07:50:19 PM PDT 24
Peak memory 273732 kb
Host smart-0f677c0d-7502-4039-93f5-9ad118041fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833792619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3833792619
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.149572334
Short name T300
Test name
Test status
Simulation time 6637075884 ps
CPU time 31.52 seconds
Started Jul 17 07:48:12 PM PDT 24
Finished Jul 17 07:48:47 PM PDT 24
Peak memory 240844 kb
Host smart-aadcaef7-3ac2-4c1d-a431-ee3503d154ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149572334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.149572334
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.3086945144
Short name T228
Test name
Test status
Simulation time 45316988494 ps
CPU time 80.66 seconds
Started Jul 17 07:48:10 PM PDT 24
Finished Jul 17 07:49:33 PM PDT 24
Peak memory 249220 kb
Host smart-af034290-0110-434c-9654-11cbb44c61cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086945144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.3086945144
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3741839578
Short name T595
Test name
Test status
Simulation time 1541159453 ps
CPU time 8.46 seconds
Started Jul 17 07:48:11 PM PDT 24
Finished Jul 17 07:48:23 PM PDT 24
Peak memory 232724 kb
Host smart-ed0bd2a2-389d-4f9f-acae-466505175c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741839578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3741839578
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.4097445980
Short name T238
Test name
Test status
Simulation time 10132174290 ps
CPU time 15.19 seconds
Started Jul 17 07:48:12 PM PDT 24
Finished Jul 17 07:48:31 PM PDT 24
Peak memory 224652 kb
Host smart-d87e3aaa-3ba8-4860-b96c-ac54c03ae2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097445980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.4097445980
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.872129265
Short name T297
Test name
Test status
Simulation time 6025480759 ps
CPU time 6.57 seconds
Started Jul 17 07:48:12 PM PDT 24
Finished Jul 17 07:48:22 PM PDT 24
Peak memory 232832 kb
Host smart-16a4a745-f79f-4956-b9b0-9e78abe085a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872129265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
872129265
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1821505228
Short name T240
Test name
Test status
Simulation time 292683223 ps
CPU time 2.59 seconds
Started Jul 17 07:48:08 PM PDT 24
Finished Jul 17 07:48:12 PM PDT 24
Peak memory 224476 kb
Host smart-2733e25f-ed6a-4c73-9791-70b5555946f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821505228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1821505228
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1713863267
Short name T577
Test name
Test status
Simulation time 289527005 ps
CPU time 6.59 seconds
Started Jul 17 07:48:10 PM PDT 24
Finished Jul 17 07:48:19 PM PDT 24
Peak memory 221628 kb
Host smart-d7d3f7a0-5ee4-42ab-9059-8cc1534b7036
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1713863267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1713863267
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1937898883
Short name T76
Test name
Test status
Simulation time 245784762 ps
CPU time 1.37 seconds
Started Jul 17 07:48:13 PM PDT 24
Finished Jul 17 07:48:18 PM PDT 24
Peak memory 236572 kb
Host smart-abd8e384-47f0-49dd-b0f3-e3e8bf223ccf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937898883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1937898883
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.4294700599
Short name T956
Test name
Test status
Simulation time 327304741891 ps
CPU time 719.17 seconds
Started Jul 17 07:48:12 PM PDT 24
Finished Jul 17 08:00:15 PM PDT 24
Peak memory 270532 kb
Host smart-9d1c47d7-c058-41cc-b109-7056a2042a5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294700599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.4294700599
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3763961936
Short name T810
Test name
Test status
Simulation time 9274181216 ps
CPU time 19.71 seconds
Started Jul 17 07:48:09 PM PDT 24
Finished Jul 17 07:48:30 PM PDT 24
Peak memory 216336 kb
Host smart-239cdc98-dad5-48be-9fa6-fbaec7a4c36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763961936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3763961936
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.811275538
Short name T817
Test name
Test status
Simulation time 484104429 ps
CPU time 1.92 seconds
Started Jul 17 07:48:11 PM PDT 24
Finished Jul 17 07:48:17 PM PDT 24
Peak memory 216256 kb
Host smart-5a3bd41f-5e68-4ae4-8a0a-84d436609549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811275538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.811275538
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.218334950
Short name T806
Test name
Test status
Simulation time 145581423 ps
CPU time 2.38 seconds
Started Jul 17 07:48:10 PM PDT 24
Finished Jul 17 07:48:15 PM PDT 24
Peak memory 215104 kb
Host smart-f2e3c3fb-9c5f-4464-8a07-76742353640e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218334950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.218334950
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.780653524
Short name T360
Test name
Test status
Simulation time 104655406 ps
CPU time 0.93 seconds
Started Jul 17 07:48:10 PM PDT 24
Finished Jul 17 07:48:14 PM PDT 24
Peak memory 205960 kb
Host smart-f8147687-61a2-49bf-b4df-e55b70941b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780653524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.780653524
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.712693231
Short name T792
Test name
Test status
Simulation time 5908940500 ps
CPU time 7.15 seconds
Started Jul 17 07:48:11 PM PDT 24
Finished Jul 17 07:48:22 PM PDT 24
Peak memory 232832 kb
Host smart-5afd5782-b66b-4ea9-acba-19716711c5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712693231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.712693231
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1642972503
Short name T937
Test name
Test status
Simulation time 37679033 ps
CPU time 0.74 seconds
Started Jul 17 07:51:21 PM PDT 24
Finished Jul 17 07:51:25 PM PDT 24
Peak memory 204960 kb
Host smart-aa77ba55-66a9-40a8-827c-66f4f3f47199
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642972503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1642972503
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.416758313
Short name T347
Test name
Test status
Simulation time 343265283 ps
CPU time 5.58 seconds
Started Jul 17 07:51:20 PM PDT 24
Finished Jul 17 07:51:28 PM PDT 24
Peak memory 224508 kb
Host smart-3ad61404-99a6-4031-b969-a57db8431cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416758313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.416758313
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3368851446
Short name T844
Test name
Test status
Simulation time 14851844 ps
CPU time 0.8 seconds
Started Jul 17 07:51:22 PM PDT 24
Finished Jul 17 07:51:25 PM PDT 24
Peak memory 206928 kb
Host smart-e283b1b0-e509-433c-b8fe-4068c8f0a6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368851446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3368851446
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1625983116
Short name T277
Test name
Test status
Simulation time 138931695661 ps
CPU time 500.16 seconds
Started Jul 17 07:51:23 PM PDT 24
Finished Jul 17 07:59:45 PM PDT 24
Peak memory 252664 kb
Host smart-c540570d-91de-49e2-a731-348ce616ed5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625983116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1625983116
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.71393221
Short name T197
Test name
Test status
Simulation time 20037765282 ps
CPU time 146.66 seconds
Started Jul 17 07:51:27 PM PDT 24
Finished Jul 17 07:53:55 PM PDT 24
Peak memory 248872 kb
Host smart-330b8086-8346-4296-ba4d-42ca752788bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71393221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.71393221
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.530213612
Short name T40
Test name
Test status
Simulation time 39674404812 ps
CPU time 133.96 seconds
Started Jul 17 07:51:19 PM PDT 24
Finished Jul 17 07:53:36 PM PDT 24
Peak memory 254784 kb
Host smart-28429f01-733c-46c1-98ae-eb7deabd86eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530213612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.530213612
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2727713811
Short name T851
Test name
Test status
Simulation time 12181117120 ps
CPU time 49.11 seconds
Started Jul 17 07:51:23 PM PDT 24
Finished Jul 17 07:52:14 PM PDT 24
Peak memory 249192 kb
Host smart-498c3d21-3a0e-4d76-88fd-1ad0a11e9288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727713811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2727713811
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.2561744623
Short name T215
Test name
Test status
Simulation time 23973290898 ps
CPU time 162.43 seconds
Started Jul 17 07:51:23 PM PDT 24
Finished Jul 17 07:54:08 PM PDT 24
Peak memory 249264 kb
Host smart-bda9fd20-8e25-4961-98c7-cd1531bbbd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561744623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.2561744623
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.833449451
Short name T367
Test name
Test status
Simulation time 547406185 ps
CPU time 3.68 seconds
Started Jul 17 07:51:21 PM PDT 24
Finished Jul 17 07:51:27 PM PDT 24
Peak memory 224444 kb
Host smart-bbddf411-5bdf-495e-9071-d23cd0d40a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833449451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.833449451
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2139378741
Short name T340
Test name
Test status
Simulation time 52609832 ps
CPU time 2.65 seconds
Started Jul 17 07:51:22 PM PDT 24
Finished Jul 17 07:51:28 PM PDT 24
Peak memory 232852 kb
Host smart-5a2f5e9e-1891-4297-ac20-dc2029dd01c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139378741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2139378741
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3935894957
Short name T921
Test name
Test status
Simulation time 6534174049 ps
CPU time 16.06 seconds
Started Jul 17 07:51:22 PM PDT 24
Finished Jul 17 07:51:41 PM PDT 24
Peak memory 240976 kb
Host smart-556bf440-3a21-4550-9991-39906c7b0037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935894957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3935894957
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3988882532
Short name T255
Test name
Test status
Simulation time 900009237 ps
CPU time 4.26 seconds
Started Jul 17 07:51:23 PM PDT 24
Finished Jul 17 07:51:30 PM PDT 24
Peak memory 224508 kb
Host smart-207e14df-67d9-4a25-b030-9e9a2039c6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988882532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3988882532
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.894061554
Short name T498
Test name
Test status
Simulation time 2609392887 ps
CPU time 9.5 seconds
Started Jul 17 07:51:27 PM PDT 24
Finished Jul 17 07:51:37 PM PDT 24
Peak memory 222752 kb
Host smart-febaff76-3b40-47c6-8bcc-c7d5d32eb07c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=894061554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.894061554
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3296531287
Short name T443
Test name
Test status
Simulation time 173038732 ps
CPU time 1.07 seconds
Started Jul 17 07:51:21 PM PDT 24
Finished Jul 17 07:51:25 PM PDT 24
Peak memory 215332 kb
Host smart-aa02e022-3887-41aa-a2eb-c4071496c43b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296531287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3296531287
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.667437207
Short name T563
Test name
Test status
Simulation time 2032150791 ps
CPU time 20.02 seconds
Started Jul 17 07:51:22 PM PDT 24
Finished Jul 17 07:51:45 PM PDT 24
Peak memory 216284 kb
Host smart-2dcd4031-e4d1-4a7d-96a8-ef4beec4c749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667437207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.667437207
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3276506533
Short name T445
Test name
Test status
Simulation time 12868085 ps
CPU time 0.72 seconds
Started Jul 17 07:51:21 PM PDT 24
Finished Jul 17 07:51:25 PM PDT 24
Peak memory 205740 kb
Host smart-a5fdca38-5175-4d5d-adcc-99489153f809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276506533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3276506533
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2154452319
Short name T683
Test name
Test status
Simulation time 276893752 ps
CPU time 1.28 seconds
Started Jul 17 07:51:23 PM PDT 24
Finished Jul 17 07:51:27 PM PDT 24
Peak memory 216280 kb
Host smart-23ec2f49-eadb-490d-acb6-62fd75651366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154452319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2154452319
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3348108828
Short name T503
Test name
Test status
Simulation time 147609731 ps
CPU time 0.97 seconds
Started Jul 17 07:51:24 PM PDT 24
Finished Jul 17 07:51:27 PM PDT 24
Peak memory 207016 kb
Host smart-f713c7e1-71d6-4cfa-ad6b-ae7bb54220e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348108828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3348108828
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.628412743
Short name T158
Test name
Test status
Simulation time 3889518297 ps
CPU time 12.01 seconds
Started Jul 17 07:51:22 PM PDT 24
Finished Jul 17 07:51:37 PM PDT 24
Peak memory 233000 kb
Host smart-4352be23-918d-497d-a6fc-c781f1c6c353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628412743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.628412743
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.4046976284
Short name T407
Test name
Test status
Simulation time 53417936 ps
CPU time 0.68 seconds
Started Jul 17 07:51:44 PM PDT 24
Finished Jul 17 07:51:48 PM PDT 24
Peak memory 204980 kb
Host smart-252ecdfe-4a10-4638-833a-1bbe23c24ce2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046976284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
4046976284
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.905403973
Short name T99
Test name
Test status
Simulation time 127933065 ps
CPU time 2.56 seconds
Started Jul 17 07:51:43 PM PDT 24
Finished Jul 17 07:51:49 PM PDT 24
Peak memory 232712 kb
Host smart-5a77511c-8704-4575-b303-9250e759581f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905403973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.905403973
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3371852811
Short name T329
Test name
Test status
Simulation time 84985170 ps
CPU time 0.79 seconds
Started Jul 17 07:51:27 PM PDT 24
Finished Jul 17 07:51:29 PM PDT 24
Peak memory 205152 kb
Host smart-64883bb4-a13f-4660-9920-1513106d9dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371852811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3371852811
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3385774521
Short name T87
Test name
Test status
Simulation time 4829704353 ps
CPU time 51.22 seconds
Started Jul 17 07:51:42 PM PDT 24
Finished Jul 17 07:52:34 PM PDT 24
Peak memory 253888 kb
Host smart-a225d5f4-4e74-4027-a407-b8543a79fb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385774521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3385774521
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3790702424
Short name T583
Test name
Test status
Simulation time 8610529198 ps
CPU time 57.86 seconds
Started Jul 17 07:51:41 PM PDT 24
Finished Jul 17 07:52:40 PM PDT 24
Peak memory 249332 kb
Host smart-15e583d7-3528-4eb3-ae73-6cdda4e78d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790702424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3790702424
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.726796126
Short name T285
Test name
Test status
Simulation time 5160325593 ps
CPU time 117.35 seconds
Started Jul 17 07:51:46 PM PDT 24
Finished Jul 17 07:53:48 PM PDT 24
Peak memory 265644 kb
Host smart-2424d60f-f5fe-4753-bbed-549ace7f9c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726796126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.726796126
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.982480964
Short name T263
Test name
Test status
Simulation time 77903548007 ps
CPU time 184.01 seconds
Started Jul 17 07:51:40 PM PDT 24
Finished Jul 17 07:54:45 PM PDT 24
Peak memory 252764 kb
Host smart-e79bd4e1-2580-4187-94e0-bddbbde5c017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982480964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds
.982480964
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.84277236
Short name T828
Test name
Test status
Simulation time 1183106411 ps
CPU time 6.29 seconds
Started Jul 17 07:51:40 PM PDT 24
Finished Jul 17 07:51:48 PM PDT 24
Peak memory 232648 kb
Host smart-073c02fe-8755-461c-90df-b91b627b4abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84277236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.84277236
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2537640428
Short name T548
Test name
Test status
Simulation time 146800276 ps
CPU time 3.2 seconds
Started Jul 17 07:51:43 PM PDT 24
Finished Jul 17 07:51:48 PM PDT 24
Peak memory 232708 kb
Host smart-a2c736cf-b573-4b01-9128-9df9a8d9824a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537640428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2537640428
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3809799497
Short name T960
Test name
Test status
Simulation time 1606261825 ps
CPU time 3.61 seconds
Started Jul 17 07:51:42 PM PDT 24
Finished Jul 17 07:51:47 PM PDT 24
Peak memory 224440 kb
Host smart-d434fae9-e241-488e-a047-3d4e4698f020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809799497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3809799497
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2718551416
Short name T872
Test name
Test status
Simulation time 8953980961 ps
CPU time 9.71 seconds
Started Jul 17 07:51:41 PM PDT 24
Finished Jul 17 07:51:52 PM PDT 24
Peak memory 232800 kb
Host smart-7f495cc0-aa12-4b60-aca4-1299a7ded938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718551416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2718551416
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1322101696
Short name T572
Test name
Test status
Simulation time 3329628128 ps
CPU time 11.98 seconds
Started Jul 17 07:51:41 PM PDT 24
Finished Jul 17 07:51:54 PM PDT 24
Peak memory 219432 kb
Host smart-17724d0c-8caa-43a1-8534-7501058a3221
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1322101696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1322101696
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1665458231
Short name T602
Test name
Test status
Simulation time 1892915391 ps
CPU time 5.67 seconds
Started Jul 17 07:51:42 PM PDT 24
Finished Jul 17 07:51:49 PM PDT 24
Peak memory 216316 kb
Host smart-1d8dbc4d-42ba-4295-9ad1-50b8a669c812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665458231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1665458231
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3380107100
Short name T24
Test name
Test status
Simulation time 7728023736 ps
CPU time 7.84 seconds
Started Jul 17 07:51:26 PM PDT 24
Finished Jul 17 07:51:35 PM PDT 24
Peak memory 216376 kb
Host smart-69c268e3-0195-44cd-8856-5c636bc94725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380107100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3380107100
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.117225430
Short name T22
Test name
Test status
Simulation time 841078460 ps
CPU time 2.87 seconds
Started Jul 17 07:51:47 PM PDT 24
Finished Jul 17 07:51:55 PM PDT 24
Peak memory 216252 kb
Host smart-93493504-d702-4821-958b-c345f48d5d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117225430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.117225430
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3220603332
Short name T877
Test name
Test status
Simulation time 72396968 ps
CPU time 0.9 seconds
Started Jul 17 07:51:42 PM PDT 24
Finished Jul 17 07:51:45 PM PDT 24
Peak memory 205984 kb
Host smart-3712ee8a-2784-4657-9661-da1728d88645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220603332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3220603332
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2242027934
Short name T251
Test name
Test status
Simulation time 15500361254 ps
CPU time 24.8 seconds
Started Jul 17 07:51:43 PM PDT 24
Finished Jul 17 07:52:11 PM PDT 24
Peak memory 232776 kb
Host smart-d13fb953-ecc0-4095-a55c-614e8400de77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242027934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2242027934
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1233816820
Short name T773
Test name
Test status
Simulation time 18150564 ps
CPU time 0.72 seconds
Started Jul 17 07:51:46 PM PDT 24
Finished Jul 17 07:51:51 PM PDT 24
Peak memory 205528 kb
Host smart-43d914e4-0cf9-43ef-a19b-9fcc9af35d31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233816820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1233816820
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3914060046
Short name T194
Test name
Test status
Simulation time 360751700 ps
CPU time 2.49 seconds
Started Jul 17 07:51:44 PM PDT 24
Finished Jul 17 07:51:49 PM PDT 24
Peak memory 224432 kb
Host smart-47323262-1a49-4283-9b27-9a9a08a8d012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914060046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3914060046
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.349970828
Short name T521
Test name
Test status
Simulation time 29951030 ps
CPU time 0.83 seconds
Started Jul 17 07:51:44 PM PDT 24
Finished Jul 17 07:51:48 PM PDT 24
Peak memory 206616 kb
Host smart-bca86640-62b2-420d-8e2e-a6df15bd8e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349970828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.349970828
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3998979815
Short name T657
Test name
Test status
Simulation time 6760954023 ps
CPU time 44.37 seconds
Started Jul 17 07:51:43 PM PDT 24
Finished Jul 17 07:52:31 PM PDT 24
Peak memory 249212 kb
Host smart-b4281691-304b-40cd-b33a-dc66e2addd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998979815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3998979815
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.785758549
Short name T967
Test name
Test status
Simulation time 2216441632 ps
CPU time 6.14 seconds
Started Jul 17 07:51:43 PM PDT 24
Finished Jul 17 07:51:53 PM PDT 24
Peak memory 217492 kb
Host smart-0a325fad-bb86-4c1f-9dea-b700cd8aef14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785758549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.785758549
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.496731306
Short name T58
Test name
Test status
Simulation time 13836509632 ps
CPU time 114.1 seconds
Started Jul 17 07:51:47 PM PDT 24
Finished Jul 17 07:53:46 PM PDT 24
Peak memory 236892 kb
Host smart-85feb2e9-42cf-43be-896a-a17b968fac5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496731306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.496731306
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1774180897
Short name T561
Test name
Test status
Simulation time 298959814 ps
CPU time 6.08 seconds
Started Jul 17 07:51:46 PM PDT 24
Finished Jul 17 07:51:57 PM PDT 24
Peak memory 224476 kb
Host smart-674e54ce-aba8-4cf6-a6eb-9481ee34610c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774180897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1774180897
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.1062075329
Short name T752
Test name
Test status
Simulation time 8936155573 ps
CPU time 34.76 seconds
Started Jul 17 07:51:47 PM PDT 24
Finished Jul 17 07:52:27 PM PDT 24
Peak memory 241012 kb
Host smart-87490c3f-8043-4f03-b0e8-b6dfbde6a5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062075329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.1062075329
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.155827376
Short name T156
Test name
Test status
Simulation time 21159408008 ps
CPU time 23.57 seconds
Started Jul 17 07:51:47 PM PDT 24
Finished Jul 17 07:52:16 PM PDT 24
Peak memory 232760 kb
Host smart-82b3a81a-c35f-4a00-8bf0-a9ac8f78ae65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155827376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.155827376
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.604092534
Short name T934
Test name
Test status
Simulation time 2915508074 ps
CPU time 12.37 seconds
Started Jul 17 07:51:44 PM PDT 24
Finished Jul 17 07:52:01 PM PDT 24
Peak memory 232776 kb
Host smart-e9262362-6e4d-4f68-9e5d-a49812f3007d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604092534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.604092534
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2329422427
Short name T383
Test name
Test status
Simulation time 562154915 ps
CPU time 3.25 seconds
Started Jul 17 07:51:46 PM PDT 24
Finished Jul 17 07:51:54 PM PDT 24
Peak memory 224488 kb
Host smart-84b50b25-7722-4e6d-9d17-debee64400bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329422427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2329422427
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1655162937
Short name T422
Test name
Test status
Simulation time 3620056046 ps
CPU time 12.77 seconds
Started Jul 17 07:51:43 PM PDT 24
Finished Jul 17 07:51:58 PM PDT 24
Peak memory 232792 kb
Host smart-608e2254-de51-4bd8-9486-3c454f535188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655162937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1655162937
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3028284656
Short name T628
Test name
Test status
Simulation time 2593089637 ps
CPU time 11.34 seconds
Started Jul 17 07:51:45 PM PDT 24
Finished Jul 17 07:52:02 PM PDT 24
Peak memory 223404 kb
Host smart-1f962ed1-e2d4-439b-baaa-b78dcfab27cd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3028284656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3028284656
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2071039561
Short name T29
Test name
Test status
Simulation time 1846318356 ps
CPU time 5.31 seconds
Started Jul 17 07:51:45 PM PDT 24
Finished Jul 17 07:51:56 PM PDT 24
Peak memory 216264 kb
Host smart-7e1373e1-4c93-4f7c-881c-7e4466c40b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071039561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2071039561
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2247738454
Short name T941
Test name
Test status
Simulation time 35541943752 ps
CPU time 15.71 seconds
Started Jul 17 07:51:41 PM PDT 24
Finished Jul 17 07:51:57 PM PDT 24
Peak memory 216304 kb
Host smart-9d4f2c97-7675-4b28-bbb2-c90756f5bea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247738454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2247738454
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3254871007
Short name T589
Test name
Test status
Simulation time 193055902 ps
CPU time 1.38 seconds
Started Jul 17 07:51:42 PM PDT 24
Finished Jul 17 07:51:44 PM PDT 24
Peak memory 216272 kb
Host smart-a87c0c0f-92b9-4b6a-acb4-df7d5df55cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254871007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3254871007
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2789642150
Short name T959
Test name
Test status
Simulation time 474270565 ps
CPU time 0.86 seconds
Started Jul 17 07:51:47 PM PDT 24
Finished Jul 17 07:51:53 PM PDT 24
Peak memory 205960 kb
Host smart-49781a08-bde9-414a-bca3-c1494b8d786c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789642150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2789642150
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1159253326
Short name T459
Test name
Test status
Simulation time 10723126007 ps
CPU time 36.06 seconds
Started Jul 17 07:51:44 PM PDT 24
Finished Jul 17 07:52:25 PM PDT 24
Peak memory 238824 kb
Host smart-dd8926ec-be21-402b-9cb8-2a269eb39b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159253326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1159253326
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3932831959
Short name T886
Test name
Test status
Simulation time 26813884 ps
CPU time 0.73 seconds
Started Jul 17 07:51:50 PM PDT 24
Finished Jul 17 07:51:54 PM PDT 24
Peak memory 205524 kb
Host smart-ba9fea45-79e5-4c6b-8bc4-329c67e3127f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932831959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3932831959
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2489634144
Short name T630
Test name
Test status
Simulation time 279742514 ps
CPU time 3.37 seconds
Started Jul 17 07:51:50 PM PDT 24
Finished Jul 17 07:51:57 PM PDT 24
Peak memory 232672 kb
Host smart-5f331946-1b24-4fcc-b60b-4f353ad19804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489634144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2489634144
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3048283039
Short name T642
Test name
Test status
Simulation time 16464232 ps
CPU time 0.82 seconds
Started Jul 17 07:51:46 PM PDT 24
Finished Jul 17 07:51:52 PM PDT 24
Peak memory 206620 kb
Host smart-e4404cc7-5baf-42d3-a223-36aac8369b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048283039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3048283039
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2908852986
Short name T568
Test name
Test status
Simulation time 37462194689 ps
CPU time 137.64 seconds
Started Jul 17 07:51:47 PM PDT 24
Finished Jul 17 07:54:10 PM PDT 24
Peak memory 255688 kb
Host smart-2bbde874-7559-40d6-ab1e-10a8b06bf863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908852986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2908852986
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1638557651
Short name T596
Test name
Test status
Simulation time 15843058408 ps
CPU time 144.03 seconds
Started Jul 17 07:51:49 PM PDT 24
Finished Jul 17 07:54:17 PM PDT 24
Peak memory 249264 kb
Host smart-9c4b45ca-5dbc-4d5f-8669-9daaec1d319e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638557651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1638557651
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.260625277
Short name T209
Test name
Test status
Simulation time 1800899006 ps
CPU time 38.61 seconds
Started Jul 17 07:51:49 PM PDT 24
Finished Jul 17 07:52:32 PM PDT 24
Peak memory 249160 kb
Host smart-0fe5cbd7-e57e-4b90-b352-9fbe42d6fe79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260625277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle
.260625277
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.4054901376
Short name T913
Test name
Test status
Simulation time 29361305768 ps
CPU time 24.4 seconds
Started Jul 17 07:51:53 PM PDT 24
Finished Jul 17 07:52:21 PM PDT 24
Peak memory 240672 kb
Host smart-54bc808a-dbf4-4295-89d2-7a07f72bd3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054901376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.4054901376
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.4241436988
Short name T718
Test name
Test status
Simulation time 89916827749 ps
CPU time 93.72 seconds
Started Jul 17 07:51:53 PM PDT 24
Finished Jul 17 07:53:29 PM PDT 24
Peak memory 255596 kb
Host smart-1e853c84-3409-4d34-8a59-b95ade00153e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241436988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.4241436988
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1818596666
Short name T929
Test name
Test status
Simulation time 29298882607 ps
CPU time 26.11 seconds
Started Jul 17 07:51:53 PM PDT 24
Finished Jul 17 07:52:22 PM PDT 24
Peak memory 224568 kb
Host smart-49716ac5-bebe-4455-b504-20d574993acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818596666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1818596666
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1133648977
Short name T803
Test name
Test status
Simulation time 52955008 ps
CPU time 2.09 seconds
Started Jul 17 07:51:48 PM PDT 24
Finished Jul 17 07:51:55 PM PDT 24
Peak memory 222632 kb
Host smart-8b8388d4-dc17-4dc9-967b-5591b9d4e614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133648977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1133648977
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2253458987
Short name T519
Test name
Test status
Simulation time 1157399042 ps
CPU time 3.05 seconds
Started Jul 17 07:51:45 PM PDT 24
Finished Jul 17 07:51:52 PM PDT 24
Peak memory 224488 kb
Host smart-94eb73f1-bd1f-4f82-b6d1-207d5252181b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253458987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2253458987
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.161560140
Short name T648
Test name
Test status
Simulation time 1526632354 ps
CPU time 5.41 seconds
Started Jul 17 07:51:51 PM PDT 24
Finished Jul 17 07:52:00 PM PDT 24
Peak memory 232672 kb
Host smart-490a0490-f4c2-414c-8581-15add2acd720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161560140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.161560140
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1052690703
Short name T475
Test name
Test status
Simulation time 2899923701 ps
CPU time 5.63 seconds
Started Jul 17 07:51:50 PM PDT 24
Finished Jul 17 07:52:00 PM PDT 24
Peak memory 223304 kb
Host smart-bdf72319-05d9-49a5-b765-e418b422393b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1052690703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1052690703
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.294796411
Short name T296
Test name
Test status
Simulation time 409869677441 ps
CPU time 426.15 seconds
Started Jul 17 07:51:47 PM PDT 24
Finished Jul 17 07:58:58 PM PDT 24
Peak memory 273364 kb
Host smart-1008ca51-4ca9-419f-a0c7-a32c92ec2f8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294796411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.294796411
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2088823020
Short name T314
Test name
Test status
Simulation time 19502296678 ps
CPU time 13.85 seconds
Started Jul 17 07:51:46 PM PDT 24
Finished Jul 17 07:52:05 PM PDT 24
Peak memory 219748 kb
Host smart-4581afa8-02f0-458f-983f-3b2ddfe653cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088823020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2088823020
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2083299671
Short name T770
Test name
Test status
Simulation time 24374181337 ps
CPU time 20.05 seconds
Started Jul 17 07:51:49 PM PDT 24
Finished Jul 17 07:52:13 PM PDT 24
Peak memory 217312 kb
Host smart-3b876ce8-f386-4605-854d-6ef81f9573c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083299671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2083299671
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2515633644
Short name T379
Test name
Test status
Simulation time 168637722 ps
CPU time 2.39 seconds
Started Jul 17 07:51:49 PM PDT 24
Finished Jul 17 07:51:56 PM PDT 24
Peak memory 215764 kb
Host smart-c6bdc563-68bf-48a8-bf4d-76b818921d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515633644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2515633644
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.611739114
Short name T656
Test name
Test status
Simulation time 349460179 ps
CPU time 0.94 seconds
Started Jul 17 07:51:49 PM PDT 24
Finished Jul 17 07:51:54 PM PDT 24
Peak memory 205512 kb
Host smart-0ed196aa-8d9b-48c3-acfc-b38a655be51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611739114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.611739114
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1027509786
Short name T247
Test name
Test status
Simulation time 10936930708 ps
CPU time 10.73 seconds
Started Jul 17 07:51:48 PM PDT 24
Finished Jul 17 07:52:03 PM PDT 24
Peak memory 224600 kb
Host smart-b2ffbc07-aa52-4ef5-8b10-53ca3f5219e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027509786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1027509786
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2414482270
Short name T945
Test name
Test status
Simulation time 12856752 ps
CPU time 0.71 seconds
Started Jul 17 07:51:45 PM PDT 24
Finished Jul 17 07:51:50 PM PDT 24
Peak memory 205568 kb
Host smart-b6240b28-33d2-4049-8151-d185ee1247d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414482270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2414482270
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.47815524
Short name T565
Test name
Test status
Simulation time 1512412341 ps
CPU time 3.82 seconds
Started Jul 17 07:51:44 PM PDT 24
Finished Jul 17 07:51:52 PM PDT 24
Peak memory 232672 kb
Host smart-1e1a3f08-3e8d-4cf6-b69b-fd5f358c0224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47815524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.47815524
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3429989151
Short name T979
Test name
Test status
Simulation time 43158781 ps
CPU time 0.83 seconds
Started Jul 17 07:51:46 PM PDT 24
Finished Jul 17 07:51:51 PM PDT 24
Peak memory 206604 kb
Host smart-b64ea96e-1991-4c0a-960d-7090ce8dd10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429989151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3429989151
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.4180728025
Short name T63
Test name
Test status
Simulation time 8006856918 ps
CPU time 70.93 seconds
Started Jul 17 07:51:43 PM PDT 24
Finished Jul 17 07:52:56 PM PDT 24
Peak memory 249204 kb
Host smart-71e9abd6-8f94-42a9-ae1a-4b39896fae61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180728025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.4180728025
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.4163083622
Short name T647
Test name
Test status
Simulation time 137385654144 ps
CPU time 116.24 seconds
Started Jul 17 07:51:47 PM PDT 24
Finished Jul 17 07:53:47 PM PDT 24
Peak memory 249268 kb
Host smart-4ac4c98c-0844-4691-b4a3-c3c6b6c8a346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163083622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.4163083622
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3173229121
Short name T37
Test name
Test status
Simulation time 282550211 ps
CPU time 6.21 seconds
Started Jul 17 07:51:43 PM PDT 24
Finished Jul 17 07:51:53 PM PDT 24
Peak memory 224432 kb
Host smart-6dc2b299-bd16-422f-a462-2920fcee16c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173229121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3173229121
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.1091627831
Short name T687
Test name
Test status
Simulation time 110920072 ps
CPU time 0.78 seconds
Started Jul 17 07:51:46 PM PDT 24
Finished Jul 17 07:51:51 PM PDT 24
Peak memory 215776 kb
Host smart-e0c06b69-470c-469d-b282-4212efe34436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091627831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.1091627831
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.312193609
Short name T637
Test name
Test status
Simulation time 5066735588 ps
CPU time 25.69 seconds
Started Jul 17 07:51:44 PM PDT 24
Finished Jul 17 07:52:13 PM PDT 24
Peak memory 224624 kb
Host smart-d3edb3a1-bdef-4b05-991a-2566e2f3367c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312193609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.312193609
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.4210063622
Short name T705
Test name
Test status
Simulation time 5662961517 ps
CPU time 44.52 seconds
Started Jul 17 07:51:50 PM PDT 24
Finished Jul 17 07:52:38 PM PDT 24
Peak memory 238704 kb
Host smart-6152db4c-49f9-4923-863f-720387a2238e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210063622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.4210063622
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.780667662
Short name T280
Test name
Test status
Simulation time 3536500051 ps
CPU time 7.25 seconds
Started Jul 17 07:51:53 PM PDT 24
Finished Jul 17 07:52:03 PM PDT 24
Peak memory 232676 kb
Host smart-4d7087ec-3c14-46c7-87cf-e62251e809a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780667662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.780667662
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2419842445
Short name T651
Test name
Test status
Simulation time 1304062688 ps
CPU time 6.81 seconds
Started Jul 17 07:51:56 PM PDT 24
Finished Jul 17 07:52:05 PM PDT 24
Peak memory 232672 kb
Host smart-23843838-f5cf-41bf-aab0-df9836544047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419842445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2419842445
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.563618717
Short name T462
Test name
Test status
Simulation time 1949207424 ps
CPU time 10.54 seconds
Started Jul 17 07:51:43 PM PDT 24
Finished Jul 17 07:51:57 PM PDT 24
Peak memory 222928 kb
Host smart-ac9a322e-7410-48e4-b904-46b43d823817
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=563618717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.563618717
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1889615403
Short name T149
Test name
Test status
Simulation time 52802767645 ps
CPU time 404.04 seconds
Started Jul 17 07:51:43 PM PDT 24
Finished Jul 17 07:58:29 PM PDT 24
Peak memory 265716 kb
Host smart-775db0f3-f01c-45d7-91a2-759beee0ef9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889615403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1889615403
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.419662830
Short name T858
Test name
Test status
Simulation time 10379534994 ps
CPU time 19.8 seconds
Started Jul 17 07:51:56 PM PDT 24
Finished Jul 17 07:52:18 PM PDT 24
Peak memory 216384 kb
Host smart-0faf5c58-3649-4cd8-804f-c4bbb7a70c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419662830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.419662830
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1659467772
Short name T402
Test name
Test status
Simulation time 3030780427 ps
CPU time 9.2 seconds
Started Jul 17 07:51:56 PM PDT 24
Finished Jul 17 07:52:07 PM PDT 24
Peak memory 216304 kb
Host smart-86cac2d9-9799-41ba-b5cf-cc3655867f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659467772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1659467772
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1855633534
Short name T529
Test name
Test status
Simulation time 229527918 ps
CPU time 1.43 seconds
Started Jul 17 07:51:53 PM PDT 24
Finished Jul 17 07:51:57 PM PDT 24
Peak memory 216220 kb
Host smart-45a1b61c-e4d7-43d9-8df0-183be0535871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855633534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1855633534
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1245243463
Short name T932
Test name
Test status
Simulation time 110955010 ps
CPU time 0.92 seconds
Started Jul 17 07:51:56 PM PDT 24
Finished Jul 17 07:51:59 PM PDT 24
Peak memory 207004 kb
Host smart-abe54dd3-c099-47ef-a6f7-40db1171c696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245243463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1245243463
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1967707980
Short name T354
Test name
Test status
Simulation time 2896970333 ps
CPU time 6.78 seconds
Started Jul 17 07:51:43 PM PDT 24
Finished Jul 17 07:51:53 PM PDT 24
Peak memory 239596 kb
Host smart-cdfb22e3-7471-4f90-84a0-9495f60865d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967707980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1967707980
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3718388368
Short name T719
Test name
Test status
Simulation time 12814226 ps
CPU time 0.72 seconds
Started Jul 17 07:51:48 PM PDT 24
Finished Jul 17 07:51:54 PM PDT 24
Peak memory 205468 kb
Host smart-af4e8e5c-4fd9-40bb-9365-d97c58b30285
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718388368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3718388368
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.745266233
Short name T385
Test name
Test status
Simulation time 1002985376 ps
CPU time 3.04 seconds
Started Jul 17 07:51:46 PM PDT 24
Finished Jul 17 07:51:54 PM PDT 24
Peak memory 232648 kb
Host smart-ff394695-d402-440d-a4fb-4c3e0f9f78c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745266233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.745266233
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3949414683
Short name T543
Test name
Test status
Simulation time 15461149 ps
CPU time 0.77 seconds
Started Jul 17 07:51:45 PM PDT 24
Finished Jul 17 07:51:51 PM PDT 24
Peak memory 205572 kb
Host smart-545e5f70-10cb-42dd-ac11-b44f81af9ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949414683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3949414683
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.4265232139
Short name T785
Test name
Test status
Simulation time 3174954644 ps
CPU time 23.64 seconds
Started Jul 17 07:51:48 PM PDT 24
Finished Jul 17 07:52:17 PM PDT 24
Peak memory 238060 kb
Host smart-35ab472e-6e8a-451c-88af-c989c8e7582e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265232139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.4265232139
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2213227982
Short name T234
Test name
Test status
Simulation time 33847571603 ps
CPU time 61.73 seconds
Started Jul 17 07:51:47 PM PDT 24
Finished Jul 17 07:52:54 PM PDT 24
Peak memory 265568 kb
Host smart-543907d0-a997-49c4-9191-f4a7a457d107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213227982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2213227982
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.49297618
Short name T750
Test name
Test status
Simulation time 98571275587 ps
CPU time 202.74 seconds
Started Jul 17 07:51:47 PM PDT 24
Finished Jul 17 07:55:15 PM PDT 24
Peak memory 251084 kb
Host smart-9c9d7a7b-93bd-49a6-a724-ee6ff5c121a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49297618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle.49297618
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3027634031
Short name T971
Test name
Test status
Simulation time 933164400 ps
CPU time 21.58 seconds
Started Jul 17 07:51:47 PM PDT 24
Finished Jul 17 07:52:14 PM PDT 24
Peak memory 235740 kb
Host smart-04dffb60-0149-47de-8669-2363e3dac89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027634031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3027634031
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.4233388082
Short name T992
Test name
Test status
Simulation time 4655977610 ps
CPU time 43.07 seconds
Started Jul 17 07:51:47 PM PDT 24
Finished Jul 17 07:52:35 PM PDT 24
Peak memory 248920 kb
Host smart-8a673285-9e00-4403-a440-aae24a04de09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233388082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.4233388082
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.4024656740
Short name T627
Test name
Test status
Simulation time 16531911517 ps
CPU time 38.89 seconds
Started Jul 17 07:51:43 PM PDT 24
Finished Jul 17 07:52:25 PM PDT 24
Peak memory 224552 kb
Host smart-bfe35d35-6637-4135-9469-e98e1a6a0b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024656740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.4024656740
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1951359928
Short name T805
Test name
Test status
Simulation time 2847409417 ps
CPU time 20.09 seconds
Started Jul 17 07:51:43 PM PDT 24
Finished Jul 17 07:52:07 PM PDT 24
Peak memory 232704 kb
Host smart-2cf9e596-7fd8-413f-8cf2-1ee69ff7710c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951359928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1951359928
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1804895502
Short name T766
Test name
Test status
Simulation time 2446756841 ps
CPU time 4.68 seconds
Started Jul 17 07:51:44 PM PDT 24
Finished Jul 17 07:51:54 PM PDT 24
Peak memory 232824 kb
Host smart-cc49e97f-e3a6-4f52-8091-fa2a0df3f169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804895502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1804895502
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2931173285
Short name T333
Test name
Test status
Simulation time 16431226216 ps
CPU time 14.64 seconds
Started Jul 17 07:51:44 PM PDT 24
Finished Jul 17 07:52:02 PM PDT 24
Peak memory 232784 kb
Host smart-b180e750-e250-4478-96be-c0236916eb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931173285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2931173285
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2268199502
Short name T715
Test name
Test status
Simulation time 434515191 ps
CPU time 5.1 seconds
Started Jul 17 07:51:45 PM PDT 24
Finished Jul 17 07:51:54 PM PDT 24
Peak memory 220172 kb
Host smart-540d219c-b73e-4b24-8a54-9a9467dececd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2268199502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2268199502
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2080479822
Short name T170
Test name
Test status
Simulation time 14139907950 ps
CPU time 134.68 seconds
Started Jul 17 07:51:45 PM PDT 24
Finished Jul 17 07:54:04 PM PDT 24
Peak memory 250292 kb
Host smart-dc62d04f-7f7d-490b-83fe-7a36bd9af8b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080479822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2080479822
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3828379452
Short name T756
Test name
Test status
Simulation time 6145883075 ps
CPU time 36.05 seconds
Started Jul 17 07:51:47 PM PDT 24
Finished Jul 17 07:52:28 PM PDT 24
Peak memory 216264 kb
Host smart-501817f2-1a6a-41e6-9f73-8e442f44cde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828379452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3828379452
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2747449778
Short name T620
Test name
Test status
Simulation time 2321994905 ps
CPU time 3.57 seconds
Started Jul 17 07:51:46 PM PDT 24
Finished Jul 17 07:51:54 PM PDT 24
Peak memory 208024 kb
Host smart-d729a773-f019-4246-961d-641598d1d604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747449778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2747449778
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3964778438
Short name T155
Test name
Test status
Simulation time 217949376 ps
CPU time 1.4 seconds
Started Jul 17 07:51:44 PM PDT 24
Finished Jul 17 07:51:49 PM PDT 24
Peak memory 216220 kb
Host smart-a3ef1db0-f5a4-4fc8-9666-78b31431ccfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964778438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3964778438
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2701281708
Short name T394
Test name
Test status
Simulation time 82384395 ps
CPU time 0.91 seconds
Started Jul 17 07:51:47 PM PDT 24
Finished Jul 17 07:51:52 PM PDT 24
Peak memory 206520 kb
Host smart-27caed55-6610-43aa-b002-6e7384b38494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701281708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2701281708
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1753943250
Short name T140
Test name
Test status
Simulation time 3275146805 ps
CPU time 4.8 seconds
Started Jul 17 07:51:47 PM PDT 24
Finished Jul 17 07:51:56 PM PDT 24
Peak memory 232836 kb
Host smart-f442a2af-f646-4438-bf9c-3aa4a2745058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753943250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1753943250
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2834264281
Short name T138
Test name
Test status
Simulation time 149268206 ps
CPU time 0.79 seconds
Started Jul 17 07:52:08 PM PDT 24
Finished Jul 17 07:52:11 PM PDT 24
Peak memory 204984 kb
Host smart-66a1ac18-8133-48f2-bf29-8d37fb1c2ee2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834264281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2834264281
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.192840633
Short name T984
Test name
Test status
Simulation time 1752052689 ps
CPU time 3.49 seconds
Started Jul 17 07:51:56 PM PDT 24
Finished Jul 17 07:52:01 PM PDT 24
Peak memory 224320 kb
Host smart-4be7a2d6-53ad-4999-9533-960207ef82d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192840633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.192840633
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.818091039
Short name T552
Test name
Test status
Simulation time 19000722 ps
CPU time 0.74 seconds
Started Jul 17 07:51:48 PM PDT 24
Finished Jul 17 07:51:53 PM PDT 24
Peak memory 205508 kb
Host smart-914988ff-bac4-4ee0-9ab1-c567c70f64bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818091039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.818091039
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3008559834
Short name T176
Test name
Test status
Simulation time 38369922 ps
CPU time 0.75 seconds
Started Jul 17 07:51:46 PM PDT 24
Finished Jul 17 07:51:51 PM PDT 24
Peak memory 215792 kb
Host smart-a5a431a8-008f-4e6a-bbea-9a65fe7a279d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008559834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3008559834
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3721805277
Short name T56
Test name
Test status
Simulation time 21382654420 ps
CPU time 66.91 seconds
Started Jul 17 07:51:53 PM PDT 24
Finished Jul 17 07:53:03 PM PDT 24
Peak memory 257412 kb
Host smart-434ab736-c470-4b8f-a20c-5f42dc1ab081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721805277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3721805277
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3495958996
Short name T987
Test name
Test status
Simulation time 9934804545 ps
CPU time 69.51 seconds
Started Jul 17 07:51:53 PM PDT 24
Finished Jul 17 07:53:05 PM PDT 24
Peak memory 250928 kb
Host smart-61d66cde-d9d3-4e50-bc5c-3703c854d2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495958996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3495958996
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2239313579
Short name T408
Test name
Test status
Simulation time 209456939 ps
CPU time 3.02 seconds
Started Jul 17 07:51:56 PM PDT 24
Finished Jul 17 07:52:01 PM PDT 24
Peak memory 224336 kb
Host smart-b1651ad7-dca9-40c1-b429-4bd2a9e986f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239313579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2239313579
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.3488191247
Short name T288
Test name
Test status
Simulation time 62497663072 ps
CPU time 118.77 seconds
Started Jul 17 07:51:49 PM PDT 24
Finished Jul 17 07:53:52 PM PDT 24
Peak memory 241016 kb
Host smart-4ac85a9e-bb7f-4bd3-8dbe-d73c5905e0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488191247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.3488191247
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.4224582921
Short name T208
Test name
Test status
Simulation time 2752385557 ps
CPU time 12.7 seconds
Started Jul 17 07:51:53 PM PDT 24
Finished Jul 17 07:52:08 PM PDT 24
Peak memory 232828 kb
Host smart-7272bf0e-adde-4ac1-8ecb-fc98cf9907c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224582921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.4224582921
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3206346020
Short name T894
Test name
Test status
Simulation time 4073221546 ps
CPU time 10.84 seconds
Started Jul 17 07:51:47 PM PDT 24
Finished Jul 17 07:52:02 PM PDT 24
Peak memory 232192 kb
Host smart-d52666e1-4899-4856-8ea3-dbde7900d219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206346020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3206346020
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.912550988
Short name T494
Test name
Test status
Simulation time 12792277690 ps
CPU time 39.57 seconds
Started Jul 17 07:51:51 PM PDT 24
Finished Jul 17 07:52:34 PM PDT 24
Peak memory 248544 kb
Host smart-5eb99aad-b597-4fbd-a1a6-c8cdb42aeb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912550988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.912550988
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2233636386
Short name T257
Test name
Test status
Simulation time 165378315370 ps
CPU time 18.7 seconds
Started Jul 17 07:51:53 PM PDT 24
Finished Jul 17 07:52:15 PM PDT 24
Peak memory 224568 kb
Host smart-ecaeb340-b931-4bc5-89a7-f5d06edff0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233636386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2233636386
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2496426244
Short name T46
Test name
Test status
Simulation time 2424289094 ps
CPU time 23.51 seconds
Started Jul 17 07:51:53 PM PDT 24
Finished Jul 17 07:52:19 PM PDT 24
Peak memory 218908 kb
Host smart-e9641408-526a-4628-a6d0-68f8c9d82f42
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2496426244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2496426244
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1876766258
Short name T522
Test name
Test status
Simulation time 8739140863 ps
CPU time 82.44 seconds
Started Jul 17 07:51:45 PM PDT 24
Finished Jul 17 07:53:12 PM PDT 24
Peak memory 241272 kb
Host smart-00b3dedc-fb46-4ec7-9cf2-dd3cdc31581f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876766258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1876766258
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3894898975
Short name T957
Test name
Test status
Simulation time 14710971 ps
CPU time 0.73 seconds
Started Jul 17 07:51:48 PM PDT 24
Finished Jul 17 07:51:53 PM PDT 24
Peak memory 206028 kb
Host smart-b12ea1d4-8751-4626-9722-4438205c1992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894898975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3894898975
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1008104869
Short name T34
Test name
Test status
Simulation time 53411359790 ps
CPU time 11.53 seconds
Started Jul 17 07:51:48 PM PDT 24
Finished Jul 17 07:52:04 PM PDT 24
Peak memory 216452 kb
Host smart-452210d7-f0d5-4cb4-95be-3070b69c624a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008104869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1008104869
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2573424705
Short name T909
Test name
Test status
Simulation time 140967518 ps
CPU time 1.76 seconds
Started Jul 17 07:51:53 PM PDT 24
Finished Jul 17 07:51:58 PM PDT 24
Peak memory 216260 kb
Host smart-3c658ec2-c870-4c1f-8fd1-3a77f64c512f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573424705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2573424705
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.639728284
Short name T675
Test name
Test status
Simulation time 94246837 ps
CPU time 1 seconds
Started Jul 17 07:51:47 PM PDT 24
Finished Jul 17 07:51:52 PM PDT 24
Peak memory 205988 kb
Host smart-135da6ef-f566-4d46-ba68-9d4a464ca0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639728284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.639728284
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2685701230
Short name T272
Test name
Test status
Simulation time 147243292 ps
CPU time 2.72 seconds
Started Jul 17 07:51:47 PM PDT 24
Finished Jul 17 07:51:55 PM PDT 24
Peak memory 224424 kb
Host smart-ee7a865e-c482-4115-bd7d-72e5ef8086c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685701230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2685701230
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2278141888
Short name T910
Test name
Test status
Simulation time 37169717 ps
CPU time 0.74 seconds
Started Jul 17 07:52:10 PM PDT 24
Finished Jul 17 07:52:13 PM PDT 24
Peak memory 205540 kb
Host smart-2db39e62-8647-4226-aa66-fcccb83aef65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278141888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2278141888
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2857480002
Short name T428
Test name
Test status
Simulation time 105504198 ps
CPU time 2.32 seconds
Started Jul 17 07:52:11 PM PDT 24
Finished Jul 17 07:52:15 PM PDT 24
Peak memory 224096 kb
Host smart-288c5818-5654-438c-b08b-13a81c8f7b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857480002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2857480002
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3221463291
Short name T660
Test name
Test status
Simulation time 26486375 ps
CPU time 0.76 seconds
Started Jul 17 07:52:04 PM PDT 24
Finished Jul 17 07:52:06 PM PDT 24
Peak memory 205596 kb
Host smart-331eb15a-5937-4c96-a98d-01494dae740b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221463291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3221463291
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1932272992
Short name T753
Test name
Test status
Simulation time 23514673480 ps
CPU time 187.05 seconds
Started Jul 17 07:52:08 PM PDT 24
Finished Jul 17 07:55:17 PM PDT 24
Peak memory 252128 kb
Host smart-86a155bf-bd51-4f43-9401-615707b8b08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932272992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1932272992
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3930841256
Short name T241
Test name
Test status
Simulation time 54135633725 ps
CPU time 45.51 seconds
Started Jul 17 07:52:06 PM PDT 24
Finished Jul 17 07:52:53 PM PDT 24
Peak memory 256400 kb
Host smart-12d4a95c-426a-4f71-a768-6c68e35dc2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930841256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3930841256
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.182004938
Short name T201
Test name
Test status
Simulation time 57955413916 ps
CPU time 247.8 seconds
Started Jul 17 07:52:05 PM PDT 24
Finished Jul 17 07:56:14 PM PDT 24
Peak memory 235648 kb
Host smart-4ea7a726-6365-4b18-8b12-7bb427018da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182004938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.182004938
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.69301413
Short name T608
Test name
Test status
Simulation time 463891086 ps
CPU time 11.75 seconds
Started Jul 17 07:52:08 PM PDT 24
Finished Jul 17 07:52:22 PM PDT 24
Peak memory 249096 kb
Host smart-85103ebe-8ea1-4ec5-b11c-06f58aabe8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69301413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.69301413
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.2457031593
Short name T51
Test name
Test status
Simulation time 8364168904 ps
CPU time 50.37 seconds
Started Jul 17 07:52:04 PM PDT 24
Finished Jul 17 07:52:55 PM PDT 24
Peak memory 252908 kb
Host smart-aabd6e27-9570-4451-aadc-4954c901e48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457031593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.2457031593
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3587959120
Short name T477
Test name
Test status
Simulation time 1876122131 ps
CPU time 10.27 seconds
Started Jul 17 07:52:06 PM PDT 24
Finished Jul 17 07:52:19 PM PDT 24
Peak memory 224476 kb
Host smart-06512598-911b-4373-bf78-4d50baff1ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587959120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3587959120
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2871201344
Short name T550
Test name
Test status
Simulation time 318087494 ps
CPU time 4.7 seconds
Started Jul 17 07:52:04 PM PDT 24
Finished Jul 17 07:52:10 PM PDT 24
Peak memory 232712 kb
Host smart-1fff5fb1-d6bc-4bdb-bb6d-f0af8bbe90e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871201344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2871201344
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.758890373
Short name T38
Test name
Test status
Simulation time 674504219 ps
CPU time 7.49 seconds
Started Jul 17 07:52:05 PM PDT 24
Finished Jul 17 07:52:14 PM PDT 24
Peak memory 232632 kb
Host smart-b49a7e82-7c18-4fd0-9322-6e9d1eaeecba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758890373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.758890373
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.4007567785
Short name T397
Test name
Test status
Simulation time 7322118891 ps
CPU time 11 seconds
Started Jul 17 07:52:07 PM PDT 24
Finished Jul 17 07:52:21 PM PDT 24
Peak memory 232848 kb
Host smart-687001df-145d-499b-adec-f64283197bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007567785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.4007567785
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3008177697
Short name T431
Test name
Test status
Simulation time 900490352 ps
CPU time 6.87 seconds
Started Jul 17 07:52:07 PM PDT 24
Finished Jul 17 07:52:17 PM PDT 24
Peak memory 223172 kb
Host smart-439651bb-c6f8-4cb6-8069-76c193c0dec8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3008177697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3008177697
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.436062297
Short name T848
Test name
Test status
Simulation time 9453014530 ps
CPU time 37.3 seconds
Started Jul 17 07:52:07 PM PDT 24
Finished Jul 17 07:52:47 PM PDT 24
Peak memory 249280 kb
Host smart-f3ff4e7d-d428-499e-8fc0-e11b188a0122
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436062297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.436062297
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.189780667
Short name T1010
Test name
Test status
Simulation time 13812230 ps
CPU time 0.71 seconds
Started Jul 17 07:52:05 PM PDT 24
Finished Jul 17 07:52:07 PM PDT 24
Peak memory 205708 kb
Host smart-05a9714e-836c-42ec-9688-e055d20cce25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189780667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.189780667
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1598763525
Short name T881
Test name
Test status
Simulation time 1741621193 ps
CPU time 5.23 seconds
Started Jul 17 07:52:06 PM PDT 24
Finished Jul 17 07:52:13 PM PDT 24
Peak memory 216244 kb
Host smart-85fc12b2-8415-462f-8ae3-30866d5078e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598763525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1598763525
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2535347895
Short name T819
Test name
Test status
Simulation time 67943170 ps
CPU time 2.71 seconds
Started Jul 17 07:52:06 PM PDT 24
Finished Jul 17 07:52:10 PM PDT 24
Peak memory 216260 kb
Host smart-3126b362-7353-4e67-bff8-091b753ba1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535347895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2535347895
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.4078579007
Short name T892
Test name
Test status
Simulation time 39185959 ps
CPU time 0.91 seconds
Started Jul 17 07:52:21 PM PDT 24
Finished Jul 17 07:52:23 PM PDT 24
Peak memory 206612 kb
Host smart-9cb9eea8-52c5-4a25-b994-3a5b18cd390b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078579007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.4078579007
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3705207886
Short name T270
Test name
Test status
Simulation time 4096859507 ps
CPU time 16.56 seconds
Started Jul 17 07:52:13 PM PDT 24
Finished Jul 17 07:52:31 PM PDT 24
Peak memory 238712 kb
Host smart-9d2eb366-c095-4c13-8181-33eaef48c91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705207886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3705207886
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3226071783
Short name T339
Test name
Test status
Simulation time 11960632 ps
CPU time 0.71 seconds
Started Jul 17 07:52:04 PM PDT 24
Finished Jul 17 07:52:06 PM PDT 24
Peak memory 205540 kb
Host smart-cfd586bd-ea08-49ab-af88-b925e91e4349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226071783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3226071783
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1762535562
Short name T714
Test name
Test status
Simulation time 337258450 ps
CPU time 5.49 seconds
Started Jul 17 07:52:05 PM PDT 24
Finished Jul 17 07:52:12 PM PDT 24
Peak memory 224448 kb
Host smart-cd7c4a0c-b6fd-40a2-92e8-d3e7765fc96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762535562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1762535562
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1681654592
Short name T511
Test name
Test status
Simulation time 16537869 ps
CPU time 0.77 seconds
Started Jul 17 07:52:06 PM PDT 24
Finished Jul 17 07:52:08 PM PDT 24
Peak memory 205588 kb
Host smart-92f09441-7df7-479f-84eb-caba4e4f29a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681654592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1681654592
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1064844842
Short name T218
Test name
Test status
Simulation time 14901378972 ps
CPU time 90.23 seconds
Started Jul 17 07:52:19 PM PDT 24
Finished Jul 17 07:53:50 PM PDT 24
Peak memory 273140 kb
Host smart-d468cf08-41ac-4842-a61a-b6db5c6e7c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064844842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1064844842
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3296271207
Short name T530
Test name
Test status
Simulation time 42766194272 ps
CPU time 113.79 seconds
Started Jul 17 07:52:11 PM PDT 24
Finished Jul 17 07:54:07 PM PDT 24
Peak memory 252856 kb
Host smart-56424b6e-d917-4290-b0df-aa0516cdc190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296271207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3296271207
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.45902801
Short name T281
Test name
Test status
Simulation time 21802749770 ps
CPU time 65.98 seconds
Started Jul 17 07:52:07 PM PDT 24
Finished Jul 17 07:53:16 PM PDT 24
Peak memory 257452 kb
Host smart-86dbc127-d5f2-4e22-80dc-d0f9e14a3f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45902801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle.45902801
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2659290213
Short name T758
Test name
Test status
Simulation time 1522074659 ps
CPU time 8.54 seconds
Started Jul 17 07:52:04 PM PDT 24
Finished Jul 17 07:52:14 PM PDT 24
Peak memory 232684 kb
Host smart-cfe69a07-26da-440c-a714-126e6ee697a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659290213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2659290213
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.2151186103
Short name T570
Test name
Test status
Simulation time 34431151021 ps
CPU time 229.94 seconds
Started Jul 17 07:52:03 PM PDT 24
Finished Jul 17 07:55:54 PM PDT 24
Peak memory 257396 kb
Host smart-b2eb831b-b381-4c12-a328-062d85f077c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151186103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.2151186103
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1108405012
Short name T833
Test name
Test status
Simulation time 1399304865 ps
CPU time 4.87 seconds
Started Jul 17 07:52:07 PM PDT 24
Finished Jul 17 07:52:14 PM PDT 24
Peak memory 224392 kb
Host smart-a2622482-445d-4a65-a031-2010690e9445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108405012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1108405012
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2413021097
Short name T254
Test name
Test status
Simulation time 10608038179 ps
CPU time 43.35 seconds
Started Jul 17 07:52:08 PM PDT 24
Finished Jul 17 07:52:54 PM PDT 24
Peak memory 232844 kb
Host smart-126561a3-8bcc-4ab3-8406-fc490179122f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413021097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2413021097
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1532037741
Short name T699
Test name
Test status
Simulation time 3133120305 ps
CPU time 4.66 seconds
Started Jul 17 07:52:13 PM PDT 24
Finished Jul 17 07:52:19 PM PDT 24
Peak memory 232692 kb
Host smart-96ea8d1f-15eb-4f3b-a5d2-24ba6e305f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532037741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1532037741
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.86069380
Short name T524
Test name
Test status
Simulation time 537381578 ps
CPU time 7.5 seconds
Started Jul 17 07:52:11 PM PDT 24
Finished Jul 17 07:52:20 PM PDT 24
Peak memory 232776 kb
Host smart-27d384b0-56e3-431b-9293-e92ae1993935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86069380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.86069380
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1899247160
Short name T790
Test name
Test status
Simulation time 2206227065 ps
CPU time 9.22 seconds
Started Jul 17 07:52:05 PM PDT 24
Finished Jul 17 07:52:16 PM PDT 24
Peak memory 218832 kb
Host smart-c5af3306-e977-45be-a3ec-959e196cf3f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1899247160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1899247160
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.428325230
Short name T566
Test name
Test status
Simulation time 1979975488 ps
CPU time 18.24 seconds
Started Jul 17 07:52:08 PM PDT 24
Finished Jul 17 07:52:29 PM PDT 24
Peak memory 224440 kb
Host smart-003de1bf-1505-483d-89d7-2f3093d7608f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428325230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.428325230
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1916166804
Short name T808
Test name
Test status
Simulation time 44358026733 ps
CPU time 26.45 seconds
Started Jul 17 07:52:07 PM PDT 24
Finished Jul 17 07:52:35 PM PDT 24
Peak memory 216440 kb
Host smart-fc08e6fe-7f53-4c33-84bd-d502712b0d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916166804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1916166804
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1370521910
Short name T468
Test name
Test status
Simulation time 4384613601 ps
CPU time 7.08 seconds
Started Jul 17 07:52:12 PM PDT 24
Finished Jul 17 07:52:21 PM PDT 24
Peak memory 216380 kb
Host smart-70d1aec7-c58b-4988-b357-6c23761da89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370521910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1370521910
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3446585452
Short name T469
Test name
Test status
Simulation time 47125579 ps
CPU time 1.45 seconds
Started Jul 17 07:52:07 PM PDT 24
Finished Jul 17 07:52:11 PM PDT 24
Peak memory 216212 kb
Host smart-b0b7af19-d38a-4311-a362-cc663994c684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446585452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3446585452
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.4173969737
Short name T344
Test name
Test status
Simulation time 35283042 ps
CPU time 0.71 seconds
Started Jul 17 07:52:06 PM PDT 24
Finished Jul 17 07:52:08 PM PDT 24
Peak memory 205988 kb
Host smart-15338c83-b4fe-4b3c-8fbe-f04102dce448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173969737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.4173969737
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2884845165
Short name T949
Test name
Test status
Simulation time 5308271467 ps
CPU time 19.79 seconds
Started Jul 17 07:52:06 PM PDT 24
Finished Jul 17 07:52:28 PM PDT 24
Peak memory 240968 kb
Host smart-8ae5b280-0040-4ac2-83d5-3b8854dcee0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884845165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2884845165
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2638975721
Short name T403
Test name
Test status
Simulation time 41332459 ps
CPU time 0.75 seconds
Started Jul 17 07:52:08 PM PDT 24
Finished Jul 17 07:52:11 PM PDT 24
Peak memory 205548 kb
Host smart-201f4903-dc51-4d0e-b809-fc2c49c8a7c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638975721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2638975721
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.672487268
Short name T876
Test name
Test status
Simulation time 88643309 ps
CPU time 2.29 seconds
Started Jul 17 07:52:07 PM PDT 24
Finished Jul 17 07:52:11 PM PDT 24
Peak memory 224480 kb
Host smart-b55b8108-bd7a-48d3-a548-5cee61a592f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672487268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.672487268
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3368375744
Short name T489
Test name
Test status
Simulation time 32260750 ps
CPU time 0.79 seconds
Started Jul 17 07:52:08 PM PDT 24
Finished Jul 17 07:52:11 PM PDT 24
Peak memory 206620 kb
Host smart-1e9cf4b3-d6b9-404f-84da-5a3cbab927d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368375744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3368375744
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1048872310
Short name T336
Test name
Test status
Simulation time 1002185904 ps
CPU time 6.01 seconds
Started Jul 17 07:52:12 PM PDT 24
Finished Jul 17 07:52:19 PM PDT 24
Peak memory 232832 kb
Host smart-b41391cf-d7c4-4589-b0b0-c46de570512e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048872310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1048872310
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1239959216
Short name T147
Test name
Test status
Simulation time 8075349257 ps
CPU time 73.85 seconds
Started Jul 17 07:52:06 PM PDT 24
Finished Jul 17 07:53:22 PM PDT 24
Peak memory 249276 kb
Host smart-d1d287e8-09e9-4d0f-9c44-a9b3325c590f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239959216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1239959216
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.151387952
Short name T954
Test name
Test status
Simulation time 18357805273 ps
CPU time 165.11 seconds
Started Jul 17 07:52:09 PM PDT 24
Finished Jul 17 07:54:56 PM PDT 24
Peak memory 249272 kb
Host smart-ff49fafe-d5b2-4655-917c-795d65d2d926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151387952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.151387952
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3392655971
Short name T982
Test name
Test status
Simulation time 34930916967 ps
CPU time 48.11 seconds
Started Jul 17 07:52:07 PM PDT 24
Finished Jul 17 07:52:57 PM PDT 24
Peak memory 232776 kb
Host smart-57e75b1c-7293-46a9-80cd-9fc041507ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392655971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3392655971
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.4098972977
Short name T975
Test name
Test status
Simulation time 3796758084 ps
CPU time 36.17 seconds
Started Jul 17 07:52:05 PM PDT 24
Finished Jul 17 07:52:42 PM PDT 24
Peak memory 257396 kb
Host smart-18aa44fa-5b5f-4a53-bc33-80023fc52c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098972977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.4098972977
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3288041670
Short name T609
Test name
Test status
Simulation time 148384286 ps
CPU time 2.76 seconds
Started Jul 17 07:52:07 PM PDT 24
Finished Jul 17 07:52:12 PM PDT 24
Peak memory 224400 kb
Host smart-e816da17-3660-4170-a9b3-3b6d3ba3430f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288041670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3288041670
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2292078005
Short name T866
Test name
Test status
Simulation time 735313029 ps
CPU time 8.23 seconds
Started Jul 17 07:52:06 PM PDT 24
Finished Jul 17 07:52:17 PM PDT 24
Peak memory 240616 kb
Host smart-e78967e5-4c79-4efe-b30c-e221bb2b7b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292078005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2292078005
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.4218115875
Short name T518
Test name
Test status
Simulation time 5349867064 ps
CPU time 19.26 seconds
Started Jul 17 07:52:09 PM PDT 24
Finished Jul 17 07:52:31 PM PDT 24
Peak memory 240540 kb
Host smart-7b9bc7ce-1af3-4b24-a54a-739eab55e943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218115875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.4218115875
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.75450933
Short name T604
Test name
Test status
Simulation time 2591475917 ps
CPU time 11.52 seconds
Started Jul 17 07:52:09 PM PDT 24
Finished Jul 17 07:52:23 PM PDT 24
Peak memory 232816 kb
Host smart-288f5f59-6b99-4069-91d2-f355fe2db616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75450933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.75450933
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1812499050
Short name T748
Test name
Test status
Simulation time 9203512820 ps
CPU time 13.03 seconds
Started Jul 17 07:52:12 PM PDT 24
Finished Jul 17 07:52:26 PM PDT 24
Peak memory 220176 kb
Host smart-530c7acc-e411-493e-8fd2-203d1391f52b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1812499050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1812499050
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1393433248
Short name T180
Test name
Test status
Simulation time 96219572 ps
CPU time 1.03 seconds
Started Jul 17 07:52:08 PM PDT 24
Finished Jul 17 07:52:11 PM PDT 24
Peak memory 206992 kb
Host smart-962fe3f7-7794-45a8-9483-27bd011b6507
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393433248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1393433248
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.30786189
Short name T484
Test name
Test status
Simulation time 1246794039 ps
CPU time 4.01 seconds
Started Jul 17 07:52:05 PM PDT 24
Finished Jul 17 07:52:10 PM PDT 24
Peak memory 216180 kb
Host smart-d6a18f24-1a41-489f-9e71-e5be64811362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30786189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.30786189
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1374843604
Short name T779
Test name
Test status
Simulation time 1109722592 ps
CPU time 4.21 seconds
Started Jul 17 07:52:06 PM PDT 24
Finished Jul 17 07:52:12 PM PDT 24
Peak memory 216196 kb
Host smart-a238dd4a-d21a-4cc0-906d-cac0558a3b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374843604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1374843604
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1748335134
Short name T399
Test name
Test status
Simulation time 68279264 ps
CPU time 1.55 seconds
Started Jul 17 07:52:07 PM PDT 24
Finished Jul 17 07:52:11 PM PDT 24
Peak memory 216324 kb
Host smart-77df6017-8f1c-401c-bbf3-3ab1a694382f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748335134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1748335134
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2442546100
Short name T93
Test name
Test status
Simulation time 19332565 ps
CPU time 0.74 seconds
Started Jul 17 07:52:05 PM PDT 24
Finished Jul 17 07:52:07 PM PDT 24
Peak memory 205992 kb
Host smart-ce19b952-2fed-41e4-b78c-1f27baaf7214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442546100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2442546100
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2931906137
Short name T250
Test name
Test status
Simulation time 8078052263 ps
CPU time 8.32 seconds
Started Jul 17 07:52:04 PM PDT 24
Finished Jul 17 07:52:13 PM PDT 24
Peak memory 232824 kb
Host smart-418db69b-3730-48e9-9c35-ea0404c78c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931906137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2931906137
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2855594914
Short name T723
Test name
Test status
Simulation time 66786843 ps
CPU time 0.73 seconds
Started Jul 17 07:48:12 PM PDT 24
Finished Jul 17 07:48:16 PM PDT 24
Peak memory 205544 kb
Host smart-b1514902-cf63-49ba-a992-b3dcdd989205
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855594914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
855594914
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1397894266
Short name T729
Test name
Test status
Simulation time 623715692 ps
CPU time 2.76 seconds
Started Jul 17 07:48:11 PM PDT 24
Finished Jul 17 07:48:17 PM PDT 24
Peak memory 224404 kb
Host smart-81d16418-e93c-451a-a885-00fc76b845b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397894266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1397894266
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.919901872
Short name T532
Test name
Test status
Simulation time 37285910 ps
CPU time 0.77 seconds
Started Jul 17 07:48:12 PM PDT 24
Finished Jul 17 07:48:17 PM PDT 24
Peak memory 206932 kb
Host smart-96b35662-96e6-445d-b8f0-dd2234d64e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919901872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.919901872
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3918697627
Short name T265
Test name
Test status
Simulation time 65381491467 ps
CPU time 445.18 seconds
Started Jul 17 07:48:20 PM PDT 24
Finished Jul 17 07:55:47 PM PDT 24
Peak memory 265460 kb
Host smart-5720609c-8285-4664-93fd-f2b97a87729c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918697627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3918697627
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.358955644
Short name T136
Test name
Test status
Simulation time 22372959399 ps
CPU time 215.59 seconds
Started Jul 17 07:48:24 PM PDT 24
Finished Jul 17 07:52:00 PM PDT 24
Peak memory 254116 kb
Host smart-976729a6-f5a7-4cc0-b22d-88196b2cbb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358955644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.358955644
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.859163042
Short name T822
Test name
Test status
Simulation time 38441933814 ps
CPU time 117.11 seconds
Started Jul 17 07:48:26 PM PDT 24
Finished Jul 17 07:50:23 PM PDT 24
Peak memory 265656 kb
Host smart-87fba337-3a57-4d69-8a5e-d933fb34a248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859163042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
859163042
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3277384616
Short name T899
Test name
Test status
Simulation time 815072629 ps
CPU time 11.96 seconds
Started Jul 17 07:48:19 PM PDT 24
Finished Jul 17 07:48:32 PM PDT 24
Peak memory 224500 kb
Host smart-5251d584-be02-4ffc-9403-a8269544cb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277384616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3277384616
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.1335563679
Short name T98
Test name
Test status
Simulation time 12008189208 ps
CPU time 55.79 seconds
Started Jul 17 07:48:20 PM PDT 24
Finished Jul 17 07:49:16 PM PDT 24
Peak memory 254220 kb
Host smart-ff27452a-ff91-4845-9f1b-b1c41d19426d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335563679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.1335563679
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2334953320
Short name T427
Test name
Test status
Simulation time 810905357 ps
CPU time 4.55 seconds
Started Jul 17 07:48:13 PM PDT 24
Finished Jul 17 07:48:21 PM PDT 24
Peak memory 224428 kb
Host smart-7f84bf25-5729-4f74-815b-082a935ac4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334953320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2334953320
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2674997595
Short name T786
Test name
Test status
Simulation time 22110193940 ps
CPU time 23.61 seconds
Started Jul 17 07:48:13 PM PDT 24
Finished Jul 17 07:48:40 PM PDT 24
Peak memory 232688 kb
Host smart-f37561d6-ab5c-4181-851e-7b803b551f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674997595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2674997595
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2222667344
Short name T943
Test name
Test status
Simulation time 4855411159 ps
CPU time 8.27 seconds
Started Jul 17 07:48:20 PM PDT 24
Finished Jul 17 07:48:29 PM PDT 24
Peak memory 238020 kb
Host smart-dbe07a69-c2b4-4688-b812-6e8e032a7d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222667344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2222667344
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2390167073
Short name T458
Test name
Test status
Simulation time 13470569576 ps
CPU time 14.2 seconds
Started Jul 17 07:48:13 PM PDT 24
Finished Jul 17 07:48:30 PM PDT 24
Peak memory 224568 kb
Host smart-4e89ede9-e1b3-4d96-be14-fd0c06cb76e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390167073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2390167073
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2362141144
Short name T746
Test name
Test status
Simulation time 5983076667 ps
CPU time 11.78 seconds
Started Jul 17 07:48:11 PM PDT 24
Finished Jul 17 07:48:26 PM PDT 24
Peak memory 220200 kb
Host smart-11925380-dcac-48d3-a7a2-332e1867b8c9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2362141144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2362141144
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.4014368447
Short name T424
Test name
Test status
Simulation time 243134680580 ps
CPU time 262.79 seconds
Started Jul 17 07:48:26 PM PDT 24
Finished Jul 17 07:52:49 PM PDT 24
Peak memory 257104 kb
Host smart-165b1db7-aa2e-43cb-acf1-fae7c5bf7f4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014368447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.4014368447
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2007774403
Short name T635
Test name
Test status
Simulation time 2750267939 ps
CPU time 8.52 seconds
Started Jul 17 07:48:13 PM PDT 24
Finished Jul 17 07:48:25 PM PDT 24
Peak memory 216252 kb
Host smart-d84caf6a-9d0a-423d-8102-8a96741cff56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007774403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2007774403
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1212725444
Short name T654
Test name
Test status
Simulation time 19106842504 ps
CPU time 13.25 seconds
Started Jul 17 07:48:13 PM PDT 24
Finished Jul 17 07:48:30 PM PDT 24
Peak memory 216320 kb
Host smart-32789c06-1761-4aef-a62e-261a98551557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212725444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1212725444
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2137098780
Short name T667
Test name
Test status
Simulation time 69707744 ps
CPU time 1.46 seconds
Started Jul 17 07:48:14 PM PDT 24
Finished Jul 17 07:48:18 PM PDT 24
Peak memory 216248 kb
Host smart-4390acdc-52ac-4cc1-a0b3-07c47988d27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137098780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2137098780
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2110259386
Short name T884
Test name
Test status
Simulation time 31039503 ps
CPU time 0.73 seconds
Started Jul 17 07:48:13 PM PDT 24
Finished Jul 17 07:48:17 PM PDT 24
Peak memory 205980 kb
Host smart-3deba3a4-b348-4cd2-9f8e-06e3ec599e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110259386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2110259386
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2718459307
Short name T248
Test name
Test status
Simulation time 4053876471 ps
CPU time 4.02 seconds
Started Jul 17 07:48:20 PM PDT 24
Finished Jul 17 07:48:25 PM PDT 24
Peak memory 232816 kb
Host smart-56652c9b-83a0-443b-bc8f-b962769e0b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718459307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2718459307
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2724887500
Short name T679
Test name
Test status
Simulation time 21643798 ps
CPU time 0.71 seconds
Started Jul 17 07:48:37 PM PDT 24
Finished Jul 17 07:48:38 PM PDT 24
Peak memory 204964 kb
Host smart-c9221856-4310-4316-8caa-7e6dd925d633
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724887500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
724887500
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3137980246
Short name T96
Test name
Test status
Simulation time 83108156 ps
CPU time 2.66 seconds
Started Jul 17 07:48:37 PM PDT 24
Finished Jul 17 07:48:42 PM PDT 24
Peak memory 232648 kb
Host smart-c77ef95c-dc95-40fe-99f3-895cce2cb271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137980246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3137980246
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.813471856
Short name T364
Test name
Test status
Simulation time 193273658 ps
CPU time 0.82 seconds
Started Jul 17 07:48:11 PM PDT 24
Finished Jul 17 07:48:16 PM PDT 24
Peak memory 206612 kb
Host smart-ee37ac11-1e93-42cb-af26-7de726f64fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813471856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.813471856
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1125423486
Short name T955
Test name
Test status
Simulation time 3367716156 ps
CPU time 61.99 seconds
Started Jul 17 07:48:36 PM PDT 24
Finished Jul 17 07:49:39 PM PDT 24
Peak memory 256532 kb
Host smart-7664cad3-6fc8-4daf-a57c-da9b28a5cffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125423486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1125423486
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1237048296
Short name T564
Test name
Test status
Simulation time 75960706670 ps
CPU time 120.82 seconds
Started Jul 17 07:48:36 PM PDT 24
Finished Jul 17 07:50:38 PM PDT 24
Peak memory 249260 kb
Host smart-9d6a3027-9cc0-4daf-9e18-08fccebfe2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237048296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.1237048296
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3697713838
Short name T418
Test name
Test status
Simulation time 1106856692 ps
CPU time 20.89 seconds
Started Jul 17 07:48:36 PM PDT 24
Finished Jul 17 07:48:58 PM PDT 24
Peak memory 232648 kb
Host smart-d8c01440-d464-4000-92d0-0f04f7634bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697713838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3697713838
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.1647114704
Short name T235
Test name
Test status
Simulation time 23177661846 ps
CPU time 196.76 seconds
Started Jul 17 07:48:39 PM PDT 24
Finished Jul 17 07:51:59 PM PDT 24
Peak memory 240980 kb
Host smart-918a3d48-d600-4a83-b9c4-1ac06ad88cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647114704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.1647114704
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3651738724
Short name T939
Test name
Test status
Simulation time 186521171 ps
CPU time 3.87 seconds
Started Jul 17 07:48:14 PM PDT 24
Finished Jul 17 07:48:21 PM PDT 24
Peak memory 232716 kb
Host smart-7ea78286-eecd-45d4-86a0-2f0f1f133d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651738724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3651738724
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1333674947
Short name T918
Test name
Test status
Simulation time 790350433 ps
CPU time 5.33 seconds
Started Jul 17 07:48:11 PM PDT 24
Finished Jul 17 07:48:21 PM PDT 24
Peak memory 235684 kb
Host smart-53c0cac9-ffa9-4f66-a555-7831e5c0d65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333674947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1333674947
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.555389876
Short name T23
Test name
Test status
Simulation time 17982058272 ps
CPU time 15.47 seconds
Started Jul 17 07:48:12 PM PDT 24
Finished Jul 17 07:48:31 PM PDT 24
Peak memory 232820 kb
Host smart-57487be4-6910-44a0-a96e-88312ef9977f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555389876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
555389876
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1389950087
Short name T258
Test name
Test status
Simulation time 4057357891 ps
CPU time 13.2 seconds
Started Jul 17 07:48:24 PM PDT 24
Finished Jul 17 07:48:38 PM PDT 24
Peak memory 232844 kb
Host smart-c548917f-a4c0-48de-bb93-50d0e5082abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389950087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1389950087
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3330390946
Short name T763
Test name
Test status
Simulation time 182172743 ps
CPU time 3.56 seconds
Started Jul 17 07:48:36 PM PDT 24
Finished Jul 17 07:48:41 PM PDT 24
Peak memory 218856 kb
Host smart-8683c00f-2ef3-4eb3-8a7f-adab20e9b45d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3330390946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3330390946
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3483234822
Short name T834
Test name
Test status
Simulation time 139312266 ps
CPU time 0.97 seconds
Started Jul 17 07:48:35 PM PDT 24
Finished Jul 17 07:48:37 PM PDT 24
Peak memory 206876 kb
Host smart-dbad408c-bae4-44a7-bc36-6592f56512cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483234822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3483234822
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2656361114
Short name T86
Test name
Test status
Simulation time 9920919957 ps
CPU time 8.73 seconds
Started Jul 17 07:48:14 PM PDT 24
Finished Jul 17 07:48:25 PM PDT 24
Peak memory 219940 kb
Host smart-f2a401f3-33d3-4898-8d0f-2b41a2d61ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656361114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2656361114
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3213914429
Short name T619
Test name
Test status
Simulation time 7932203576 ps
CPU time 5.17 seconds
Started Jul 17 07:48:24 PM PDT 24
Finished Jul 17 07:48:30 PM PDT 24
Peak memory 216140 kb
Host smart-c1e897f8-f058-432a-bff4-27b08663cdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213914429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3213914429
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1036902907
Short name T371
Test name
Test status
Simulation time 235693420 ps
CPU time 7.2 seconds
Started Jul 17 07:48:10 PM PDT 24
Finished Jul 17 07:48:21 PM PDT 24
Peak memory 216208 kb
Host smart-5c1205d0-98af-4e12-9339-80709477f96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036902907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1036902907
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3262748596
Short name T837
Test name
Test status
Simulation time 66637450 ps
CPU time 0.78 seconds
Started Jul 17 07:48:14 PM PDT 24
Finished Jul 17 07:48:17 PM PDT 24
Peak memory 205976 kb
Host smart-ab55d15a-3d2a-4f15-9dd9-642b7ceb7c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262748596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3262748596
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1382664946
Short name T426
Test name
Test status
Simulation time 1351590190 ps
CPU time 7.75 seconds
Started Jul 17 07:48:24 PM PDT 24
Finished Jul 17 07:48:32 PM PDT 24
Peak memory 232668 kb
Host smart-602b46d1-125f-4836-a59d-a3bc79b67914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382664946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1382664946
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3983332092
Short name T597
Test name
Test status
Simulation time 14778603 ps
CPU time 0.75 seconds
Started Jul 17 07:48:40 PM PDT 24
Finished Jul 17 07:48:44 PM PDT 24
Peak memory 205508 kb
Host smart-f4a15570-00ef-4dda-b8b0-2a4d1a873bfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983332092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
983332092
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.4263409951
Short name T787
Test name
Test status
Simulation time 275907247 ps
CPU time 5.44 seconds
Started Jul 17 07:48:38 PM PDT 24
Finished Jul 17 07:48:45 PM PDT 24
Peak memory 232732 kb
Host smart-7212d4ee-71dc-48fd-b45b-d4fa559372c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263409951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.4263409951
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3772936029
Short name T545
Test name
Test status
Simulation time 35377453 ps
CPU time 0.76 seconds
Started Jul 17 07:48:35 PM PDT 24
Finished Jul 17 07:48:37 PM PDT 24
Peak memory 206956 kb
Host smart-75840875-b40e-4d69-89d8-e2678d350639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772936029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3772936029
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3783679603
Short name T279
Test name
Test status
Simulation time 203982282109 ps
CPU time 165.89 seconds
Started Jul 17 07:48:38 PM PDT 24
Finished Jul 17 07:51:27 PM PDT 24
Peak memory 250344 kb
Host smart-950519f0-b36a-453e-9a17-dbf1b38b240c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783679603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3783679603
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1754408649
Short name T310
Test name
Test status
Simulation time 140729373727 ps
CPU time 286.43 seconds
Started Jul 17 07:48:41 PM PDT 24
Finished Jul 17 07:53:30 PM PDT 24
Peak memory 257388 kb
Host smart-b7ce77b4-6c65-46f8-9cdb-c022cd8ad591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754408649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1754408649
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3335809543
Short name T350
Test name
Test status
Simulation time 438254733 ps
CPU time 3.03 seconds
Started Jul 17 07:48:35 PM PDT 24
Finished Jul 17 07:48:38 PM PDT 24
Peak memory 224484 kb
Host smart-15f5fb48-3def-46cd-b797-8d955c9a9af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335809543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3335809543
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.374090622
Short name T840
Test name
Test status
Simulation time 194465907 ps
CPU time 4.14 seconds
Started Jul 17 07:48:40 PM PDT 24
Finished Jul 17 07:48:47 PM PDT 24
Peak memory 224456 kb
Host smart-67d4dd66-58dc-495c-a569-63f792106abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374090622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.374090622
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.529990807
Short name T843
Test name
Test status
Simulation time 3441502510 ps
CPU time 25.69 seconds
Started Jul 17 07:48:36 PM PDT 24
Finished Jul 17 07:49:02 PM PDT 24
Peak memory 232776 kb
Host smart-60da4266-ef5d-4918-b1b2-d91123d820e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529990807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.529990807
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.812723566
Short name T571
Test name
Test status
Simulation time 7437292385 ps
CPU time 7.2 seconds
Started Jul 17 07:48:40 PM PDT 24
Finished Jul 17 07:48:50 PM PDT 24
Peak memory 232764 kb
Host smart-f05e12ef-cf63-4f9a-8f39-a09964871737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812723566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
812723566
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1456929238
Short name T671
Test name
Test status
Simulation time 1468225162 ps
CPU time 3.48 seconds
Started Jul 17 07:48:38 PM PDT 24
Finished Jul 17 07:48:44 PM PDT 24
Peak memory 232660 kb
Host smart-54275a9a-3e1e-41e9-aa2a-d088166981ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456929238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1456929238
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1132229867
Short name T154
Test name
Test status
Simulation time 219116860 ps
CPU time 3.41 seconds
Started Jul 17 07:48:38 PM PDT 24
Finished Jul 17 07:48:44 PM PDT 24
Peak memory 222600 kb
Host smart-87a79b16-5b25-4630-b002-3a9cf7289793
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1132229867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1132229867
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.808943353
Short name T410
Test name
Test status
Simulation time 162986139 ps
CPU time 0.98 seconds
Started Jul 17 07:48:42 PM PDT 24
Finished Jul 17 07:48:45 PM PDT 24
Peak memory 207680 kb
Host smart-064469b1-220c-4bc5-9e85-0d75549dde19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808943353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.808943353
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.50720058
Short name T438
Test name
Test status
Simulation time 3462205811 ps
CPU time 26.35 seconds
Started Jul 17 07:48:37 PM PDT 24
Finished Jul 17 07:49:04 PM PDT 24
Peak memory 216384 kb
Host smart-a97ca5fb-04da-4094-bee2-97f976792bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50720058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.50720058
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.157371416
Short name T575
Test name
Test status
Simulation time 201204809 ps
CPU time 1.04 seconds
Started Jul 17 07:48:38 PM PDT 24
Finished Jul 17 07:48:41 PM PDT 24
Peak memory 207240 kb
Host smart-e9002737-4f1e-4c66-810f-07af32261bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157371416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.157371416
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.312741223
Short name T825
Test name
Test status
Simulation time 74997472 ps
CPU time 1.09 seconds
Started Jul 17 07:49:12 PM PDT 24
Finished Jul 17 07:49:14 PM PDT 24
Peak memory 207404 kb
Host smart-2e8ea037-ef9f-4492-bc7a-500dfc3e33ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312741223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.312741223
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1383830579
Short name T411
Test name
Test status
Simulation time 51806147 ps
CPU time 0.87 seconds
Started Jul 17 07:48:39 PM PDT 24
Finished Jul 17 07:48:43 PM PDT 24
Peak memory 206208 kb
Host smart-7e1da816-1560-47b3-8bb5-07cf1c7bef96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383830579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1383830579
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.4143837361
Short name T775
Test name
Test status
Simulation time 3303691423 ps
CPU time 11.32 seconds
Started Jul 17 07:48:37 PM PDT 24
Finished Jul 17 07:48:50 PM PDT 24
Peak memory 224552 kb
Host smart-5b58b58e-37ea-427a-8d33-e5f7175f7271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143837361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.4143837361
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.425774582
Short name T920
Test name
Test status
Simulation time 46021011 ps
CPU time 0.72 seconds
Started Jul 17 07:48:37 PM PDT 24
Finished Jul 17 07:48:39 PM PDT 24
Peak memory 205528 kb
Host smart-a94e867f-c6ae-4bd1-aa43-e52ab2f8baa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425774582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.425774582
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1497932518
Short name T867
Test name
Test status
Simulation time 34468866 ps
CPU time 2.33 seconds
Started Jul 17 07:48:38 PM PDT 24
Finished Jul 17 07:48:43 PM PDT 24
Peak memory 232368 kb
Host smart-34ab21d0-d828-4b0d-8281-ddcd00e458a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497932518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1497932518
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3361507347
Short name T904
Test name
Test status
Simulation time 19448254 ps
CPU time 0.77 seconds
Started Jul 17 07:48:41 PM PDT 24
Finished Jul 17 07:48:45 PM PDT 24
Peak memory 206920 kb
Host smart-d1700c25-ee7d-46c4-902d-2c0a25d6bb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361507347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3361507347
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1948873723
Short name T287
Test name
Test status
Simulation time 12573053690 ps
CPU time 83.74 seconds
Started Jul 17 07:48:38 PM PDT 24
Finished Jul 17 07:50:05 PM PDT 24
Peak memory 249196 kb
Host smart-d0e6d5a5-b83e-4aa5-8daa-387583404760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948873723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1948873723
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2012098205
Short name T741
Test name
Test status
Simulation time 10841085963 ps
CPU time 131.66 seconds
Started Jul 17 07:48:40 PM PDT 24
Finished Jul 17 07:50:55 PM PDT 24
Peak memory 261296 kb
Host smart-d2286e82-f646-4802-8479-e3a58ac518f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012098205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2012098205
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3836331864
Short name T225
Test name
Test status
Simulation time 19168059201 ps
CPU time 121.9 seconds
Started Jul 17 07:48:37 PM PDT 24
Finished Jul 17 07:50:41 PM PDT 24
Peak memory 249480 kb
Host smart-e3d29881-dc8f-4497-88e3-39aab54d2005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836331864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3836331864
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3484519348
Short name T433
Test name
Test status
Simulation time 499306744 ps
CPU time 9.85 seconds
Started Jul 17 07:48:39 PM PDT 24
Finished Jul 17 07:48:51 PM PDT 24
Peak memory 234628 kb
Host smart-0d895c49-a6d7-4eb1-b866-d679cdd97fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484519348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3484519348
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.3437647285
Short name T290
Test name
Test status
Simulation time 33055217009 ps
CPU time 58.28 seconds
Started Jul 17 07:48:40 PM PDT 24
Finished Jul 17 07:49:42 PM PDT 24
Peak memory 237828 kb
Host smart-d7e1f658-cc7c-428e-ae8a-ee970b04359b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437647285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.3437647285
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2377786612
Short name T448
Test name
Test status
Simulation time 165891300 ps
CPU time 3.63 seconds
Started Jul 17 07:48:36 PM PDT 24
Finished Jul 17 07:48:40 PM PDT 24
Peak memory 232648 kb
Host smart-6b8a87af-6452-4eed-ba69-79665d6ba064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377786612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2377786612
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1901562729
Short name T551
Test name
Test status
Simulation time 36288058 ps
CPU time 2.23 seconds
Started Jul 17 07:48:38 PM PDT 24
Finished Jul 17 07:48:42 PM PDT 24
Peak memory 232708 kb
Host smart-0730253b-6ac3-4675-b7c5-e2f66409de58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901562729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1901562729
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.590858429
Short name T417
Test name
Test status
Simulation time 61307892 ps
CPU time 2.31 seconds
Started Jul 17 07:48:38 PM PDT 24
Finished Jul 17 07:48:43 PM PDT 24
Peak memory 232712 kb
Host smart-2bf0f5ac-1598-4833-891a-2460760b47ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590858429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
590858429
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2958467933
Short name T743
Test name
Test status
Simulation time 1158676384 ps
CPU time 5.04 seconds
Started Jul 17 07:48:40 PM PDT 24
Finished Jul 17 07:48:48 PM PDT 24
Peak memory 224436 kb
Host smart-9eaab2d5-bcac-4dcd-b9c8-276acfe21963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958467933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2958467933
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1142895631
Short name T585
Test name
Test status
Simulation time 661675471 ps
CPU time 4.15 seconds
Started Jul 17 07:48:37 PM PDT 24
Finished Jul 17 07:48:42 PM PDT 24
Peak memory 222148 kb
Host smart-53b831ba-87f1-4ac2-9331-6bebac36e2e3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1142895631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1142895631
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.785978265
Short name T846
Test name
Test status
Simulation time 146763111 ps
CPU time 1.02 seconds
Started Jul 17 07:48:38 PM PDT 24
Finished Jul 17 07:48:42 PM PDT 24
Peak memory 207664 kb
Host smart-0876e815-9380-40b3-8e0d-44f7e52279fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785978265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.785978265
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.506660881
Short name T712
Test name
Test status
Simulation time 7986974732 ps
CPU time 22.72 seconds
Started Jul 17 07:48:40 PM PDT 24
Finished Jul 17 07:49:06 PM PDT 24
Peak memory 216576 kb
Host smart-d30f045e-a3f0-41df-9c0f-cefd16c63bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506660881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.506660881
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.629752884
Short name T783
Test name
Test status
Simulation time 1640194317 ps
CPU time 4.18 seconds
Started Jul 17 07:48:39 PM PDT 24
Finished Jul 17 07:48:46 PM PDT 24
Peak memory 216196 kb
Host smart-bcb18147-596d-414f-8817-2bdaa58fce24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629752884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.629752884
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.195639553
Short name T935
Test name
Test status
Simulation time 225120883 ps
CPU time 1.78 seconds
Started Jul 17 07:48:38 PM PDT 24
Finished Jul 17 07:48:41 PM PDT 24
Peak memory 216240 kb
Host smart-272c0b8c-2301-4f64-8bdf-e5bf3d27ae75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195639553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.195639553
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1167185630
Short name T666
Test name
Test status
Simulation time 187528908 ps
CPU time 0.88 seconds
Started Jul 17 07:48:38 PM PDT 24
Finished Jul 17 07:48:41 PM PDT 24
Peak memory 206192 kb
Host smart-e467c882-90b5-4295-a453-12480a8ee187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167185630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1167185630
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1288978468
Short name T182
Test name
Test status
Simulation time 5865309757 ps
CPU time 24.94 seconds
Started Jul 17 07:48:39 PM PDT 24
Finished Jul 17 07:49:08 PM PDT 24
Peak memory 249236 kb
Host smart-6f42fe00-4632-4bc9-9e92-0d79c9cfd4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288978468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1288978468
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1481152198
Short name T980
Test name
Test status
Simulation time 138061373 ps
CPU time 0.71 seconds
Started Jul 17 07:48:41 PM PDT 24
Finished Jul 17 07:48:45 PM PDT 24
Peak memory 205512 kb
Host smart-ce40148f-ee9f-4be2-962f-a8d99dc88087
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481152198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
481152198
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2379756298
Short name T429
Test name
Test status
Simulation time 102937010 ps
CPU time 2.78 seconds
Started Jul 17 07:48:39 PM PDT 24
Finished Jul 17 07:48:46 PM PDT 24
Peak memory 224492 kb
Host smart-f7a63c64-b93f-44b6-b93b-f9264411b2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379756298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2379756298
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.4075479985
Short name T579
Test name
Test status
Simulation time 44515678 ps
CPU time 0.77 seconds
Started Jul 17 07:48:40 PM PDT 24
Finished Jul 17 07:48:44 PM PDT 24
Peak memory 206616 kb
Host smart-aede259d-51d4-4765-afec-b3d9409e8c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075479985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.4075479985
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.4048424581
Short name T789
Test name
Test status
Simulation time 8803807104 ps
CPU time 92.31 seconds
Started Jul 17 07:48:38 PM PDT 24
Finished Jul 17 07:50:13 PM PDT 24
Peak memory 253684 kb
Host smart-f9a7c382-9f8b-4e45-805c-3b1e3e30daef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048424581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.4048424581
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2546434639
Short name T839
Test name
Test status
Simulation time 19394628488 ps
CPU time 40.78 seconds
Started Jul 17 07:48:37 PM PDT 24
Finished Jul 17 07:49:19 PM PDT 24
Peak memory 239912 kb
Host smart-5ee1800e-3aa4-449b-bd8f-dd4d68d28b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546434639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2546434639
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.1591684475
Short name T7
Test name
Test status
Simulation time 21387377006 ps
CPU time 24.48 seconds
Started Jul 17 07:48:37 PM PDT 24
Finished Jul 17 07:49:04 PM PDT 24
Peak memory 224676 kb
Host smart-b50603d4-ebd2-4ca1-92a4-598de118434d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591684475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.1591684475
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.35194163
Short name T299
Test name
Test status
Simulation time 427502546 ps
CPU time 10.97 seconds
Started Jul 17 07:48:41 PM PDT 24
Finished Jul 17 07:48:55 PM PDT 24
Peak memory 232700 kb
Host smart-4e845168-f60d-4de9-bd7b-7b118614b9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35194163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.35194163
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.2315414235
Short name T227
Test name
Test status
Simulation time 5039139987 ps
CPU time 20.43 seconds
Started Jul 17 07:48:40 PM PDT 24
Finished Jul 17 07:49:04 PM PDT 24
Peak memory 250036 kb
Host smart-218aeb62-43e7-4946-a756-5157dda5fadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315414235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.2315414235
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.500249263
Short name T346
Test name
Test status
Simulation time 3931587079 ps
CPU time 12.5 seconds
Started Jul 17 07:48:39 PM PDT 24
Finished Jul 17 07:48:55 PM PDT 24
Peak memory 232832 kb
Host smart-ca338173-b046-4f5e-b58a-ecb9cd2acffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500249263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.500249263
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3257749332
Short name T888
Test name
Test status
Simulation time 12216506013 ps
CPU time 30.12 seconds
Started Jul 17 07:48:39 PM PDT 24
Finished Jul 17 07:49:12 PM PDT 24
Peak memory 224620 kb
Host smart-39403143-9dc3-4c3e-96bf-373351acfb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257749332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3257749332
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1210800943
Short name T906
Test name
Test status
Simulation time 4206566756 ps
CPU time 14.52 seconds
Started Jul 17 07:48:36 PM PDT 24
Finished Jul 17 07:48:52 PM PDT 24
Peak memory 232764 kb
Host smart-9d4f1893-02e6-4edf-81f2-96ca09674b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210800943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1210800943
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1801361490
Short name T516
Test name
Test status
Simulation time 43947553463 ps
CPU time 25.67 seconds
Started Jul 17 07:48:37 PM PDT 24
Finished Jul 17 07:49:05 PM PDT 24
Peak memory 224512 kb
Host smart-b09d4e71-804c-4563-84bd-8e41765669b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801361490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1801361490
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2463749694
Short name T847
Test name
Test status
Simulation time 416450746 ps
CPU time 4.04 seconds
Started Jul 17 07:48:37 PM PDT 24
Finished Jul 17 07:48:43 PM PDT 24
Peak memory 223068 kb
Host smart-23c0d4b8-f89e-4371-b625-3b74e67e71e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2463749694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2463749694
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.384205736
Short name T309
Test name
Test status
Simulation time 1319598316 ps
CPU time 7.55 seconds
Started Jul 17 07:48:38 PM PDT 24
Finished Jul 17 07:48:48 PM PDT 24
Peak memory 216248 kb
Host smart-7ecccb89-0e49-4065-b929-c0c8b85bd8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384205736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.384205736
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3121280276
Short name T94
Test name
Test status
Simulation time 1841511160 ps
CPU time 4.63 seconds
Started Jul 17 07:48:36 PM PDT 24
Finished Jul 17 07:48:42 PM PDT 24
Peak memory 216200 kb
Host smart-5bffb90f-c5fc-4dbd-bf22-51556adf5077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121280276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3121280276
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1702729404
Short name T590
Test name
Test status
Simulation time 46856024 ps
CPU time 1.02 seconds
Started Jul 17 07:48:38 PM PDT 24
Finished Jul 17 07:48:42 PM PDT 24
Peak memory 207308 kb
Host smart-7efa7f7e-5b18-4d02-9eb6-a22c5cd68214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702729404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1702729404
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.4182543385
Short name T816
Test name
Test status
Simulation time 10992063 ps
CPU time 0.68 seconds
Started Jul 17 07:48:39 PM PDT 24
Finished Jul 17 07:48:43 PM PDT 24
Peak memory 205632 kb
Host smart-9820ec08-95a7-422c-ba3a-d65ea86f22ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182543385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.4182543385
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.92418673
Short name T472
Test name
Test status
Simulation time 151119317 ps
CPU time 2.72 seconds
Started Jul 17 07:48:39 PM PDT 24
Finished Jul 17 07:48:45 PM PDT 24
Peak memory 224484 kb
Host smart-114b1fd2-1b44-4e44-9ff4-f52b0a584ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92418673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.92418673
Directory /workspace/9.spi_device_upload/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%