Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2706218	1			T1	1876		T2	13304		T3	1241
all_values[1]	2706218	1			T1	1876		T2	13304		T3	1241
all_values[2]	2706218	1			T1	1876		T2	13304		T3	1241
all_values[3]	2706218	1			T1	1876		T2	13304		T3	1241
all_values[4]	2706218	1			T1	1876		T2	13304		T3	1241
all_values[5]	2706218	1			T1	1876		T2	13304		T3	1241
all_values[6]	2706218	1			T1	1876		T2	13304		T3	1241
all_values[7]	2706218	1			T1	1876		T2	13304		T3	1241

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21075079

1

T1

15008

T2

106432

T3

9928

auto[1]

574665

1

T13

55

T14

71

T16

70

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21623217

1

T1

14777

T2

106403

T3

9928

auto[1]

26527

1

T1

231

T2

29

T8

4

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2637527	1			T1	1756		T2	13277		T3	1241
all_values[0]	auto[0]	auto[1]	12758	1			T1	120		T2	27		T8	4
all_values[0]	auto[1]	auto[0]	55367	1			T13	6		T14	5		T16	7
all_values[0]	auto[1]	auto[1]	566	1			T13	3		T14	6		T16	6
all_values[1]	auto[0]	auto[0]	2590731	1			T1	1782		T2	13303		T3	1241
all_values[1]	auto[0]	auto[1]	7768	1			T1	94		T2	1		T13	51
all_values[1]	auto[1]	auto[0]	107227	1			T13	5		T14	3		T16	6
all_values[1]	auto[1]	auto[1]	492	1			T13	2		T14	7		T16	1
all_values[2]	auto[0]	auto[0]	2639956	1			T1	1859		T2	13303		T3	1241
all_values[2]	auto[0]	auto[1]	2955	1			T1	17		T2	1		T13	40
all_values[2]	auto[1]	auto[0]	63102	1			T13	10		T14	5		T17	2
all_values[2]	auto[1]	auto[1]	205	1			T14	3		T16	2		T17	1
all_values[3]	auto[0]	auto[0]	2680225	1			T1	1876		T2	13304		T3	1241
all_values[3]	auto[0]	auto[1]	205	1			T13	2		T16	3		T17	4
all_values[3]	auto[1]	auto[0]	25627	1			T13	1		T14	9		T16	6
all_values[3]	auto[1]	auto[1]	161	1			T14	4		T16	2		T18	2
all_values[4]	auto[0]	auto[0]	2652145	1			T1	1876		T2	13304		T3	1241
all_values[4]	auto[0]	auto[1]	197	1			T13	4		T14	2		T16	2
all_values[4]	auto[1]	auto[0]	53694	1			T13	4		T14	6		T16	8
all_values[4]	auto[1]	auto[1]	182	1			T13	1		T14	6		T16	5
all_values[5]	auto[0]	auto[0]	2623976	1			T1	1876		T2	13304		T3	1241
all_values[5]	auto[0]	auto[1]	181	1			T13	2		T14	6		T16	3
all_values[5]	auto[1]	auto[0]	81909	1			T13	8		T14	6		T16	5
all_values[5]	auto[1]	auto[1]	152	1			T13	3		T14	2		T16	3
all_values[6]	auto[0]	auto[0]	2584786	1			T1	1876		T2	13304		T3	1241
all_values[6]	auto[0]	auto[1]	188	1			T13	3		T14	2		T16	2
all_values[6]	auto[1]	auto[0]	121076	1			T13	3		T14	3		T16	6
all_values[6]	auto[1]	auto[1]	168	1			T14	3		T16	6		T18	3
all_values[7]	auto[0]	auto[0]	2641307	1			T1	1876		T2	13304		T3	1241
all_values[7]	auto[0]	auto[1]	174	1			T13	3		T14	5		T16	4
all_values[7]	auto[1]	auto[0]	64562	1			T13	7		T14	2		T16	2
all_values[7]	auto[1]	auto[1]	175	1			T13	2		T14	1		T16	5