Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	32930	1			T1	79		T2	58		T3	73
auto[SpiFlashAddrCfg]	7633	1			T1	12		T2	29		T3	24
auto[SpiFlashAddr3b]	9165	1			T1	19		T2	29		T3	35
auto[SpiFlashAddr4b]	7910	1			T1	16		T2	29		T3	28

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34094

1

T1

88

T2

88

T3

89

auto[1]

23544

1

T1

38

T2

57

T3

71

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29461

1

T1

42

T2

76

T3

82

auto[1]

28177

1

T1

84

T2

69

T3

78

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	37624	1			T1	101		T2	74		T3	92
values[1]	1089	1			T1	2		T2	5		T3	1
values[2]	1548	1			T1	1		T2	1		T3	10
values[3]	1508	1			T1	3		T2	3		T3	10
values[4]	1522	1			T1	2		T2	2		T3	1
values[5]	1436	1			T2	9		T5	9		T8	3
values[6]	1438	1			T1	6		T2	10		T3	6
values[7]	1474	1			T1	2		T2	5		T3	6
values[8]	9999	1			T1	9		T2	36		T3	34

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33484

1

T4

8

T5

694

T7

2

auto[1]

24154

1

T1

126

T2

145

T3

160

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

54461

1

T1

118

T2

135

T3

139

write

3177

1

T1

8

T2

10

T3

21

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19305

1

T1

40

T2

82

T3

71

valids[0x1]

38333

1

T1

86

T2

63

T3

89

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1493	1			T1	4		T2	3		T3	6
internal_process_ops[0x5a]	1600	1			T1	4		T2	7		T3	12
internal_process_ops[0x05]	19303	1			T1	47		T2	11		T3	6
internal_process_ops[0x35]	1491	1			T1	1		T2	10		T3	6
internal_process_ops[0x15]	1577	1			T1	2		T2	2		T3	11
internal_process_ops[0x03]	1106	1			T2	2		T5	4		T8	3
internal_process_ops[0x0b]	1092	1			T1	1		T2	1		T3	2
internal_process_ops[0x3b]	1180	1			T1	1		T2	4		T4	2
internal_process_ops[0x6b]	1116	1			T1	1		T2	5		T3	3
internal_process_ops[0xbb]	1055	1			T2	7		T3	4		T5	10
internal_process_ops[0xeb]	1144	1			T2	1		T3	1		T5	8

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56098

1

T1

121

T2

136

T3

159

auto[1]

1540

1

T1

5

T2

9

T3

1

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55329

1

T1

116

T2

142

T3

140

auto[1]

2309

1

T1

10

T2

3

T3

20

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12018

1

T4

4

T5

300

T8

12

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6372

1

T5

231

T8

8

T13

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2270

1

T5

28

T7

2

T8

14

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1897

1

T5

10

T8

5

T13

3

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2666

1

T5

31

T8

7

T45

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2267

1

T5

33

T8

4

T13

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2293

1

T4

4

T5

31

T8

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2035

1

T5

14

T8

4

T13

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

122

1

T8

1

T15

1

T41

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

107

1

T15

1

T41

3

T39

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

95

1

T5

1

T8

1

T40

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

110

1

T5

2

T13

1

T15

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

123

1

T5

1

T40

1

T163

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

78

1

T40

2

T15

1

T18

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

99

1

T40

1

T41

2

T42

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

101

1

T5

1

T39

1

T18

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

119

1

T40

2

T15

2

T164

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

79

1

T5

5

T40

2

T15

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

93

1

T5

1

T8

1

T15

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

101

1

T15

6

T20

1

T21

5

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

129

1

T5

2

T15

5

T42

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

105

1

T8

2

T40

2

T15

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

97

1

T5

1

T40

1

T15

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

108

1

T5

2

T40

3

T15

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8654

1

T1

69

T2

40

T3

44

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5092

1

T1

7

T2

13

T3

18

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1413

1

T1

4

T2

10

T3

12

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1278

1

T1

8

T2

14

T3

10

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1773

1

T1

9

T2

19

T3

20

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1682

1

T1

7

T2

10

T3

13

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1413

1

T1

5

T2

18

T3

6

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1338

1

T1

9

T2

11

T3

16

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

96

1

T3

5

T13

3

T91

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

68

1

T113

3

T165

3

T150

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

105

1

T1

2

T3

6

T27

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

91

1

T1

1

T2

5

T13

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

107

1

T3

1

T113

1

T91

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

83

1

T2

1

T27

1

T113

7

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

98

1

T2

1

T3

1

T13

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

86

1

T2

3

T20

2

T166

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

77

1

T13

1

T27

3

T53

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

98

1

T13

4

T27

9

T113

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

97

1

T3

2

T27

2

T113

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

113

1

T1

3

T13

1

T27

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

88

1

T3

1

T113

1

T17

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

115

1

T1

1

T13

1

T27

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

92

1

T1

1

T3

4

T167

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

97

1

T3

1

T113

3

T167

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4077	1			T5	49		T8	6		T13	3
auto[0]	values[0]	valids[0x1]	17331	1			T4	4		T5	506		T8	18
auto[0]	values[1]	valids[0x1]	607	1			T5	7		T8	3		T13	2
auto[0]	values[2]	valids[0x0]	611	1			T5	9		T46	6		T93	4
auto[0]	values[2]	valids[0x1]	369	1			T5	1		T13	2		T28	2
auto[0]	values[3]	valids[0x0]	553	1			T5	14		T8	1		T93	2
auto[0]	values[3]	valids[0x1]	378	1			T5	3		T8	1		T46	4
auto[0]	values[4]	valids[0x0]	596	1			T5	4		T8	1		T30	2
auto[0]	values[4]	valids[0x1]	359	1			T5	6		T8	2		T30	2
auto[0]	values[5]	valids[0x0]	558	1			T5	6		T40	3		T15	7
auto[0]	values[5]	valids[0x1]	299	1			T5	3		T8	3		T144	6
auto[0]	values[6]	valids[0x0]	537	1			T4	2		T5	6		T8	3
auto[0]	values[6]	valids[0x1]	320	1			T5	3		T40	1		T15	5
auto[0]	values[7]	valids[0x0]	587	1			T5	11		T8	1		T28	2
auto[0]	values[7]	valids[0x1]	300	1			T4	2		T45	2		T144	2
auto[0]	values[8]	valids[0x0]	3904	1			T5	42		T7	2		T8	14
auto[0]	values[8]	valids[0x1]	2098	1			T5	24		T8	10		T93	2
auto[1]	values[0]	valids[0x0]	3588	1			T1	26		T2	30		T3	34
auto[1]	values[0]	valids[0x1]	12628	1			T1	75		T2	44		T3	58
auto[1]	values[1]	valids[0x1]	482	1			T1	2		T2	5		T3	1
auto[1]	values[2]	valids[0x0]	317	1			T1	1		T2	1		T3	5
auto[1]	values[2]	valids[0x1]	251	1			T3	5		T13	4		T27	2
auto[1]	values[3]	valids[0x0]	317	1			T1	2		T2	3		T3	5
auto[1]	values[3]	valids[0x1]	260	1			T1	1		T3	5		T13	3
auto[1]	values[4]	valids[0x0]	312	1			T1	1		T2	1		T3	1
auto[1]	values[4]	valids[0x1]	255	1			T1	1		T2	1		T13	3
auto[1]	values[5]	valids[0x0]	327	1			T2	9		T13	2		T27	4
auto[1]	values[5]	valids[0x1]	252	1			T27	4		T113	5		T90	1
auto[1]	values[6]	valids[0x0]	369	1			T1	5		T2	9		T3	3
auto[1]	values[6]	valids[0x1]	212	1			T1	1		T2	1		T3	3
auto[1]	values[7]	valids[0x0]	342	1			T2	3		T3	3		T13	5
auto[1]	values[7]	valids[0x1]	245	1			T1	2		T2	2		T3	3
auto[1]	values[8]	valids[0x0]	2310	1			T1	5		T2	26		T3	20
auto[1]	values[8]	valids[0x1]	1687	1			T1	4		T2	10		T3	14