Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3241744

1

T1

1330

T2

5488

T3

10375

auto[1]

30387

1

T1

46

T2

5

T3

212

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

930867

1

T1

40

T2

40

T3

391

auto[1]

2341264

1

T1

1336

T2

5453

T3

10196

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	585084	1			T1	32		T2	1031		T3	3521
auto[524288:1048575]	411709	1			T1	20		T2	451		T3	17
auto[1048576:1572863]	383925	1			T2	1164		T3	3468		T5	4836
auto[1572864:2097151]	342530	1			T1	6		T2	1443		T3	1353
auto[2097152:2621439]	394023	1			T2	641		T3	173		T5	12266
auto[2621440:3145727]	383507	1			T1	1055		T3	830		T5	515
auto[3145728:3670015]	399103	1			T2	763		T3	279		T5	134
auto[3670016:4194303]	372250	1			T1	263		T3	946		T5	5304

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2378487

1

T1

1374

T2

5493

T3

10573

auto[1]

893644

1

T1

2

T3

14

T5

12

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2825362

1

T1

1376

T2

4977

T3

9110

auto[1]

446769

1

T2

516

T3

1477

T5

3544

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	175443	1			T1	10		T2	4		T3	40
auto[0]	auto[0]	auto[0:524287]	auto[1]	354084	1			T1	3		T2	1025		T3	3469
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	139840	1			T1	5		T2	1		T3	14
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	216457	1			T1	3		T2	450		T5	257
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	82573	1			T2	7		T3	15		T5	6
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	220671	1			T2	1153		T3	2921		T5	2449
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	99157	1			T1	4		T2	10		T3	35
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	181666	1			T1	1		T2	1176		T3	386
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	90073	1			T2	1		T3	34		T5	20
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	240204	1			T2	640		T3	1		T5	12093
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	85143	1			T1	6		T3	26		T5	3
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	249613	1			T1	1036		T3	768		T5	512
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	133785	1			T2	10		T3	8		T5	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	221860	1			T2	495		T3	256		T5	128
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	113579	1			T1	5		T3	67		T5	10
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	196247	1			T1	257		T3	866		T5	5175
auto[0]	auto[1]	auto[0:524287]	auto[0]	1340	1			T3	3		T5	11		T13	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	51015	1			T5	1039		T13	2		T40	1439
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	883	1			T13	5		T27	5		T15	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	51366	1			T13	513		T27	1		T15	6
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1441	1			T2	3		T3	8		T5	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	72948	1			T3	512		T5	2352		T40	2516
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	903	1			T2	1		T3	25		T8	4
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	57771	1			T2	256		T3	896		T8	257
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	599	1			T3	8		T5	1		T27	7
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	59699	1			T27	1925		T15	1924		T113	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	647	1			T3	17		T87	2		T15	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	44083	1			T15	1770		T41	5		T17	387
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	767	1			T111	3		T87	15		T15	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	40253	1			T2	256		T5	4		T41	723
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	869	1			T5	2		T13	2		T113	4
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	56765	1			T5	2		T13	1300		T15	2
auto[1]	auto[0]	auto[0:524287]	auto[0]	367	1			T1	3		T2	1		T3	6
auto[1]	auto[0]	auto[0:524287]	auto[1]	2391	1			T1	16		T2	1		T5	63
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	390	1			T1	3		T3	3		T5	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1990	1			T1	9		T13	8		T27	5
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	444	1			T2	1		T3	12		T5	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	5138	1			T5	27		T40	14		T41	6
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	336	1			T1	1		T3	9		T27	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1737	1			T27	2		T15	10		T39	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	371	1			T3	12		T5	5		T27	5
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2486	1			T3	118		T5	147		T27	15
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	371	1			T1	2		T3	16		T27	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	3293	1			T1	11		T27	11		T40	14
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	324	1			T2	1		T3	12		T27	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1676	1			T2	1		T3	3		T27	6
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	392	1			T1	1		T3	13		T5	4
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	3261	1			T5	53		T13	3		T27	72
auto[1]	auto[1]	auto[0:524287]	auto[0]	63	1			T3	3		T5	4		T40	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	381	1			T5	70		T40	13		T21	5
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	94	1			T13	1		T15	1		T41	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	689	1			T15	1		T41	33		T90	34
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	141	1			T15	2		T42	1		T90	6
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	569	1			T15	40		T42	2		T167	34
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	81	1			T3	2		T8	1		T27	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	879	1			T8	1		T27	4		T40	29
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	122	1			T27	3		T15	1		T113	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	469	1			T27	24		T15	13		T113	6
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	79	1			T3	3		T17	3		T39	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	278	1			T17	4		T20	9		T192	12
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	111	1			T167	1		T20	3		T174	7
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	327	1			T167	19		T20	4		T222	10
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	139	1			T5	2		T13	2		T15	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	998	1			T5	56		T13	6		T15	3

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1909106	1			T1	1329		T2	4972		T3	8906
auto[0]	auto[0]	auto[1]	891289	1			T1	1		T5	5		T7	1190
auto[0]	auto[1]	auto[0]	439655	1			T2	516		T3	1469		T5	3409
auto[0]	auto[1]	auto[1]	1694	1			T5	3		T27	1		T40	2
auto[1]	auto[0]	auto[0]	24458	1			T1	45		T2	5		T3	192
auto[1]	auto[0]	auto[1]	509	1			T1	1		T3	12		T5	1
auto[1]	auto[1]	auto[0]	5268	1			T3	6		T5	129		T8	2
auto[1]	auto[1]	auto[1]	152	1			T3	2		T5	3		T27	2