Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2706218	1			T1	1876		T2	13304		T3	1241
all_pins[1]	2706218	1			T1	1876		T2	13304		T3	1241
all_pins[2]	2706218	1			T1	1876		T2	13304		T3	1241
all_pins[3]	2706218	1			T1	1876		T2	13304		T3	1241
all_pins[4]	2706218	1			T1	1876		T2	13304		T3	1241
all_pins[5]	2706218	1			T1	1876		T2	13304		T3	1241
all_pins[6]	2706218	1			T1	1876		T2	13304		T3	1241
all_pins[7]	2706218	1			T1	1876		T2	13304		T3	1241

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21526365	1			T1	15008		T2	106432		T3	9928
values[0x1]	123379	1			T13	11		T14	32		T16	30
transitions[0x0=>0x1]	121764	1			T13	9		T14	25		T16	24
transitions[0x1=>0x0]	121775	1			T13	9		T14	25		T16	24

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2705605	1			T1	1876		T2	13304		T3	1241
all_pins[0]	values[0x1]	613	1			T13	3		T14	6		T16	6
all_pins[0]	transitions[0x0=>0x1]	434	1			T13	3		T14	4		T16	6
all_pins[0]	transitions[0x1=>0x0]	353	1			T13	2		T14	5		T16	1
all_pins[1]	values[0x0]	2705686	1			T1	1876		T2	13304		T3	1241
all_pins[1]	values[0x1]	532	1			T13	2		T14	7		T16	1
all_pins[1]	transitions[0x0=>0x1]	478	1			T13	2		T14	5		T16	1
all_pins[1]	transitions[0x1=>0x0]	159	1			T14	1		T16	2		T17	1
all_pins[2]	values[0x0]	2706005	1			T1	1876		T2	13304		T3	1241
all_pins[2]	values[0x1]	213	1			T14	3		T16	2		T17	1
all_pins[2]	transitions[0x0=>0x1]	176	1			T14	2		T16	1		T17	1
all_pins[2]	transitions[0x1=>0x0]	124	1			T14	3		T16	1		T18	2
all_pins[3]	values[0x0]	2706057	1			T1	1876		T2	13304		T3	1241
all_pins[3]	values[0x1]	161	1			T14	4		T16	2		T18	2
all_pins[3]	transitions[0x0=>0x1]	127	1			T14	3		T16	2		T18	2
all_pins[3]	transitions[0x1=>0x0]	148	1			T13	1		T14	5		T16	5
all_pins[4]	values[0x0]	2706036	1			T1	1876		T2	13304		T3	1241
all_pins[4]	values[0x1]	182	1			T13	1		T14	6		T16	5
all_pins[4]	transitions[0x0=>0x1]	146	1			T14	5		T16	4		T18	5
all_pins[4]	transitions[0x1=>0x0]	1317	1			T13	2		T14	1		T16	2
all_pins[5]	values[0x0]	2704865	1			T1	1876		T2	13304		T3	1241
all_pins[5]	values[0x1]	1353	1			T13	3		T14	2		T16	3
all_pins[5]	transitions[0x0=>0x1]	163	1			T13	3		T14	2		T16	1
all_pins[5]	transitions[0x1=>0x0]	118960	1			T14	3		T16	4		T18	3
all_pins[6]	values[0x0]	2586068	1			T1	1876		T2	13304		T3	1241
all_pins[6]	values[0x1]	120150	1			T14	3		T16	6		T18	3
all_pins[6]	transitions[0x0=>0x1]	120116	1			T14	3		T16	6		T18	3
all_pins[6]	transitions[0x1=>0x0]	141	1			T13	2		T14	1		T16	5
all_pins[7]	values[0x0]	2706043	1			T1	1876		T2	13304		T3	1241
all_pins[7]	values[0x1]	175	1			T13	2		T14	1		T16	5
all_pins[7]	transitions[0x0=>0x1]	124	1			T13	1		T14	1		T16	3
all_pins[7]	transitions[0x1=>0x0]	573	1			T13	2		T14	6		T16	4