Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20109

1

T4

8

T5

398

T7

2

auto[1]

13375

1

T5

296

T8

23

T13

11

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3544	1			T5	212		T145	2		T111	4
values[1]	3745	1			T5	20		T8	22		T93	10
values[2]	4292	1			T9	16		T29	6		T40	20
values[3]	4538	1			T5	79		T30	10		T15	118
values[4]	4807	1			T5	131		T144	28		T40	73
values[5]	4095	1			T5	198		T45	12		T40	50
values[6]	4569	1			T4	8		T5	54		T8	41
values[7]	3894	1			T7	2		T46	10		T87	18

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3136	1			T93	10		T40	35		T15	60
values[1]	5953	1			T29	6		T163	8		T15	63
values[2]	4194	1			T5	40		T8	21		T9	16
values[3]	3805	1			T5	72		T28	14		T40	20
values[4]	3922	1			T5	152		T40	128		T111	4
values[5]	4123	1			T4	8		T5	33		T8	22
values[6]	4298	1			T5	271		T7	2		T144	28
values[7]	4053	1			T5	126		T8	20		T45	12

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	213	1			T18	3		T217	12		T186	12
auto[0]	values[0]	values[1]	269	1			T43	17		T223	12		T192	13
auto[0]	values[0]	values[2]	360	1			T15	16		T41	24		T39	13
auto[0]	values[0]	values[3]	270	1			T5	13		T15	9		T224	6
auto[0]	values[0]	values[4]	314	1			T111	4		T15	22		T41	45
auto[0]	values[0]	values[5]	230	1			T5	27		T145	2		T18	7
auto[0]	values[0]	values[6]	251	1			T5	121		T15	14		T20	20
auto[0]	values[0]	values[7]	283	1			T176	14		T58	11		T174	10
auto[0]	values[1]	values[0]	188	1			T93	10		T225	73		T226	24
auto[0]	values[1]	values[1]	277	1			T199	9		T190	46		T80	8
auto[0]	values[1]	values[2]	376	1			T5	10		T13	9		T44	12
auto[0]	values[1]	values[3]	304	1			T39	26		T20	17		T192	13
auto[0]	values[1]	values[4]	387	1			T176	10		T184	33		T179	91
auto[0]	values[1]	values[5]	259	1			T8	16		T15	11		T197	10
auto[0]	values[1]	values[6]	426	1			T40	13		T15	25		T39	8
auto[0]	values[1]	values[7]	129	1			T199	7		T174	17		T227	12
auto[0]	values[2]	values[0]	248	1			T228	6		T20	12		T229	10
auto[0]	values[2]	values[1]	465	1			T43	12		T56	2		T190	13
auto[0]	values[2]	values[2]	332	1			T9	16		T15	14		T42	15
auto[0]	values[2]	values[3]	294	1			T201	25		T194	13		T210	9
auto[0]	values[2]	values[4]	382	1			T40	8		T230	24		T21	8
auto[0]	values[2]	values[5]	281	1			T15	19		T18	11		T192	76
auto[0]	values[2]	values[6]	297	1			T231	24		T192	9		T47	14
auto[0]	values[2]	values[7]	277	1			T15	12		T39	7		T190	13
auto[0]	values[3]	values[0]	190	1			T15	20		T55	12		T190	11
auto[0]	values[3]	values[1]	655	1			T39	10		T52	8		T185	49
auto[0]	values[3]	values[2]	227	1			T15	14		T199	51		T232	10
auto[0]	values[3]	values[3]	191	1			T15	11		T39	15		T192	10
auto[0]	values[3]	values[4]	257	1			T5	68		T20	16		T174	14
auto[0]	values[3]	values[5]	340	1			T18	12		T20	29		T52	17
auto[0]	values[3]	values[6]	362	1			T15	24		T21	17		T47	11
auto[0]	values[3]	values[7]	433	1			T39	18		T43	14		T216	11
auto[0]	values[4]	values[0]	247	1			T40	9		T192	14		T184	14
auto[0]	values[4]	values[1]	545	1			T163	8		T41	12		T18	25
auto[0]	values[4]	values[2]	181	1			T42	13		T176	12		T174	5
auto[0]	values[4]	values[3]	317	1			T41	44		T18	10		T200	14
auto[0]	values[4]	values[4]	327	1			T5	50		T15	7		T214	14
auto[0]	values[4]	values[5]	343	1			T40	15		T18	13		T52	33
auto[0]	values[4]	values[6]	321	1			T144	28		T41	31		T43	17
auto[0]	values[4]	values[7]	523	1			T5	15		T20	31		T52	37
auto[0]	values[5]	values[0]	270	1			T15	12		T43	17		T233	10
auto[0]	values[5]	values[1]	429	1			T15	36		T18	6		T234	2
auto[0]	values[5]	values[2]	221	1			T5	11		T39	14		T18	14
auto[0]	values[5]	values[3]	238	1			T5	6		T40	10		T15	9
auto[0]	values[5]	values[4]	232	1			T5	11		T40	23		T41	16
auto[0]	values[5]	values[5]	239	1			T15	18		T20	23		T190	14
auto[0]	values[5]	values[6]	344	1			T5	12		T15	14		T18	13
auto[0]	values[5]	values[7]	418	1			T5	42		T45	12		T41	14
auto[0]	values[6]	values[0]	183	1			T41	7		T192	9		T184	12
auto[0]	values[6]	values[1]	568	1			T18	17		T52	4		T235	41
auto[0]	values[6]	values[2]	271	1			T8	13		T21	13		T47	15
auto[0]	values[6]	values[3]	366	1			T28	14		T184	26		T190	15
auto[0]	values[6]	values[4]	397	1			T40	68		T92	16		T211	16
auto[0]	values[6]	values[5]	297	1			T4	8		T39	18		T21	6
auto[0]	values[6]	values[6]	353	1			T5	12		T216	23		T47	12
auto[0]	values[6]	values[7]	344	1			T8	11		T42	12		T205	14
auto[0]	values[7]	values[0]	276	1			T18	10		T21	23		T199	15
auto[0]	values[7]	values[1]	450	1			T39	10		T20	11		T192	10
auto[0]	values[7]	values[2]	354	1			T15	25		T164	26		T18	10
auto[0]	values[7]	values[3]	368	1			T185	51		T186	64		T201	17
auto[0]	values[7]	values[4]	214	1			T233	8		T201	28		T202	29
auto[0]	values[7]	values[5]	335	1			T46	10		T87	18		T236	20
auto[0]	values[7]	values[6]	197	1			T7	2		T237	2		T238	6
auto[0]	values[7]	values[7]	174	1			T21	12		T216	16		T191	34
auto[1]	values[0]	values[0]	130	1			T18	19		T186	8		T239	10
auto[1]	values[0]	values[1]	154	1			T43	3		T192	7		T240	9
auto[1]	values[0]	values[2]	219	1			T15	49		T41	8		T39	10
auto[1]	values[0]	values[3]	150	1			T5	39		T15	11		T80	11
auto[1]	values[0]	values[4]	190	1			T15	71		T41	9		T233	6
auto[1]	values[0]	values[5]	109	1			T5	6		T18	13		T174	2
auto[1]	values[0]	values[6]	209	1			T5	6		T15	6		T20	10
auto[1]	values[0]	values[7]	193	1			T176	6		T58	9		T174	10
auto[1]	values[1]	values[0]	104	1			T218	16		T225	10		T241	6
auto[1]	values[1]	values[1]	267	1			T199	13		T190	12		T80	12
auto[1]	values[1]	values[2]	184	1			T5	10		T13	11		T44	36
auto[1]	values[1]	values[3]	192	1			T39	5		T20	3		T242	14
auto[1]	values[1]	values[4]	199	1			T176	12		T184	17		T243	16
auto[1]	values[1]	values[5]	132	1			T8	6		T15	9		T202	6
auto[1]	values[1]	values[6]	216	1			T40	7		T15	5		T39	12
auto[1]	values[1]	values[7]	105	1			T199	13		T174	3		T227	8
auto[1]	values[2]	values[0]	173	1			T20	8		T244	10		T207	9
auto[1]	values[2]	values[1]	284	1			T29	6		T43	8		T245	20
auto[1]	values[2]	values[2]	334	1			T15	20		T42	5		T44	9
auto[1]	values[2]	values[3]	230	1			T198	6		T201	18		T194	7
auto[1]	values[2]	values[4]	170	1			T40	12		T21	12		T192	7
auto[1]	values[2]	values[5]	119	1			T15	21		T18	9		T192	8
auto[1]	values[2]	values[6]	229	1			T192	18		T47	8		T227	4
auto[1]	values[2]	values[7]	177	1			T15	8		T39	19		T190	7
auto[1]	values[3]	values[0]	159	1			T15	20		T246	2		T190	9
auto[1]	values[3]	values[1]	422	1			T39	10		T52	12		T185	10
auto[1]	values[3]	values[2]	227	1			T15	6		T199	5		T232	15
auto[1]	values[3]	values[3]	134	1			T15	19		T39	5		T192	10
auto[1]	values[3]	values[4]	148	1			T5	11		T20	6		T174	6
auto[1]	values[3]	values[5]	501	1			T30	10		T18	8		T20	5
auto[1]	values[3]	values[6]	92	1			T15	4		T21	3		T47	9
auto[1]	values[3]	values[7]	200	1			T39	3		T43	6		T216	9
auto[1]	values[4]	values[0]	191	1			T40	26		T192	7		T184	7
auto[1]	values[4]	values[1]	381	1			T41	29		T18	20		T43	8
auto[1]	values[4]	values[2]	251	1			T42	9		T176	8		T174	15
auto[1]	values[4]	values[3]	243	1			T41	13		T18	10		T200	6
auto[1]	values[4]	values[4]	182	1			T5	3		T15	13		T39	8
auto[1]	values[4]	values[5]	228	1			T40	23		T18	7		T52	6
auto[1]	values[4]	values[6]	240	1			T41	3		T43	7		T247	8
auto[1]	values[4]	values[7]	287	1			T5	63		T20	19		T52	13
auto[1]	values[5]	values[0]	163	1			T15	8		T43	3		T233	10
auto[1]	values[5]	values[1]	254	1			T15	27		T18	15		T203	9
auto[1]	values[5]	values[2]	152	1			T5	9		T39	6		T18	6
auto[1]	values[5]	values[3]	187	1			T5	14		T40	10		T15	17
auto[1]	values[5]	values[4]	192	1			T5	9		T40	7		T41	9
auto[1]	values[5]	values[5]	281	1			T15	4		T20	49		T248	4
auto[1]	values[5]	values[6]	218	1			T5	78		T15	6		T18	7
auto[1]	values[5]	values[7]	257	1			T5	6		T41	8		T18	50
auto[1]	values[6]	values[0]	134	1			T41	15		T192	36		T184	8
auto[1]	values[6]	values[1]	289	1			T18	5		T52	16		T192	4
auto[1]	values[6]	values[2]	331	1			T8	8		T21	40		T47	7
auto[1]	values[6]	values[3]	206	1			T184	18		T190	5		T209	37
auto[1]	values[6]	values[4]	141	1			T40	10		T39	7		T43	4
auto[1]	values[6]	values[5]	286	1			T39	7		T21	26		T199	29
auto[1]	values[6]	values[6]	239	1			T5	42		T216	9		T47	8
auto[1]	values[6]	values[7]	164	1			T8	9		T42	11		T21	8
auto[1]	values[7]	values[0]	267	1			T18	10		T21	39		T199	7
auto[1]	values[7]	values[1]	244	1			T39	12		T249	16		T20	9
auto[1]	values[7]	values[2]	174	1			T15	5		T18	10		T21	7
auto[1]	values[7]	values[3]	115	1			T185	9		T186	6		T201	3
auto[1]	values[7]	values[4]	190	1			T233	12		T201	12		T202	9
auto[1]	values[7]	values[5]	143	1			T20	7		T58	5		T250	8
auto[1]	values[7]	values[6]	304	1			T251	6		T252	7		T154	8
auto[1]	values[7]	values[7]	89	1			T21	28		T216	4		T191	8