Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	468	1			T5	7		T7	2		T145	2
auto[ReadAddrCrossIntoMailbox]	309	1			T5	3		T13	1		T40	8
auto[ReadAddrCrossOutOfMailbox]	344	1			T5	3		T9	4		T40	6
auto[ReadAddrCrossAllMailbox]	241	1			T5	5		T9	6		T40	3
auto[ReadAddrOutsideMailbox]	3866	1			T4	2		T5	35		T8	13

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2521

1

T4

1

T5

23

T7

1

auto[1]

2707

1

T4

1

T5

30

T7

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	871	1			T5	4		T8	3		T9	6
read_ops[0x0b]	837	1			T5	6		T8	1		T13	1
read_ops[0x3b]	916	1			T4	2		T5	13		T8	2
read_ops[0x6b]	886	1			T5	12		T7	2		T8	3
read_ops[0xbb]	805	1			T5	10		T8	2		T40	12
read_ops[0xeb]	913	1			T5	8		T8	2		T46	6

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	55	1			T15	1		T92	3		T39	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T15	1		T92	3		T21	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T13	1		T15	1		T39	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T5	1		T21	1		T192	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T9	1		T15	2		T20	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T9	1		T40	1		T200	3
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T5	1		T9	2		T39	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T9	2		T199	2		T174	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	304	1			T5	1		T8	3		T46	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	351	1			T5	1		T46	2		T40	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	44	1			T41	1		T92	1		T21	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T40	1		T15	1		T92	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T40	1		T20	1		T174	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T40	1		T192	2		T184	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T40	1		T41	1		T18	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T18	3		T43	1		T233	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T41	1		T233	1		T58	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T40	1		T39	1		T20	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	283	1			T5	1		T8	1		T13	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	318	1			T5	5		T40	2		T15	9
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T92	2		T18	2		T21	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T5	1		T92	2		T18	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T20	1		T174	1		T192	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T5	1		T18	1		T20	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T9	1		T39	1		T21	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	40	1			T5	2		T9	1		T15	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T9	1		T39	1		T184	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T5	1		T9	1		T42	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	347	1			T4	1		T5	6		T8	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	335	1			T4	1		T5	2		T9	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	44	1			T5	2		T7	1		T40	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T5	1		T7	1		T15	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T5	1		T40	1		T58	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T15	1		T43	1		T209	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T5	1		T40	1		T42	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T21	1		T192	1		T253	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	27	1			T5	1		T15	2		T18	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T18	1		T192	1		T209	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	293	1			T5	3		T13	2		T28	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	354	1			T5	3		T8	3		T28	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T40	3		T214	1		T18	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T5	2		T15	1		T214	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	36	1			T40	5		T15	1		T42	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T199	1		T216	2		T192	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T40	1		T41	1		T214	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	35	1			T41	1		T214	1		T21	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T40	1		T18	1		T176	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T5	1		T15	1		T58	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	286	1			T5	5		T8	2		T40	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	297	1			T5	2		T40	1		T15	9
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	43	1			T5	1		T145	1		T15	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T145	1		T15	1		T39	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T41	1		T18	1		T20	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T15	2		T41	1		T18	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T40	1		T15	1		T18	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T40	1		T15	2		T41	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T18	1		T209	1		T194	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T5	1		T40	1		T15	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	339	1			T46	3		T144	2		T40	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	359	1			T5	6		T8	2		T46	3