Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4118	1			T5	127		T40	35		T15	125
values[1]	4890	1			T5	99		T8	21		T46	10
values[2]	4540	1			T5	120		T8	22		T30	10
values[3]	3271	1			T4	8		T5	163		T7	2
values[4]	3925	1			T5	33		T45	12		T93	10
values[5]	4619	1			T5	78		T144	28		T13	20
values[6]	4086	1			T40	40		T15	84		T39	26
values[7]	4035	1			T5	74		T8	20		T9	16

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3998	1			T5	167		T28	14		T40	78
values[1]	4973	1			T45	12		T40	35		T15	131
values[2]	4204	1			T5	20		T8	22		T145	2
values[3]	4117	1			T5	53		T9	16		T144	28
values[4]	3851	1			T5	78		T8	20		T46	10
values[5]	3988	1			T4	8		T5	169		T8	21
values[6]	4535	1			T5	154		T13	20		T40	30
values[7]	3818	1			T5	53		T7	2		T40	58

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32695

1

T4

8

T5

684

T7

2

auto[1]

789

1

T5

10

T8

2

T13

1

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	841	1			T5	125		T15	20		T41	22
auto[0]	values[0]	values[1]	903	1			T40	34		T15	65		T41	56
auto[0]	values[0]	values[2]	421	1			T246	2		T199	20		T213	20
auto[0]	values[0]	values[3]	369	1			T15	20		T39	22		T216	16
auto[0]	values[0]	values[4]	298	1			T41	34		T164	26		T190	48
auto[0]	values[0]	values[5]	425	1			T18	20		T199	35		T186	84
auto[0]	values[0]	values[6]	472	1			T15	20		T39	20		T20	34
auto[0]	values[0]	values[7]	301	1			T174	16		T201	20		T252	20
auto[0]	values[1]	values[0]	441	1			T18	45		T58	20		T200	19
auto[0]	values[1]	values[1]	764	1			T15	26		T20	52		T52	20
auto[0]	values[1]	values[2]	614	1			T5	20		T41	24		T42	23
auto[0]	values[1]	values[3]	540	1			T18	20		T237	2		T231	24
auto[0]	values[1]	values[4]	492	1			T46	10		T163	8		T41	21
auto[0]	values[1]	values[5]	567	1			T5	79		T8	19		T233	20
auto[0]	values[1]	values[6]	783	1			T40	30		T18	21		T43	23
auto[0]	values[1]	values[7]	578	1			T192	28		T184	20		T47	22
auto[0]	values[2]	values[0]	365	1			T39	21		T52	24		T192	29
auto[0]	values[2]	values[1]	655	1			T39	25		T58	20		T254	18
auto[0]	values[2]	values[2]	378	1			T8	22		T43	35		T190	34
auto[0]	values[2]	values[3]	678	1			T30	10		T39	19		T52	39
auto[0]	values[2]	values[4]	551	1			T15	17		T41	30		T43	20
auto[0]	values[2]	values[5]	478	1			T15	30		T18	46		T176	20
auto[0]	values[2]	values[6]	681	1			T5	98		T15	29		T214	14
auto[0]	values[2]	values[7]	664	1			T5	20		T43	20		T20	21
auto[0]	values[3]	values[0]	248	1			T5	20		T197	10		T174	20
auto[0]	values[3]	values[1]	429	1			T15	20		T184	25		T179	69
auto[0]	values[3]	values[2]	647	1			T18	33		T249	16		T20	18
auto[0]	values[3]	values[3]	435	1			T5	53		T15	26		T39	20
auto[0]	values[3]	values[4]	193	1			T234	2		T182	4		T227	19
auto[0]	values[3]	values[5]	623	1			T4	8		T5	88		T29	6
auto[0]	values[3]	values[6]	202	1			T15	20		T42	19		T184	19
auto[0]	values[3]	values[7]	405	1			T7	2		T18	21		T21	29
auto[0]	values[4]	values[0]	512	1			T40	76		T228	6		T245	18
auto[0]	values[4]	values[1]	355	1			T45	12		T18	16		T186	69
auto[0]	values[4]	values[2]	762	1			T216	31		T192	47		T190	36
auto[0]	values[4]	values[3]	463	1			T20	50		T216	31		T88	18
auto[0]	values[4]	values[4]	459	1			T211	16		T21	42		T190	58
auto[0]	values[4]	values[5]	500	1			T93	10		T111	4		T92	16
auto[0]	values[4]	values[6]	381	1			T21	53		T255	4		T202	21
auto[0]	values[4]	values[7]	405	1			T5	33		T40	36		T15	21
auto[0]	values[5]	values[0]	571	1			T28	14		T15	19		T42	22
auto[0]	values[5]	values[1]	577	1			T15	20		T52	20		T21	20
auto[0]	values[5]	values[2]	323	1			T39	21		T215	18		T154	22
auto[0]	values[5]	values[3]	439	1			T144	28		T39	22		T20	19
auto[0]	values[5]	values[4]	823	1			T5	78		T15	19		T247	8
auto[0]	values[5]	values[5]	529	1			T43	20		T256	2		T190	60
auto[0]	values[5]	values[6]	570	1			T13	19		T15	20		T221	18
auto[0]	values[5]	values[7]	686	1			T15	40		T41	53		T39	20
auto[0]	values[6]	values[0]	427	1			T20	21		T191	42		T219	12
auto[0]	values[6]	values[1]	540	1			T44	46		T20	20		T21	74
auto[0]	values[6]	values[2]	260	1			T40	19		T18	19		T257	47
auto[0]	values[6]	values[3]	760	1			T15	30		T39	26		T47	19
auto[0]	values[6]	values[4]	521	1			T43	20		T216	19		T185	115
auto[0]	values[6]	values[5]	424	1			T56	2		T58	20		T199	20
auto[0]	values[6]	values[6]	706	1			T15	51		T21	161		T183	51
auto[0]	values[6]	values[7]	346	1			T40	20		T18	20		T21	20
auto[0]	values[7]	values[0]	478	1			T5	18		T224	6		T18	21
auto[0]	values[7]	values[1]	635	1			T39	48		T43	20		T174	18
auto[0]	values[7]	values[2]	703	1			T145	2		T236	20		T21	39
auto[0]	values[7]	values[3]	336	1			T9	16		T87	18		T174	19
auto[0]	values[7]	values[4]	430	1			T8	20		T41	41		T44	23
auto[0]	values[7]	values[5]	347	1			T15	20		T18	19		T44	21
auto[0]	values[7]	values[6]	637	1			T5	52		T15	42		T52	48
auto[0]	values[7]	values[7]	349	1			T192	43		T184	20		T190	20
auto[1]	values[0]	values[0]	18	1			T5	2		T200	2		T194	6
auto[1]	values[0]	values[1]	17	1			T40	1		T41	1		T233	1
auto[1]	values[0]	values[2]	5	1			T244	3		T258	2		-	-
auto[1]	values[0]	values[3]	12	1			T216	4		T259	1		T260	1
auto[1]	values[0]	values[4]	9	1			T190	2		T47	2		T261	2
auto[1]	values[0]	values[5]	11	1			T199	2		T186	2		T262	1
auto[1]	values[0]	values[6]	8	1			T179	1		T207	1		T133	2
auto[1]	values[0]	values[7]	8	1			T174	4		T263	3		T189	1
auto[1]	values[1]	values[0]	10	1			T200	1		T47	2		T264	2
auto[1]	values[1]	values[1]	10	1			T203	1		T131	1		T181	3
auto[1]	values[1]	values[2]	21	1			T41	1		T18	2		T185	3
auto[1]	values[1]	values[3]	13	1			T192	2		T265	2		T266	2
auto[1]	values[1]	values[4]	15	1			T41	1		T216	3		T267	1
auto[1]	values[1]	values[5]	18	1			T8	2		T184	1		T203	2
auto[1]	values[1]	values[6]	11	1			T18	1		T43	1		T174	1
auto[1]	values[1]	values[7]	13	1			T192	2		T129	2		T132	6
auto[1]	values[2]	values[0]	7	1			T39	1		T52	2		T185	2
auto[1]	values[2]	values[1]	16	1			T254	2		T202	4		T131	1
auto[1]	values[2]	values[2]	9	1			T43	2		T190	2		T191	3
auto[1]	values[2]	values[3]	13	1			T39	1		T218	4		T252	2
auto[1]	values[2]	values[4]	9	1			T15	3		T41	2		T133	1
auto[1]	values[2]	values[5]	5	1			T18	1		T268	1		T265	3
auto[1]	values[2]	values[6]	15	1			T5	2		T15	1		T184	1
auto[1]	values[2]	values[7]	16	1			T20	1		T185	1		T244	1
auto[1]	values[3]	values[0]	9	1			T186	4		T269	1		T129	2
auto[1]	values[3]	values[1]	11	1			T184	1		T130	3		T270	2
auto[1]	values[3]	values[2]	14	1			T20	2		T21	1		T232	1
auto[1]	values[3]	values[3]	8	1			T15	2		T225	1		T271	2
auto[1]	values[3]	values[4]	13	1			T227	1		T272	10		T273	2
auto[1]	values[3]	values[5]	24	1			T5	2		T40	3		T15	2
auto[1]	values[3]	values[6]	6	1			T42	1		T184	3		T274	2
auto[1]	values[3]	values[7]	4	1			T21	3		T269	1		-	-
auto[1]	values[4]	values[0]	22	1			T40	2		T245	2		T190	1
auto[1]	values[4]	values[1]	12	1			T18	4		T186	1		T194	4
auto[1]	values[4]	values[2]	19	1			T216	1		T192	2		T47	1
auto[1]	values[4]	values[3]	9	1			T20	2		T216	1		T227	2
auto[1]	values[4]	values[4]	4	1			T191	1		T275	3		-	-
auto[1]	values[4]	values[5]	5	1			T276	2		T156	1		T277	2
auto[1]	values[4]	values[6]	5	1			T271	1		T50	2		T278	1
auto[1]	values[4]	values[7]	12	1			T40	2		T15	2		T80	2
auto[1]	values[5]	values[0]	22	1			T15	1		T21	2		T184	1
auto[1]	values[5]	values[1]	15	1			T187	2		T239	1		T225	2
auto[1]	values[5]	values[2]	9	1			T154	1		T279	1		T280	3
auto[1]	values[5]	values[3]	13	1			T39	1		T20	1		T21	2
auto[1]	values[5]	values[4]	7	1			T15	1		T279	1		T281	1
auto[1]	values[5]	values[5]	8	1			T190	3		T47	1		T239	1
auto[1]	values[5]	values[6]	18	1			T13	1		T243	6		T154	3
auto[1]	values[5]	values[7]	9	1			T41	1		T185	1		T201	3
auto[1]	values[6]	values[0]	11	1			T20	2		T282	2		T275	2
auto[1]	values[6]	values[1]	14	1			T44	2		T21	2		T184	1
auto[1]	values[6]	values[2]	5	1			T40	1		T18	1		T259	1
auto[1]	values[6]	values[3]	18	1			T47	1		T209	2		T194	1
auto[1]	values[6]	values[4]	10	1			T216	1		T185	1		T179	1
auto[1]	values[6]	values[5]	15	1			T179	2		T207	1		T283	2
auto[1]	values[6]	values[6]	19	1			T15	3		T21	2		T194	1
auto[1]	values[6]	values[7]	10	1			T259	2		T241	4		T264	3
auto[1]	values[7]	values[0]	16	1			T5	2		T18	1		T184	1
auto[1]	values[7]	values[1]	20	1			T39	4		T174	2		T183	1
auto[1]	values[7]	values[2]	14	1			T21	1		T202	1		T132	2
auto[1]	values[7]	values[3]	11	1			T174	1		T241	2		T277	3
auto[1]	values[7]	values[4]	17	1			T44	2		T209	1		T129	2
auto[1]	values[7]	values[5]	9	1			T18	1		T44	1		T184	1
auto[1]	values[7]	values[6]	21	1			T5	2		T52	2		T216	5
auto[1]	values[7]	values[7]	12	1			T192	4		T132	2		T284	4