Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	793	1			T13	11		T14	14		T16	14
all_values[1]	793	1			T13	11		T14	14		T16	14
all_values[2]	793	1			T13	11		T14	14		T16	14
all_values[3]	793	1			T13	11		T14	14		T16	14
all_values[4]	793	1			T13	11		T14	14		T16	14
all_values[5]	793	1			T13	11		T14	14		T16	14
all_values[6]	793	1			T13	11		T14	14		T16	14
all_values[7]	793	1			T13	11		T14	14		T16	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3481

1

T13

53

T14

56

T16

62

auto[1]

2863

1

T13

35

T14

56

T16

50

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2567

1

T13

49

T14

47

T16

39

auto[1]

3777

1

T13

39

T14

65

T16

73

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3634

1

T13

57

T14

64

T16

61

auto[1]

2710

1

T13

31

T14

48

T16

51

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	176	1			T13	3		T14	3		T16	2
all_values[0]	auto[0]	auto[0]	auto[1]	70	1			T18	2		T22	2		T150	1
all_values[0]	auto[0]	auto[1]	auto[0]	110	1			T13	3		T14	4		T16	1
all_values[0]	auto[0]	auto[1]	auto[1]	97	1			T14	3		T16	2		T17	4
all_values[0]	auto[1]	auto[0]	auto[1]	176	1			T13	2		T14	1		T16	4
all_values[0]	auto[1]	auto[1]	auto[1]	164	1			T13	3		T14	3		T16	5
all_values[1]	auto[0]	auto[0]	auto[0]	157	1			T13	3		T14	1		T16	3
all_values[1]	auto[0]	auto[0]	auto[1]	75	1			T13	1		T14	2		T17	2
all_values[1]	auto[0]	auto[1]	auto[0]	153	1			T13	2		T14	2		T16	4
all_values[1]	auto[0]	auto[1]	auto[1]	70	1			T13	1		T14	1		T16	1
all_values[1]	auto[1]	auto[0]	auto[1]	189	1			T13	3		T14	4		T16	4
all_values[1]	auto[1]	auto[1]	auto[1]	149	1			T13	1		T14	4		T16	2
all_values[2]	auto[0]	auto[0]	auto[0]	168	1			T13	4		T14	2		T16	1
all_values[2]	auto[0]	auto[0]	auto[1]	87	1			T14	1		T16	5		T18	2
all_values[2]	auto[0]	auto[1]	auto[0]	111	1			T13	6		T14	3		T17	1
all_values[2]	auto[0]	auto[1]	auto[1]	74	1			T14	2		T16	1		T18	3
all_values[2]	auto[1]	auto[0]	auto[1]	193	1			T14	4		T16	7		T18	4
all_values[2]	auto[1]	auto[1]	auto[1]	160	1			T13	1		T14	2		T17	1
all_values[3]	auto[0]	auto[0]	auto[0]	173	1			T13	5		T14	2		T16	4
all_values[3]	auto[0]	auto[0]	auto[1]	76	1			T17	2		T18	1		T19	1
all_values[3]	auto[0]	auto[1]	auto[0]	131	1			T14	6		T16	5		T17	1
all_values[3]	auto[0]	auto[1]	auto[1]	64	1			T14	2		T16	2		T18	1
all_values[3]	auto[1]	auto[0]	auto[1]	197	1			T13	5		T14	1		T16	3
all_values[3]	auto[1]	auto[1]	auto[1]	152	1			T13	1		T14	3		T18	3
all_values[4]	auto[0]	auto[0]	auto[0]	178	1			T13	4		T14	3		T16	3
all_values[4]	auto[0]	auto[0]	auto[1]	92	1			T13	2		T14	1		T16	2
all_values[4]	auto[0]	auto[1]	auto[0]	120	1			T13	2		T14	1		T16	3
all_values[4]	auto[0]	auto[1]	auto[1]	66	1			T14	2		T16	2		T18	3
all_values[4]	auto[1]	auto[0]	auto[1]	180	1			T13	2		T14	4		T16	1
all_values[4]	auto[1]	auto[1]	auto[1]	157	1			T13	1		T14	3		T16	3
all_values[5]	auto[0]	auto[0]	auto[0]	243	1			T13	3		T14	3		T16	5
all_values[5]	auto[0]	auto[1]	auto[0]	217	1			T13	3		T14	3		T16	3
all_values[5]	auto[1]	auto[0]	auto[1]	183	1			T13	2		T14	4		T16	4
all_values[5]	auto[1]	auto[1]	auto[1]	150	1			T13	3		T14	4		T16	2
all_values[6]	auto[0]	auto[0]	auto[0]	161	1			T13	6		T14	5		T16	1
all_values[6]	auto[0]	auto[0]	auto[1]	77	1			T13	1		T16	2		T17	1
all_values[6]	auto[0]	auto[1]	auto[0]	153	1			T13	1		T14	2		T16	3
all_values[6]	auto[0]	auto[1]	auto[1]	68	1			T16	1		T18	2		T20	1
all_values[6]	auto[1]	auto[0]	auto[1]	190	1			T13	2		T14	5		T16	3
all_values[6]	auto[1]	auto[1]	auto[1]	144	1			T13	1		T14	2		T16	4
all_values[7]	auto[0]	auto[0]	auto[0]	193	1			T13	2		T14	5		T16	1
all_values[7]	auto[0]	auto[0]	auto[1]	74	1			T13	1		T14	2		T16	1
all_values[7]	auto[0]	auto[1]	auto[0]	123	1			T13	2		T14	2		T18	2
all_values[7]	auto[0]	auto[1]	auto[1]	77	1			T13	2		T14	1		T16	3
all_values[7]	auto[1]	auto[0]	auto[1]	173	1			T13	2		T14	3		T16	6
all_values[7]	auto[1]	auto[1]	auto[1]	153	1			T13	2		T14	1		T16	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal