Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1873

1

T1

1

T2

12

T8

5

auto[1]

1851

1

T1

3

T2

5

T5

1

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2007

1

T1

2

T2

17

T5

1

auto[1]

1717

1

T1

2

T31

3

T32

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2970

1

T1

3

T2

12

T8

8

auto[1]

754

1

T1

1

T2

5

T5

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	741	1			T1	2		T2	6		T8	2
valid[1]	754	1			T2	6		T5	1		T8	3
valid[2]	774	1			T2	2		T8	2		T31	1
valid[3]	733	1			T1	2		T2	1		T8	2
valid[4]	722	1			T2	2		T33	8		T35	5

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	130	1			T2	3		T8	1		T13	1
auto[0]	auto[0]	valid[0]	auto[1]	175	1			T1	1		T33	4		T35	3
auto[0]	auto[0]	valid[1]	auto[0]	123	1			T2	4		T8	2		T13	1
auto[0]	auto[0]	valid[1]	auto[1]	184	1			T35	5		T36	1		T85	1
auto[0]	auto[0]	valid[2]	auto[0]	124	1			T2	1		T8	1		T38	1
auto[0]	auto[0]	valid[2]	auto[1]	184	1			T31	1		T33	3		T35	1
auto[0]	auto[0]	valid[3]	auto[0]	121	1			T8	1		T38	1		T13	2
auto[0]	auto[0]	valid[3]	auto[1]	154	1			T33	2		T35	1		T36	1
auto[0]	auto[0]	valid[4]	auto[0]	117	1			T2	1		T13	2		T27	1
auto[0]	auto[0]	valid[4]	auto[1]	167	1			T33	4		T35	2		T36	1
auto[0]	auto[1]	valid[0]	auto[0]	124	1			T2	2		T38	1		T113	1
auto[0]	auto[1]	valid[0]	auto[1]	182	1			T32	1		T33	2		T35	3
auto[0]	auto[1]	valid[1]	auto[0]	133	1			T8	1		T13	1		T27	1
auto[0]	auto[1]	valid[1]	auto[1]	164	1			T31	1		T32	1		T33	4
auto[0]	auto[1]	valid[2]	auto[0]	122	1			T8	1		T38	1		T27	2
auto[0]	auto[1]	valid[2]	auto[1]	172	1			T32	1		T35	4		T36	1
auto[0]	auto[1]	valid[3]	auto[0]	144	1			T1	1		T8	1		T38	3
auto[0]	auto[1]	valid[3]	auto[1]	166	1			T1	1		T31	1		T32	1
auto[0]	auto[1]	valid[4]	auto[0]	115	1			T2	1		T13	3		T17	4
auto[0]	auto[1]	valid[4]	auto[1]	169	1			T33	4		T35	3		T36	2
auto[1]	auto[0]	valid[0]	auto[0]	68	1			T2	1		T13	3		T14	1
auto[1]	auto[0]	valid[1]	auto[0]	85	1			T38	1		T27	1		T14	2
auto[1]	auto[0]	valid[2]	auto[0]	84	1			T2	1		T38	2		T13	4
auto[1]	auto[0]	valid[3]	auto[0]	76	1			T2	1		T15	1		T112	1
auto[1]	auto[0]	valid[4]	auto[0]	81	1			T13	2		T113	1		T39	2
auto[1]	auto[1]	valid[0]	auto[0]	62	1			T1	1		T8	1		T38	1
auto[1]	auto[1]	valid[1]	auto[0]	65	1			T2	2		T5	1		T15	1
auto[1]	auto[1]	valid[2]	auto[0]	88	1			T38	2		T13	2		T42	1
auto[1]	auto[1]	valid[3]	auto[0]	72	1			T14	1		T15	1		T17	1
auto[1]	auto[1]	valid[4]	auto[0]	73	1			T38	1		T13	3		T112	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal